Semiconductor device manufacturing method

Abstract

The present application discloses a method for manufacturing a semiconductor device, the method including the steps of providing a substrate, forming an epitaxial structure on one side of the substrate, and forming gates and gate connection structures on a side of the epitaxial structure away from the substrate, the gate connection structures being electrically connected to at least some of the gates. ... the epitaxial structure being electrically connected to at least some of the gates, the method including the steps of forming a gate connection structure electrically connected to at least some of the gates, the method including the steps of reducing the effect of gate resistance, improving gain, and reducing leakage current.

Description

[Technical Field]

[0001] This application relates to the field of semiconductors, and more particularly to methods of manufacturing semiconductor devices. [Background technology]

[0002] Gallium nitride semiconductor materials have significant advantages, such as a large band gap width, a high electron saturation drift rate, a high breakdown field strength, and high heat resistance, making them suitable for the fabrication of high-temperature, high-voltage, high-frequency, and high-power electronic devices. They are currently the focus of research in the semiconductor industry.

[0003] In GaN RF power amplifiers, achieving both the device's power and gain characteristics is required by application circuits, and is also pursued in GaN RF chips. However, because the gate power supply is on one side of the device, the power supply on the other side of the gate is affected by the gate resistance and decreases. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a method for manufacturing a semiconductor device that can reduce the influence of gate resistance, improve gain, and reduce leakage current. [Means for solving the problem]

[0005] According to a first aspect, the present application provides a method for manufacturing a semiconductor device, the method comprising the steps of providing a substrate, forming an epitaxial structure on one side of the substrate, and forming gates and gate connection structures on a side of the epitaxial structure remote from the substrate, the gate connection structures being electrically connected to at least some of the gates.

[0006] In a possible realization of the present application, the step of forming a gate and a gate connection structure on a side of the epitaxial structure away from the substrate includes forming the gate and the gate connection structure on a side of the epitaxial structure away from the substrate using the same process, wherein the gate connection structure includes a first gate sub-connection and a second gate sub-connection connected to each other, and along a thickness direction of the semiconductor device, the first gate sub-connection does not overlap with the gate and the second gate sub-connection is electrically connected to the gate.

[0007] In a possible realization of the present application, before forming the gate and the gate connection structure on the side of the epitaxial structure away from the substrate, the method further comprises forming a source on the side of the epitaxial structure away from the substrate, wherein along the thickness direction of the semiconductor device, the first gate sub-connection overlaps and is insulatively located with the source, or the first gate sub-connection is located on the side of the source away from the gate.

[0008] In a possible implementation of the present application, the semiconductor device includes an active region and a non-active region surrounding the active region, and the second gate sub-connection is located in the active region, or the gate includes a first gate sub-portion and a second gate sub-portion connected to each other, and both the second gate sub-portion and the second gate sub-connection are located in the non-active region, and the second gate sub-connection is electrically connected to the second gate sub-portion.

[0009] In a possible implementation of the present application, forming a gate and a gate connection structure on a side of the epitaxial structure away from the substrate includes forming a source and a gate, respectively, on a side of the epitaxial structure away from the substrate, forming a first dielectric layer on a side of the gate away from the substrate, and forming a gate connection structure and a source field plate on a side of the first dielectric layer away from the substrate using the same process, wherein the gate connection structure is electrically connected to the gate and the source field plate is electrically connected to the source.

[0010] In a possible realization of the present application, after forming a via on the side of the gate away from the substrate and forming a first dielectric layer, the method further includes forming a first connection via and a second connection via in the first dielectric layer using the same process, wherein the first connection via exposes a portion of the gate and the second connection via exposes a portion of the source, the gate connection structure is electrically connected to the gate via the first connection via, and the source field plate is electrically connected to the source via the second connection via.

[0011] In a possible implementation of the present application, the source field plate includes a field plate body and a field plate connection portion, and the field plate connection portion is electrically connected to the source through a second connection via. The gate connection structure includes a first gate sub-connection portion and a second gate sub-connection portion connected to each other, and the second gate sub-connection portion is electrically connected to the gate through the first connection via. The field plate connection portion is offset from the first connection via, and the second gate sub-connection portion is offset from the second connection via.

[0012] In a possible realization of the present application, the thickness of the gate connection structure is greater than the thickness of the first dielectric layer, and the thickness of the source field plate is greater than the thickness of the first dielectric layer.

[0013] In one possible implementation of the present application, the semiconductor device includes an active region and a non-active region surrounding the active region. The source field plate includes a field plate body and a field plate connection portion connected to each other, the field plate connection portion being electrically connected to the source. The gate connection structure includes a first gate sub-connection portion and a second gate sub-connection portion connected to each other, the second gate sub-connection portion being electrically connected to the gate.

[0014] In a possible implementation of the present application, the semiconductor device includes an active region and a non-active region surrounding the active region, and forming a gate and gate connection structure on a side of the epitaxial structure away from the substrate includes: forming a source and gate connection structure on a side of the epitaxial structure away from the substrate using the same process, the gate connection structure including a first gate sub-connection and a second gate sub-connection connected to each other, the second gate sub-connection being located in the non-active region; forming a second dielectric layer on a side of the source and gate connection structure away from the substrate; and forming a gate on the second dielectric layer away from the substrate, the gate including a first gate sub-portion and a second gate sub-portion connected to each other, the second gate sub-portion being located in the non-active region, the second gate sub-portion being electrically connected to the second gate sub-connection.

[0015] In a possible realization of the present application, forming a gate and a gate connection structure on a side of the epitaxial structure away from the substrate includes forming a gate on a side of the epitaxial structure away from the substrate, forming a third dielectric layer on a side of the gate away from the substrate, and forming a gate connection structure and a gate pad on a side of the third dielectric layer away from the substrate using the same process, wherein the gate connection structure is electrically connected to the gate and the gate pad is electrically connected to the gate.

[0016] A possible implementation of the present application further includes the steps of forming a third dielectric layer on the side of the gate away from the substrate, and then forming a fourth connection via and a fifth connection via in the third dielectric layer, wherein the fourth connection via and the fifth connection via both expose a portion of the gate, the gate connection structure is electrically connected to the gate via the fourth connection via, and the gate pad is electrically connected to the gate via the fifth connection via.

[0017] In a possible realization of the present application, forming a gate and a gate connection structure on a side of the epitaxial structure away from the substrate includes forming a gate on a side of the epitaxial structure away from the substrate, forming a fourth dielectric layer on a side of the gate away from the substrate, and forming a gate connection structure on a side of the fourth dielectric layer away from the substrate, the gate connection structure being electrically connected to the gate.

[0018] A possible implementation of the present application further includes a step of forming a fourth dielectric layer on the side of the gate away from the substrate, and then forming a sixth connection via in the fourth dielectric layer, the sixth connection via exposing a portion of the gate, and the gate connection structure being electrically connected to the gate through the sixth connection via.

[0019] In a possible realization of the present application, the gate at least partially overlaps the gate connection structure along the thickness direction of the semiconductor device. [Effects of the Invention]

[0020] The method for manufacturing a semiconductor device according to the present application forms a gate and a gate connection structure on the side of the epitaxial structure away from the substrate, and electrically connects the gate connection structure to at least some of the gates, thereby reducing gate resistance, improving gate gain, and reducing leakage current. [Brief explanation of the drawings]

[0021] In order to more clearly describe the technical solutions in the embodiments of the present application, the drawings necessary for describing the embodiments will be briefly described below. However, the drawings in the following description are only some embodiments of the present application, and it is obvious to those skilled in the art that they can obtain other drawings based on the configurations shown in these drawings without any creative efforts. [Figure 1] 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application. [Figure 2] 1 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application. [Figure 3] 1 is a schematic diagram illustrating the configuration of a semiconductor device according to an embodiment of the present application. [Figure 4] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 5] FIG. 10 is a schematic diagram illustrating the configuration of a semiconductor device according to yet another embodiment of the present application. [Figure 6] 1 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application. [Figure 7] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 8] FIG. 8 is a schematic cross-sectional view of the semiconductor device shown in FIG. 7 taken along line AA'. [Figure 9] 1 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application. [Figure 10] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 11] 11 is a schematic cross-sectional view of the semiconductor device shown in FIG. 10 taken along line BB'. FIG. [Figure 12] 1 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application. [Figure 13] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 14] FIG. 14 is a schematic cross-sectional view of the semiconductor device shown in FIG. 13 taken along line CC'. [Figure 15] 1 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application. [Figure 16] 14 is another cross-sectional view taken along the line CC' of the semiconductor device shown in FIG. 13.

[0033] FIG. [Figure 17] 1 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, but it is clear that the described embodiments are only a part of the embodiments of the present application, and are not all of the embodiments. Based on the embodiments of the present application, all other embodiments that can be obtained by those skilled in the art without any creative efforts fall within the scope of protection of the present application.

[0023] In the description of the embodiments of the present application, the terms "first" and "second" are used for descriptive purposes only and cannot be understood to indicate or imply relative importance or the number of technical features shown. Thus, a feature qualified by "first" or "second" may explicitly or implicitly include one or more features. In the description of the embodiments of the present application, "plurality" means two or more than two, unless expressly limited otherwise.

[0024] The following description is provided to enable any person skilled in the art to make and use the present application. In the following description, certain details are set forth for purposes of explanation. Those skilled in the art will be able to practice the present application without these specific details. In other instances, well-known processes are not described in detail so as to avoid obscuring the description of the embodiments of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed in the embodiments of the present application.

[0025] In the 5G communications field, the bandwidth and high frequency requirements for semiconductor RF devices are extremely high. The gate structure design and process flow are closely related to the frequency characteristics of semiconductor devices and directly affect the operating frequency of semiconductor devices. Therefore, gate structure design is particularly important in the design and manufacturing process of semiconductor devices and plays a key role in the reliability and stability of semiconductor device performance.

[0026] In GaN RF power amplifiers, achieving both device power and gain characteristics is a requirement for application circuits, and is also being pursued in GaN RF chips. Specifically, in conventional integrated circuit GaN RF chip designs, the gate power supply is located on one side of the device, so the power supply on the other side of the gate is affected by gate resistance and reduced, resulting in a significant decrease in gain. Therefore, how to further improve the bandwidth and high-frequency performance of semiconductor devices while also improving semiconductor device gain and achieving a performance balance in power amplifiers is an urgent issue that needs to be resolved.

[0027] 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application. As shown in FIG. 1, the method for manufacturing a semiconductor device includes the following steps: S101: Provide a substrate.

[0028] For example, the substrate material may be one or more combinations of sapphire, silicon carbide, silicon, gallium arsenide, gallium nitride, or aluminum nitride, or other materials suitable for growing gallium nitride. The substrate may be fabricated by atmospheric pressure chemical vapor deposition, subatmospheric pressure chemical vapor deposition, metal organic chemical vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, physico-chemical mixed vapor deposition, rapid thermal chemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, evaporation, or the like. The embodiments of the present application are not limited to these methods.

[0029] S102: Form an epitaxial structure on one side of the substrate.

[0030] For example, the epitaxial structure may be formed of one or more of III-V nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride, and a two-dimensional electron gas may be formed within the epitaxial structure. Methods for growing the epitaxial structure include, but are not limited to, metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, and liquid phase epitaxy.

[0031] S103: Forming gates and gate connection structures on the side of the epitaxial structure away from the substrate, the gate connection structures electrically connecting to at least some of the gates.

[0032] For example, the semiconductor device according to the embodiments of the present application may have a single-cell structure or a multi-cell structure, and the embodiments of the present application are not limited thereto. When the semiconductor device has a single-cell structure, the semiconductor device may include one basic source-gate-drain structure. When the semiconductor device has a multi-cell structure, the semiconductor device may include multiple basic source-gate-drain structures. The gate may extend along a first direction, and multiple gates may be arranged along a second direction. The second direction may be located in the same plane as the first direction and perpendicular to the first direction.

[0033] Furthermore, the manufacturing method according to the embodiment of the present application may further include forming a gate connection structure on a side of the epitaxial structure away from the substrate, the gate connection structure being electrically connected to at least some of the gates. The gate resistance affects the charging and discharging speed of the junction capacitance, which in turn affects the switching speed of the semiconductor device. That is, the smaller the gate resistance, the faster the switching speed of the semiconductor device. By electrically connecting the gate connection structure to at least some of the gates, the gate resistance can be reduced and the switching speed of the semiconductor device can be increased.

[0034] The method for manufacturing a semiconductor device according to the embodiment of the present application forms a gate connection structure on the side of the epitaxial structure away from the substrate, and the gate connection structure is electrically connected to at least some of the gates, thereby reducing the influence of gate resistance, improving gain, and reducing leakage current.

[0035] Optionally, Figure 2 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application. The manufacturing method shown in Figure 2 specifically describes how to form a gate and a gate connection structure. As shown in Figure 2, the method for manufacturing a semiconductor device includes the following steps: S201: Provide a substrate. S202: Form an epitaxial structure on one side of the substrate. S203: Using the same process, form gates and gate contact structures on the side of the epitaxial structure away from the substrate.

[0036] Specifically, the gate connection structure includes a first gate sub-connection portion and a second gate sub-connection portion connected to each other, and along the thickness direction of the semiconductor device, the first gate sub-connection portion does not overlap with the gate, and the second gate sub-connection portion is electrically connected to the gate.

[0037] For example, the gate and the gate connection structure can be formed using the same process, for example, by simultaneously forming the gate and the gate connection structure using the same mask process, the process of forming the gate and the gate connection structure is simplified, and by forming the gate and the gate connection structure using the same process, it can also be ensured that the gate and the gate connection structure are located in the same layer, which can simplify the structure of the semiconductor device.

[0038] FIG. 3 is a schematic diagram of a semiconductor device according to one embodiment of the present invention, and FIG. 4 is a schematic diagram of a semiconductor device according to another embodiment of the present invention. As shown in FIGS. 3 and 4, the gate connection structure 140 includes a first gate sub-connection portion 1401 and a second gate sub-connection portion 1402 connected to each other. Along the thickness direction of the semiconductor device, the first gate sub-connection portion 1401 does not overlap with the gate 130, and the second gate sub-connection portion 1402 is electrically connected to the gate 130. Specifically, the first gate sub-connection portion 1401 has a relatively large area and serves as a main adjustment structure for the gain of the gate 130, optimizing the electric field of the gate 130, reducing the resistance of the gate 130, and improving the gain of the gate 130. The second gate sub-connection portion 1402 serves as a connection portion between the gate 130 and the gate connection structure 140, ensuring a normal connection between the gate 130 and the gate connection structure 140 and thereby reducing the resistance of the gate 130. The gate 130 does not overlap the first gate sub-connection 1401 along the thickness direction of the semiconductor device 10. That is, the first gate sub-connection 1301 does not overlap the first gate sub-connection 1401 along the second direction (the X direction shown in FIGS. 3 and 4 ), that is, the first gate sub-connection 1301 is offset from the first gate sub-connection 1401. The resistance of the gate 130 affects the charging and discharging speed of the junction capacitance, which in turn affects the switching speed of the semiconductor device 10. That is, the smaller the resistance of the gate 130, the faster the switching speed of the semiconductor device 10. By electrically connecting the second gate sub-connection 1402 in the gate connection structure 140 to the gate 130, the resistance of the gate 130 can be reduced and the switching speed of the semiconductor device 10 can be increased.

[0039] 3 , semiconductor device 10 includes an active region aa and a non-active region bb surrounding active region aa. Gate 130 includes a first gate sub-portion 1301 and a second gate sub-portion 1302 connected to each other, with second gate sub-portion 1302 located in non-active region bb, and second gate sub-connection 1402 located in non-active region bb, and second gate sub-connection 1402 electrically connected to second gate sub-portion 1302.

[0040] Specifically, the active region aa may be understood as a region beneath which two-dimensional electron gas, electrons, or holes are present, and whose operating state and characteristics are affected by an external circuit, and is the active operating region of the semiconductor device 10. The non-active region bb is involved in the operation of the semiconductor device 10, but whose operating state is not affected by the external circuit. For example, an electrode lead-out structure for the active region aa may be provided in the non-active region bb, and the non-active region bb may be provided surrounding the active region aa.

[0041] The gate 130 includes a first gate sub-portion 1301 and a second gate sub-portion 1302 connected to each other, and the gate connection structure 140 includes a first gate sub-connection portion 1401 and a second gate sub-connection portion 1402 connected to each other. The first gate sub-portion 1301 includes a portion that forms a Schottky contact with the epitaxial structure 120 in the active region aa and further includes a portion that extends along the first direction Y and is connected to the gate pad 170. The first gate sub-portion 1301 functions as the gate 130 structure of the semiconductor device 10 and controls the conduction and blocking of the gate 130 in the semiconductor device 10, thereby controlling the operating state of the semiconductor device 10. The first gate sub-connection portion 1401 is located in the active region aa and has a relatively large area. It functions as a main adjustment structure for the gain of the gate 130, reducing the resistance of the gate 130 and improving the gain of the gate 130. The second gate sub-portion 1302 and the second gate sub-connection portion 1402 are both located in the non-active region bb and function as sub-connections between the gate 130 and the gate connection structure 140, ensuring a normal connection between the gate 130 and the gate connection structure 140 and thereby reducing the resistance of the gate 130. Furthermore, the second gate sub-portion 1302 and the second gate sub-connection portion 1402 are electrically connected in the non-active region bb, which does not affect the installation manner of the semiconductor device 10 in the active region aa or the normal operation and performance of the active region aa, ensuring stable performance of the semiconductor device 10. Furthermore, because the non-active region bb has a relatively large installation space, the second gate sub-portion 1302 and the second gate sub-connection portion 1402 located in the non-active region bb have a relatively large design freedom, which facilitates improving the connection stability between the second gate sub-portion 1302 and the second gate sub-connection portion 1402.

[0042] 4 , based on the above embodiment, the semiconductor device 10 includes an active region aa and a non-active region bb surrounding the active region aa, and the second gate sub-connection portion 1402 is located in the active region aa. That is, the gate connection structure 140 is electrically connected to the gate 130 in the active region aa, not in the non-active region bb, thereby reducing the resistance of the gate 130, increasing the switching speed and gain, while maintaining a compact configuration of the semiconductor device, which contributes to a miniaturized design of the semiconductor device.

[0043] Note that the gate 130 and the epitaxial structure 120 form a Schottky contact, but the gate connection structure 140 and the epitaxial structure 120 do not form a Schottky contact. Specifically, the gate connection structure 140 does not make direct electrical contact with a conductive groove (e.g., a two-dimensional electron gas) in the epitaxial structure 120. The gate connection structure 140 is connected to the gate 130 via at least two channels, thereby connecting the gate connection structure 140 and the gate 130 in parallel. Optionally, the gate connection structure 140 may be connected to the gate 130 via a second gate sub-connection 1402 and a gate pad 170 (as shown in FIG. 3 ). Optionally, the gate connection structure 140 may be connected to the gate 130 via at least two second gate sub-connections 1402 (not shown). For example, the gate connection structure 140 may be connected to the gate 130 via two second gate sub-connections 1402, one of which is located in the active region aa and the other of which is located in the non-active region bb, or both of which are located in the active region aa.

[0044] Based on the above embodiment, FIG. 5 is a structural schematic diagram of a semiconductor device according to yet another embodiment of the present application. Combining FIGS. 3, 4, and 5, a manufacturing method according to an embodiment of the present application may further include a step of forming a source on the side of the epitaxial structure away from the substrate, before forming a gate and a gate connection structure on the side of the epitaxial structure away from the substrate using the same process, so that the source forms an ohmic structure with the epitaxial structure.

[0045] Specifically, the source may be connected to the backside of the semiconductor device via a source through-hole. For example, the source through-hole may pass through the substrate and the epitaxial structure, i.e., connected to the source via a source signal input electrode (not shown) on the side of the substrate away from the epitaxial structure. That is, the source is electrically connected to the source signal input electrode via the source through-hole.

[0046] Continuing to refer to FIGS. 3 and 4, along the thickness of the semiconductor device 10, the first gate sub-connection 1401 overlaps and is insulatively located with the source 150.

[0047] 3 and 4, for example, the first gate sub-connection portion 1401 may be disposed above the source 150 so as to overlap with the projection of the source 150. On the one hand, the first gate sub-connection portion 1401 overlapping the source 150 does not affect the extraction of a signal from the gate 130. On the other hand, the first gate sub-connection portion 1401 overlapping the source 150 can reduce the area of ​​the semiconductor device 10. Furthermore, the first gate sub-connection portion 1401 can also be disposed above the source through-hole, thereby ensuring the stability of the source through-hole region and allowing the semiconductor device 10 to operate normally.

[0048] With continued reference to FIG. 5, the first gate sub-connection 1401 is located on the side of the source 150 away from the gate 130 .

[0049] 5 , in a multi-cell semiconductor device, along the second direction X, the first gate sub-connection 1401 is located on the side of the source 150 away from the gate 130, and the first gate sub-connection 1401 is located between two adjacent sources 150, and two adjacent transistor cells share the same first gate sub-connection 1401. Thus, the semiconductor device 10 has an arrangement of drain 180, gate 130, source 150, gate connection structure 140, source 150, gate 130, and drain 180, rather than an arrangement in which adjacent transistor single cells share a single source. That is, adjacent transistor single cells share a single first gate sub-connection 1401, and each single cell has a source 150, gate 130, and drain 180. This structure can reduce the effect of the resistance of the gate 130, improve gain, and reduce leakage current.

[0050] For example, still referring to FIG. 5, along the second direction X, a constant distance is maintained between the first gate sub-connection 1401 and two adjacent sources 150, and they are equally spaced.

[0051] 5 illustrates an example in which the semiconductor device includes only a multi-cell structure, but it should be understood that the semiconductor device may also include only a single-cell structure. In this case, the first gate sub-connection may also be disposed on the side of the source away from the gate in the second direction X, but this will not be described again here.

[0052] 6 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application, which specifically describes how to form a gate and a gate connection structure. As shown in FIG. 6, the method for manufacturing a semiconductor device includes the following steps: S301: Provide a substrate. S302: Form an epitaxial structure on one side of the substrate. S303: Form a source and a gate on the side of the epitaxial structure away from the substrate. S304: Form a first dielectric layer on the side of the gate away from the substrate. S305: Using the same process, form a gate connection structure and a source field plate on the side of the first dielectric layer away from the substrate, the gate connection structure being electrically connected to the gate and the source field plate being electrically connected to the source.

[0053] Fig. 7 is a schematic diagram of a semiconductor device according to another embodiment of the present application, and Fig. 8 is a schematic cross-sectional diagram of the semiconductor device shown in Fig. 7 taken along line A-A'. As shown in Figs. 7 and 8, in the manufacturing method according to the embodiment of the present application, first, a source 150 and a drain 180 are formed on the side of the epitaxial structure 120 away from the substrate 110, and the source 150 and the drain 180 together form an ohmic structure with the epitaxial structure 120. Next, a gate 130 is formed on the side of the epitaxial structure 120 away from the substrate 110 and between the source 150 and the drain 180, and the gate 130 in the active region aa and the epitaxial structure 120 form a Schottky structure.

[0054] Next, a first dielectric layer 210 is formed on the side of the source 150 and the gate 130 away from the substrate 110. The first dielectric layer 210 covers the source 150 and the gate 130. The same mask process may be used to form a first connection via K1 and a second connection via K2 in the first dielectric layer 210. The first connection via K1 exposes a portion of the gate 130, and the second connection via K2 exposes a portion of the source 150. For example, the first dielectric layer 210 may be made of materials such as silicon dioxide, silicon nitride, and aluminum oxide. Methods for forming the first dielectric layer 210 include physical vapor deposition and / or chemical vapor deposition. The first dielectric layer 210 may cover the electrode structure.

[0055] Next, the same process is used to form a gate connection structure 140 and a source field plate 160 on the side of the first dielectric layer 210 away from the substrate 110, with the gate connection structure 140 electrically connected to the gate 130 through a first connection via K1 and the source field plate 160 electrically connected to the source 150 through a second connection via K2.

[0056] The first connection via K1 exposes a portion of the gate 130, allowing the gate connection structure 140 to continue growing within the exposed region of the gate 130, and the gate connection structure 140 to be electrically connected to the gate 130 through the first connection via K1. On the one hand, the resistance of the gate 130 can be reduced and the gain can be improved, and on the other hand, the stability of the connection can be improved, thereby ensuring the operational performance of the semiconductor device. Furthermore, the second connection via K2 exposes a portion of the source 150, allowing the source field plate 160 to continue growing within the exposed region of the source 150, and the source field plate 160 to be electrically connected to the source 150 through the second connection via K2. On the one hand, the resistance of the source 150 can be reduced, and on the other hand, the stability of the connection can be improved, thereby ensuring the operational performance of the semiconductor device. The gate connection structure 140 is located in the same layer as the source field plate 160 and is formed in the same process. On the one hand, this simplifies the process flow, avoids the installation of unnecessary film layers, and simplifies the mask process, and on the other hand, it is advantageous for the design of thinner and lighter semiconductor devices.

[0057] It should be noted that the first dielectric layer in the embodiments of the present application may refer to a single dielectric layer or multiple dielectric layers, and the embodiments of the present application are not limited to these.

[0058] In summary, the manufacturing method according to the embodiment of the present application can form the gate contact structure and the source field plate using the same process and the same material, which on the one hand simplifies the process flow, avoids the installation of unnecessary film layers, and simplifies the mask process, and on the other hand is advantageous for designing a thin and lightweight semiconductor device.

[0059] 8, the thickness of the gate connection structure 140 is greater than the thickness of the first dielectric layer 210. The thickness of the source field plate 160 is greater than the thickness of the first dielectric layer 210. This arrangement can reduce gate parasitic capacitance and ensure the operating performance of the semiconductor device.

[0060] 7 and 8, the semiconductor device 10 includes an active region aa and a non-active region bb surrounding the active region aa. The source field plate 160 includes a field plate body 1601 and a field plate connection portion 1602, and the field plate connection portion 1602 is electrically connected to the source 150 through a second connection via K2. The gate connection structure 140 includes a first gate sub-connection portion 1401 and a second gate sub-connection portion 1402, which are connected to each other, and the second gate sub-connection portion 1402 is electrically connected to the gate 130 through a first connection via K1. The field plate connection portion 1602 is offset from the first connection via K1. The second gate sub-connection portion 1402 is offset from the second connection via K2.

[0061] Specifically, the field plate connection portion 1602 is electrically connected to the source 150 through the second connection via K2, thereby achieving electrical connection between the source field plate 160 and the source 150. Furthermore, the field plate connection portion 1602 is positioned offset from the first connection via K1, which prevents their projections from overlapping and prevents the field plate connection portion 1602 from overlapping with the gate connection structure 140, thereby avoiding mutual interference. Furthermore, the second gate sub-connection portion 1402 is positioned offset from the second connection via K2, which prevents mutual interference between the source field plate 160 and the second gate sub-connection portion 1402 in the gate connection structure 140 and ensures the operational performance of the semiconductor device 10.

[0062] 7 illustrates an example in which the second gate sub-connection portion 1402 is located in the non-active region, but it should be understood that the second gate sub-connection portion 1402 may be located in the active region aa or the non-active region bb. Whether the second gate sub-connection portion 1402 is located in the active region aa or the non-active region bb, the second gate sub-connection portion 1402 is positioned offset from the second connection via K2 to avoid mutual interference between the source field plate 160 and the gate connection structure 140.

[0063] Optionally, and continuing to show in FIG. 7, semiconductor device 10 includes an active area aa and a non-active area bb surrounding active area aa. The gate connection structure 140 includes a first gate sub-connection portion 1401 and a second gate sub-connection portion 1402 connected to each other, and the second gate sub-connection portion 1402 is electrically connected to the gate 130 through a first connection via K1. The second gate sub-connection portion 1402 is located in the non-active region bb. The total opening area of ​​the second connection via K2 is S1, and the source area is S2, where S1 / S2≧50%.

[0064] Specifically, the source field plate 160 is electrically connected to the source 150 via the second connection via K2, and the total opening area S1 of the second connection via K2 and the area S2 of the source 150 satisfy S1 / S2≧50%. That is, the total opening area of ​​the second connection via K2 is greater than half the area of ​​the source 150. That is, the area of ​​the source 150 exposed by the first dielectric layer 210 is relatively large, and the exposed source metal is electrically connected to the source field plate 160 over a large area via the second connection via K2. This allows the function of a source field plate to be realized on the one hand, and ensures connection stability on the other hand.

[0065] FIG. 9 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application, FIG. 10 is a schematic diagram of the configuration of a semiconductor device according to another embodiment of the present application, and FIG. 11 is a schematic cross-sectional diagram of the semiconductor device shown in FIG. 10 taken along line B-B'. As shown in FIGS. 9, 10, and 11, the method for manufacturing a semiconductor device according to an embodiment of the present application includes the following steps. S401: Provide a substrate. S402: Form an epitaxial structure on one side of a substrate. S403: Using the same process, form a source and gate connection structure on a side of the epitaxial structure away from the substrate, the gate connection structure including a first gate sub-connection portion and a second gate sub-connection portion connected to each other, the second gate sub-connection portion being located in the non-active region.

[0066] For example, the gate connection structure 140 and the source 150 are disposed in the same layer and formed in the same process, which on the one hand simplifies the process flow, avoids the deposition of unnecessary film layers, and simplifies the mask process, and on the other hand is advantageous for designing a thin and lightweight semiconductor device.

[0067] Furthermore, the gate connection structure 140 includes a first gate sub-connection portion 1401 and a second gate sub-connection portion 1402 connected to each other, and since the gate connection structure 140 needs to be electrically connected to the gate 130, the second gate sub-connection portion 1402 may be disposed in the inactive region bb, so that when the second gate sub-connection portion 1402 is electrically connected to the gate 130, no short circuit occurs between the gate connection structure 140 and the source 150.

[0068] S404: Form a second dielectric layer on the side of the source and gate contact structures away from the substrate.

[0069] For example, a second dielectric layer 220 may be formed on the side of the source 150 and the gate connection structure 140 away from the substrate 110, and the second dielectric layer 220 may cover the source 150 and the gate connection structure 140. Furthermore, a third connection via K3 may be formed in the second dielectric layer 220, and a portion of the second gate sub-connection portion 1402 may be exposed through the third connection via K3, thereby making it easier for the gate 130 to be subsequently electrically connected to the second gate sub-connection portion 1402 through the third connection via K3.

[0070] Additionally, the second dielectric layer 220 may be materials such as silicon dioxide, silicon nitride, and aluminum oxide. Methods for forming the second dielectric layer 220 include physical vapor deposition and / or chemical vapor deposition.

[0071] S405: Form a gate on a side of the second dielectric layer away from the substrate, the gate including a first gate sub-portion and a second gate sub-portion connected to each other, the second gate sub-portion being located in the non-active region, and the second gate sub-portion being electrically connected to a second gate sub-connection portion.

[0072] Specifically, the gate 130 includes a first gate sub-portion 1301 and a second gate sub-portion 1302 connected to each other, and the second gate sub-portion 1302 is electrically connected to a second gate sub-connection portion 1402 through a third connection via K3, thereby realizing an electrical connection between the gate 130 and the gate connection structure 140, which facilitates reducing the impedance of the gate 130 and improving the performance of the semiconductor device.

[0073] It should be noted that the second dielectric layer in the embodiments of the present application may refer to a single dielectric layer or multiple dielectric layers, and the embodiments of the present application are not limited to these.

[0074] In summary, the manufacturing method according to the embodiment of the present application forms source and gate connection structures on the side of the epitaxial structure away from the substrate using the same process, which on the one hand simplifies the process flow, avoids the installation of unnecessary film layers, and simplifies the mask process, and on the other hand is advantageous for designing thin and lightweight semiconductor devices.

[0075] FIG. 12 is a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application, FIG. 13 is a schematic diagram of the configuration of a semiconductor device according to another embodiment of the present application, and FIG. 14 is a schematic cross-sectional diagram of the semiconductor device shown in FIG. 13 taken along line CC'. As shown in FIGS. 12 to 14, the manufacturing method according to the embodiment of the present application includes the following steps. S501: Provide a substrate.

[0076] S502: Form an epitaxial structure on one side of the substrate.

[0077] S503: Form a gate on the side of the epitaxial structure away from the substrate.

[0078] S504: Form a third dielectric layer on the side of the gate away from the substrate.

[0079] For example, a third dielectric layer 230 may be formed on the side of the gate 130 away from the substrate 110, and the third dielectric layer 230 may cover the gate 130. Furthermore, a fourth connection via K4 and a fifth connection via K5 may also be formed in the third dielectric layer 230, and the fourth connection via K4 and the fifth connection via K5 may both expose a portion of the gate 130, thereby facilitating subsequent electrical connection of the gate connection structure 140 and the gate pad 170 to the gate 130 via the fourth connection via K4 and the fifth connection via K5, respectively.

[0080] Additionally, the third dielectric layer 230 may be materials such as silicon dioxide, silicon nitride, and aluminum oxide. Methods for forming the third dielectric layer 230 include physical vapor deposition and / or chemical vapor deposition.

[0081] S505: Using the same process, form a gate connection structure and a gate pad on the side of the third dielectric layer away from the substrate, where the gate connection structure is electrically connected to the gate and the gate pad is electrically connected to the gate.

[0082] For example, the gate connection structure 140 may be disposed in the same layer as the gate pad 170 and formed in the same process, which on the one hand simplifies the process flow, avoids the deposition of unnecessary film layers, and simplifies the mask process, and on the other hand is advantageous for designing a thin and lightweight semiconductor device.

[0083] Note that, when the gate connection structure and the gate pad are disposed on the same layer and formed by the same process, the gate connection structure and the gate may be connected in either the non-active region or the active region. The embodiments of the present application are not limited thereto. FIG. 13 illustrates an example in which the gate connection structure 140 and the gate 130 are connected in the non-active region bb. In this case, the gate 130 includes a first gate sub-portion 1301 and a second gate sub-portion 1302 connected to each other, and the second gate sub-portion 1302 is located in the non-active region bb. Correspondingly, the gate connection structure 140 includes a first gate sub-connection portion 1401 and a second gate sub-connection portion 1402 connected to each other, and the second gate sub-connection portion 1402 is located in the non-active region bb. The second gate sub-connection portion 1402 is electrically connected to the second gate sub-portion 1302 in the non-active region bb through a fourth connection via K4.

[0084] It should be noted that the gate connection structure and the gate pad may be disposed on the same layer and formed by the same process, and may use the same material. In Fig. 13, to distinguish between the gate connection structure and the gate pad, different fillers are used for the gate connection structure and the gate pad, but this is not to limit the materials but only to distinguish different results.

[0085] It should be noted that the third dielectric layer in the embodiments of the present application may refer to a single dielectric layer or multiple dielectric layers, and the embodiments of the present application are not limited thereto. In summary, the manufacturing method according to the embodiment of the present application forms the gate connection structure and the gate pad using the same process, which on the one hand simplifies the process flow, avoids the installation of unnecessary film layers, and simplifies the mask process, and on the other hand is advantageous for designing a thinner and lighter semiconductor device.

[0086] 13 and 14, the semiconductor device 10 includes an active area aa and a non-active area bb surrounding the active area aa. The fourth connection via K4 and the fifth connection via K5 are located in the non-active areas bb on opposite sides of the active area aa, respectively. This simplifies the connection relationship between the gate 130 and the gate pad 170 and the gate connection structure 140, and avoids the complicated formation process of the connection vias when they are connected to the same side.

[0087] FIG. 15 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present application, and FIG. 16 is another schematic diagram of the semiconductor device shown in FIG. 13 along CC'. As shown in FIGS. 15 and 16, the manufacturing method according to an embodiment of the present application includes the following steps:

[0088] S601: Provide a substrate.

[0089] S602: Form an epitaxial structure on one side of the substrate.

[0090] S603: Form a gate on the side of the epitaxial structure away from the substrate.

[0091] S604: Form a fourth dielectric layer on the side of the gate away from the substrate.

[0092] For example, a fourth dielectric layer 240 can be formed on the side of the gate 130 away from the substrate 110, and the fourth dielectric layer 240 can cover the gate 130. Furthermore, a sixth connecting via K6 can also be formed in the fourth dielectric layer 240, exposing a part of the gate 130 through the sixth connecting via K6, and then making it easier for the gate connecting structure 140 to be electrically connected to the gate 130 through the sixth connecting via K6.

[0093] Additionally, the fourth dielectric layer 240 may be materials such as silicon dioxide, silicon nitride, and aluminum oxide. Methods for forming the fourth dielectric layer 240 include physical vapor deposition and / or chemical vapor deposition. S605: Form a gate contact structure on the side of the fourth dielectric layer away from the substrate, where the gate contact structure is electrically connected to the gate.

[0094] For example, a gate connection structure 140 is formed on the side of the fourth dielectric layer 240 away from the substrate 110, and the gate connection structure 140 is electrically connected to the gate 130 through the sixth connection via K6, thereby achieving the purpose of reducing the gate resistance, reducing leakage current, and improving the performance of the semiconductor device.

[0095] It should be noted that the fourth dielectric layer in the embodiments of the present application may refer to a single dielectric layer or a plurality of dielectric layers, and the embodiments of the present application are not limited thereto.

[0096] In summary, the manufacturing method according to the embodiment of the present application enables the gate connection structure to be formed individually, thereby reducing the limitations on the film layer and process of the gate connection structure, improving the freedom in forming the gate connection structure, reducing the difficulty in forming the gate connection structure, and improving manufacturing efficiency.

[0097] Based on the above embodiment, and still referring to FIG. 13 , along the thickness direction of the semiconductor device, the gate 130 at least partially overlaps with the gate connecting structure 140, thereby reducing the area of ​​the semiconductor device along the second direction X and realizing a miniaturized design of the semiconductor device.

[0098] 3 , 4 , 5 , 7 , 10 , and 13 , the manufacturing method according to the embodiment of the present application may also include a step of forming a drain 180 and a drain pad 190, and the drain 180 and the drain pad 190 are electrically connected in the non-active region bb, facilitating the provision of a drain signal to the drain 180 via the drain pad 190. Furthermore, since the drain 180 may be formed in the same process and disposed in the same layer as the source 150, the drain pad 190 may be formed in the same process and disposed in the same layer as the gate pad 170, thereby simplifying the manufacturing process of the semiconductor device and ensuring the simplification of the deposition of film layers.

[0099] Optionally, Figure 17 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present application. As shown in Figure 17, the method for manufacturing a semiconductor device includes the following steps:

[0100] S701: Provide a substrate.

[0101] S702: Form a nucleation layer on one side of the substrate.

[0102] For example, with continued reference to Figures 8, 11, 14 and 16, nucleation layer 1201 may be an aluminum nitride material and is located between substrate 110 and buffer layer 1202 to serve as an adhesive for the subsequently grown semiconductor material layer.

[0103] S1003: A buffer layer is formed on the side of the nucleation layer away from the substrate.

[0104] For example, with continued reference to Figures 8, 11, 14, and 16, a buffer layer 1202 is located on the side of the nucleation layer away from the substrate 110, and the material of the buffer layer 1202 is gallium nitride, and the buffer layer 1202 may contain iron atoms, thereby achieving high resistivity characteristics of the buffer layer 1202, preventing vertical leakage current, and improving pinch-off performance of the semiconductor device.

[0105] S704: A channel layer is formed on one side of the buffer layer away from the substrate.

[0106] For example, with continued reference to FIGS. 8, 11, 14, and 16, the channel layer 1203 may be made of a Group III nitride, such as Al. x Ga 1-x N (where 0≦x<1), i.e., at the interface between the channel layer 1203 and the barrier layer 1204, the conduction band energy of the channel layer 1203 is less than the conduction band energy of the barrier layer 1204. For example, x=0 indicates that the channel layer 1203 is GaN. The channel layer 1203 may also be InGaN or other III-nitrides such as AlInGaN. The channel layer 1203 may be undoped or unintentionally doped. The channel layer 1203 may also be a multi-layer structure, such as a superlattice, a combination of GaN, or AlGaN.

[0107] S705: A barrier layer is formed on the side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure.

[0108] For example, with continued reference to Figures 8, 11, 14, and 16, the barrier layer 1204 may be AlN, AlInN, AlGaN, or AlInGaN. The barrier layer 1204 may be thick enough and have a high enough Al content to provide significant carrier concentration by doping the interface between the channel layer 1203 and the barrier layer 1204. For example, the barrier layer 1204 may be 20 nm thick and have a doping concentration of 25% Al.

[0109] 8, 11, 14, and 16, the channel layer 1203 may include GaN and the barrier layer 1204 may include AlGaN, i.e., the material of the barrier layer 1204 may have a higher bandgap than the material of the channel layer 1203, and the channel layer 1204 may have a greater electron affinity than the barrier layer 1204. Due to the bandgap difference between the barrier layer 1204 and the channel layer 1203 and the piezoelectric effect at the interface between the barrier layer 1204 and the channel layer 1203, a two-dimensional electron gas (2DEG) may be formed in the channel layer 1203 and the barrier layer 1204.

[0110] It can be understood that the epitaxial structure further includes a cap layer, the cap layer being located on a surface of the barrier layer away from the substrate, which can reduce surface states, reduce surface leakage current in subsequent semiconductor devices, and suppress current collapse, thereby improving the performance and reliability of the epitaxial structure and semiconductor devices.

[0111] S706: Forming gates and gate connection structures on the side of the epitaxial structure away from the substrate, the gate connection structures electrically connecting to at least some of the gates.

[0112] The method for fabricating a semiconductor device according to the present invention can ensure the complete formation of an epitaxial structure of a semiconductor device by forming a nucleation layer, a buffer layer, a channel layer, and a barrier layer on one side of a substrate, respectively, and further forming a gate connection structure on the side of the gate away from the substrate, where the gate connection structure is electrically connected to at least a portion of the gate, thereby reducing the effect of gate resistance, improving gain, maintaining an optimized gate electric field, and reducing leakage current.

[0113] It should be noted that the above is merely a preferred embodiment of the present application and the technical principles applied thereto. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious modifications, adjustments, and substitutions are possible without departing from the scope of protection of the present application. Therefore, although the present application has been described in detail through the above embodiments, it is not limited to the above embodiments, and many other equivalent embodiments can be included within the scope of the present application. The scope of the present application is determined by the appended claims.

Claims

1. 1. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming an epitaxial structure on one side of the substrate; forming a gate and a gate connection structure on a side of the epitaxial structure remote from the substrate, the gate connection structure electrically connecting to at least some of the gates.

2. forming a gate and a gate contact structure on a side of the epitaxial structure away from the substrate, 2. The method of claim 1, comprising forming the gate and the gate connection structure on a side of the epitaxial structure away from the substrate using the same process, wherein the gate connection structure comprises a first gate sub-connection and a second gate sub-connection connected to each other, wherein the first gate sub-connection does not overlap the gate and the second gate sub-connection is electrically connected to the gate along a thickness direction of the semiconductor device.

3. prior to forming a gate and gate contact structure on a side of the epitaxial structure remote from the substrate; forming a source on a side of the epitaxial structure away from the substrate; 3. The method of claim 2, wherein the first gate sub-connection overlaps the source and is insulated along the thickness direction of the semiconductor device, or the first gate sub-connection is located on the side of the source remote from the gate.

4. the semiconductor device includes an active region and a non-active region surrounding the active region; the second gate sub-connection is located in the active region; Alternatively, the method of claim 2 or 3, wherein the gate includes a first gate sub-portion and a second gate sub-portion connected to each other, the second gate sub-portion being located in the non-active region, the second gate sub-connection being located in the non-active region, and the second gate sub-connection being electrically connected to the second gate sub-portion.

5. forming a gate and a gate contact structure on a side of the epitaxial structure away from the substrate, forming a source and a gate on a side of the epitaxial structure away from the substrate; forming a first dielectric layer on a side of the gate remote from the substrate; and forming the gate connection structure and the source field plate on a side of the first dielectric layer away from the substrate using the same process, the gate connection structure being electrically connected to the gate and the source field plate being electrically connected to the source.

6. forming a first dielectric layer on a side of the gate remote from the substrate; 6. The method of claim 5, further comprising: forming a first connection via and a second connection via in the first dielectric layer using the same process, wherein the first connection via exposes a portion of the gate and the second connection via exposes a portion of the source, the gate connection structure being electrically connected to the gate through the first connection via, and the source field plate being electrically connected to the source through the second connection via.

7. the source field plate includes a field plate body and a field plate connection portion, the field plate connection portion being electrically connected to the source through the second connection via; the gate connection structure includes a first gate sub-connection portion and a second gate sub-connection portion connected to each other, the second gate sub-connection portion being electrically connected to the gate through the first connection via; 7. The method of claim 6, wherein the field plate connection is offset from the first connection via and the second gate sub-connection is offset from the second connection via.

8. the thickness of the gate contact structure is greater than the thickness of the first dielectric layer; 8. The method according to claim 5, wherein the thickness of the source field plate is greater than the thickness of the first dielectric layer.

9. the semiconductor device includes an active region and a non-active region surrounding the active region; the source field plate includes a field plate body and a field plate connection portion connected to each other, the field plate connection portion being electrically connected to the source; 9. The method according to claim 5, wherein the gate connection structure includes a first gate sub-connection and a second gate sub-connection connected to each other, and the second gate sub-connection is electrically connected to the gate.

10. the semiconductor device includes an active region and a non-active region surrounding the active region; forming a gate and a gate contact structure on a side of the epitaxial structure away from the substrate, forming a source and the gate connection structure on a side of the epitaxial structure away from the substrate using the same process, the gate connection structure including a first gate sub-connection and a second gate sub-connection connected to each other, the second gate sub-connection being located in the non-active region; forming a second dielectric layer on a side of the source and gate connection structures away from the substrate; 2. The method of claim 1, further comprising forming the gate on a side of the second dielectric layer away from the substrate, the gate including a first gate sub-portion and a second gate sub-portion connected to each other, the second gate sub-portion located in the non-active region, and the second gate sub-portion electrically connected to the second gate sub-connection.

11. forming a gate and a gate contact structure on a side of the epitaxial structure away from the substrate, forming the gate on a side of the epitaxial structure away from the substrate; forming a third dielectric layer on a side of the gate remote from the substrate; 2. The method of claim 1, further comprising: forming the gate connection structure and a gate pad on a side of the third dielectric layer away from the substrate using the same process, wherein the gate connection structure is electrically connected to the gate and the gate pad is electrically connected to the gate.

12. forming a third dielectric layer on a side of the gate remote from the substrate; 12. The method of claim 11, further comprising forming a fourth connection via and a fifth connection via in the third dielectric layer, wherein the fourth connection via and the fifth connection via both expose a portion of the gate, the gate connection structure is electrically connected to the gate through the fourth connection via, and the gate pad is electrically connected to the gate through the fifth connection via.

13. forming a gate and a gate connection structure on a side of the epitaxial structure away from the substrate, forming the gate on a side of the epitaxial structure away from the substrate; forming a fourth dielectric layer on a side of the gate remote from the substrate; 2. The method of claim 1, further comprising forming the gate connection structure on a side of the fourth dielectric layer away from the substrate, the gate connection structure being electrically connected to the gate.

14. forming a fourth dielectric layer on a side of the gate remote from the substrate; 14. The method of claim 13, further comprising forming a sixth connection via in the fourth dielectric layer, the sixth connection via exposing a portion of the gate, and the gate connection structure electrically connecting to the gate through the sixth connection via.

15. 15. The method of claim 13 or 14, wherein the gate at least partially overlaps the gate connection structure along the thickness of the semiconductor device.

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