Semiconductor device and manufacturing method thereof

Abstract

An embodiment of the present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a field plate body and at least one field plate end extending into a passive region. The extension width of the first field plate end and / or second field plate end located at least in the passive region is greater than the extension width of the field plate body, contributing to improved reliability and stability of the field plate. Furthermore, ensuring a certain distance between the active region and the first field plate end and / or the first boundary point of the field plate end adjusts the distribution of the electric field near the boundary gate of the active region and reduces gate-source capacitance issues. The difference in extension width between the field plate end and the field plate body satisfies a certain relationship, reducing stress between the structures and improving chip reliability and stability.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to the field of semiconductor technology, and more particularly to semiconductor devices and methods for fabricating the same. [Background technology]

[0002] Gallium nitride (GaN) as a semiconductor material has characteristics such as a wide band gap, high electron mobility, high dielectric breakdown field strength, and excellent thermal conductivity. In addition, it has strong spontaneous and piezoelectric polarization effects, making it more suitable for the manufacture of high-frequency, high-voltage, and high-temperature resistant high-power electronic devices than first- and second-generation semiconductor materials, and it shows significant advantages particularly in the high-frequency and power supply areas.

[0003] Currently, 5G communications require high bandwidth and high frequency for semiconductor devices, and the gate structure design and manufacturing process are highly dependent on the frequency characteristics of the semiconductor device, with the gate size directly affecting the operating frequency of the semiconductor device, and the gate position and the relationship with adjacent components directly affecting the performance and reliability of the device. Therefore, during the design and manufacturing process of semiconductor devices, the gate design is particularly important and plays an important role in the reliability and stability of the operating performance of the semiconductor device.

[0004] Therefore, further improving the reliability of semiconductor gates, realizing gate designs that stabilize the performance of semiconductor devices, and enabling large-scale commercial production and manufacturing are problems that need to be solved. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, embodiments of the present invention provide a semiconductor device and a manufacturing method thereof, and provide a semiconductor device with high gate reliability and stable performance, which can be applied to fields such as RF, microwave, and power electronics. [Means for solving the problem]

[0006] In a first aspect, an embodiment of the present invention provides a semiconductor device including an active region and a passive region surrounding the active region. The semiconductor device further includes a substrate, a multilayer semiconductor layer located on one side of the substrate, a source and a drain located on one side of the multilayer semiconductor layer away from the substrate, a gate located between the source and the drain, and a field plate located between the source and the drain. The field plate includes a field plate body and a field plate end portion along a first direction. At least one of the field plate end portions extends into the passive region. The first direction is parallel to the direction in which the source, the gate, and the drain extend. The extension width of the field plate body portion in the second direction is maintained constant. At least one of the field plate end portions extends from the field plate body portion toward the gate along the second direction. The extension width of at least one of the field plate end portions in the second direction is greater than the extension width of the field plate body portion. The second direction is parallel to the direction from the source to the drain.

[0007] Optionally, the field plate edges contact the source, the gate and the drain, respectively, with zero contact.

[0008] Optionally, in the second direction, within the passive region, a projection of the field plate end onto the substrate partially overlaps a projection of the gate onto the substrate, and a projection of the field plate end onto the substrate does not overlap a projection of the source onto the substrate.

[0009] Optionally, the field plate end includes a first boundary line and a second boundary line along a first direction, the second boundary line being located on one side of the first boundary line away from the active region, and the first boundary line and the second boundary line of at least one of the field plate ends being located within the passive region.

[0010] Optionally, the distance between the first boundary line of at least one of the field plate edges and the adjacent active area is d, where d≦5 μm.

[0011] Optionally, the field plate edge includes a first field plate edge and a second field plate edge, the distance between the first boundary line of the first field plate edge and the adjacent active area is d1, and the distance between the first boundary line of the second field plate edge and the adjacent active area is d2, where d1=d2.

[0012] Optionally, the gate further includes a first gate end, a middle gate portion, and a second gate end, the first gate end and / or the second gate end being located within the passive region, and the second boundary line of the field plate end being located between the adjacent first gate end and / or the adjacent second gate end and the active region.

[0013] Optionally, the second boundary line of the field plate end is located on one side of a dividing line between the adjacent first end and / or second end of the gate and the intermediate portion, closer to the active region.

[0014] Optionally, the distance between the boundary line between the first gate end and / or the second gate end and the intermediate portion and the second boundary line of the adjacent field plate end is b, where b<3 um.

[0015] Optionally, the field plate edges include a first field plate edge and a second field plate edge. A distance b1 is between the second boundary line of the first field plate edge and a line separating the adjacent first gate edge and the intermediate portion. A distance b2 is between the second boundary line of the second field plate edge and a line separating the adjacent second gate edge and the intermediate portion, where b1=b2.

[0016] Optionally, the difference between the width of the field plate edge extending to the gate and the extension width of the field plate body is L, where L≧0.5*D.

[0017] Optionally, the field plate edge further includes an extended termination line located on one side of the gate away from the field plate.

[0018] Optionally, the field plate further includes a field plate connection portion located in the active region and extending from the field plate body to the source until it contacts the source, and the field plate body portion, field plate end portion, and field plate connection portion are integrally molded.

[0019] As a second aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor device. The method includes providing a substrate, fabricating a multilayer semiconductor layer on one side of the substrate, fabricating a source, a drain, and a gate located between the source and the drain on one side of the multilayer semiconductor layer away from the substrate, fabricating a medium layer on one side of the gate away from the substrate, and fabricating a field plate near the gate on one side of the medium layer away from the substrate. The field plate includes a field plate body and at least one field plate end extending into a passive region. The field plate end extends from the field plate body portion toward the gate, and the extension width of the field plate end is greater than the extension width of the field plate body portion.

[0020] Optionally, a portion of the source is exposed before fabricating the field plate and the field plate structure is integrally formed in the same fabrication process.

[0021] In a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention, the extension width of the first field plate edge and / or the second field plate edge located at least in the passive region is made larger than the extension width of the field plate body, thereby improving the reliability and stability of the field plate. By ensuring a certain distance between the active region and the first field plate edge and / or the first boundary point of the field plate edge and by ensuring a certain relationship between the extension widths of the field plate edge and the field plate body, the electric field distribution near the boundary gate of the active region is adjusted while reducing gate-source capacitance issues. Furthermore, by ensuring a certain relationship between the extension widths of the field plate edge and the field plate body, stress between the structures is reduced, thereby improving the reliability and stability of the chip. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a structural schematic diagram of a semiconductor device according to an embodiment of the present invention, seen from above; [Figure 2] 1 is a structural schematic diagram of a semiconductor device according to an embodiment of the present invention, seen from above; [Figure 3] FIG. 10 is a structural schematic diagram of another semiconductor device according to an embodiment of the present invention, as viewed from above. [Figure 4] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention will be described in more detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are merely for the purpose of understanding the present invention and are not intended to limit the present invention. For the sake of convenience, the drawings show only a portion related to the present invention, and not all of the structures.

[0024] The technical solutions in the embodiments of the present invention are clearly and fully described with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments that can be obtained by those skilled in the art based on the embodiments of the present invention without requiring creative efforts are encompassed in the protection scope of the present invention.

[0025] FIG. 1 is a structural schematic diagram of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 20 according to the embodiment of the present invention includes an active region aa and a passive region bb surrounding the active region aa. The semiconductor device 20 further includes a substrate 21, a multilayer semiconductor layer 22 located on one side of the substrate 21, a source 23 and a drain 25 located on one side of the multilayer semiconductor layer 22 away from the substrate 21, a gate 24 located between the source 23 and the drain 25, a field plate 26 located between the source 23 and the drain 25, and a medium layer 27 located on the one side of the multilayer semiconductor layer 22 away from the substrate 21 and between the gate 24 and the field plate 26. The field plate 26 includes a field plate body 260 and at least one field plate end 261 extending along a first direction (the X direction shown in the figure) toward the passive region bb. In the second direction (the Y direction in the figure), the extension width of the field plate main body 260 in the second direction is kept constant and maintained at a fixed value D. The field plate in the embodiment of the present invention includes at least one field plate end portion extending into the passive region. An example will be described in which the field plate end portion 261 of the present invention is the first field plate end portion 261. The field plate end portion 261 extends from the field plate main body portion 260 toward the gate 24, and has an extension width greater than the extension width D of the field plate main body portion 260. The field plate end portion 261 makes zero-touch contact with the source 23, gate 24, and drain 25, respectively. This structural design can improve the reliability and stability of the field plate 26. Note that zero-touch contact means that the field plate end portion 261 does not directly contact any of the source 23, gate 24, and drain 25 electrodes, but may be isolated by a medium layer or may be spaced apart by a certain distance.

[0026] Alternatively, the substrate 21 may be made of one or more of the following materials: silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, diamond, or other materials suitable for gallium nitride growth.

[0027] The multilayer semiconductor layer 22 is located on one side of the substrate 21 and may be made of a III-V compound semiconductor material, such as one or more of gallium arsenide, aluminum gallium arsenide, gallium nitride, aluminum gallium nitride, or indium gallium nitride. The active region aa may be understood as the active operating region of the semiconductor device, below which there is a two-dimensional electron gas, electron, or hole region, whose operating state and characteristics are affected by an external circuit.

[0028] For example, as shown in FIG. 1 , the source 23, gate 24, and drain 25 extend along the first direction and are arranged along the second direction. The source 23 and drain 25 are both located within the active region aa. The gate 24 includes a portion located within the active region aa and a portion located within the passive region bb. In the second direction, the projection of the field plate end 261 onto the substrate 21 partially overlaps with the projection of the gate 24 onto the substrate 21 within the passive region bb, while the projection of the field plate end 261 onto the substrate 21 does not overlap with the projection of the source 23 onto the substrate 21. This optimizes the distribution of the electric field near the gate 24 at the boundary between the active and passive regions. Although the projection of the field plate end 261 onto the substrate 21 partially overlaps with the projection of the gate 24 onto the substrate 21 within the passive region bb, the medium layer 27 is provided between the field plate end 261 and the gate 24, preventing contact between the field plate end 261 and the gate 24.

[0029] Specifically, as shown in FIG. 1 , the field plate 26 includes a first field plate end 261, a field plate main body 260, and a second field plate end 262, arranged sequentially along the first direction. At least a majority of the field plate main body 260 is located within the active region aa, and its extension width in the second direction is maintained constant at a fixed value D. If at least one of the first field plate end 261 and the second field plate end 262 satisfies the above requirements, the reliability of the field plate and the distribution of the electric field at the edge of the active region can be improved. Preferably, the first field plate end 261 and the second field plate end 262 are respectively located at both ends of the field plate along the first direction, extending toward the gate 24 and having an extension width greater than the extension width D of the field plate main body 260, thereby contributing to ensuring stable radio frequency characteristics of the semiconductor device.

[0030] Furthermore, as shown in FIG. 1 , the field plate end includes a first boundary line and a second boundary line along a first direction. The second boundary line is located on one side of the first boundary line away from the active region. Exemplarily, the first field plate end 261 includes a first boundary line 2611 and a second boundary line 2612. The second boundary line 2612 is located on one side of the first boundary line 2611 away from the active region aa. Preferably, the first boundary line 2611 and the second boundary line 2612 of the first field plate end 261 are both located within the passive region bb, which can adjust the distribution of the electric field near the active region in the passive region and reduce the influence of the passive region on the active region, thereby reducing the occurrence of dielectric breakdown. Specifically, as shown in FIG. 1 , the second field plate end 262 includes a first boundary line 2613 and a second boundary line 2614. The second boundary line 2614 of the second field plate end 262 is located on one side of the first boundary line 2613 away from the active region aa. Furthermore, by arranging the first boundary line 2611 and the second boundary line 2612 of the first field plate end 261 so that they are both located within the passive region bb, and by arranging the first boundary line 2613 and the second boundary line 2614 of the second field plate end 262 so that they are both located within the passive region bb, this contributes to further ensuring the stability of the radio frequency characteristics of the semiconductor device.

[0031] Further research has revealed that the field plate edge includes a first boundary line and a second boundary line along a first direction, with the second boundary line located on one side of the first boundary line away from the active region. The distance between the first boundary line of at least one field plate edge and the adjacent active region aa is d. If d is 5 μm or less, an increase in the gate-source capacitance of the device can be avoided. Furthermore, if d≦3 μm, the gate-source capacitance can be further reduced. For example, d may be 0.5 μm, 1 μm, 2 μm, 2.5 μm, etc. Preferably, if d is within the range of 0.2 μm to 2 μm, the distribution of the boundary electric field in the active region can be effectively adjusted, the gate-source capacitance of the semiconductor device can be minimized, and the stability of the device performance can be improved.

[0032] Specifically, the distance between the first boundary 2611 of the first field plate end 261 and the adjacent active area aa is d1. When d1≦5 μm, preferably d1≦3 μm, the gate-source capacitance of the device on one side of the active area can be reduced and the distribution of the electric field at the boundary gate of the corresponding active area can be adjusted. Furthermore, to improve the reliability of the active area of ​​the entire chip, the distance between the first boundary 2611 of the first field plate end 261 and the adjacent active area aa must be ensured, and the distance between the first boundary 2613 of the second field plate end 262 and the adjacent active area aa must be d2, and d2≦5 μm. Note that d1 and d2 only need to satisfy the requirements d1≦5 μm and d2≦5 μm. While the values ​​of d1 and d2 may be different, to ensure chip reliability and stable radio frequency characteristics, satisfying d1≦5 μm and d2≦5 μm and setting d1=d2 improves the reliability and stability of the entire device.

[0033] 1 , field plate 26 further includes field plate connection portion 263, which is located in the active region and extends from field plate main body portion 260 to source 23 until it contacts source 23. The projection of field plate connection portion 263 onto substrate 21 overlaps the projection of source 23 onto substrate 21. In the present invention, field plate connection portion 263 differs in position and function from field plate end portion 261, and its main role is to electrically connect the field plate to source 23. Furthermore, because field plate connection portion 263 and field plate end portion 261 have different positions and roles, field plate main body portion 260, field plate end portion 261, and field plate connection portion 263 of field plate 26 can be completed in the same manufacturing process. Integrating field plate main body portion 260, field plate end portion 261, and field plate connection portion 263 reduces process complexity and avoids the need to drill holes to connect field plate 26 to source 23.

[0034] In summary, in the semiconductor device according to the embodiment of the present invention, the extension width of the first field plate end and / or second field plate end located at least in the passive region is made larger than the extension width of the field plate body, and a certain distance is maintained between the active region and the first field plate end and / or the first boundary location of the field plate end. This adjusts the electric field distribution near the boundary gate of the active region and reduces gate-source capacitance issues, further improving the reliability and stability of the chip.

[0035] In another embodiment, as shown in FIG. 2 , a semiconductor device 20 according to an embodiment of the present invention includes a field plate end 261. The field plate end 261 further includes an extension end line 2610 extending to the gate. Preferably, the distance between the extension end line 2610 of the field plate end 261 and the field plate main body 260 is L, or the difference between the width of the field plate end 261 extending to the gate and the extension width of the field plate main body 260 is L. Furthermore, if the difference in the extension widths of the field plate end 261 and the field plate main body 260 satisfies L≧0.5*D, the structural stability and reliability of the field plate passive region can be effectively improved. Furthermore, if the difference in the extension widths of the field plate end 261 and the field plate main body 260 satisfies L≦10*D, the gate-source capacitance problem can be further reduced, improving the reliability and stability of the chip. Here, D is the extension width of the field plate main body 260. For example, the difference L in the extension width between field plate end 261 and field plate body 260 may be D, 1.5*D, 2*D, 2.5*D, 3*D, 3.5*D, 4*D, 4.5*D, 5*D, 6*D, etc. Although no specific numerical values ​​are given in the embodiments of the present invention, ensuring that 0.5*D≦L≦10*D is satisfied not only improves the reliability of the passive region of the field plate but also further reduces the gate-source capacitance problem, thereby improving the reliability and stability of the chip.

[0036] Based on the above embodiment, as shown in FIG. 2, the relative position of the field plate 26 and the gate 24 varies depending on the device structure. Therefore, the extension width and relative position of the field plate body 260 to the gate 24 also vary depending on the device. For example, the field plate 26 is located between the drain 25 and the source 23 along the second direction (the Y direction in the figure). The body 260 of the field plate 26 is located between the drain 25 and the boundary of the gate 24 closer to the source 23. The projection of the body of the field plate 26 onto the substrate 21 may or may not overlap with the projection of the gate 24 onto the substrate 21. Therefore, in the second direction (the Y direction in the figure), the end line of the field plate end 261 is positioned on one side of the gate 24 away from the field plate 26, ensuring that the field plate end 261 completely covers the gate 24 in the second direction. This adjusts the electric field distribution around the gate in the passive region close to the active region from multiple directions. Specifically, the end line of first field plate edge 261 is 2610, and the end line of second field plate edge 262 is 2620. It is only necessary to ensure that at least one of end line 2610 of first field plate edge 261 and / or end line 2620 of second field plate edge 262 completely covers gate 24 in the second direction. Preferably, end line 2610 of first field plate edge 261 and end line 2620 of second field plate edge 262 are located on one side of gate 24 away from field plate 26, which contributes to comprehensive and sufficient adjustment of the electric field around the gate in passive regions on both sides of the active region, and also improves the stability and reliability of the field plates.

[0037] Further research has revealed that the end line of field plate end 261 must be located on one side of gate 24 away from field plate 26 and on one side of source 23 closer to gate 24. This configuration prevents stress issues caused by process errors during the field plate manufacturing process, particularly in a process structure in which field plate body 260, field plate end 261, and field plate connection portion 263 are integrally molded, between the passive region field plate end and the source. Specifically, as shown in FIG. 2 , the end line of first field plate end 261 must be located at 2610, on one side of gate 24 away from field plate 26, and on one side of source 23 closer to gate 24. Furthermore, to ensure chip reliability and stable radio frequency characteristics, the end line of second field plate end 262 must be located at 2620, on one side of gate 24 away from field plate 26 and on one side of source 23 closer to gate 24.

[0038] In the above-described embodiment of the present invention, the difference in the extension width between field plate end 261 and field plate body 260 satisfies a certain relationship, thereby improving the reliability and stability of the field plate in the passive region and reducing capacitance issues between the gate and source. Furthermore, since the relative positions of field plate 26 and gate 24 are different, the end line of field plate end 261 is positioned on one side of gate 24 away from field plate 26 and one side of source 23 closer to gate 24, thereby preventing stress issues in the passive region field plate end and the surrounding structure of the source during the field plate manufacturing process. The shapes of first field plate end 261 and second field plate end 262 may be the same or different, but this is not a limitation in the embodiment of the present invention.

[0039] As shown in FIG. 3 , in another embodiment of the present invention, the gate 24 further includes a first end 241, an intermediate portion 242, and a second end 243 along the first direction. A majority of the gate intermediate portion 242 is located within the active region aa. The first end 241 and / or the second end 243 are located within the passive region bb. A small portion of the gate intermediate portion 242 is located within the passive region. The extension width of at least the first end 241 and the second end 243 in the second direction, which are located within the passive region bb, is set to be larger than the extension width of the gate intermediate portion 242 in the second direction. Furthermore, the boundary line 2411 between the first end 241 and the gate intermediate portion 242 and / or the boundary line 2412 between the second end 243 and the gate intermediate portion 242 are located within the passive region. This contributes to adjusting the electric field distribution near the source corner and reduces the occurrence of dielectric breakdown.

[0040] Furthermore, the gate first end 241 and / or gate second end 243 are located within the passive region bb. The second boundary line of the field plate end 261 is located between the adjacent gate first end 241 and / or gate second end 243 and the active region aa. Alternatively, the boundary line extending along the first direction of the field plate 26 into the passive region bb is located between the active region aa and the gate first end 241. Note that the second boundary line of the field plate end 261 being located between the adjacent gate first end 241 and / or gate second end 243 and the active region aa may mean that the second boundary line of the field plate end 261 is located at any position between the boundary of the gate first end 241 and / or gate second end 243 and the active region. That is, the projection of the field plate end 261 onto the substrate may overlap the projection of the gate first end 241 and / or the gate second end 243 onto the substrate, or the projection of the field plate end 261 onto the substrate may overlap the projection of the middle portion 242 onto the substrate. Preferably, to increase the ease of industrial manufacturing, the second boundary line of the field plate end 261 is located on one side of the dividing line 2411 between the first end 241 and the middle portion 242, closer to the active region aa. This design contributes to improving the distribution of the electric field near the gate 24, which is closer to the active region aa, within the passive region bb. Optionally, in the first direction (the X direction shown in the figure), the field plate 26 extends from within the active region aa toward the gate second end 243 into the passive region bb. That is, both boundary lines of the field plate 26 on both sides of the active area are located within the passive area bb, on one side closer to the active area of ​​the dividing line between the first gate end 241 and / or the second gate end 243 and the intermediate portion, which contributes to improving the distribution of the electric field at the edge of the entire active area and improves the reliability and stability of the chip.

[0041] Further research has revealed the following. As shown in FIG. 3 , the distance b between the boundary line 2411 between the first end 241 and the middle portion 242 of the gate 24 and / or the boundary line 2412 between the second end 243 and the middle portion 242 and the second boundary line of the adjacent field plate edge is set to be less than 3 μm, thereby improving the electric field distribution at the gate edge and reducing electrical resistance. For example, b may be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, etc. By setting the distance b1 between the second boundary line 2612 of the first field plate edge 261 and the boundary line 2411 between the first end 241 and the middle portion 242 of the gate to be less than 3 μm, the electric field distribution near the first end 241 of the gate can be improved. Optionally, the distance b2 between the second boundary line 2614 of the second field plate edge 262 and the boundary line 2412 between the second end 243 and the middle portion 242 of the gate can be set to be less than 3 μm. Note that b1 and b2 only need to satisfy the relationship b1<3 μm and b2<3 μm. While the values ​​of b1 and b2 may differ, it is preferable that b1<3 μm and b2<3 μm and that b1=b2 in order to improve the reliability of the entire chip and the stability of its radio frequency characteristics. Preferably, the distance between the demarcation line 2411 between the first end 241 and the middle portion 242 of the gate 24 and / or the demarcation line 2412 between the second end 243 and the middle portion 242 and the second boundary line of the adjacent field plate end is within the range of 0.1 μm to 1.5 μm, which can more effectively improve the electric field distribution at the first end and enhance the reliability and stability of the chip.

[0042] In an embodiment of the present invention, the shape of the field plate end may optionally include at least one of a rectangle, a hammerhead shape, a circle, a semicircle, a bulb shape, a T shape, and an L shape, but is not limited to these in an embodiment of the present invention.

[0043] Alternatively, the multilayer semiconductor layer 22 according to an embodiment of the present invention may specifically include a nucleation layer 221 disposed on the substrate 10, a buffer layer 222 disposed on one side of the nucleation layer 221 away from the substrate 21, a channel layer 223 disposed on one side of the buffer layer 222 away from the nucleation layer 221, and a barrier layer 224 disposed on one side of the channel layer 223 away from the buffer layer 222. The barrier layer 224 and the channel layer 223 form a heterojunction structure, and a two-dimensional electron gas (2DEG) is formed at the heterojunction interface. The multilayer semiconductor layer 22 may further include a cap layer disposed on one side of the barrier layer away from the substrate 21. The source 23, the gate 24, and the drain 25 are disposed on one side of the semiconductor layer away from the substrate 21. The field plate 26 is disposed near the gate 24 and on one side away from the substrate 21. A medium layer 27 may further be disposed between the field plate 26 and the gate 24. The side of the field plate 26 facing away from the substrate 21 may further include a passivation layer 28 .

[0044] For example, the materials of the nucleation layer 221 and the buffer layer 222 may be nitrides, specifically GaN, AlN, or other nitrides. The nucleation layer 221 and the buffer layer 222 are compatible with the material of the substrate 10 and the epitaxial channel layer 223. The material of the channel layer 223 may be GaN or other semiconductor materials, such as InAlN. The barrier layer 224 is located above the channel layer 223. The material of the barrier layer 224 can form a heterojunction structure with the channel layer 223 and may be any semiconductor material, including gallium-based compound semiconductor materials or nitride semiconductor materials, such as InxAlyGazN1-xyz, where 0≦x≦1, 0≦y≦1, and 0≦z≦1. Optionally, the channel layer 223 and the barrier layer 224 form a semiconductor heterojunction structure, and a high concentration of two-dimensional electron gas is formed at the interface between the channel layer 223 and the barrier layer 224.

[0045] The gallium nitride RF device formed by the semiconductor device structure of the present invention improves the power and frequency of the gallium nitride RF device, maintaining device reliability while maintaining stable performance of the semiconductor device, making it more applicable to the high-frequency 5G communication area.

[0046] The embodiment of the present invention improves the output power of the semiconductor device by adjusting the structural design of the semiconductor device. The semiconductor device may include, but is not limited to, a high-power gallium nitride high electron mobility transistor (HEMT) that operates under a high voltage and high current environment, a silicon-on-insulator (SOI) transistor, a gallium arsenide (GaAs)-based transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-semiconductor field-effect transistor (MISFET), a double heterojunction field-effect transistor (DHFET), a junction field-effect transistor (JFET), a metal-semiconductor field-effect transistor (MESFET), a metal-semiconductor heterojunction field-effect transistor (MISHFET), or other field-effect transistors.

[0047] According to the same inventive concept, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, comprising the steps of: S110: Provide a substrate.

[0048] Illustratively, the substrate material may be Si, SiC, gallium nitride, or sapphire, or other materials suitable for gallium nitride growth. The substrate may be fabricated by atmospheric pressure chemical vapor deposition, subatmospheric pressure chemical vapor deposition, metal organic chemical vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical chemical vapor deposition, rapid thermal chemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.

[0049] S120: Fabricating a multi-layer semiconductor layer on one side of the substrate.

[0050] Exemplarily, a multi-layer semiconductor layer is located on one side of the substrate, and the multi-layer semiconductor layer may be specifically a III-V compound semiconductor material, in which a 2DEG is formed.

[0051] S130: A source, a gate, and a drain are fabricated on one side of the multi-layer semiconductor layer, and a medium layer is fabricated on one side of the gate away from the substrate.

[0052] Illustratively, the medium layer at least covers the gate to avoid connecting the gate to the field plate in subsequent processes, and preferably is fabricated so that the medium layer is entirely within the active area of ​​the device, with the gate extending into the passive area.

[0053] S140: A field plate is fabricated near the gate on one side of the medium layer away from the substrate. The field plate includes a field plate body and at least one field plate end extending into the passive region. The field plate end extends from the field plate body toward the gate, and has an extension width greater than that of the field plate body.

[0054] For example, the extension width of the field plate body 260 in the second direction (the Y direction in the figure) is kept constant and maintained at a fixed value D. The field plate end 261 makes zero-touch contact with the source 23, gate 24, and drain 25, respectively. The first field plate end 261 further includes a first boundary line close to the active region. The first boundary line is located within the passive region bb. This structural design not only improves the reliability and stability of the field plate 26, but also adjusts the electric field distribution in the passive region.

[0055] In a preferred process, the distance d between the first boundary line of the field plate edge and the adjacent active region aa is set to 3 μm or less.

[0056] In a preferred process, the difference in extension width between field plate end 261 and field plate main body 260 satisfies L≧0.5*D, and the difference in extension width between field plate end 261 and field plate main body 260 satisfies L≦10*D.

[0057] S150: Before fabricating the field plate, a portion of the source is exposed, and then the field plate structure is integrally formed in the same fabrication process.

[0058] For example, exposing a portion of the source structure reserves most of the source structure during the process of fabricating the medium layer in step S130, i.e., the medium layer need not be deposited in the reserved portion, or a portion of the medium layer above the source may be removed after the medium layer is deposited. This contributes to integrally forming the field plate body, field plate end, and field plate connection portion, and enables the field plate connection portion to directly contact the source and the field plate end to contact the source in a zero-touch manner.

[0059] In summary, in a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention, the extension width of the field plate end is made larger than the extension width of the field plate body in the second direction, and a relationship is established between the extension widths of the field plate end and the field plate body, thereby improving the reliability and stability of the field plate, and the distance relationship between the first boundary of the field plate end and the adjacent active region improves the distribution of the electric field near the passive region and the active region, thereby reducing the gate-source capacitance. After ensuring that most of the source is exposed before manufacturing the field plate, the field plate body, field plate end, and field plate connection are integrally formed in the same manufacturing process, thereby reducing process risks of this structure and improving the reliability and stability of the device.

[0060] It should be noted that the above-described embodiments are merely preferred embodiments of the present invention and the technical principles employed therein, and it is understood by those skilled in the art that the present invention is not limited to the specific embodiments described herein, and that those skilled in the art can make various obvious changes, adjustments, mutual combinations, and substitutions without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail by the above embodiments, the present invention is not limited to the above embodiments, and can include many other equivalent embodiments without departing from the concept of the present invention, and the scope of protection of the present invention is determined by the appended claims.

Claims

1. an active area and a passive area surrounding the active area; A substrate; a multi-layer semiconductor layer located on one side of the substrate; a source and a drain located on one side of the multi-layer semiconductor layer away from the substrate, and a gate located between the source and the drain; a field plate located between the source and the drain, the field plate includes a field plate body and a field plate end along a first direction; At least one of the field plate edges extends into the passive region; the first direction is parallel to an extension direction of the source, the gate, and the drain; an extension width of the field plate main body in the second direction is kept constant; at least one of the field plate ends extends from the field plate body toward the gate along the second direction; an extension width of at least one of the field plate ends in the second direction being greater than the extension width of the field plate body; The semiconductor device is characterized in that the second direction is parallel to a direction from the source to the drain.

2. 2. The semiconductor device according to claim 1, wherein the field plate edge contacts the source, the gate, and the drain in a zero-touch manner.

3. 2. The semiconductor device according to claim 1, wherein in the second direction, a projection of an end of the field plate onto the substrate partially overlaps a projection of the gate onto the substrate within the passive region, and a projection of the end of the field plate onto the substrate does not overlap a projection of the source onto the substrate.

4. the field plate edge includes a first boundary line and a second boundary line along a first direction; the second boundary line is located on one side of the first boundary line away from the active area, 2. The semiconductor device according to claim 1, wherein the first boundary line and the second boundary line of at least one of the field plate ends are both located within the passive region.

5. a distance d between the first boundary line of at least one of the field plate edges and the adjacent active region; 5. The semiconductor device according to claim 4, wherein d≦5 μm.

6. the field plate edges include a first field plate edge and a second field plate edge; a distance d1 between the first boundary line at the end of the first field plate and the adjacent active region; a distance d2 between the first boundary line at the end of the second field plate and the adjacent active region; 5. The semiconductor device according to claim 4, wherein d1=d2.

7. the gate further includes a gate first end, a gate middle portion, and a gate second end; the first end of the gate and / or the second end of the gate are located within the passive region; 5. The semiconductor device according to claim 4, wherein the second boundary line of the field plate end is located between the adjacent first gate end and / or second gate end and the active region.

8. 8. The semiconductor device of claim 7, wherein the second boundary line of the field plate end is located on one side of a dividing line between the adjacent first gate end and / or second gate end and the intermediate portion, the dividing line being closer to the active region.

9. 8. The semiconductor device according to claim 7, wherein a distance b between a boundary line between the first gate end and / or the second gate end and the intermediate portion and the second boundary line of an adjacent field plate end is b, and b<3 μm.

10. the field plate edges include a first field plate edge and a second field plate edge; a distance b1 between the second boundary line of the first field plate end and a dividing line between the adjacent first gate end and the intermediate portion; a distance b2 between the second boundary line of the second field plate end and a dividing line between the adjacent second gate end and the intermediate portion; 10. The semiconductor device according to claim 9, wherein b1=b2.

11. 11. The semiconductor device according to claim 1, wherein a difference between a width of the field plate end portion extending toward the gate and an extension width of the field plate main body portion is L, and L≧0.5*D.

12. 11. The semiconductor device of claim 1, wherein the field plate end further comprises an extended end line located on one side of the gate away from the field plate.

13. the field plate further includes a field plate connection portion; the field plate connection is located in the active region and extends from the field plate body to the source until it contacts the source; 11. The semiconductor device according to claim 1, wherein the field plate body, the field plate end portion, and the field plate connection portion are integrally molded.

14. A method for manufacturing a semiconductor device according to any one of claims 1 to 13, comprising the steps of: Providing a substrate; fabricating a multi-layer semiconductor layer on one side of the substrate; forming a source, a drain, and a gate located between the source and the drain on one side of the multi-layer semiconductor layer away from the substrate; fabricating a medium layer on one side of the gate away from the substrate; fabricating a field plate adjacent the gate on one side of the medium layer away from the substrate; the field plate includes a field plate body and at least one field plate end extending into a passive region; the field plate end extends from the field plate body toward the gate, and the extension width of the field plate end is greater than the extension width of the field plate body.

15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein a portion of the source is exposed before the field plate is manufactured, and the field plate is integrally formed in the same manufacturing process.

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