Communication systems for power supply noise reduction

Abstract

1. A method and apparatus for transferring data signals, comprising: receiving a digital data signal by a first input of a multiplexer of a transmitter operatively coupled to a data link; transmitting the digital data signal by a digital data signal output of the multiplexer to a receiver operatively coupled to the data link; receiving a first select signal by a select signal input of the multiplexer, the first select signal indicating an idle mode for the transmitter; receiving a patterned data signal by a second input of the multiplexer; and transmitting the patterned data signal to the receiver by the digital data signal output and in response to the first select signal.

Description

[Background technology]

[0001] The present invention relates to data transfer techniques, and more particularly to data transfer techniques over one or more data links.

[0002] A data link is an interconnect between agents, where in a given data transaction, one agent is the "sender" and the other agent is the "receiver." Exemplary data links may be located between a processor and a disk drive, processors on separate boards in a computer system, and / or processors on the same board or package, among other examples. In order for two agents to communicate, both agents agree on the timing for sending and receiving data. This agreement is commonly known in link design as a clocking scheme.

[0003] For example, in a "common clock" scheme, all components in the interconnect share a single clock when transmitting and receiving data. In a "source synchronous" clocking scheme, a clock signal is transmitted along with the data signal. An "embedded" clocking scheme embeds a clock signal in the data transfer, but is not without drawbacks, including the need for clock data recovery circuitry and bandwidth limitations. Within a given clocking scheme, a transmission protocol defines when the transmitter transmits data and when the receiver samples the transmitted data.

[0004] Transmission protocols may include techniques for idling or otherwise idling agents that may not have data to send, but such idling introduces various delays, data overhead, and complexities. Summary of the Invention

[0005] According to a first embodiment of the present invention, a method comprises receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting the digital data signal by a digital data signal output of the multiplexer to a receiver operably coupled to the data link; receiving a first select signal by a select signal input of the multiplexer, the first select signal indicating an idle mode for the transmitter; receiving a patterned data signal by a second input of the multiplexer; and transmitting the patterned data signal to the receiver by the digital data signal output and in response to the first select signal.

[0006] In a first aspect of the first embodiment, the method further comprises intermittently communicating the patterned data signal to the second input, thereby reducing a switching rate of the patterned data signal received by the second input of the multiplexer.

[0007] In a second aspect, in combination with the first embodiment and / or aspect thereof, the method further comprises receiving, by the selection signal input of the multiplexer, a second selection signal indicating a data signal transmission mode for the transmitter, and transmitting the digital data signal comprises transmitting the digital data signal to the receiver in response to the second selection signal.

[0008] In a third aspect, in combination with the first embodiment and / or its aspects, the method further comprises selecting the idle mode for the transmitter based on the digital data signal. In a fourth aspect, the selecting comprises selecting the idle mode for the transmitter based on a switching activity value of the digital data signal. In a fifth aspect, the selecting comprises detecting at least one of an idle flit in the digital data signal and an idle phit in the digital data signal, and selecting the idle mode for the transmitter based on at least one of the idle flit and the idle phit.

[0009] In a sixth aspect, in combination with the first embodiment and / or any aspect thereof, a first processor comprises the transmitter and a second processor comprises the receiver.

[0010] According to a second embodiment of the present invention, a method comprises receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting a clock signal by a first counter; sending a first select signal to a first select signal input of the transmitter multiplexer by the first counter and in response to the first counter counting a threshold number of clock cycles; and alternately transmitting the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver in response to the first select signal and by a first digital data signal output of the transmitter multiplexer, the receiver and the digital data signal output being operably coupled to a data link.

[0011] In a first aspect of the second embodiment, the receiver comprises a second counter and a receiver multiplexer arranged to receive the transmitter output signal, the method further comprising receiving the transmitter output signal via a second data input of the receiver multiplexer; inverting the transmitter output signal via a second inverter, thereby providing an inverted transmitter output signal; receiving the inverted digital data signal via a second inverted data input of the receiver multiplexer; counting the clock signal via a second counter; sending a second select signal to a second select signal input of the receiver multiplexer by the second counter and in response to the second counter counting the threshold number of clock cycles; and alternately providing the transmitter output signal and the inverted transmitter output signal via a second digital data signal output of the receiver multiplexer in response to the select signal.

[0012] In a second aspect of the second embodiment, the counting step with the first counter includes counting each occurrence of a threshold number of counted clock cycles with the first counter and providing the first select signal in response to each occurrence of the threshold number of counted clock cycles, and the countering step with the second counter includes counting each occurrence of the threshold number of counted clock cycles with the second counter and providing the second select signal in response to each occurrence of the threshold number of counted clock cycles.

[0013] In a third aspect of the second embodiment, in combination with the second embodiment and / or any aspect thereof, the method further comprises synchronizing the first counter and the second counter. In a fourth aspect, in combination with the second embodiment and / or any aspect thereof, the first processor comprises the transmitter multiplexer and the second processor comprises the receiver multiplexer.

[0014] As described herein, the first and second embodiments and aspects thereof may be combined in further embodiments.

[0015] According to a third embodiment of the present invention, a system comprises a data link; a receiver operatively coupled to the data link; a memory for storing data for generating a patterned data signal; and a transmitter operatively coupled to the data link and the memory, the transmitter arranged to transmit a digital data signal, the transmitter having a multiplexer including a first input arranged to receive the digital data signal, a second input arranged to receive the patterned data signal, a selection signal input arranged to receive a mode selection signal, and a digital data signal output arranged to transmit a multiplexer output signal to the data link, the multiplexer adapted to selectively output the digital data signal and the patterned data signal as the multiplexer output signal in response to receiving the mode selection signal, the mode selection signal representing an idle mode of the transmitter and a data signal transmission mode of the transmitter.

[0016] In a first aspect of a third embodiment, the system further comprises a switch disposed between the memory and the patterned data signal input for intermittently communicating the patterned data signal to the patterned data signal input.

[0017] In a second aspect of the third embodiment, in combination with the third embodiment and / or any aspect thereof, a processor comprises at least one of the memory and the transmitter. In a third aspect of the third embodiment, in combination with the third embodiment and / or any aspect thereof, the memory comprises a processor register for storing the data for generating the patterned data signal.

[0018] In a fourth aspect of the third embodiment, the system further comprises a serializer operably coupled to the processor register and the second input, the serializer adapted to serialize the data to generate the patterned data signal. In a fifth aspect of the third embodiment, in combination with the third embodiment and / or aspects thereof, the multiplexer comprises a 2 to 1 multiplexer.

[0019] In a sixth aspect of the third embodiment, in combination with the third embodiment and / or aspects thereof, the system further comprises a mode selection controller adapted to provide the mode selection signal based on the digital data signal. In a seventh aspect of the third embodiment, the mode selection controller is adapted to provide the mode selection signal in response to the digital data signal including a flow control message indicating the idle mode. In an eighth aspect of the third embodiment, the mode selection controller is adapted to provide the mode selection signal in response to the digital data signal including a flow control message indicating the data signal transmission mode.

[0020] In a ninth aspect of the third embodiment, in combination with the third embodiment and / or any aspect thereof, the transmitter is configured to transmit a clockless data signal as the digital data signal. In a tenth aspect of the third embodiment, in combination with the third embodiment and / or any aspect thereof, the memory comprises a programmable memory configured to receive the data for generating the patterned data signal.

[0021] According to a fourth embodiment of the present invention, a system comprises a first inverter arranged to receive a digital data signal, a clock, a first counter operatively coupled to the clock, and a transmitter multiplexer having a first input arranged to receive the digital data signal, a first inverted data input operatively coupled to the first inverter and arranged to receive an inverted digital data signal, a first select signal input operatively coupled to the first counter and arranged to receive a first select signal, and a first output arranged to transmit a transmitter multiplexer output signal, wherein the first counter is adapted to provide the first select signal in response to a threshold number of counted clock cycles, whereby the transmitter multiplexer alternately transmits the digital data signal and the inverted digital data signal as the transmitter multiplexer output signal.

[0022] In a first aspect of the fourth embodiment, the system further comprises a second inverter arranged to receive the transmitter multiplexer output signal, a second counter, a receiver multiplexer, and a data link operably coupled to the transmitter multiplexer and the receiver multiplexer, the receiver multiplexer having a second input arranged to receive the transmitter multiplexer output signal, a second inverted data input operably coupled to the second inverter and arranged to receive an inverted transmitter multiplexer output signal, a second select signal input operably coupled to the second counter and arranged to receive a second select signal, and a second output arranged to provide a receiver multiplexer output signal, the second counter adapted to provide the second select signal in response to a threshold number of counted clock cycles, whereby the receiver multiplexer alternately provides the transmitter multiplexer output signal and the inverted transmitter multiplexer output signal as the receiver multiplexer output signal.

[0023] In a second aspect of the fourth embodiment, in combination with the fourth embodiment and / or any aspect thereof, the system further comprises a processor operably coupled to a computer readable storage medium having computer readable program code embodied therein, the computer readable program code being executable by the processor to synchronize the first and second counters.

[0024] In a third aspect of the fourth embodiment, in combination with the fourth embodiment and / or any aspect thereof, a first processor comprises the transmitter multiplexer and a second processor comprises the receiver multiplexer.

[0025] In a fourth aspect of the fourth embodiment, in combination with the fourth embodiment and / or any aspect thereof, the first counter is the programmable counter adapted to vary the threshold number of counted clock cycles to which the programmable counter is responsive by providing the first select signal. In a fifth aspect of the fourth embodiment, in combination with the fourth embodiment and / or any aspect thereof, the first counter is the first programmable counter adapted to vary the threshold number of counted clock cycles to which the programmable counter is responsive by providing the first select signal, and the second counter is the second programmable counter adapted to vary the threshold number of counted clock cycles to which the second programmable counter is responsive by providing the second select signal.

[0026] As described herein, the third and fourth embodiments and aspects thereof may be combined in further embodiments. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 illustrates an example of a communication system.

[0028] [Figure 2]FIG. 1 illustrates an example of a transmitter agent.

[0029] [Figure 3] FIG. 2 illustrates an example of a transmitter agent.

[0030] [Figure 4] FIG. 1 illustrates an example of a communication system.

[0031] [Figure 5] FIG. 1 illustrates an exemplary method for data communication.

[0032] [Figure 6] FIG. 1 illustrates an exemplary method for data communication.

[0033] [Figure 7] FIG. 1 illustrates an exemplary method for data communication.

[0034] [Figure 8] FIG. 2 illustrates an example of a transmitter agent.

[0035] [Figure 9] FIG. 1 illustrates an exemplary computing environment. DETAILED DESCRIPTION OF THE INVENTION

[0036] Various aspects of the present disclosure are described through text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. For any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in successive flowchart blocks may be performed in reverse order, as a single integrated step, simultaneously, or in an at least partially overlapping manner.

[0037] A computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media (also referred to as "media") collectively included in a set of one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. The computer-readable storage medium may be, but is not limited to, an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (such as punch cards or pits / lands formed on a major surface of a disk), or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, is not to be construed as storage in the form of a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through fiber optic cables, electrical signals communicated through wires, and / or other transmission media.As will be appreciated by those skilled in the art, data is typically moved at some infrequent time during the normal operation of a storage device, such as during access, defragmentation, or garbage collection, but the above does not make the storage device temporary, as the data is not temporary while it is stored.

[0038] Idle agents (e.g., processors) operate aggressively against a small power budget. This causes a large delta in current on the I / O voltage supply when transitioning from idle to active. This delta in current translates into large voltage noise due to package inductance. This voltage noise will cause performance degradation in either the I / O producing the noise or other I / O operably coupled to the same power supply. In one aspect, some embodiments may effectively provide a data link noise ceiling by ensuring that minimal switching activity occurs over the data link.

[0039] The power consumption of a digital circuit may be characterized in terms of the switching activity of a digital signal (e.g., a digital data signal or a clock signal). The switching activity may be characterized as an activity factor (e.g., a switching activity value) of the digital signal that has a probability for a power consumption transition per clock cycle of the digital signal. A clock signal has an activity factor expressed as a percentage of 100%, meaning that the digital data signal will include a power consumption transition during 5% to 15% of the clock cycles, in contrast to a digital data signal that has an activity factor between 5% and 15%.

[0040] 1, a communication system 100, in one embodiment, includes a circuit board 101 having agents 102a and 102b and optional agent 102c. Agent 102a includes a transmitter 106a and a receiver 122a. Agent 102b includes a transmitter 106b and a receiver 122b, and optional agent 102c includes a transmitter 106c and a receiver 122c. Transmitters 106a and 106b and receivers 122a, 122b may communicate over respective data links 120a and 120b. In one aspect, data links 120a and 120b may be clockless data links (e.g., data links that do not use an embedded clock signal to convey data).

[0041] The transmitter 106a and receiver 122a may be included in a processor occupying a computer motherboard, where the data link 26 is a bus interconnecting the processors. Alternatively, the transmitter 106a and receiver 122a may be located in separate chips, each located on a respective circuit board. The transmitter 106a and receiver 122a may be in close proximity to each other or may be separated by signal traces, such as 100 inches (254 cm) or longer. In one aspect, the transmitter 106a and receiver 122a may reside on a multi-chip package. In one aspect, the data links 120a and 120b include one or more physical interconnects (e.g., point-to-point physical interconnects), thereby defining a physical link at the physical layer of the system 100.

[0042] The multiplexer 108, in one embodiment, includes a digital data input 110, a data pattern input 112, a mode selection input 114, and a digital data output 118. The digital data output 118 may be operatively coupled to the Tx circuitry 116. In one aspect, the input 110 may receive a digital data signal for transmission over the data link 120a. In one aspect, the mode selection input 114 may receive a signal indicating that the transmitter 106a is in an idle mode.

[0043] Any of several criteria can be used to initiate this idle mode. Example embodiments include trigger conditions for initiating idle mode, such as detecting an idle flit, an output signal below a switching activity threshold, and an empty transaction queue for the transmitting agent, or when the queue reaches a non-zero minimum threshold. Additionally or alternatively, the trigger conditions may reflect a software trigger event, an event triggered by a higher protocol layer, and / or a power management event.

[0044] Upon receiving an idle mode selection signal via input 114, multiplexer 108 transmits the data pattern being received via data pattern input 112. In one aspect, the data pattern is based on predetermined data to ensure minimal switching activity over data link 120a. Thus, the data pattern does not contain actual data for processing, but rather data to ensure a maximum noise level or noise ceiling for data link 120a and operatively coupled agents. In one aspect, the transmitted data pattern is not processed by the receiving agent.

[0045] When input 114 receives a selection signal indicating a data signal transmission mode for transmitter 106a, multiplexer 108 transmits the digital data signal received by digital data input 110 to at least agent 102b. In some embodiments, multiplexer 108 is a 2-to-1 multiplexer.

[0046] 2 illustrates an agent 202 that, in one embodiment, includes a processor 204, an optional switch controller 224, and a mode selection controller 228. In one embodiment, the processor 204 includes the switch controller 224 and the mode selection controller 228.

[0047] In one embodiment, the processor 204 includes the multiplexer 108 having the above-mentioned digital data input 110, data pattern input 112, mode selection input 114, and digital data output 118. In one embodiment, the processor 204 may further include a clock 216 and internal memory 218. The internal memory 218 may contain data for generating the patterned data signal. In some embodiments, the internal memory 218 includes programmable memory, thereby allowing the patterned signal data to be changed and / or supplemented.

[0048] For example, processor 204 may be included in a wide range of different computing systems and subsystems, each with a different upper noise threshold to prevent transmitted data from being corrupted through voltage noise. Different patterned signal data may be provided in memory 218 so that different upper noise thresholds can be accommodated for different computing systems / subsystems. In some embodiments, different patterned signal data characterize the patterned data signal with different activity coefficients. In programmable memory embodiments of internal memory 218, a programmable communication protocol is achieved by programmably defining the patterned signal data.

[0049] In one embodiment, internal memory 218 may be relatively small (e.g., the embodiment shown in FIG. 3) and store a small range of data values ​​with a relatively high activity factor for idle mode. For example, the patterned data signal may have an activity factor of 6% or greater. In one embodiment, switch 220 toggles the application of the patterned data signal to input 112, thereby lowering the activity factor. In one aspect, switch 220 reduces the activity factor by approximately half, so that a signal with a 6% activity factor now has an activity factor of approximately 3.25%.

[0050] In one embodiment, the switch controller 224 is adapted to control the application and / or switching rate of the switch 220. The variable switching rate may further provide a patterned data input signal of different activity coefficients to the input 112. For example, in some embodiments, the switch controller 224 may increase or decrease the switching speed of the switch 220 to intermittently provide the patterned data signal. In one embodiment, at least one of the switch 220 and the switch controller 224 is programmable, thereby allowing at least one instruction to define the switching rate, among other possible instructions.

[0051] In one embodiment, the mode selection controller 228 may detect flits or phits 230. "FLIT" is an abbreviation for "flow control unit / digit" and "PHIT" is an abbreviation for "physical digit." The smallest unit of information transferred to / from the link layer is called a "flit." The smallest unit of data transferred from one agent to another at the physical layer is called a "phit."

[0052] During idle mode, no data is transmitted over the data link, which may result in an arbitrary voltage (e.g., noise) on the data link. In contrast, in one embodiment, flit / phit 230 may include one of an idle flit and an idle phit. In some embodiments, mode selection controller 228 may detect an idle flit and / or an idle phit indicating an idle mode of transmitter 206 and / or processor 204, and in response provide an idle mode selection signal, thereby causing multiplexer 108 to transmit a patterned data signal.

[0053] In one embodiment, mode selection controller 228 may monitor transaction queue 210 and / or the data therein. In one embodiment, controller 228 provides an idle mode selection signal in response to an empty and / or nearly empty transaction queue 210.

[0054] 3 illustrates an agent 302 that, in one embodiment, includes a processor 304 having a transmitter 206, a clock 216, a receiver 306, a serializer 308, and an internal memory 218. In one embodiment, the internal memory 218 includes a processor register 318 for storing (or otherwise storing) data 320 for generating a patterned data signal. In one embodiment, the processor register 318 may include 16-bit data, shown in hexadecimal format in FIG. 3. In one aspect, storing the data 320 in the processor register 318 is a particularly efficient implementation in terms of memory utilization, computational resources, and messaging efficiency for providing a patterned data signal during idle mode.

[0055] The optional serializer 308 may receive data 320 in parallel via the input 310 and serialize the data 320 as a patterned data signal for the input 112. That is, the serializer 308 may include a parallel in serial out (PISO) block structure. In one aspect, the serializer 308 may be a SerDes (i.e., serializer / deserializer) component. Alternatively, the data 320 may be output directly from the memory 218 to the input 112 in a serial manner.

[0056] In one embodiment, even when the transmitter 206 is in idle mode, the processor 304 may still receive data and process this data received from the data output 340. That is, in some embodiments, the transmitter 206 and receiver 306 may be independently put into idle state.

[0057] 4 illustrates an example communication system 400 that includes, in one embodiment, processors 404a and 404b, a data link 420, and a clock link 444. In one embodiment, the data link 420 and / or the clock link 444 include one or more physical interconnects (e.g., point-to-point physical interconnects), thereby defining physical links at a physical layer of the system 400.

[0058] 4, system 400 illustrates an embodiment of a "source synchronous" clocking scheme, although other embodiments may include embodiments of a "common clock" scheme. For example, clock 416a may be external to processor 404a, and clock 416a provides clock signals to processors 404a and 404b.

[0059] The processor 404a, in one embodiment, includes a transmitter 406 and a clock 416a. The transmitter 406, in one embodiment, includes an inverter 403a, a multiplexer 408a, a counter 414a, and a Tx circuit 416. The multiplexer 408a (e.g., a transmitter multiplexer) includes a digital data input 110, an inverted data input 410, a select signal input 412a, and a data output 418.

[0060] Processor 404b, in one embodiment, includes receiver 422 and optional clock 416b. In one embodiment, clock 416b receives a clock signal for generating a further clock signal. In one embodiment, processor 404b does not include clock 416b and utilizes an external clock signal.

[0061] Receiver 422, in one embodiment, includes inverter 403b, multiplexer 408b, counter 414b, and Rx circuitry 424. Multiplexer 408b (e.g., a receiver multiplexer) includes a digital data input 426, an inverted data input 428, a select signal input 412b, and a data output 440. In some embodiments, multiplexers 408a and 408b are 2-to-1 multiplexers.

[0062] In one embodiment, counters 414a and 414b are synchronized and send select signals to respective multiplexers 408a and 408b after at least a threshold number of clock cycles of clock 416a. In one aspect, multiplexers 408a and 408b synchronously switch from outputting data or inverted data. For example, in one embodiment mode, data provided to data input 110 of transmitter 406 is provided via data link 420, received by data input 426, and provided by data output 440. In another embodiment mode, counters 414a and 414b synchronously provide (e.g., send) select signals to respective select signal inputs 412a and 412b such that multiplexers 408a and 408b synchronously switch to output the inverted data signals provided to their respective inverted data inputs 410 and 428.

[0063] In inverted mode embodiments, the original data signal is inverted twice (e.g., first by inverter 403a and then by 403b), thereby providing the correct data signal at output 440. In one advantageous aspect, because either the data signal or the inverted data signal is provided independently of the data content, a minimum activity factor (and therefore a noise ceiling) can be established. For example, real data may contain long strings of zeros or ones, which may bias circuits or otherwise introduce noise. However, in some embodiments, at least a portion of the long strings of zeros or ones may be inverted, thereby increasing the activity factor of the data signal.

[0064] In another advantageous aspect, toggling between the data signal and the inverted data signal may maintain circuit integrity. For example, by ensuring a minimum amount of switching every threshold number of clock cycles, circuit components are more likely to stay within design tolerances with minimum power consumption, especially in embodiments with long periods of minimal or no data transmission (e.g., processors with long periods of empty transaction queues).

[0065] In one embodiment, counters 414a and 414b are programmable. For example, in one embodiment, counters 414a and 414b may be adapted via instructions to change the threshold number of counted clock cycles that trigger a select signal. An example threshold may be 32,000 clock cycles, which may be updated to a different clock cycle value in a programmable embodiment. In a programmable embodiment of counters 414a and 414b, for example, a programmable communication protocol may be achieved by programmably defining the number of clock cycles that trigger counters 414a and 414b to synchronously transmit their respective select signals.

[0066] System 400 may be included in a wide range of different computing systems and subsystems, each with a different upper noise threshold to prevent transmitted data from being corrupted through voltage noise. Different trigger clock cycle values ​​may be provided to clocks 416a and 416b for different computing systems / subsystems so that different upper noise thresholds can be accommodated.

[0067] 5 illustrates an exemplary method 500 for data communication, which in one embodiment includes the steps shown. Method 500 may correspond, in some embodiments, to agent 102a of FIG. 1, agent 202 of FIG. 2, and / or agent 302 of FIG. 3.

[0068] Step 502 includes receiving a data link signal via a first input of a transmitter multiplexer operably coupled to the data link, and step 504 includes transmitting a digital data signal via a digital data signal output of the multiplexer to a receiver operably coupled to the data link.

[0069] Stage 506 includes receiving, via a select signal input of the multiplexer, a first select signal indicating an idle mode for the transmitter. In some embodiments, the idle mode may be selected based on detecting a digital data signal, such as a switching activity value of the digital data signal, and / or at least one of an idle flit and an idle phit.

[0070] Optional step 508 includes intermittently communicating the patterned data signal to a second signal input. As described with reference to Figure 2, the switch may intermittently couple or otherwise communicate the patterned data signal. In some embodiments, step 508 modifies the switching activity of the patterned data signal, including decreasing an activity coefficient of the patterned data signal.

[0071] Step 510 includes receiving the patterned data signal via a second input of the multiplexer. Step 512 includes transmitting the patterned data signal to the receiver via a digital data signal output and in response to the first select signal. Optional step 514 includes receiving a second select signal via a select signal input of the multiplexer, the second select signal indicating a data signal transmission mode for the transmitter. Method 500 may then, in one embodiment, return to step 504, which is associated with the data signal transmission mode.

[0072] 6 illustrates an exemplary method 600 for data communication, which in one embodiment includes the steps shown. Method 600 may correspond to communication system 400 in some embodiments. Optional step 602 includes synchronizing at least a receiver counter and a transmitter counter. For example, a memory may include computer program instructions executable by a processor to synchronize two or more counters. In some embodiments, the counters may already be synchronized, such that the method of the embodiment may be step 604.

[0073] Stage 604 includes receiving a digital data signal via a first input of a transmitter multiplexer. Stage 606 includes receiving an inverted digital data signal via a second input of the transmitter multiplexer. Stage 608 includes transmitting, by a transmitter counter and in response to the transmitter counter counting a threshold number of clock cycles, a first select signal to a select signal input of the transmitter multiplexer. In some embodiments, counting includes counting each occurrence of the threshold number of counted clock cycles and providing the select signal of stage 608 in response to each occurrence of the threshold number of counted clock cycles.

[0074] Stage 610 includes, in response to the first selection signal and via the digital data signal output of the transmitter multiplexer, alternately transmitting the digital data signal and the inverted digital data signal to the receiver. As described above, the communication system of some embodiments (e.g., system 400) may toggle between transmitting data and transmitting inverted data independently of the idle mode or the data signal transmission mode.

[0075] 7 illustrates an exemplary method 700 for data communications, which in one embodiment includes the steps shown. Method 700 may correspond to communication system 400 in some embodiments. Method 700 may include step 610. Step 702 includes alternately receiving a digital data signal and an inverted digital data signal from a transmitter via a first input of a receiver multiplexer. Step 704 includes receiving an inverted version of the digital data signal or the inverted digital data signal received in step 702 via a second input of the receiver multiplexer.

[0076] Stage 706 includes transmitting, by the receiver counter and in response to the receiver counter counting the threshold number of clock cycles, a second select signal to a select signal input of the receiver multiplexer. In some embodiments, stage 706 may be performed synchronously with stage 608 of method 600 such that the transmitter and receiver alternately process the data input signal or the inverted data input signal. In some embodiments, counting includes counting each occurrence of the threshold number of counted clock cycles and providing the select signal of stage 706 in response to each occurrence of the threshold number of counted clock cycles.

[0077] Step 708 includes providing a digital data signal in response to the second selection signal and via the digital data signal output of the multiplexer. In one embodiment, the digital data signal of step 604 is faithfully reproduced as the digital data signal of step 708, given that the receiving and transmitting counters are synchronized.

[0078] Referring now to FIG. 8 , agent 802, in one embodiment, includes processor 804 and transmitter 806. In one embodiment, transmitter 806 includes multiplexer 108 of FIG. 1 operably coupled to multiplexer 408a of FIG. 4 . In such an embodiment, digital data output 118 provides either the (actual) data signal or the patterned data signal as the received digital data signal to digital data input 810 and inverted data input 410 of multiplexer 408a based on the idle mode or the data signal transmission mode, as discussed above. As discussed above, multiplexer 408a alternately provides either the received digital data signal or the inverted digital data signal to digital data output 418 based on counter 414a counting a threshold number of clock cycles. Thus, agent 902, in some embodiments, combines the features and advantages thereof of FIGS. 1 and 4 .

[0079] Computing environment 900 comprises an example of an environment for the execution of at least a portion of computer code involved in performing the methodology of the present invention, such as programmable communications protocol code block 1000. In addition to block 1000, computing environment 900 includes, for example, a computer 901, a wide area network (WAN) 902, an end user device (EUD) 903, a remote server 904, a public cloud 905, and a private cloud 906. In this embodiment, computer 901 includes a set of processors 910 (including processing circuitry 920 and cache 921), a communications fabric 911, volatile memory 912, persistent storage 913 (including an operating system 922 and block 1000 as identified above), a set of peripheral devices 914 (including a set of user interface (UI) devices 923, storage 924, and a set of Internet of Things (IoT) sensors 925), and a network module 915. Remote server 904 includes a remote database 930. The public cloud 905 includes a gateway 940, a cloud orchestration module 941, a set of host physical machines 942, a set of virtual machines 943, and a set of containers 944.

[0080] Computer 901 may take the form of a desktop computer, a laptop computer, a tablet computer, a smartphone, a smartwatch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database, such as remote database 930. As is well understood in the art of computer technology, and depending on the technology, execution of a computer-implemented method may be distributed among multiple computers and / or among multiple locations. While in this presentation of computing environment 900, to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 901. Although computer 901 is not depicted in the cloud of FIG. 9, it may be located in a cloud. However, computer 901 is not required to reside within a cloud except to any extent that may be expressly indicated.

[0081] The processor set 910 includes one or more computer processors of any type now known or later developed. The processing circuitry 920 may be distributed across multiple packages, e.g., multiple coordinated integrated circuit chips. The processing circuitry 920 may implement multiple processor threads and / or multiple processor cores. The cache 921 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on the processor set 910. Cache memory is typically organized into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all caches for a processor set may be located “off-chip.” In some computing environments, the processor set 910 may be designed to operate with qubits and perform quantum computing.

[0082] Computer-readable program instructions are typically loaded onto the computer 901 to cause a series of operational steps to be performed by the processor set 910 of the computer 901, thereby realizing a computer-implemented method, whereby the instructions so executed instantiate the method specified in the flowcharts and / or descriptions of the computer-implemented method contained herein (collectively referred to as the "methods of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 921 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 910 to control and direct the execution of the methods of the present invention. In the computing environment 900, at least some of the instructions for performing the methods of the present invention may be stored in block 1000 in persistent storage 913.

[0083] Communications fabric 911 is the signal-conducting pathway that allows various components of computer 901 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as those that make up buses, bridges, physical input / output ports, and the like. Other types of signal communication pathways may be used, such as fiber optic and / or wireless communication pathways.

[0084] Volatile memory 912 may be any type of volatile memory now known or later developed. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory 912 is characterized by random access, although this is not required unless expressly indicated. In computer 901, volatile memory 912 is located in a single package and is internal to computer 901, although alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 901.

[0085] Persistent storage 913 is any form of non-volatile storage for a computer, now known or developed in the future. The non-volatility of this storage means that stored data remains whether or not power is supplied to computer 901 and / or to persistent storage 913 directly. Persistent storage 913 may be read-only memory (ROM), but typically at least a portion of persistent storage allows data to be written, data to be deleted, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 922 may take several forms, such as various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems that employ a kernel. The code contained in block 1000 typically includes at least a portion of the computer code involved in performing the methods of the present invention.

[0086] The peripheral device set 914 includes a set of peripheral devices of the computer 901. Data communication connections between the peripheral devices and other components of the computer 901 may be implemented in various ways, such as Bluetooth connections, Near-Field Communication (NFC) connections, connections made by cable (such as a universal serial bus (USB)-type cable), insertion-type connections (e.g., a secure digital (SD) card), connections made over a local area communication network, and even connections made over a wide area network such as the Internet. In various embodiments, the UI device set 923 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. The storage 924 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. The storage 924 may be persistent and / or volatile. In some embodiments, storage 924 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 901 is required to have a large amount of storage (e.g., computer 901 stores and manages large databases locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. IoT sensor set 925 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another sensor may be a motion detector.

[0087] The network module 915 is a collection of computer software, hardware, and firmware that enables the computer 901 to communicate with other computers over the WAN 902. The network module 915 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of the network module 915 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of the network module 915 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for implementing the methods of the present invention can be downloaded to the computer 901 from an external computer or external storage device, typically through a network adapter card or network interface included in the network module 915.

[0088] WAN 902 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances by any technology for communicating computer data, now known or later developed. In some embodiments, WAN 902 may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0089] End-user device (EUD) 903 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 901) and may take any of the forms discussed above in connection with computer 901. EUD 903 typically receives useful and useful data from the operation of computer 901. For example, in the hypothetical case where computer 901 is designed to provide recommendations to the end user, the recommendations would typically be communicated from computer 901's network module 915 over WAN 902 to EUD 903. In this manner, EUD 903 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 903 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0090] Remote server 904 is any computer system that provides at least some data and / or functionality to computer 901. Remote server 904 may be controlled and used by the same entity that operates computer 901. Remote server 904 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 901. For example, in the hypothetical case where computer 901 is designed and programmed to provide recommendations based on historical data, then this historical data may be provided to computer 901 from a remote database 930 of remote server 904.

[0091] A public cloud 905 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer functionality, particularly data storage (cloud storage) and computing power, without direct active management by users. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct active management of the public cloud 905's computing resources is performed by the computer hardware and / or software of a cloud orchestration module 941. The computing resources provided by the public cloud 905 are typically implemented by virtual computing environments running on various computers that comprise a host physical machine set 942, which is the universe of physical computers in and / or available to the public cloud 905. A virtual computing environment (VCE) typically takes the form of a virtual machine from a virtual machine set 943 and / or a container from a container set 944. It is understood that these VCEs may be stored as images and can be transferred among and between various physical machine hosts, either as images or after instantiation of the VCE. The cloud orchestration module 941 manages the transfer and storage of images, deploys new instantiations of the VCE, and manages active instantiations of VCE deployments. The gateway 940 is a collection of computer software, hardware, and firmware that enables the public cloud 905 to communicate over the WAN 902.

[0092] Some further description of a virtualized computing environment (VCE) is now provided. A VCE can be stored as an "image." A new, active instance of a VCE can be instantiated from the image. Two well-known types of VCE are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows for the existence of multiple isolated user space instances called containers. These isolated user space instances typically behave as actual computers from the perspective of programs running in them. A computer program running on a normal operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and of the devices assigned to the container; this feature is known as containerization.

[0093] Private cloud 906 is similar to public cloud 905, except that the computing resources are available only for use by a single enterprise. While private cloud 906 is shown as communicating with WAN 902, in other embodiments, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often each implemented by a different vendor. While each of the multiple clouds remains a separate, discrete entity, the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both public cloud 905 and private cloud 906 are part of a larger hybrid cloud.

[0094] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0095] In the foregoing, reference has been made to embodiments presented in this disclosure. However, the scope of the disclosure is not limited to the particular described embodiments. Instead, any combination of features and elements, whether associated with different embodiments, is contemplated for implementing and practicing the contemplated embodiments. Moreover, while the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of the disclosure. Therefore, the aspects, features, embodiments, and advantages discussed herein are exemplary only and should not be considered elements or limitations of the appended claims unless expressly recited in the claims. Similarly, references to "the present invention" should not be construed as a generalization of any inventive subject matter disclosed herein, and should not be considered elements or limitations of the appended claims unless expressly recited in the claims.

[0096] Aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be collectively referred to herein as a "circuit," "module," or "system."

[0097] The forgoing is directed to embodiments of the present invention; however, other and further embodiments of the invention may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, via the digital data signal output of said multiplexer, said digital data signal to a receiver operably coupled to said data link; receiving, by a select signal input of said multiplexer, a first select signal indicating an idle mode for said transmitter; receiving a patterned data signal by a second input of the multiplexer; and transmitting the patterned data signal to the receiver via the digital data signal output and in response to the first selection signal. A method comprising:

2. 10. The method of claim 1, further comprising intermittently communicating the patterned data signal to the second input, thereby reducing a switching rate of the patterned data signal received by the second input of the multiplexer.

3. 2. The method of claim 1, further comprising receiving a second selection signal by the selection signal input of the multiplexer indicating a data signal transmission mode for the transmitter, and wherein transmitting the digital data signal comprises transmitting the digital data signal to the receiver in response to the second selection signal.

4. The method of claim 1 , further comprising selecting the idle mode for the transmitter based on the digital data signal.

5. 5. The method of claim 4, wherein the selecting step comprises selecting the idle mode for the transmitter based on a switching activity value of the digital data signal.

6. 5. The method of claim 4, wherein the selecting step comprises detecting at least one of an idle flit of the digital data signal and an idle phit of the digital data signal, and selecting the idle mode for the transmitter based on at least one of the idle flit and the idle phit.

7. The method of claim 1 , wherein a first processor comprises the transmitter and a second processor comprises the receiver.

8. receiving the digital data signal or the patterned data signal as a received digital data signal by a first data input of a transmitter multiplexer operatively coupled to the digital data signal output; inverting the received digital data signal with a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting the clock signal with a first counter; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first select signal to a first select signal input of the transmitter multiplexer; and alternately transmitting the digital data signal and the inverted digital data signal as the transmitter output signal to the receiver in response to the first selection signal and via a first digital data signal output of the transmitter multiplexer, the digital data signal output being operably coupled to the data link; The method of claim 1 further comprising:

9. The receiver comprises a second counter and a receiver multiplexer arranged to receive the transmitter output signal, and the method comprises: receiving the transmitter output signal via a second data input of the receiver multiplexer; inverting the transmitter output signal with a second inverter, thereby providing an inverted transmitter output signal; receiving the inverted digital data signal by a second inverted data input of the receiver multiplexer; counting the clock signal with a second counter; transmitting a second select signal to a second select signal input of the receiver multiplexer by the second counter and in response to the second counter counting the threshold number of clock cycles; and providing, in response to said selection signal and by a second digital data signal output of said receiver multiplexer, alternately said transmitter output signal and said inverted transmitter output signal. The method of claim 8 further comprising:

10. 10. The method of claim 9, wherein the counting with the first counter comprises counting each occurrence of a threshold number of counted clock cycles with the first counter and providing the first select signal in response to each occurrence of the threshold number of counted clock cycles, and wherein the countering with the second counter comprises counting each occurrence of the threshold number of counted clock cycles with the second counter and providing the second select signal in response to each occurrence of the threshold number of counted clock cycles.

11. Data link; a receiver operably coupled to said data link; a memory for storing data for generating a patterned data signal; and a transmitter operably coupled to the data link and the memory; the transmitter is arranged to transmit a digital data signal and comprises a multiplexer, the multiplexer comprising: a first input arranged to receive said digital data signal; a second input arranged to receive the patterned data signal; a selection signal input arranged to receive a mode selection signal; and a digital data signal output arranged to transmit the multiplexer output signal to said data link; wherein the multiplexer is adapted to selectively output the digital data signal and the patterned data signal as the multiplexer output signal in response to receiving the mode selection signal, the mode selection signal representing an idle mode of the transmitter and a data signal transmission mode of the transmitter.

12. 12. The system of claim 11, further comprising a switch disposed between the memory and the patterned data signal input for intermittently communicating the patterned data signal to the patterned data signal input.

13. The system of claim 11 , wherein a processor comprises at least one of the memory and the transmitter.

14. 14. The system of claim 13, wherein the memory comprises a processor register that stores the data for generating the patterned data signal.

15. 15. The system of claim 14, further comprising a serializer operably coupled to the processor register and the second input, the serializer adapted to serialize the data to generate the patterned data signal.

16. The system of claim 11 , further comprising a mode selection controller adapted to provide the mode selection signal based on the digital data signal.

17. 17. The system of claim 16, wherein the mode selection controller is adapted to provide the mode selection signal in response to the digital data signal including a flow control message indicating the idle mode.

18. 17. The system of claim 16, wherein the mode selection controller is adapted to provide the mode selection signal in response to the digital data signal including a flow control message indicating the data signal transmission mode.

19. 12. The system of claim 11, wherein the transmitter is arranged to transmit a clockless data signal as the digital data signal.

20. 12. The system of claim 11, wherein the memory comprises a programmable memory arranged to receive the data for generating the patterned data signal.

21. A computer program comprising a program code adapted to perform the steps of the method according to any one of claims 1 to 10, when said program is run on a computer.

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