Pixel architecture with multi-pixel binning

Abstract

A structure is disclosed for binning sets of two or more pixels in a pixel array to share the same readout circuit. The binned pixel design provides the advantage of space savings on the chip and also improves overall image quality. In some embodiments, each binned pixel includes a photodetector and its own transfer gate. The readout circuit includes its own second transfer gate connected to the transfer gate of each binned pixel and isolating the pixel from a gain mode selection block. The gain mode selection block may include capacitors of different sizes and one or more switches that control which capacitors receive charge from any one of the binned pixels. The readout circuit may further include a potential barrier (e.g., a diode) that allows charge to be pumped to one or more capacitors in the gain mode selection block.

Description

[Background technology]

[0001] Image sensors are widely used in many different applications across a large portion of the electromagnetic spectrum. Many image sensor designs use an array of sensors that capture light over a given region. Each sensor may be considered a pixel in a sensor array, with the pixels arranged in any number of rows and columns. Each pixel contains some form of photodetector and circuitry that collects charge from the photodetector in response to light input. Designing circuitry that provides both a high dynamic range and a high conversion gain presents a number of significant challenges. [Brief explanation of the drawings]

[0002] [Figure 1] FIG. 1 is a block diagram of an image sensor using a pixel array according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a block diagram illustrating various components of a binned set of pixels of the pixel array of FIG. 1 according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic diagram illustrating the binned pixels of FIG. 2 according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a timing diagram for various signals that control certain elements of the binned pixel circuit of FIG. 3 in a first mode of operation, according to an embodiment of the present disclosure. [Figure 5] FIG. 4 is a timing diagram for various signals that control certain elements of the binned pixel circuit of FIG. 3 in a second mode of operation, according to an embodiment of the present disclosure. [Figure 6] 2 illustrates an example computing platform that may include the image sensor of FIG. 1 according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0003] These and other features of the present embodiments will be better understood from the following detailed description taken in conjunction with the drawings described herein.

[0004] A structure is disclosed for binned sets of pixels (e.g., 2x2 sets of pixels) of a pixel array that share the same readout circuit. The binned pixel design provides the advantage of space savings on the chip and also improves overall image quality. In some embodiments, each binned pixel includes a photodetector and its own transfer gate. The readout circuit includes its own second transfer gate connected to the transfer gate of each binned pixel and isolating the pixel from the gain mode selection block. The gain mode selection block may include capacitors of different sizes and one or more switches that control which capacitors receive charge from any one of the binned pixels. Depending on the state of the one or more switches, different conversion gains can be selected to increase the dynamic range of the pixel. The readout circuit may further include a potential barrier (e.g., a diode) that allows charge to be pumped to one or more capacitors of the gain mode selection block. The photodetector signal may be amplified via a source follower component and ultimately readout to a column amplifier.

[0005] overview As noted above, there remain numerous significant challenges in designing pixel arrays for image sensors. For example, the charge from each pixel must be read out using a readout circuit with a given conversion gain. When thousands of pixels are used in an array, problems arise in fitting the necessary components for so many readout circuits, especially when capacitors are used to adjust the conversion gain as variously described herein, given that capacitors occupy a relatively large amount of space on a chip.

[0006] Therefore, and in accordance with embodiments of the present disclosure, techniques are disclosed for designing pixel arrays having binned pixels that share a common readout circuit. The sensor array of pixels can be, for example, any type of charge-coupled device (CCD) designed to receive light for the purpose of generating an image from the light received across the sensor array, although other pixel-based imaging arrays may also be useful. The pixels can be binned, for example, into a 2x2 array, although other arrangements are possible. Furthermore, five or more pixels may be binned with a common readout circuit, although four is used as an example throughout this disclosure. Each pixel may have its own photodetector and its own transfer gate (e.g., a set of first transfer gates), while the readout circuit includes a single second transfer gate that transfers charge from any of the binned pixels to a sensing node.

[0007] In some embodiments, a sense node in the readout circuit is configured to be connected to one or more different capacitors based on the state of one or more switches in the readout circuit. By varying which capacitor is used to store charge from the sense node, in some embodiments, different conversion gains can be achieved for the charge read from the photodetector based on the total capacitance connected to the sense node. For any selected conversion gain, the charge received from a given photodetector of a binned pixel can be used to generate a current signal that is ultimately supplied to a column amplifier or other amplifier element before being converted to a digital signal via an analog-to-digital converter (ADC).

[0008] In some embodiments, the potential barrier may be connected to the output of the second transfer gate of the readout circuit (between the output of the second transfer gate and ground). By including the potential barrier, the second transfer gate may act as a pump gate that pumps charge to the sense node. In some embodiments, readout circuits with or without the potential barrier operate in a first mode in which the second transfer gate provides a single on / off transfer of charge to the sense node, and readout circuits with the potential barrier operate in a second mode in which the transfer gate may pump charge to the sense node any number of times. A PN diode is an example of a potential barrier.

[0009] According to an exemplary embodiment, the CCD includes at least two pixels, each pixel of the at least two pixels including a photodetector and a corresponding first transfer gate connected to the photodetector, a second transfer gate having an input connected to the output of each of the first transfer gates of each of the at least two pixels, a potential barrier connected to the output of the second transfer gate, and a capacitor connected to the output of the second transfer gate. In some embodiments, the CCD includes a second capacitor and a switch connected between the output of the second transfer gate and the second capacitor. The potential barrier may be a PN diode.

[0010] According to other exemplary embodiments, an image sensor includes a pixel array having at least one column of addressable pixels, a readout circuit, column amplifiers connected to the readout circuit, an analog-to-digital converter (ADC) connected to the column amplifiers, and a processor connected to the ADC. The at least one column of addressable pixels includes at least two pixels, each of the at least two pixels including a photodetector and a corresponding first transfer gate connected to the photodetector. The readout circuit includes a second transfer gate having an input connected to the output of each of the first transfer gates of each of the at least two pixels, a potential barrier connected to the output of the second transfer gate, and a capacitor connected to the output of the second transfer gate. According to some such exemplary embodiments, the readout circuit further includes a second capacitor and a switch connected between the output of the second transfer gate and the second capacitor.

[0011] According to another exemplary embodiment, the CCD includes four pixels, each pixel of the four pixels including a photodetector and a corresponding first transfer gate connected to the photodetector, a second transfer gate having a single input connected to the output of each of the first transfer gates of each of the four pixels, and a capacitor connected to the output of the second transfer gate. According to some embodiments, the CCD further includes a second capacitor and a switch connected between the output of the second transfer gate and the second capacitor. The four pixels may be arranged in, for example, a 2x2 grid, although other grids may be used.

[0012] The description uses the phrases "in one embodiment" or "in embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, when used with respect to embodiments of the present disclosure, are synonymous.

[0013] Various operations may be described as multiple independent acts or operations and in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that the operations are necessarily order dependent. In particular, the operations need not be performed in the order presented. The operations described may be performed in a different order than in the described embodiment. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

[0014] System Architecture FIG. 1 is a block diagram of an exemplary image sensor 100 according to some embodiments. Image sensor 100 may be, or may be an integral part of, a charge-coupled device (CCD) camera or other type of imaging device. In some embodiments, image sensor 100 may be configured to capture different portions of the electromagnetic spectrum, such as visible light, ultraviolet light, infrared light, or X-rays, to name a few. Image sensor 100 may include a pixel array 102, column amplifiers 106, an ADC 108, and a processor 110. Each of the illustrated components may be included together on the same printed circuit board (PCB) or in a single chip package (e.g., a system-in-package or system-on-chip). In some other embodiments, any one or more of the elements may be provided in separate chip packages and / or on separate PCBs.

[0015] In some embodiments, the pixel array 102 includes a plurality of pixels arranged in a matrix. Each pixel in the pixel array 102 may have a similar architecture, including a photodetector and a transfer gate. The photodetection area of ​​each pixel that may be impinged by incident radiation may vary from embodiment to embodiment, but in some exemplary cases has a physical size of about 1 μm×1 μm to about 5 μm×5 μm. Similarly, the shape of the photodetection area (e.g., photodiode) and lens configuration (if present) may also vary from example to example, depending on factors such as the desired fill factor of the array. In some embodiments, each row of pixels may be connected together to a common row select line (e.g., word line) to provide an individually addressable row of pixels.

[0016] As shown in the bubble, a group of pixels can be binned together to share a common readout circuit. In the illustrated example, four pixels in a 2x2 array have each of their transfer gates (TX1A-TX1D) connected to a common readout circuit that reads charge from each photodetector of each binned pixel. As noted above, any number and arrangement of pixels in pixel array 102 can be binned together to share a common readout circuit.

[0017] In some embodiments, outputs from N different columns of pixels are received by column amplifiers 106. In some embodiments, column amplifiers 106 represent N separate column amplifiers, with a given column amplifier configured to receive outputs from a corresponding column of pixels (i.e., binned pixels of the corresponding column) of pixel array 102. In this manner, pixels in a given row (i.e., one row of binned pixels) of pixel array 102 can be selected via a row select line and simultaneously read out via the N column amplifiers 106. In some embodiments, column amplifiers 106 can include any type of amplifier configuration, such as any number of source follower FETs or operational amplifiers. In some embodiments, a single column amplifier 106 can be used in conjunction with a multiplexer to receive each of the N column outputs from pixel array 102.

[0018] In some embodiments, binned groups of pixels (such as the illustrated 2x2 array of pixels connected to common readout circuitry) are arranged in rows and columns across pixel array 102. In this way, the total number of column amplifiers may be reduced, as a single column amplifier reads from a given column of binned pixels rather than a single column of pixels.

[0019] In some embodiments, the outputs from the column amplifiers 106 are received by the ADCs 108. As noted above, the ADCs 108 may be N different ADCs, with a given ADC configured to receive the output from a corresponding column amplifier 106. The ADCs 108 may be any known type of ADC, without limitation.

[0020] The processor 110 may be configured to receive the digitized signals from the ADC 108 (or N digitized signals across the N ADCs) and perform any number of operations on the signals. For example, the processor 110 may receive signal data from a given row of pixels (i.e., a row of binned pixels) of the pixel array 102 and use the signal data to generate an image or portion of an image captured by the pixel array 102. As used herein, the term “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory. The processor 110 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, custom semiconductors, or any other suitable processing devices.

[0021] Binned pixel design 2 illustrates a block diagram of a group of binned pixels 200 of pixel array 102, which includes four binned pixels, each of which is connected to readout circuitry 203, according to some embodiments. Each of the four binned pixels includes a photodetector 202A-202D and a corresponding transfer gate 204A-204D. The photodetectors 202A-202D may include any type of photosensitive design, such as a PN diode. Note that the term "pixel," as used herein, may refer to the photodetection area of ​​a given pixel as well as the functional pixel circuitry.

[0022] In some embodiments, the readout circuit 203 includes a transfer gate 206 connected to the output of each of the four pixel transfer gates 204A-204D. The transfer gate 206 acts like a gatekeeper for the charge generated by any one of the photodetectors 202A-202D in response to the light input. In some embodiments, the transfer gate 206 may include a single field effect transistor (FET), such as a p-doped or n-doped metal oxide semiconductor device (PMOS or NMOS). In some embodiments, a potential barrier, such as a PN diode, is connected to the output of the transfer gate 206 to enable charge pumping through the transfer gate 206.

[0023] In some embodiments, transfer gate 206 is configured to allow charge from any one of photodetectors 202A-202D to be transferred to gain mode selection block 208, where the charge is stored in one or more selected capacitors. As noted above, the active area (e.g., the area sensitive to incident light and generating a corresponding signal based on the intensity of that light) and optional lens configuration of a given photodetector may vary depending on a given application. Gain mode selection block 208 may include one or more switches and any number of capacitors, the states of which can be used to select an operating conversion gain mode. For example, one switch and two capacitors may be arranged to enable two different conversion gain modes. In another example, two switches and three capacitors may be arranged to enable three different conversion gain modes. However, other layouts may include more switches and / or more capacitors to create any number of additional conversion gain modes. Charge passing through transfer gate 206 may be stored at a given conversion gain based on which capacitor is connected to the sense node in gain mode selection block 208.

[0024] In some embodiments, the sense node of the gain mode select block 208, which is connected to the selected capacitor or capacitors, is further connected to an amplifier 210 that generates an output signal. The amplifier 210 may be implemented as a single source follower NMOS or PMOS device or as an operational amplifier.

[0025] In some embodiments, the row select switch 212 is included within the readout circuitry 203. The row select switch 212 may have a gate or select input connected to a common row line (e.g., a word line) along with other pixels in the same row (i.e., binned pixels). Thus, when the current row is activated to be read out, the row select switch 212 is activated and turned on to read out an output signal to the column amplifiers 106. When the current row is not selected, the row select switch 212 is not activated and no signal is read out to the column amplifiers 106. The row select switch 212 may be implemented, for example, as an NMOS or PMOS device, with the row line connected to the gate of the NMOS or PMOS device.

[0026] 3 shows an example circuit diagram of a given group of binned pixels of pixel array 102 along with a shared readout circuit, according to some embodiments. Each of the illustrated FETs can be either an NMOS or PMOS device, depending on the layout. Furthermore, in some embodiments, any of the FETs may be replaced with other transistor architectures, such as a bipolar junction transistor (BJT). According to some embodiments, the pixel readout circuit includes a current source I that provides a bias current for operating a source follower amplifier SF. b Includes:

[0027] In some embodiments, four pixels are connected to a single transfer gate TX2 of the readout circuit. More specifically, each of the four pixels includes a photodetector PD and a first transfer gate (one of TX1A-TX1D). In some embodiments, only one pixel receives charge at any given time. Thus, only one of the first transfer gates TX1A-TX1D may be activated at any given time to utilize charge from the corresponding photodetector PD.

[0028] When light strikes each photodetector PD, it is converted into an electric charge that can flow as a photocurrent. At a given moment, at least a portion of the converted electric charge from one of the pixels is released to a sense node SN through its corresponding first transfer gate TX1A-TX1D and second transfer gate TX2 by turning on each of the gates for a predetermined number of clock cycles. Once the electric charge is released to the sense node SN, it can be stored in various capacitors depending on the state of switch DCG. In one example, DCG is turned off (e.g., unbiased) so that the electric charge at the sense node SN is stored only in the first capacitor Cfd. In some examples, capacitor Cfd may have a relatively small capacitance of about 1 femtofarad (fF) or about 0.2 fF to about 3 fF. The conversion gain may be relatively high in this first configuration, such as about 170 μV / electron to about 200 μV / electron. In another example, the DCG is turned on (e.g., biased) so that the charges at both the sense node SN and the second node N2 are stored in the parallel first capacitor Cfd and second capacitor Cg1. In some examples, the capacitor Cg1 may have a high capacitance compared to the capacitor Cfd. For example, the capacitor Cg1 may have a capacitance of about 10 fF or about 5 fF to about 15 fF. The conversion gain in the second configuration may be relatively lower than the conversion gain in the first configuration described above. For example, the conversion gain in the second configuration may be about 17 μV / electron to about 20 μV / electron.

[0029] In some embodiments, the readout circuit may include a potential barrier (shown as a diode PN) connected to the sense node SN (e.g., in parallel with the capacitor Cfd). The inclusion of the potential barrier PN enables the second transfer gate TX2 to act as a pump gate PG that pumps charge to the sense node SN. In some embodiments, a first mode of operating the readout circuit transfers charge to the sense node SN through the second transfer gate TX2 with a single charge transfer for both low and high conversion gain situations, as shown in more detail by the timing diagram of FIG. 4. In some embodiments, a second mode of operating the readout circuit transfers charge to the sense node SN with multiple pumped charge transfers through the second transfer gate TX2 (or pump gate PG in the second operating mode) for either or both low and high conversion gain situations, as shown in more detail by the timing diagram of FIG. 5.

[0030] In any of the above modes of operation, the stored potential (at a given conversion gain based on the state of switch DCG) activates source follower amplifier SF to generate an output signal to send to column amplifier 106. Source follower amplifier SF can be a single FET device or any other amplifier structure, such as an operational amplifier. Source follower amplifier SF can be powered by a power rail VPix, for example, between about 2 V and about 2.5 V, or other suitable rail voltage. The output signal generated by source follower amplifier SF can only be sent to column amplifier 106 when row select switch RS is biased. In some such examples, all pixels in a given row (i.e., binned pixels) of pixel array 102 share the same row select line (e.g., word line) that connects to the gate of row select switch RS. If row select switch RS is not biased, the current pixel (i.e., binned set of pixels) is part of a row that is not currently being read out, and no signal is sent from the current pixel (i.e., binned set of pixels) to column amplifier 106.

[0031] In some embodiments, the potential of either the sensing node SN or the second node N2 can be reset to a baseline or reference value by a reset switch RST. When the reset switch RST is biased, the rail voltage VPix is ​​applied to all of the nodes connected to the end of the reset switch RST. For example, when the reset switch RST is biased to apply the voltage VPix to both the sensing node SN and the second node N2, DCG can also be biased to overwrite all of the charge from any of the photodetectors PD. Although the reset switch RST is connected to the second node N2, the reset switch RST may be connected to any node in the readout circuit, such as the sensing node SN.

[0032] Timing diagrams for various operating modes 4 and 5 each provide example timing diagrams for various of the above-described operational modes of the pixel readout circuit. FIG. 4 provides an example timing diagram for various control signals during a first operational mode (e.g., only one charge transfer occurs for the second transfer gate TX2). FIG. 5 provides an example timing diagram for various control signals during a second operational mode (e.g., multiple charge pumps to the sense node SN). Note that for both timing diagrams, TX1 refers to a single first transfer gate (e.g., one of TX1A-TX1D) of one of the binned pixels. Therefore, the various operations performed in a given timing diagram are repeated for each of the other first transfer gates in the binned pixels.

[0033] For both modes of operation, the same first initialization period t is used to reset the potentials of various nodes around the circuit before light capture occurs. i1 A first initialization period t i1In , RST is biased for at least one clock cycle while DCG, TX1, and TX2 are also biased. During this time, all nodes connected to DCG, TX1, and TX2 are reset at the rail voltage VPix. In some embodiments, the various switches are then turned off in this order: TX1 is debiased first, followed by both DCG and TX2. During this process, the row select RS does not need to be biased, since no pixels are being read during this time.

[0034] In some embodiments, for either mode of operation, a second initialization period t i2 A second initialization period t i2 In the first initialization period t, RST is biased for at least one clock cycle while both DCG and TX2 are biased. During this time, all nodes connected to DCG and TX2 are reset to the rail voltage VPix. i1 Unlike in the previous example, the node connected to the photodetector PD is not reset because it now retains charge from receiving light. In some embodiments, the various switches are then turned off in order, first TX2, then DCG, to be unbiased. During this process, the row select RS can be biased to begin reading a baseline value from one of the nodes.

[0035] Referring to FIG. 4, after initialization proceeds in the first mode of operation, the row select RS remains biased during the first period t1, and a baseline reading is captured at the potential of the sense node SN. During the second period t2, photodetector charge is dumped to the sense node SN by biasing both TX1 and TX2. During the third period t3, TX1 is unbiased, while TX2 remains biased, to ensure that any photodetector charge remaining in the line between TX1 and TX2 is dumped to the sense node SN. During the fourth period t4, TX2 is unbiased, and a reading is captured from the sense node SN with the charge stored on capacitor Cfd because DCG is unbiased. Because only capacitor Cfd is used, this reading has a relatively high conversion gain. During the fifth period t5, DCG is also biased along with both TX1 and TX2, so the photodetector charge is dumped to both the sense node SN and the second node N2. During the sixth period t6, TX1 is unbiased and TX2 remains biased to ensure that any photodetector charge remaining in the line between TX1 and TX2 is bled to both the sense node SN and the second node N2. During the seventh period t7, TX2 is unbiased, and because DCG is still biased, a reading is captured from the sense node SN and the second node N2 of the charge stored on the parallel capacitors Cfd and Cg1. Due to the use of parallel capacitors Cfd and Cg1, this reading has a lower conversion gain compared to the reading obtained during the fourth period t4. During the eighth period t8, RST is biased to reset the potentials of both the sense node SN and the second node N2 back to the baseline rail voltage VPix. During the ninth period t9, a baseline reading is captured of the potentials of both the sense node SN and the second node N2.

[0036] In some embodiments, the baseline readings are compared to signal readings to capture differences associated with the amount of light incident on a given one of the binned pixel photodetectors PD. For example, during a first mode of operation, a baseline reading captured at time period t1 is compared to a signal reading captured at time period t4, and a baseline reading captured at time period t9 is compared to a signal reading captured at time period t7.

[0037] Referring to FIG. 5, after initialization proceeds in the second mode of operation, the row select RS remains biased during the first period t1, and a baseline reading is captured at the potential of the sense node SN. During the second period t2, photodetector charge is dumped to the sense node SN by biasing both TX1 and TX2. During the third period t3, TX1 is unbiased, while TX2 remains biased, to ensure that any photodetector charge remaining in the line between TX1 and TX2 is dumped to the sense node SN. During the fourth period t4, TX2 is unbiased, and a reading is captured from the sense node SN with the charge stored on capacitor Cfd because DCG is unbiased. Because only capacitor Cfd is used, this reading has a relatively high conversion gain. During the fifth period t5, DCG is also biased along with both TX1 and TX2, so the photodetector charge is dumped to both the sense node SN and the second node N2. During the sixth period t6, TX1 is unbiased and TX2 remains biased to ensure that any photodetector charge remaining on the line between TX1 and TX2 is discharged to both the sense node SN and the second node N2. The operations performed during the fifth and sixth periods t5 and t6 to discharge charge to the sense node SN and the second node N2 can be considered a first charge pump operation. During the seventh period t7, the photodetector charge is redischarged to the sense node SN and the second node N2 by biasing TX1 back (and also by biasing both TX2 and DCG). This charge accumulates with the charge previously pumped using the potential barrier PN. During the eighth period t8, TX1 is unbiased and TX2 remains biased to ensure that any photodetector charge remaining on the line between TX1 and TX2 is discharged to both the sense node SN and the second node N2. The operation performed during the seventh period t7 and the eighth period t8 of discharging charge into the sense node SN and the second node N2 can be considered a second charge pump operation.

[0038] In some embodiments, the third charge pump operation occurs during the ninth and tenth periods (t9 and t 10) to pump more charge into the sense node SN and the second node N2. The third charge pump operation functions similarly to both the first and second charge pump operations. Any number of successive charge pump operations may be performed in this manner to continue accumulating charge at the sense node SN and the second node N2. In some embodiments, a read may be performed following any of the charge pump operations as long as RS remains biased.

[0039] 11th period t 11 In the twelfth period t4, the final pumping operation is completed and the DCG is still biased, so a reading is captured from the sense node SN and the second node N2 with the charge stored on the parallel capacitors Cfd and Cg1. Because parallel capacitors Cfd and Cg1 are used, this reading has a lower conversion gain compared to the reading taken in the fourth period t4. The pumping operation allows more charge to be present across the sense node SN and the second node N2, which may help compensate for the lower conversion gain. In the twelfth period t5, 12 During the thirteenth period t, RST is biased to reset the potentials of both the sense node SN and the second node N2 back to the baseline rail voltage VPix. 13 Now, a baseline reading is taken at the potential of both the sense node SN and the second node N2.

[0040] In some embodiments, the baseline reading is compared to the signal reading to capture differences related to the amount of light incident on a given one of the binned pixel photodetectors PD. For example, during the second mode of operation, a baseline reading captured during time period t1 is compared to a signal reading captured during time period t4, and a baseline reading captured during time period t5 is compared to a signal reading captured during time period t6. 13 The baseline reading captured during period t 11 The signal reading is compared to the signal readout captured by the

[0041] Exemplary Computing Platform 6 illustrates an exemplary computing platform 600 interfacing with image sensor 100 configured in accordance with certain embodiments of the present disclosure. In some embodiments, computing platform 600 may host or be incorporated into a personal computer, a workstation, a server system, a laptop computer, an ultra-laptop computer, a tablet, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a mobile phone, a combination mobile phone and PDA, a smart device (e.g., a smartphone or smart tablet), a mobile internet device (MID), a messaging device, a data communication device, an imaging device, a wearable device, an embedded system, or the like. Any combination of various devices may be used in certain embodiments. Computing platform 600 may host a controller area network (CAN) used in a vehicle. In some embodiments, computing platform 600 represents one system in a network of systems interconnected via a CAN bus.

[0042] In some embodiments, computing platform 600 may include any combination of processor 602, memory 604, image sensor 100, network interface 606, input / output (I / O) system 608, user interface 610, and storage system 612. In some embodiments, one or more components of image sensor 100 are implemented as part of processor 602. As will be further appreciated, buses and / or interconnects are also provided to enable communication between the various components listed above and / or other components not shown. Computing platform 600 may be connected to a network 616 via network interface 606 to enable communication with other computing devices, platforms, or resources. Other components and functionality not reflected in the block diagram of FIG. 6 will be apparent in light of this disclosure, and it should be understood that other embodiments are not limited to a particular hardware configuration.

[0043] Processor 602 may be any suitable processor and may include one or more coprocessors or controllers that assist in control and processing operations associated with computing platform 600. In some embodiments, processor 602 may be implemented as any number of processor cores. A processor (or processor core) may be any type of processor, such as, for example, a microprocessor, an embedded processor, a digital signal processor (DSP), a graphics processor (GPU), a network processor, a field programmable gate array, or other device configured to execute code. A processor may be a multithreaded core that may include two or more hardware thread contexts (i.e., "logical processors") per core.

[0044] Memory 604 may be implemented using any suitable type of digital storage, such as, for example, flash memory and / or random access memory (RAM). In some embodiments, memory 604 may include various layers of memory hierarchy and / or memory caches known to those skilled in the art. Memory 604 may be implemented as a volatile memory device, such as, but not limited to, a RAM, a dynamic RAM (DRAM), or a static RAM (SRAM) device. Storage system 612 may be implemented as a non-volatile storage device, such as, but not limited to, one or more of a hard disk drive (HDD), a solid-state drive (SSD), a universal serial bus (USB) drive, an optical disk drive, a tape drive, an internal storage device, an external storage device, flash memory, a battery-backed synchronous DRAM (SDRAM), and / or a network-accessible storage device. In some embodiments, storage system 612 may include technology to enhance storage performance and protection for valuable digital media when multiple hard drives are included.

[0045] Processor 602 may be configured to execute operating system (OS) 614, which may comprise any suitable operating system, such as Google Android® (Google, Inc., Mountain View, Calif.), Microsoft Windows® (Microsoft Corporation, Redmond, Wash.), Apple OS X (Apple Inc., Cupertino, Calif.), Linux®, or a real-time operating system (RTOS). As will be appreciated in light of this disclosure, the techniques provided herein may be implemented regardless of the particular operating system provided in conjunction with computing platform 600, and thus may be implemented using any suitable existing or later-developed platform.

[0046] The network interface 606 may be any suitable network chip or chipset that enables wired and / or wireless connections between the computing platform 600 and / or other components of the network 616, thereby enabling the computing platform 600 to communicate with other local and / or remote computing systems, servers, cloud-based servers, and / or other resources. The wired communication may conform to existing (or yet to be developed) standards such as, for example, Ethernet. The wireless communication may conform to existing (or yet to be developed) standards such as, for example, Long Term Evolution (LTE), Wireless Fidelity (Wi-Fi), Bluetooth, and / or Near Field Communication (NFC). Exemplary wireless networks include, but are not limited to, wireless local area networks, wireless personal area networks, wireless metropolitan area networks, cellular networks, and satellite networks.

[0047] The I / O system 608 may be configured to interface between various I / O devices and other components of the computing platform 600. The I / O devices may include, but are not limited to, a user interface 610. The user interface 610 may include devices (not shown), such as a display element, a touchpad, a keyboard, a mouse, and speakers. The I / O system 608 may include a graphics subsystem configured to process images for rendering on a display element. The graphics subsystem may be, for example, a graphics processing unit or a visual processing unit (VPU). An analog or digital interface may be used to communicatively connect the graphics subsystem to the display element. For example, the interface may be any of High-Definition Multimedia Interface (HDMI), DisplayPort, Wireless HDMI, and / or any other suitable interface using wireless high-definition enabled technology. In some embodiments, the graphics subsystem may be integrated into the processor 602 or any chipset of the computing platform 600.

[0048] It should be appreciated that in some embodiments, the various components of computing platform 600 may be combined or integrated into a system-on-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0049] In various embodiments, computing platform 600 may be implemented as a wireless system, a wired system, or a combination of both. If implemented as a wireless system, computing platform 600 may include components and interfaces suitable for communication over a wireless shared medium, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, control logic, etc. Examples of wireless shared media may include portions of a wireless spectrum, such as the radio frequency spectrum. If implemented as a wired system, computing platform 600 may include components and interfaces suitable for communication over a wired communication medium, such as input / output adapters, physical connectors connecting the input / output adapters to corresponding wired communication media, network interface cards (NICs), disk controllers, video controllers, audio controllers, etc. Examples of wired communication media may include wires, cable metal leads, printed circuit boards (PCBs), backplanes, switch fabrics, semiconductor materials, twisted pair wires, coaxial cable, fiber optics, etc.

[0050] Unless otherwise specified, terms such as "processing," "computing," "calculating," "determining," and the like may be understood to refer to the operations and / or processing of a computer or computer system or similar electronic computing device that manipulates and / or transforms data represented as physical quantities (e.g., electronic quantities) in the registers and / or memory units of the computer system into other data similarly represented as physical quantities in the registers, memory units, or other such information storage and transmission or display of the computer system. Embodiments are not limited in this context.

[0051] The term "circuit" or "circuitry" as used herein in any embodiment may include, for example, alone or in any combination, hardwired circuitry, programmable circuitry such as a computer processor with one or more individual instruction processing cores, state machine circuitry, and / or firmware that stores instructions executed by the programmable circuitry. The circuitry may include a processor and / or controller configured to execute one or more instructions to perform one or more operations described herein. The instructions may be embodied, for example, as an application, software, firmware, etc. configured to cause the circuitry to perform any of the operations described above. Software may be embodied as a software package, code, instructions, instruction sets, and / or data recorded on a computer-readable storage device. Software may be implemented or performed to include any number of processes, and processes may be implemented or performed to include any number of threads, etc., in a hierarchical manner. Firmware may be embodied as hard-coded (e.g., non-volatile) code, instructions, instruction sets, and / or data in a memory device. The circuits may be implemented as circuits that collectively or individually comprise part of a larger system, such as an integrated circuit (IC), an application specific integrated circuit (ASIC), a system on a chip (SoC), a desktop computer, a laptop computer, a tablet computer, a server, a smartphone, etc. Other embodiments may be implemented as software executed by a programmable control device. As described herein, various embodiments may be implemented using hardware elements, software elements, or any combination thereof. Examples of hardware elements may include a processor, a microprocessor, a circuit, a circuit element (e.g., a transistor, a resistor, a capacitor, an inductor, etc.), an integrated circuit, an application specific integrated circuit (ASIC), a programmable logic device (PLD), a digital signal processor (DSP), a field programmable gate array (FPGA), a logic gate, a register, a semiconductor device, a chip, a microchip, a chipset, etc.

[0052] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices, digital signal processors, FPGAs, GPUs, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The decision of whether an embodiment is implemented using hardware and / or software elements may depend on any number of factors, such as desired computational speed, power levels, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speeds, and other design or performance constraints.

[0053] Further exemplary embodiments The following examples relate to further embodiments, from which numerous variations and configurations should become apparent.

[0054] Example 1 is a charge-coupled device (CCD) including a first pixel and a second pixel, each of which includes a photodetector and a corresponding first transfer gate connected to the photodetector. The CCD further includes a second transfer gate having an input connected to the output of each of the first transfer gates of the first and second pixels, a potential barrier connected to the output of the second transfer gate, and a capacitor connected to the output of the second transfer gate.

[0055] A second embodiment includes the CCD according to the first embodiment, and the first transfer gate corresponding to each of the first and second pixels is a field effect transistor (FET).

[0056] Example 3 includes the CCD according to example 1 or 2, wherein the capacitor is a first capacitor, and the CCD includes a second capacitor and a switch connected between the output of the second transfer gate and the second capacitor.

[0057] A fourth embodiment includes the CCD according to the third embodiment, wherein the second capacitor has a higher capacitance than the first capacitor.

[0058] Example 5 includes the CCD according to example 3 or 4, and further includes a reset switch connected to the shared node between the switch and the second capacitor.

[0059] A sixth embodiment includes a CCD according to any one of the first to fifth embodiments, and the potential barrier is a PN diode.

[0060] A seventh embodiment includes the CCD according to any one of the first to sixth embodiments, and the output of the second transfer gate is connected to the gate of the FET.

[0061] Example 8 includes the CCD according to any one of Examples 1 to 7, wherein the first and second pixels are arranged in a 2x2 grid with four pixels.

[0062] Example 9 is an image sensor including a pixel array having at least one column of addressable pixels, a readout circuit, column amplifiers connected to the readout circuit, an analog-to-digital converter (ADC) connected to the column amplifiers, and a processor connected to the ADC. The at least one column of addressable pixels includes at least two pixels, each pixel of the at least two pixels including a photodetector and a corresponding first transfer gate connected to the photodetector. The readout circuit includes a second transfer gate having an input connected to the output of each of the first transfer gates of each of the at least two pixels, a potential barrier connected to the output of the second transfer gate, and a capacitor connected to the output of the second transfer gate.

[0063] Example 10 includes the image sensor according to Example 9, in which the corresponding first transfer gate of each of the at least two pixels is a field effect transistor (FET).

[0064] Example 11 includes the image sensor according to Example 9 or 10, wherein the capacitor is a first capacitor, and the readout circuit includes a second capacitor and a switch connected between the output of the second transfer gate and the second capacitor.

[0065] A twelfth example includes the image sensor according to the eleventh example, in which the second capacitor has a higher capacitance than the first capacitor.

[0066] Example 13 includes the image sensor according to example 11 or 12, in which the readout circuit further comprises a reset switch connected to the shared node between the switch and the second capacitor.

[0067] A fourteenth embodiment includes the image sensor according to any one of the ninth to thirteenth embodiments, and the potential barrier is a PN diode.

[0068] A fifteenth embodiment includes the image sensor according to any one of the ninth to fourteenth embodiments, wherein the output of the second transfer gate is connected to the gate of the FET.

[0069] Example 16 includes the image sensor according to any one of Examples 9 to 15, wherein the at least two pixels include four pixels arranged in a 2x2 grid.

[0070] Example 17 is a charge-coupled device (CCD) including four pixels, each pixel including a photodetector and a corresponding first transfer gate connected to the photodetector, a second transfer gate having a single input connected to the output of each of the first transfer gates of each of the four pixels, and a capacitor connected to the output of the second transfer gate.

[0071] An eighteenth embodiment includes the CCD according to the seventeenth embodiment, in which the first transfer gate corresponding to each of the four pixels is a field effect transistor (FET).

[0072] Example 19 includes the CCD according to example 17 or 18, wherein the capacitor is a first capacitor, and the CCD includes a second capacitor and a switch connected between the output of the second transfer gate and the second capacitor.

[0073] Example 20 includes the CCD according to Example 19, wherein the second capacitor has a higher capacitance than the first capacitor.

[0074] Example 21 includes the CCD according to example 19 or 20, further comprising a reset switch connected to the shared node between the switch and the second capacitor.

[0075] Example 22 includes the CCD according to any one of Examples 17 to 21, and the second transfer gate is a FET.

[0076] A twenty-third embodiment includes the CCD according to any one of the seventeenth to twenty-second embodiments, and the output of the second transfer gate is connected to the gate of the FET.

[0077] A twenty-fourth embodiment includes the CCD according to any one of the seventeenth to twenty-third embodiments, and four pixels are arranged in a 2×2 grid.

[0078] Numerous specific details have been described herein to provide a thorough understanding of the embodiments. However, it will be understood by those skilled in the art that the embodiments may be practiced without these specific details. In other instances, well-known operations, components, and circuits have not been described in detail so as not to obscure the embodiments. It will be understood that specific structural and functional details disclosed herein are representative and do not necessarily limit the scope of the embodiments. Furthermore, although subject matter has been described in language specific to structural features and / or methodological acts, it will be understood that the subject matter defined in the following claims is not necessarily limited to the specific features or acts described herein. Rather, the specific features and acts described herein are disclosed as example forms of implementing the claims.

Claims

1. a charge coupled device (CCD), a first pixel and a second pixel, each of the first and second pixels including a photodetector and a corresponding first transfer gate connected to the photodetector; a second transfer gate having an input connected to the output of each of the first transfer gates of the first and second pixels; a potential barrier connected to the output of the second transfer gate; a capacitor connected to the output of the second transfer gate; A CCD equipped with:

2. 2. The CCD of claim 1, wherein the corresponding first transfer gate of each of the first and second pixels is a field effect transistor (FET).

3. the capacitor is a first capacitor; 2. The CCD of claim 1, further comprising: a second capacitor; and a switch connected between the output of the second transfer gate and the second capacitor.

4. 4. The CCD of claim 3, wherein the second capacitor has a higher capacitance than the first capacitor.

5. 4. The CCD of claim 3, further comprising a reset switch connected to a shared node between the switch and the second capacitor.

6. 2. The CCD of claim 1, wherein the potential barrier is a PN diode.

7. 2. The CCD of claim 1, wherein the output of the second transfer gate is connected to the gate of an FET.

8. 2. The CCD of claim 1, wherein the first and second pixels are arranged in a 2x2 grid of four pixels.

9. An image sensor, a pixel array having at least one column of addressable pixels, the at least one column of addressable pixels including at least two pixels, each pixel of the at least two pixels including a photodetector and a corresponding first transfer gate connected to the photodetector; a readout circuit; a column amplifier connected to the readout circuit; an analog-to-digital converter (ADC) connected to the column amplifiers; a processor connected to the ADC; Equipped with The readout circuit includes: a second transfer gate having an input connected to the output of each first transfer gate of each of the at least two pixels; a potential barrier connected to the output of the second transfer gate; a capacitor connected to the output of the second transfer gate; An image sensor comprising:

10. 10. The image sensor of claim 9, wherein the capacitor is a first capacitor, and the readout circuitry comprises a second capacitor and a switch connected between the output of the second transfer gate and the second capacitor.

11. The image sensor of claim 10 , wherein the second capacitor has a higher capacitance than the first capacitor.

12. The image sensor of claim 10 , wherein the readout circuitry further comprises a reset switch connected to a shared node between the switch and the second capacitor.

13. 10. The image sensor of claim 9, wherein the potential barrier is a PN diode.

14. 10. The image sensor of claim 9, wherein the at least two pixels comprise four pixels arranged in a 2x2 grid.

15. a charge coupled device (CCD), four pixels, each pixel of the four pixels including a photodetector and a corresponding first transfer gate connected to the photodetector; a second transfer gate having a single input connected to the output of each first transfer gate of each of said four pixels; a capacitor connected to the output of the second transfer gate; A CCD equipped with:

16. the capacitor is a first capacitor; 16. The CCD of claim 15, further comprising: a second capacitor; and a switch connected between the output of the second transfer gate and the second capacitor.

17. 17. The CCD of claim 16, wherein the second capacitor has a higher capacitance than the first capacitor.

18. 17. The CCD of claim 16, further comprising a reset switch connected to a shared node between the switch and the second capacitor.

19. 16. The CCD of claim 15, wherein the output of the second transfer gate is connected to the gate of a FET.

20. 16. The CCD of claim 15, wherein the four pixels are arranged in a 2x2 grid.

Images