Integrated superconducting memory and logic pipeline

Abstract

A time division multiplexed (TDM) lookup circuit for use in a superconducting cache includes at least one superconducting memory configured to function as a directory in the lookup circuit, and at least one comparator circuit. The comparator circuit has a first input adapted to receive a first physical address corresponding to a requested data location and a second input adapted to receive a second physical address corresponding to a main memory external to the TDM lookup circuit. The comparator circuit is configured to perform at least one comparison process in which the first physical address is compared to the second physical address, and to generate an output signal indicating whether a match occurs between the first physical address and the second physical address. The comparator circuit is configured to perform multiple comparison processes per lookup access period.

Description

[Technical Field]

[0001] This application claims the benefit of and priority under § 119 of U.S. Provisional Patent Application No. 63 / 425,160, entitled "Superconducting Memory, Programmable Logic Arrays, and Fungible Arrays," filed November 14, 2022; U.S. Provisional Patent Application No. 63 / 412,317, entitled "Superconducting Cache Memory, Memory Control Logic, and Fungible Memories," filed September 30, 2022; and U.S. Provisional Patent Application No. 63 / 394,130, entitled "Control and Data Flow Logic for Reading and Writing Large Capacity Memories, Logic Arrays, and Interchangeable Memory and Logic Arrays Within Superconducting Systems," filed August 1, 2022, the disclosures of which are incorporated herein by reference in their entireties for all purposes.

[0002] The present invention relates generally to quantum and classical digital superconducting electronics, and more particularly to the integration of memory and logic circuits in engineered pipelines. [Background technology]

[0003] Virtual addressing refers to the process of assigning easily manageable, temporary memory addresses to physical memory. Essentially, it is to computer random-access memory (RAM) organizational systems what the Dewey Decimal System is to libraries. Virtual memory helps with code sharing between multiple processes, data security, and preventing memory fragmentation and errors. In most cases, virtual memory extends the address space into "pages" stored in the file system (i.e., disk or flash memory). Data movement (i.e., page movement) between main memory (physical addresses) and the file system is managed by the operating system.

[0004] A cache is a form of memory that improves processing speed by storing most recently used data and spatially related data (e.g., the next instruction in a program) closer to the processor element (relative to other types of memory) so that future similar operations can occur faster. Caches can vary in size, structure, and cost, with the general trend being for multiple levels of caches to decrease in size and increase in energy cost as they are brought closer to the CPU.

[0005] To support ultra-low power systems in the near future and ultimately quantum computing, cache memory capable of operating in a temperature range of approximately 3 to 4.2 degrees Kelvin will be required. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] PCT / US23 / 16090 [Patent Document 2] U.S. Patent Application No. 17 / 993,543 [Non-patent literature]

[0007] [Non-Patent Document 1] Burnett, R. et al., “Demonstration of Superconducting Memory for an RQL CPU,” Proceedings of the International Symposium on Memory Systems, ACM (2018) (“Burnett 2018”) [Non-patent document 2] Herr, Q et al. “Superconducting Pulse Conserving Logic and Josephson-SRAM”, Applied Physics Letters 122, no. 18 (2023) (“Herr 2023”) Summary of the Invention

[0008] DETAILED DESCRIPTION OF THE INVENTION The present invention, as manifested in one or more embodiments, is directed to exemplary systems, circuits, devices and / or methods for forming superconducting memories and logic pipelines.

[0009] In accordance with one embodiment of the inventive concept, a time-division multiplexed (TDM) lookup circuit for use in a superconducting cache is provided. The TDM lookup circuit includes at least one superconducting memory configured to function as a directory in the lookup circuit and at least one comparator circuit. The comparator circuit includes a first input adapted to receive a first physical address corresponding to a location of requested data and a second input adapted to receive a second physical address corresponding to a main memory external to the TDM lookup circuit. The comparator circuit is configured to perform at least one comparison process in which the first physical address is compared to the second physical address and to generate an output signal indicating whether a match occurs between the first physical address and the second physical address. The comparator circuit is configured to perform multiple comparison processes per lookup access period.

[0010] The techniques of the present invention can provide substantial beneficial technical effects. By way of example only, and without limitation, techniques for utilizing RQL / SFQ memory and logic in caches and CAMs and as variable latency memories according to one or more embodiments of the present invention may provide one or more of the following advantages, among others: - Improved wiring availability to comparators performing RAM-to-RAM output comparisons, which advantageously reduces busing / comparator width and / or number of bus / contenders in selected embodiments by using several time division multiplexing (TDM) techniques in conjunction with copy / duplication techniques; - providing a means for read and write row-oriented time division multiplexing, generating two waves of data for every memory read operation and storing two waves of data for every memory write operation; - providing a means for read and write control oriented time division multiplexing, generating two waves of data for every memory read operation and storing two waves of data for every memory write operation, operation for a specific designed function, such as lookup, - providing a means for space-based and time-based confluence of signals for substantially simultaneous virtual translation lookups and directory lookups and associated address matching of the lookups to identify whether the data RAM stores the requested data (hit or miss); - Maintaining the same data array output skew - signal timing - regardless of the match position / column within the match array, enabling seamless physical and timing integration of the match array and data array components of a content addressable memory (CAM); - Integrate RAM output skew with various serially evaluating comparator implementations (or, more generally, other output logic) using a novel skewed serial comparator; - Offset RAM output skew to improve comparator output timing by using a new skewed serial comparator (or other logic); Rather than fixing all latencies to the slowest path, aspects of the inventive concept provide a means for addresses to have variable raw delays through memory, e.g., slow, medium slow, medium fast, and fast, in order to have lower latency access of memory where and when possible. - Reducing the total layers of metal required to support integrated memory and logic related to cache lookups.

[0011] These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0012] The accompanying drawings, which are included to provide a further understanding of the present invention and are incorporated in and form a part of this application, are presented by way of illustration only and not by way of limitation, and in which like reference numerals (when used) indicate corresponding elements throughout the several views. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram conceptually illustrating at least a portion of a dual-port reciprocal quantum logic (RQL) / single flux quantum (SFQ) memory cell 100. FIG. [Figure 2] FIG. 1 is a block diagram conceptually illustrating memory elements and logic circuits that identify relative memory cell and logic gate orientations using orientation indicators, show alternative memory cell orientations and aspect ratios / sizes (e.g., based on RQL), and specify associated timing allocations for each. [Figure 3A] FIG. 1 is a timing diagram that can be used to conceptually explain how the physical location of the read row and read column lines in an exemplary 128×128 memory array can affect their output delay, or that of a superconducting array system. [Figure 3B] FIG. 1 is a timing diagram that can be used to conceptually explain how the physical location of the read row and read column lines in an exemplary 128×128 memory array can affect their output delay, or that of a superconducting array system. [Figure 3C] FIG. 1 is a timing diagram that can be used to conceptually explain how the physical location of the read row and read column lines in an exemplary 128×128 memory array can affect their output delay, or that of a superconducting array system. [Figure 4] 1 is a block diagram illustrating at least a portion of a cache system in accordance with one or more embodiments of the present invention. [Figure 5]FIG. 1 is a block diagram conceptually illustrating an exemplary address anatomy of a level 1 cache, which serves to define different addresses in operation within the level 1 cache. [Figure 6A] FIG. 1 is a block diagram illustrating at least a portion of an exemplary lookup path for a four-way set-associative cache having a fully associative translation lookaside buffer (TLB) (based on a content-addressable memory (CAM)), in accordance with one or more embodiments of the present invention. [Figure 6B] FIG. 1 is a block diagram illustrating at least a portion of an exemplary serial AND-OR array circuit capable of supporting any Boolean function, in accordance with one or more embodiments of the present invention. [Figure 7] FIG. 1 conceptually illustrates a more detailed illustration of an exemplary TLB within the lookup path of a four-way set associative cache in accordance with one or more embodiments of the present invention, defining the required read and write line orientations and flow directions within its internal memory (i.e., TLB_MATCH and TLB_ARRAY) and relative to the Directory RAM. [Figure 8] FIG. 2 conceptually illustrates a detailed illustration of an exemplary TLB within a lookup path of a four-way set associative cache, in accordance with one or more embodiments of the present invention. [Figure 9] 7A and 7B are exemplary timing diagrams conceptually summarizing the component latencies of the TLB pipeline for different exemplary translation paths (e.g., paths 1 and 2 of FIGS. 7A and 7B, respectively) in accordance with one or more embodiments of the present invention. [Figure 10] FIG. 6B is a block diagram conceptually illustrating a more detailed illustration of an exemplary directory RAM and serial compare equality determination circuitry of the lookup path of the four-way set associative cache shown in FIG. 6A in accordance with one or more embodiments of the present invention. [Figure 11] 1 is a block diagram illustrating at least a portion of an exemplary serial compare equality determination circuit, in accordance with one or more embodiments of the present invention. [Figure 12] 12 is a block diagram illustrating at least a portion of an exemplary serial comparison equality determination circuit having increased bandwidth compared to the exemplary serial comparison equality determination circuit shown in FIG. 11 in accordance with one or more embodiments of the present invention. [Figure 13] 1 is a flow diagram conceptually illustrating at least a portion of an exemplary lookup path for a two-way set associative cache that implements virtual-to-physical address translation and has a fully associative TLB (based on a CAM), in accordance with one or more embodiments of the present invention. [Figure 14] 1 is a flow diagram illustrating at least a portion of an exemplary lookup path for a direct-mapped cache that implements virtual-to-physical address translation with a fully associative TLB (based on a CAM) in accordance with one or more embodiments of the present invention. [Figure 15] 1 is a schematic diagram illustrating at least a portion of an exemplary serial compare equality determination circuit, in accordance with one or more embodiments of the present invention. [Figure 16] 1 is a flow diagram of at least a portion of an exemplary lookup path for a two-way set associative cache with a fully associative TLB (based on a CAM), in accordance with one or more embodiments of the present invention. [Figure 17] 1 is a flow diagram of at least a portion of an exemplary lookup path for a two-way set associative cache with a fully associative TLB (based on a CAM) that implements virtual-to-physical address translation in accordance with one or more embodiments of the present invention. [Figure 18] FIG. 1 is a schematic diagram illustrating at least a portion of an exemplary RQL (or SFQ) based time division multiplexed memory array using TDM to read data from memory cells (or fixed switch / ROM cells as known in the art) in the array, in accordance with one or more embodiments of the present invention. [Figure 19] FIG. 19 is a timing diagram conceptually illustrating certain example signals within the example time division multiplexed memory array shown in FIG. 18 during a TDM read operation, in accordance with one or more embodiments of the present invention. [Figure 20] 1A-1C are block diagrams and corresponding write timing diagrams conceptually illustrating a time-division demultiplexed memory array and an exemplary write operation associated therewith, in accordance with one or more embodiments of the present invention; [Figure 21] 1A-1C are block diagrams and corresponding write timing diagrams conceptually illustrating a time-division demultiplexed memory array and an exemplary write operation associated therewith, in accordance with one or more embodiments of the present invention; [Figure 22] 1 is a flow diagram of at least a portion of an exemplary lookup path for a two-way set associative cache that implements virtual-to-physical address translation and has a fully associative TLB, in accordance with one or more embodiments of the present invention. [Figure 23] 1 illustrates an exemplary flow diagram of a TLB virtual address match portion of a lookup path for a four-way set associative cache that implements virtual-to-physical address translation in accordance with one or more embodiments of the present invention. [Figure 24] 1 illustrates an exemplary flow diagram of a TLB virtual address match portion of a lookup path for a four-way set associative cache that implements virtual-to-physical address translation in accordance with one or more embodiments of the present invention. [Figure 25] 1A-1C collectively illustrate lookup paths for an exemplary two-way set associative cache having a two-way set associative TLB as a whole, in accordance with one or more embodiments of the present invention. [Figure 26] 1A-1C collectively illustrate lookup paths for an exemplary two-way set associative cache having a two-way set associative TLB as a whole, in accordance with one or more embodiments of the present invention. [Figure 27] FIG. 2 is a block diagram illustrating at least a portion of an exemplary variable delay pipelined SFQ memory array, according to one or more embodiments. [Figure 28]1 is a block diagram illustrating at least a portion of an exemplary four-way set-associative cache having a fully associative TLB capable of metamorphosis in accordance with one or more alternative embodiments of the inventive concepts. [Figure 29] FIG. 1 is a block diagram conceptually illustrating at least a portion of an exemplary variable delay pipelined memory array, in accordance with one or more embodiments of the present invention. [Figure 30] 30 is a block diagram illustrating at least a portion of an exemplary variable delay pipelined memory array 3000 including added delay elements, in accordance with one or more embodiments of the present invention. [Figure 31] 1 conceptually illustrates an exemplary collision case, in accordance with one or more embodiments of the present invention. [Figure 32] 1 illustrates an alternative embodiment of a control circuit for a variable latency RAM having multiple mimicked delay pipelines and their associated address request entities, in accordance with one or more embodiments of the present invention. [Figure 33] 1 illustrates inputs, outputs, and states of an address request entity in accordance with one or more embodiments of the present invention. [Figure 34] 1 illustrates a scheduler and injection decision circuit in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] It should be understood that elements in the figures are illustrated for simplicity and clarity, and that common but well-understood elements that may be useful or necessary in a commercially feasible embodiment are not necessarily shown to facilitate a more unobtrusive view of the described embodiment.

[0015] The principles of the present invention, as manifested in one or more embodiments, will be described herein in the context of a cache and its associated memory. It should be understood, however, that the present invention is not limited to the specific devices, circuits, systems, and / or methods explicitly shown and described herein. Rather, given the teachings herein, it will be apparent to those skilled in the art that numerous modifications to the illustrated embodiments are contemplated and are within the scope of the inventive concepts. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.

[0016] FIG. 1 is a block diagram conceptually illustrating at least a portion of a dual-port reciprocal quantum logic (RQL) / single flux quantum (SFQ) memory cell 100. The RQL / SFQ memory cell 100 includes a memory element 102, a plurality of Josephson transmission lines 104 (hereafter referred to as JTL), and at least one logic gate 106 (here, an OR gate). Like most known superconducting memory cells (with at least one exception, where the ports are coupled), the RQL / SFQ memory cell 100 also (and particularly) includes independent read and write ports, enabling advantageous data flow arrangements and functionality. While FIG. 1 represents a schematic diagram of a particular RQL / SFQ memory cell, it can also provide a functional representation for a high-level description of other memory cells at the next level of hierarchy within a memory system architecture and can be used to indicate / assess latency. For purposes of this disclosure, Figure 1 may represent / depict timing features present in different SFQ memories, for example, as described in Burnett, R. et al., "Demonstration of Superconducting Memory for an RQL CPU," Proceedings of the International Symposium on Memory Systems, ACM (2018) ("Burnett 2018"), or Herr, Q. et al., "Superconducting Pulse Conserving Logic and Josephson-SRAM," Applied Physics Letters 122, no. 18 (2023) ("Herr 2023"), the disclosures of which are incorporated herein by reference in their entireties, although their behavioral / functional descriptions may not be identical.

[0017] FIG. 2 is a block diagram conceptually illustrating horizontal and vertical features of memory cells 204 and logic circuits 206 that identify relative memory cell and logic circuit orientations using orientation indicators 202, indicate alternative memory cell orientations and aspect ratios / sizes 208 (e.g., based on RQL), and specify associated timing allocations. Used throughout the detailed description and integrated into its associated figures, orientation indicators 202 relate circuit orientations to the read row lines (RRL) and read column lines (RCL) of the associated memory array, or define the orientation of memory cells within the memory array itself. In general, orientation indicators 202 define signal flow direction and indicate cumulative time (with the exception of all comparator circuits shown in FIGS. 11, 12, and 15, which have opposing top and bottom inputs, which are shown exclusively as bottom inputs in the schematic diagrams). One or more interrelated physical, logical, and timing relationships may be established with orientation indicators 202 later in this specification.

[0018] Referring to Figure 2, the memory cell 204 placement will be discussed for timing as it relates to the physical design. Also shown in Figure 2 are timing rules specifying that the time allotment "T" of a given select signal passing through a read row line (RRL) in a memory device can be equal to the time allotment "T" of data passing through a read column line (RCL) of memory cells in several possible orientations and / or aspect ratios through careful design of the memory cells 204. Specific aspect ratios may be required for memory-to-memory and memory-to-logic data flow integration, such as those described below with respect to cache and content-addressable memory (CAM) embodiments.

[0019] For illustrative purposes only and without limitation, latency / timing numbers can be derived for a memory array size of 128 columns by 128 rows (128 x 128 array) based on the circuitry of Burnett 2018. This exemplary memory is 16,384 bits, equivalent to 2 kilobytes (KB), where 1 byte is 8 bits, or if 9 bits are allocated to a byte for error correction code (ECC) / parity, 2 KB equals 18,432 bits of data storage. Burnett 2018 reported that in their design, a traversal of 32 memory cells in either the row or column dimension occurs over a given memory cycle. Therefore, it takes 4 RQL cycles to traverse a complete row of memory cells or a complete column of memory cells. The cycle time was 500 picoseconds (ps) for the D-Wave technology / process utilized. With process improvements, cycle time was expected to drop to 200 ps. Other changes to the design, such as pipeline depth, may yield further improvements in speed or other metrics.

[0020] 3A, 3B, and 3C are timing diagrams that can be used to conceptually illustrate how the physical location of the read row and read column lines in an exemplary 128×128 memory array can affect their output delay, or that of a superconducting array system ("output <n>" where N is an integer, 0, 1, 2, ...). Incremental inter-period skew is shown for the far, middle, and near read row lines, respectively. Output delay is shown across columns. Although not explicitly shown in Figures 3A, 3B, and 3C, an intra-period delay (called phase delay) also exists due to the particular row and column location within the memory circuit. In this example, the output signal output <0> Column 0 produces the output <96> 3A, 3B, and 3C for the purpose of clearly identifying when latency occurs in an exemplary 128x128 memory array.

[0021] Period skew can occur in many forms of RQL / SFQ memory interactions, including (i) memory-to-logic interactions, (ii) memory-to-memory interactions, or (iii) interactions from logic located between memories (where the memory can serve as the principal function source of the logic). Skew can occur, for example, in cache lookup paths, programmable logic array (PLA) paths, and content-addressable memories (CAMs). Multi-period memory skew in these various memory paths can be mitigated by one or more embodiments of the inventive concepts.

[0022] 3A, 3B, and 3C, timing diagrams 300, 350, and 370 respectively illustrate three exemplary read requests to different addresses of a 128-bit by 128-bit RQL array, where the first read request shown in FIG. 3A is output to the "far" read row line (i.e., the output) associated with the first address. <n>) which is furthest in time from the first address, where the second read request shown in FIG. 3B selects the "middle" read row line (i.e., the output (output <n>) (middle in time from the 0x0 ... <n>) (closest in time to the last memory cell). The latency of the OR gate and the Josephson transmission line (JTL) associated with a given column (part of each memory cell) is most noticeable in read operations directed to the "far" read row line, occupying four RQL periods (four boxes labeled "1" with diagonal fill lines) due to the signal traversal of 128 memory cells within the column read line. Row-column line (RCL) latency indicators 314 and 364 highlight the cumulative latency in the column dimension for "far" and "intermediate" row addresses, respectively, associated with Figures 3A and 3B. In contrast, the latency of a single column OR and its JTL (part of the last memory cell) is only slightly noticeable in read operations directed to the "near" read row line due to the signal traversal of one memory cell within the column read line, as shown in Figure 3C.

[0023] The accumulating boxes indicate the output with the closest line latency, <0> , the output furthest from, the output <96> , indicates that the data output grows across the line until the line reaches a blank. The blank boxes labeled "1" represent row periods. The read row line (RRL) latency indicator 312 is shown at the output of Figures 3A, 3B, and 3C. <96> 1 highlights the cumulative latency in the row lines to reach

[0024] In general, it should be understood that the column lines may be formed with inherent logic that performs Boolean operations other than OR, such as AND.

[0025] Cache Logic, Circuits, and Floorplans Aspects according to an embodiment of the present invention will be described using various cache "lookup" paths (i.e., flows). To ensure technical clarity in the detailed description, some categorizations may be made, and some terminology will be defined thereafter.

[0026] 4 is a block diagram illustrating at least a portion of a cache system 400 in accordance with one or more embodiments of the present invention. Cache system 400 may include at least one lookup path (i.e., circuitry) 402 and at least one data RAM 408 or other addressable storage element. Cache system 400 is shown primarily for the purposes of establishing consistent terminology within this disclosure and to define certain functional / logical features of a comprehensive system that are seamlessly enabled, at less expense than conventional approaches, by the unique physical and pipeline implementation disclosed in embodiments of the present invention.

[0027] An exemplary lookup path 402 may include a directory 404 and a translation lookaside buffer (TLB) 406, often defined as a memory cache that stores recent translations of logical / virtual memory to absolute / physical memory. In one or more embodiments, data RAM 408 may be configured to perform logic, memory, and mixed memory and logic operations, which may be interchangeable. Data RAM 408 is preferably configured to store lines of data, each line of data including, for example, contiguous data, independently addressable, and / or contiguous instructions, also independently addressable. Additionally, data RAM 408 may include data, one or more operands, one or more instructions, and / or one or more operators stored in at least a portion of the data RAM. In one or more embodiments, metamorphosing memory (MM) 410 may include additional elements, relative to those commonly associated with data RAM, for performing unique logical operations within the addresses and data streams of the data RAM. Metamorphosing memories suitable for use in conjunction with aspects of the inventive concepts may be found, for example, in PCT Application No. PCT / US23 / 16090, entitled "Metamorphosing Memory," filed in the United States Receiving Office on March 23, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0028] There may be many different possibilities for translation and associativity regarding the lookup path 402 of the cache system 400. Some first level cache implementation alternatives may include: (i) a fully associative translation lookaside buffer (TLB) and a set associative directory; (ii) a set-associative TLB and a fully associative directory; (iii) a set-associative TLB and a set-associative directory; and (iv) Fully associative TLB and fully associative directory.

[0029] Full associativity allows any address to be stored in any line of the cache. When a memory operation is sent to a fully associative cache, the request's address must be compared to each entry in the tag array to determine if the data referenced by the operation is contained in the cache. In a direct-mapped cache, each memory address can only be stored in one location in the cache. When a memory operation is sent to a direct-mapped cache, a subset of the bits in the address are used to select the line in the cache that can contain the address, and another subset of the bits are used to select the byte within the cache line to which the address points. A set-associative cache is a compromise between a fully associative cache and a direct-mapped cache. In a set-associative cache, there are a fixed number of locations (called the "set") in which a given address can be stored. The number of such locations defines the cache's associativity.

[0030] Similarly, caches can be divided into four categories: (i) Physically indexed, physically tagged, (ii) Virtually indexed, virtually tagged, (iii) Virtually indexed, physically tagged, and (iv) physically indexed, virtually tagged;

[0031] While some embodiments of caches will be described herein with reference to physically indexed, physically tagged directories for economy and clarity of description, it should be understood that the structures highlighted by the cache embodiments shown and described herein may be applied more broadly to all four categories of caches, as well as other memory systems, as will be apparent to those skilled in the art given the teachings herein. Additionally, it is assumed that, with respect to RAMs, arrays, and CAMs, the timing of signals driving read row lines (RRLs) can be selectively adjusted so that the "far" RRL receives the earliest input and the "near" RRL receives the most recent input. This type of adjustment can ensure that, regardless of the RRL selected, data will arrive with the same (or nearly the same) latency as the corresponding output of the memory array (RAM), i.e., in accordance with embodiments of the inventive concepts, the latency of requested data will be constant regardless of where the data resides within the memory array.

[0032] For CAM applications, additional delays may be added to the bits of the virtual or logical addresses being compared, not explicitly shown in the lookup path schematic diagram. For RAMs, a decoder included in the RAM may be configured, in accordance with an aspect of the inventive concept, to add additional latency to each successive input RRL select signal when moving from a distant RRL to a nearby RRL, with the farthest RRL receiving the least (or no) additional latency and the nearest RRL receiving the most additional latency.

[0033] FIG. 5 is an exemplary address anatomy diagram of a level 1 cache (where P Q-1 I N-1 5, the first and second rows of bits represent the virtual (i.e., logical) addresses (V0 to V1). k-1 ) to the physical address relative to main memory (P0 to P J-1 ) translation into

[0034] When a file is moved from slower storage to much faster main memory for processing, the operating system oversees the virtual-to-physical address translation. Virtual addresses, or logical addresses, may be generated by various processes initiated by future code / computations executed by Boolean processors and potentially quantum processors. In all or most exemplary embodiments of cache lookup paths according to aspects of the inventive concept, a virtual-to-physical address translator, often referred to as a translation lookaside buffer (TLB), may be incorporated into the lookup path schematic.

[0035] In practice, physical addresses may be needed for processors to communicate with higher level memories (e.g., level 2 cache, level 3 cache, main memory, etc.) that preferably operate on physical addresses, and from those higher level memories to other processors. Therefore, the virtual address bits are often used as the upper physical address bits (P J-1 From P Q ), an address translator is often the integer part of the address lookup path in a first level cache system. Thus, a virtual address presented to such a system can be expressed as: V k-1 *************V 索引 **********V0,P Q-1 ***********P0 (V 索引 (Note that is included in this address definition to help define the index address range for the TLB virtual tag arrays of Figures 23 and 25.)

[0036] Virtual addresses can be translated into the following physical addresses, which are almost always smaller in degree / size: P J-1 ************P Q , P Q-1 ***********P0 (Little endian addressing convention)

[0037] For all or some lookup path embodiments, the location where the virtual bits end (V0 and P Q ) and the location where the entire address that remains unchanged under translation (also called a virtual address, the term is contextual) begins (P Q-1 It is important to note the boundary between . This boundary defines the "page" size, which is typically 4 KB but can be as large as 1 MB or 2 GB, although embodiments of the inventive concept are not limited to a particular page size. Some cache implementations may require simultaneous support for multiple page sizes. The page size may determine the allowable upper limit of the directory, in terms of size, for what is known as a physically tagged, physically indexed cache—one of the simplest caches to design given the lack of "synonyms."

[0038] Continuing with Figure 5, a set-associative directory primarily consists of tag bits, T0 through T M-1 , and the index bits, I0 to I N-1 The index bits are invariant under translation and therefore correspond to at least one particular set of tag bits (T0 through T M-1 The directory index address bits, together with at least one set of tag bits, can serve to identify a line of data stored in the cache. In an N-way set-associative cache, a line of data can be stored in any of N locations within the cache.

[0039] Block offset address, B0 to B P-1 The line offset address points to the data to be fetched or stored within the cache line. To increase the hit rate (i.e., the likelihood that the cache will hold the data), spatially related data with addresses closest to the requested data can be moved to and from higher levels of memory as part of a line.

[0040] 6A is a block diagram illustrating at least a portion of an exemplary lookup path 600 of a four-way set associative cache having a fully associative TLB (based on a CAM), according to one or more embodiments. Specifically, FIG. 6A illustrates an exemplary flow diagram of the lookup path 600 of a four-way set associative cache configured, in part, to implement virtual (i.e., logical) to physical address translation. The superconducting set associative lookup path in this exemplary embodiment may implement a physically indexed and physically tagged directory.

[0041] A complementary metal-oxide-semiconductor (CMOS) designer attempting to accurately gauge the complexity of RQL memory circuit timing synthesis should assess, for example, the timing diagrams shown in Figures 3A, 3B, and 3C. This timing complexity does not currently exist in CMOS designs. Within one or more embodiments of the inventive concept, timing can be managed through the physically and logically directed confluence of timing signals over multiple periods (and small sub-periods known as phases).

[0042] Before discussing timing adjustments, it is important to recognize that the exemplary embodiment of the cache lookup path 600 shown in FIG. 6A may have certain disadvantages that may be addressed by other embodiments described herein. Such disadvantages may include, for example: (i) excessive latency in the virtual address translation path through the translation lookaside buffer (TLB) implemented as a CAM 606; (ii) excessive metal / wiring layers across the directory RAM 608; and (iii) lower bandwidth. However, the discussion of the first embodiment highlights memory design opportunities (e.g., those of RAM, CAM, and PLA) and teaches how to visualize the flow of information within and at the output of RQL / SFQ memories.

[0043] As known to those skilled in the art, the lookup architecture of a modern level 1 cache in a microprocessor with virtual memory may include a TLB, which is the cache itself and performs virtual-to-physical address translation. The content-addressable memory (CAM) 606, which functions as the TLB in the lookup architecture 600 of FIG. 6A, may be formed by the combination of TLB_Match 602 and TLB_Array 604, which store virtual and physical addresses, respectively. FIG. 6A also includes: (i) a four-way set-associate directory, physically divided into four regions—DIRECTORY_RAM_0 608 through DIRECTORY_RAM_3 608—that indicate whether and where the requested data is stored in the data RAM of the level 1 cache; and (ii) a “serial compare equality” circuit 1100 to ensure that the cache and main memory hold the appropriate pages of file system data. (The data stored in main memory is typically managed by the operating system.)

[0044] The lookup path of an N-way set associative cache (shown in FIG. 6A as a 4-way set associative cache, easily modified to be N-way, where N is an integer greater than 1) may include at least one TLB_Match 602 (TLB CAM holding virtual / logical addresses), at least one TLB Array 604 (TLB RAM holding physical addresses), at least one serial compare equality determiner 1100 (evaluating over multiple RQL cycles), and at least one Directory_RAM 608 (containing physical address bits and cache management bits such as MESI representing modified, exclusive, shared, and invalidated). All components may be accessed in sequential data flow order from application of the virtual address and index address to generation of one or more hit results (e.g., hits 0, 1, 2, and 3).

[0045] In one or more embodiments, wave pipelining in the logic may be implemented to avoid the use of intermediate latches or registers, which is particularly advantageous in a superconducting environment given that latches are extremely expensive in terms of physical real estate. Signals associated with virtual address requests travel through TLB_Match 602 and then TLB_Array 604 substantially simultaneously with waves associated with index address requests traveling through Directory RAM 608. The outputs of TLB_Array 604 and Directory RAM 608 both converge to a serial compare equality determination circuit 1100 over a range of RQL / SFQ periods and phases, processing physical comparisons in bit-timing order relative to the TLB_Array 604 and Directory RAM 608 output bit timing. (These are coincident timings, as seen in exemplary FIGS. 7 (and 8) and 10, which both have approximate / near-identical timing at a given physical pitch assigned to the serial compare equality determination circuit, XOR, and each bit mismatch circuit.) The output propagates intermediate mismatches forward, combining them with the next bit mismatch result until a full tag comparison (physical address bits) is completed, then other control bits may be processed / merged (e.g., a "valid" bit indicating the line is valid) to produce a hit result.

[0046] In conventional CMOS designs, all output signals emerge from a single RAM on the same or, at most, a few subsequent cycles of its access. Comparisons are generally completed in less than a single cycle, and intermediate results are processed not in a bit-wise fashion but in parallel, where bit mismatches feed wide ORs with substantially similar timing inputs / requirements (i.e., as measured by the input-to-output latency of the wide OR). In other words, the memory / array outputs reach the XOR of the comparator circuit on the same cycle.

[0047] To replicate the functionality and timing activities associated with the first cache embodiment, the serial compare equality determination circuit receives phase and period shift address bits (e.g., physical address bits in our example of a physically tagged, physically indexed cache) retrieved from at least one TLB_ARRAY 604 and at least one DIRECTORY_RAM 608. These addresses may be compared to determine whether they are equal. A true hit signal, one of N different hit signals associated with N different sets, preferably indicates that a data cache (not formally part of the lookup path) stores the subject requested line and specifies a particular direction / set (e.g., 0, 1, 2, or 3) of the N directions / sets that contains the requested line. If all hit signals are false, a miss to the data cache is recognized, i.e., the data cache does not contain the requested line.

[0048] To reduce wiring congestion, the read path data flows of TLB_ARRAY 604 and DIRECTORY RAM 608 may be configured to be mirror images of each other (i.e., rotated 180 degrees) as indicated by the orientation indicator 202 associated with each memory array. Additionally, the read path circuitry associated with each TLB array may be made to be orthogonal (see, e.g., FIGS. 7 and 8). As will be described in connection with the CAM example, TLB_MATCH 602 and TLB_ARRAY 604 may be pitch-matched and timing-aligned (see, e.g., FIGS. 7 and 8) in a manner that consumes minimal circuitry (e.g., array and operatively associated circuitry) and minimizes their latency (as depicted in FIG. 9) and ensures identical latency for any match associated with TLB_MATCH 602.

[0049] Many other factors in cache design can be considered, including their place in the SFQ-based lookup path and how its timing and other resource requirements can affect the overall design. The memory array itself is where some of the most significant variations from traditional designs are expected to occur, with the understanding that the cache design will very likely include some choices that are considered unconventional to conventional designs.

[0050] Unique to this exemplary lookup pathway embodiment 600 is the combination of logic functionality, circuit physical orientation, and temporal placement / configuration (as manifested by the expressed phase assignments of the RQL logic and memory cells) described herein for managing the processing of cache read / fetch, write / store, or other requests / operations (e.g., nondestructive read-out (NDRO)) through its RQL / SFQ circuitry and memory cells. A lookup pathway based on a wave-pipelined RQL / SFQ can be implemented with extremely low latency and low circuit overhead, maintaining proper processing of requests.

[0051] Lookup path 600 features a TLB bypass input that would be included in all other alternative lookup path embodiments, including those described with respect to Figures 13, 14, 16, 17, 24, 26, and 28. Each TLB bypass bit prevents a memory cell from bypassing the output of its associated memory (e.g., Phys TLB This bypass supplies the read column lines that are normally used to transfer the state of the input (or output) to the output (or output). Such a bypass can also be enabled in the serial AND-OR array circuit of FIG. 6B. In that situation, it is called a "bypass to output."

[0052] It should be understood that the same underlying logic, its memory cell timing constraints (allocations), and physical structure related to CAM 606 can be used to form a generalized Boolean logic function, or CAM, including two serial PLAs, one acting as an AND plane (using an OR-based column Boolean inversion transformation) and the other acting as an OR plane. With reference to Figures 7, 8, and 9, a detailed description of the signal flow and timing enabled by an embodiment of the physical structure of a CAM (and also a serial PLAs, collectively referred to herein as an SFQ serial AND-OR array circuit) will be provided.

[0053] A match array (e.g., TLB_Match 602) of a CAM (e.g., TLB_CAM 606) may store true and complement bits of each address bit along a column. CAM 606 may receive true and complement row signals, address bits (virtual or logical addresses, V, of TLB_Match in FIG. 7), around the match array. Less restrictive than the CAM match array, the PLA can hold any desired state in its memory cells, forming its AND (OR) plane logic. However, like the CAM match array, the PLA's data path may, in limited cases, include bit pairs with both a true version of the first bit and a complement of the first bit. Unlike a CAM, inverters are placed between the memory arrays to implement the required Boolean conversions, as will be explained later.

[0054] 6B is a block diagram illustrating at least a portion of an exemplary SFQ (or RQL) serial AND-OR array circuit 650, which may be configured to support any Boolean function, in accordance with one or more embodiments of the present invention. The SFQ serial AND-OR array circuit 650 includes a first OR array 652 having first memory cells with timing allocation T along their read row line and read column line dimensions, a second OR array 654 having second memory cells with timing allocation, T, along their read row line and read column line dimensions that are substantially similar to those of the first memory cells (also T), an inverter 656, and an input <0> from <n-1>until, where N is a positive integer, and the output <0> from <m-1>where M is a positive integer, and <0> from <n-1>The output of the first OR array 652 provides the input of an inverter 656 (which converts the OR signal to an AND signal), the output of the inverter 656 provides the input of a second OR array 654, and the output of the second OR array 654 provides the output <0> from <m-1>Supply up to.

[0055] 7 conceptually shows a more detailed illustration of an exemplary TLB 700 (CAM TLB 606) in the lookup path of a four-way set associative cache according to one or more embodiments, defining the necessary read and write line orientations and flow directions (i.e., RRL, read column line (RCL), write row line (WRL), and data column line (DCL)) within its internal memory (i.e., TLB_MATCH 602 and TLB_ARRAY 604) and to the directory RAM 608 (as represented by FIG. 10). Other notable details of the exemplary TLB 700 shown in FIG. 7 may include one or more of the following: (i) TLB_MATCH 602 and TLB_ARRAY 604 relative positions and orientations (the read lines are indicated by the orientation indicators 202 in each array 602, 604); (ii) a virtual address input bus (which may be encoded); (iii) different memory cells—cell_1 and cell_2—both having exemplary aspect ratios (e.g., 1:1) but having different internal relative read and write orientations; (iv) superimposed "1" RQL periodic boxes (delineating the time of flight in space, as explained later); (v) the preferred location of the write decoder 702 for the TLB_Match 602; (vi) the preferred location of the write data port 704 of the TLB_Match 602; (vii) Translation Hit Detection Logic (i.e., TLB_Match_Hit…), (viii) the preferred location of the write decoder 706 in the TLB_Array 604; (ix) the preferred location of the write data port 708 of the TLB_array 604; and (x) Physical address output (for example, PA_8-RQL to PA_12-RQL).

[0056] Regarding the lookup control logic, it is important to note that the translation hit logic may be a sequentially placed OR of the TLB_Match outputs, and the relative positioning of the write data port and RCL outputs may affect the relative timing of cache fetches compared to their stores. Memory locations in the TLB may require updating before the next translation can be processed.

[0057] The relative orientation between TLB_MATCH 602 and TLB_ARRAY 604 may be indicated using the general direction of data flow of lookup path 600 through TLB_MATCH 602 and TLB_ARRAY 604 indicated by orientation indicator 202. In one or more embodiments, the RRL of TLB_MATCH 602 may be rotated 90 degrees clockwise relative to that of TLB_ARRAY 604. The write lines may be configured according to the requirements of the CAM match circuit (e.g., TLB_MATCH 602) and the requirements of the representative array (e.g., TLB_ARRAY 604). The orientation of the data column lines (DCL) and write row lines (WRL) are shown at 602, 604 in FIG. 7.

[0058] Logical functionality can be ensured by (i) proper timing allocation (with RQL phase) along the RRL and RCL of memory cells and (ii) any rotation or mirror image of these combined oriented physical designs of TLB_MATCH 602 (or more simply abstracted for other uses such as a CAM—fully associative directory) and TLB_ARRAY 604 (or more simply RAM), with both memory cell circuits allocated to the appropriate locations within the RQL phases timed consistently across TLB_MATCH 602 and TLB_ARRAY 604. Memory cells along the RRL of TLB_MATCH 602 occupy the same allocated time as memory cells along the RCL of TLB_ARRAY 604 interlaced timing interactions (e.g., timing granularity within the RQL phase) from the RCL output of TLB_MATCH 602 to the RRL input of TLB_ARRAY 604, driven by operatively connected row select signals. Other logic circuits, for example (and their underlying PLAs), fall within the scope of this broadly "sequentially accessed / located memory / array" embodiment. As will be described below, these physical orientations and timing assignments ensure consistent latency regardless of what column "hits" or misses in the match array (e.g., TLB_Match 602) or what column generates a "1" or a "0" in the PLA (e.g., OR_Array_1 652 or OR_Array_2 654).

[0059] Continuing with reference to FIG. 7, by way of example only and without limitation or loss of generality, superimposed on TLB_MATCH 602 and TLB_ARRAY 604 are boxes labeled "1" that can be used to indicate the spatial propagation of a signal over a period corresponding to a single RQL cycle, corresponding to the traversal of 32 memory cells. For better understanding, note that only the RQL / SFQ signal flight, which originates at the input of the "far" RRL of TLB_MATCH 602, is highlighted by the "1" box. That signal can further be considered as generating multiple outputs—from PA_8-RQL to PA_12-RQL. For the exemplary TLB hit, the logical address signal is traced along the "far" RRL. It propagates along the far RRL for three RQL cycles, corresponding to the traversal of 96 memory cells, as a positive and negative flux quantum pair (RQL) pair or SFQ. After accessing the 96th memory cell, the signal then propagates down the RCL for four RQL cycles, corresponding to a traversal of 128 memory cells, in the absence of an RQL pair representing a "match" or "compare equal" at this location in TLB_MATCH 602. The column in which this particular logical address assessment occurs in TLB_MATCH 602 is labeled the "merge column." The results from all bitwise matches (actually mismatches) of the applied logical address and the stored logical address literally merge into a single bit in the merge column. Merging of bitwise mismatches (or matches) can occur at all RCLs during one set of RQL / SFQ cycles associated with each TLB_MATCH 602 operation.

[0060] Along the merge column, any mismatch will generate an RQL pair that will propagate down the column. In contrast, a signal representing a match can be thought of as having no RQL pair. At the end of the RCL in TLB_Match 602, the signal is inverted, generating a match (hit) RQL pair that is applied to the RRL of TLB_Array 604, where it propagates along the RRL over four RQL cycles, enabling memory cells as it passes through them. When a memory cell is selected, representing a particular physical address bit associated with the matching virtual address in TLB_Match 602, its state propagates to its indicated TLB_Array 604 output over one additional RQL / SFQ cycle (corresponding to a traversal of 32 memory cells). Only one RRL may be active in TLB_Array 604 (this is generally not true for other similar structures, such as two-PLA groupings). In reaching the first / closest output, 256 total cells are traversed in this example, and the total number of RQL cycles is 8. The last / furthest TLB pass measures a total of 12 RQL cycles because the wave must traverse the RRLs in TLB_Array 604, which adds four RQL / SFQ cycles to the overall latency. It can be shown that the latency through the TLB is unchanged regardless of which RCL (e.g., closest or farthest) is matched in the merge column in TLB_Match 602, due to the memory cell timing assignment "T" and RCL output and RRL input interfaces in FIG. 2.

[0061] Moving down the column, memory cells within TLB_Match 602, each representing one bit, are compared with the associated stored logical address bit to form a signal indicating a mismatch, but are subsequently inverted to form a match. The associated logical address bit at the input of the nearby RRL (with respect to the TLB_Match 602 output) may be applied later in time than the logical address bits applied at the input of the distant RRL to meet timing requirements for signal convergence. Thus, an algebraic merge of logic bitwise comparisons evolves as it moves from the top to the bottom of TLB_Match 602, propagating along the merge column labeled as an RRL pulse pair (representing a logic "1") or the absence of such a pair (representing a logic "0"). Any progression in value is from a logic "0" or "1" to a logic "1," given the OR logic functionality inherent in the RRL (for the exemplary memory cell shown in FIG. 1). What is shown in TLB_MATCH 602 as it relates to the "1" box is only the far RRL signal progression of the logic bit associated with the far RRL.

[0062] In TLB_ARRAY, RQL signal branching can occur, and a set of unique paths through TLB_ARRAY are shown along with their corresponding outputs, PA_8-RQL through PA_12-RQL, primarily because they factor into the timing and thus the structure of serial compare equality determination 1100 described in connection with Figures 6, 7, and 10. Serial compare equality determination circuit 1100 follows TLB_ARRAY 604 in terms of signal flow. One embodiment of serial compare equality determination circuit 1100 will be described in detail with respect to Figure 11, in accordance with aspects of the inventive concept. Illustrated appearances from the example TLB_ARRAY 604 of Figure 7 are cycle-packed physical addresses appearing as PA_8-RQL through PA_12-RQL.

[0063] With regard to terminology, the term "PA_8-RQL" as used herein refers to a set of physical address outputs having an approximate latency of eight RQL periods (i.e., signal delays ranging from exactly eight RQL periods to just under nine RQL periods, where the set may include fractional periods known as phases). The latency recorded in the signal name simply indicates the combined latency of TLB_Match 602 and TLB_Array 604, which does not include additional latency in feeding and passing through "translation hit" logic that may be included in the lookup signal path.

[0064] FIG. 8 conceptually illustrates a detailed illustration of an exemplary TLB in a lookup path of a four-way set associative cache, according to one or more embodiments. The exemplary TLB illustrated in FIG. 8 may be functionally and physically similar to that illustrated in FIG. 7, with one difference: timing "path 1" is superimposed on FIG. 7 and timing "path 2" is superimposed on FIG. 8, both of which will be discussed with respect to the exemplary timing diagram of FIG. 9. Again, each of the boxes labeled "1" represents a spatial traversal of a signal over one RQL / SFQ period.

[0065] 9 is an exemplary timing diagram conceptually summarizing the component latencies of the TLB pipeline for different exemplary translation paths (e.g., paths 1 and 2 of FIGS. 7 and 8, respectively) in accordance with one or more embodiments of the inventive concepts. While the component delay latencies for the two different paths may differ—RRL measures three RQL periods for path 1, while RRL measures one RQL period for path 2—the overall latency remains constant for any path through the TLB, measuring eight RQL periods for the PA_8-RQL output. This ability for latency to necessarily remain unchanged regardless of signal path through the TLB is due at least in part to the orthogonal nature of the signal flow across the memory cell, in which both the read row circuitry (RRL) and read column circuitry (RCL) operate and are assigned the same maximum latency below which within each RQL phase.

[0066] Generally, deliberate skewing of RRL inputs to an RQL memory array according to their inherent column line latencies, while ensuring row operation independence (i.e., no collision of RQL pulses of different read operations / waves directed to the memory array), introduces an overall latency adder of the full column delay regardless of which RRL is selected within the array. Such skewing of latency should be applied to the logical address, with the additional latency ranging from 0 RQL periods (i.e., no latency) of the farthest RRL to 4 RQL periods of the nearest read row line. If such skewing is implemented on the logical address regardless of its path through TLB_Match 602 and TLB_Array 604, then all path delays will total the same value at any particular output (e.g., PA_8-RQL) as shown in FIG. 9.

[0067] It should be understood that the individual latencies associated with each memory cell may not be precisely represented in FIG. 9. These exemplary diagrams are intended merely to represent the 32 memory cell granularity associated with each RQL cycle. For example, the eighth RQL cycle completes at the TLB_Match 604 output. Thus, the latency from the TLB's logical address input to the PA_8-RQL output is the sum of 8 RQL cycles and an additional memory cell delay (e.g., 1 / 32 of a cycle, using a 32 memory cell granularity).

[0068] Additionally, it is important to note that the physical address outputs arrive one after the other and feed into a serial compare equality determination circuit 1100, which will be described in more detail with respect to Figure 11. An instantiation of the serial compare equality determination circuit 1100 can be seen in Figures 6A and 10, which will be described below.

[0069] FIG. 10 is a block diagram conceptually illustrating a more detailed illustration of an exemplary directory RAM 608 and serial compare equality determination circuit 1100 of the lookup pathway 600 of the four-way set associative cache shown in FIG. 6A, in accordance with one or more embodiments. FIG. 10 defines the required read and write line orientation and flow direction (i.e., RRL, RCL, write row line (WRL), and data column line (DCL)) for the exemplary TLB_Match 602 and TLB_Array 604 shown in FIG. 7. Note in particular the direction indicator 202. It should be understood that, unlike CMOS interconnections, the interconnections between the functional blocks (e.g., JTL or JTL and OR gates) shown in FIG. 10 are directional.

[0070] Other notable details of the directory RAM 608 shown in FIG. 10 may include one or more of the following: (i) the relative location and orientation of the directory RAM 608 and the serial compare equality determination circuit 1100 (note the orientation indicator 602); (ii) the highlighted internal circuit path of the physical address bits going from the directory 608 to the serial compare equality determination circuit 1100; (iii) Memory cell 2, having an exemplary aspect ratio (e.g., 1:1), has the same footprint / aspect ratio (e.g., 1:1) as memory cell 1 shown in Figure 7. One difference between memory cell 1 and memory cell 2 may be their read and write port orientation, reflected by the read and write column line relative orientation difference between the two arrays (TLB_MATCH 602 and DIRECTORY_RAM 608). (iv) superimposed "1" RQL period boxes delineating the time of flight of signals in directory 608; (v) the preferred location of the write decoder 1004 in the directory RAM 608; (vi) the preferred location of the write data port 1006 in the directory RAM 608; (vii) Preferred location of directory RAM 608 read decoder 1002 (directory RAM 608 has a strategically inserted 4 RQL period delay for the shortest path through the read decoder to allow for a "far" RRL for this example only. The delay is added to account for the necessary physical address timing adjustments). (viii) a serial compare equality determination circuit 1100, which forms the core of the hit logic of the lookup path 600, which compares the translated address (i.e., virtual to physical translation) with four potential addresses stored in the four sets of the directory to see if the four-way set associative cache stores the requested line of data; (ix) an exemplary passive transmission line (PTL) or JTL pass-through upper or lower interconnection (which is intended to represent all PTL or JTL pass-through upper or lower interconnections); and (x) Hit outputs 0, 1, 2, and 3, which indicate whether the associated set of a four-way set associative cache stores the requested line of data.

[0071] In a manner consistent with the exemplary TLB, superimposed on the directory RAM 608 (dir_RAM) are boxes labeled "1," each representing the spatial propagation of a signal for a period corresponding to a single RQL cycle. For better understanding, note that only the RQL signal flight, initiated at the "far" RRL input of the directory RAM 608, is highlighted by the "1" box in FIG. 10. That "far" RRL trigger signal generates multiple outputs—PA_8-RQL through PA_12-RQL. For this example, without limitation, if the array size is fixed at 128 rows by 128 columns, a 4 RQL cycle delay was added to the directory RAM's read decoder to balance (i.e., equalize) the latency through the translation (i.e., TLB) and directory paths so that their physical address bits arrive at the serial compare equality determination circuit 1100 simultaneously.

[0072] The actual sizing of a superconducting cache can help bound the actual directory RAM 608 size. If the data RAM 408 of FIG. 4 (which illustrates lookups and is not shown in FIG. 6A ) is four-way set associative, its line size is 32 bytes, and its capacity is 16 Kbytes (chosen to avoid "synonyms"), then the directory RAM 608 can be addressed with 7 bits (directory RAM 608 is 128 bits deep). Perhaps a more reasonable two-way TLB would be addressed with 7 bits (TLB_RAM is 128 bits deep). (Note that in this illustrative example of FIGS. 6 and 7 , the TLB was fully associative.) Depending on the number of TLB entries needed to ensure a high "hit" rate on virtual-to-physical translations, it may not be obvious how TLB_ARRAY 604 and directory RAM 608 depths will compare to each other.

[0073] Increasing the number of directions / sets reduces the required directory RAM 608 depth. Thus, increased associativity may appear to result in a significant reduction in the overall latency of the directory RAM, due at least in part to the reduced RAM depth. However, if the directory RAM 608 could not be split into four separate directory RAM 608 instances corresponding to the four separate directions, as is done in FIG. 6A, this simple conclusion overlooks the expansion of the directory RAM 608 RRL required to include tag bits for each direction / set.

[0074] Specifically, as discussed above for four separate directory instances, issues arise in the distribution of TLB tag bits to each directory instance's remote direction / set via the PTL or JTL pass-through upward or downward interconnect, which can significantly impact yield (e.g., due to additional levels of wiring) and performance (e.g., constrained cycle times of multiple flux quantum (MFQ) PTL circuits). Multiple flux quantum cannot be generated fast enough to support the inherent bandwidth of RQL / SFQ memory and logic. While (i) the CAM circuit 606 embodiment of FIG. 6A , which manages the timing between TLB_Match 602 and TLB_Array 604, and (ii) the serial compare equality determiner circuit 1100, are shown, a comprehensive alternative cache embodiment (and the expanded line discussed above) appears unsatisfactory. One or more embodiments of cache lookup pathways will be developed later, taking into account various circuit enhancements to support alternative caches and TLB associativity.

[0075] It is important to discuss in detail yield-reducing circuit issues that may be inherent in the lookup path design 600 shown in FIG. 6A and the associated directory design of FIG. 10, including the PTL or JTL or pass-through upper or lower interconnects shown in FIGS. 6 and 10. Superconducting processes have far fewer layers for signal transmission than semiconductor processes. The PTL or JTL or pass-through upper or lower interconnects carry physical address signals to the serial compare equality determination circuit 1100 in association with the directory RAMs 608 (DIRECTORY_RAM_1, 2, 3). These address signals are logical replicas of the physical address bits of TLB_ARRAY 604 (e.g., PA_8_RQL through PA_12_RQL). They are included in the schematic diagram of FIG. 6A and the physical design of FIG. 10 and are labeled as such to clarify the additional burden (in the physical design) of propagating signals through, above, or below the DIRECTORY_RAM_0, 1, 2, 3 608. Such a solution, if implemented, may be conceptually simpler than alternatives, but may come at significant expense, including: (i) more layers may be added to a superconducting process already burdened by yield issues, or (ii) the pass-through signal may be contained in an area allocated to memory cells, again resulting in yield issues. These yield-reducing circuit issues (as well as the peak bandwidth issues imposed by PTL) may be addressed by wave pipelining (e.g., time division multiplexing, TDM) embodiments of the inventive concepts, which will be discussed in more detail herein below.

[0076] FIG. 11 is a block diagram illustrating at least a portion of an exemplary serial comparison equality determination circuit 1100 in accordance with one or more embodiments of the inventive concepts. The serial comparison equality determination circuit 1100 may use logic gates to implement three principle internal functions: an XOR gate (e.g., formed from an AND-OR gate and an AnotB gate) configured to detect bitwise mismatches, an OR gate to accumulate mismatch results, and an AnotB gate to convert the overall miss signal (i.e., indicating a mismatch has occurred) to a hit signal (i.e., indicating a match has been found). Each spine OR gate, labeled "OR_s," is configured to merge the most recent mismatch result of the XOR gate with all previous mismatch results. Any single-bit mismatch causes a miss equal to "1" or a hit equal to "0" to be registered by the serial comparison equality determination circuit logic.

[0077] More specifically, serial compare equality determination circuit 1100 includes a plurality of XOR gates, each configured to receive as inputs a pair of physical address bits from directory RAM 608 and from TLB array 604 corresponding to a given RQL period and phase. The output generated by each XOR gate is provided as an input to a corresponding one of the spine OR gates. The output generated by each spine OR gate is provided as an input to a subsequent adjacent spine OR gate in a string of sequentially connected spine OR gates.

[0078] Regarding the subtle timing constraints 1104 on the latency of OR_s of the serial compare equality determination circuit 1100, it should be understood that they vary according to (i) non-TDM, (ii) TDM, and (iii) other non-TDM contexts: the latency of OR_s is (i) for FIG. 6A when it does not utilize TDM in its lookup path for less than one time of each memory cell's allocated time "T"; and (ii) for FIGS. 13 and 16 when it does not utilize TDM in its lookup path for less than two times of each memory cell's allocated time "T."

[0079] In Figure 11, the serial compare equality determination circuit 1100 may be rotated 90 degrees counterclockwise with respect to the TLB array 604 and director RAM 608 of Figure 6A. The directory RAM inputs are also shown on the same side as the TLB inputs. The orientation indicators 1102 for the label read column lines of the TLB array 604 (RCL_TLB), the read column lines of the directory array 608 (RCL_Dir), and the read row lines of both arrays 604, 608 (RRL_Both) represent both the previously mentioned 90 degree counterclockwise rotation and the dominant signal flow for all arrays 604, 608 as it relates to the serial compare equality determination circuit 1100. Also noteworthy is that for simplicity, the JTL is not shown (although that is true for embodiments of the present invention).

[0080] In the schematic diagram, a specific physical bit address number, its assigned RQL period, and its assigned phase are shown on the TLB and directory inputs to each XOR gate according to the convention: PA<specific_physical_bit_address_number>_RQL_period<RQL_phase_in_period>-RQL. Entries in italics have the actual physical numbers assigned in the schematic diagram as they relate to (and follow) the 128x128 memory array sizing being discussed. Final Output - "Valid"_12 <p0>-RQL- follows the physical address bit (PA) in this timing sequence. This timing relationship is where other "valid" bits are added. <p0>-RQL (or as "effective" _12-RQL) remains consistent regardless of how it appears or will appear in the schematic diagrams (Figs. 7, 8, 10, 11, 12, and 15).

[0081] FIG. 12 is a block diagram illustrating at least a portion of an exemplary serial comparison equality determination circuit 1200 having increased bandwidth compared to the exemplary serial comparison equality determination circuit 1100 shown in FIG. 11 , according to one or more embodiments. Specifically, the exemplary serial comparison equality determination circuit 1200 may provide increased bandwidth due, at least in part, to mixed parallel and serial logic processing associated with its basic mismatch propagation building blocks, enclosed by dashed box 1204 (i.e., three JTL, AND-OR, AnotB, and OR_s gates, where the serially connected AND-OR and AnotB gates implement the XOR functionality). Similar to the embodiment shown in FIG. 11 , the serial comparison equality determination circuit 1200 may use the following logic gates to implement the noted internal functions: (i) an XOR gate for detecting bitwise mismatches, (ii) an OR gate for summing / combining mismatch results, and (iii) an AnotB gate for converting the overall miss signal to a hit signal.

[0082] Referring to FIG. 12 , each spine OR (“OR_s”) in serial comparison equality determination circuit 1200 can be configured to merge the mismatch result from the corresponding XOR gate with all previous mismatch results. Serial comparison equality determination circuit 1200 includes four parallel mismatch paths, 1 through 4, that will be identical and within their phase positions as shown in FIG. 12 , except for a possible one RQL period shift (occurring from phase 3 to phase 1), any single phase shift. This final point may not be represented by the schematic diagram, and therefore is not shown in the schematic diagram; rather, the setting value will derive from timing assessment of the actual design. In one or more embodiments, three OR gates 1206, 1208, and 1210, fed by the four mismatch paths 1 through 4, are configured to merge the separate path results into a single mismatch result for the entire physical address field associated with the directory and TLB tag addresses. Any single-bit mismatch anywhere along the single-mismatch path will generate a miss signal equal to "1" or a hit signal equal to "0" to be registered by the serial compare equality decision logic.

[0083] The critical point with respect to timing relaxation is that serial compare equality determination circuit 1200 has four times fewer stages along its parallel mismatch paths 1 through 4 spines than serial compare equality determination circuit 1100 has along its single spine. Therefore, four times more latency can be allocated to each stage as shown in schematic diagram 1200. A key design rule—a timing constraint on the latency of ORs 1202—may be that the latency of all spine ORs (OR_s) cannot exceed four times the allocated time “T” of each memory cell.

[0084] The exemplary embodiment shown in Figure 12 may be referred to as a serial compare equality determination circuit given the nature of how it merges timing-order physical address bit comparisons, but it may also be referred to as a parallel-serial compare equality determination circuit because it includes both parallel and serial ORing components. In this example, the internal circuitry (three JTL, AND-OR, AnotB, and OR_s gates) may be configured with an inherent RQL phase latency four times that of a memory cell. Because the topology includes at least eight OR gates and eight JTLs, the minimum phase latency of the memory array may be inferred, for example, from Burnett 2018.

[0085] 13 is a flow diagram conceptually illustrating at least a portion of an exemplary lookup path 1300 of a two-way set-associative cache that implements virtual-to-physical address translation and has a fully associative TLB (based on a CAM), according to one or more embodiments. This lookup path 1300 may be configured to implement what is known in the art as physically indexed and physically tagged directories. While several logical features of this exemplary embodiment are specifically mentioned, it should be understood that embodiments of the present invention are not limited thereto.

[0086] The lookup pathway of an N-way set associative cache (shown in FIG. 13 as a 2-way set associative cache) may include TLB_Match 602 (e.g., Translation Lookaside Buffer Content Addressable Memory), TLB Array 604 (Physical) (a Translation Lookaside Buffer array that holds physical addresses), multiple Serial Compare Equals Determining Circuits 1100 (e.g., where the majority is practically constrained to two here due to memory cell dimensions associated with pitch matching between the TLB_Array and Directory_RAM), and Directory_RAM 1308 (Physical and MESI), where, when accessed, Directory_RAM 1308 stores two different Tag-Phys for separate application to the two Serial Compare Equals Determining Circuits 1100. Dir _0, Phys Dir _1-, and the TLB_Array 604 generates a physical address corresponding to one set of high-order physical address bits—Phys_1- for application to both serial compare equality determination circuits 1100. TLB_配列 Hits / misses can be resolved to physical addresses using techniques known in the art and as described above.

[0087] Important to this two-way set associative cache is that directory_RAM 1308 holds tags and MESIs corresponding to directions / sets 0 and 1. Given that directory 1308 is two-way (i.e., two tag entries), while a fully associative TLB has only one tag entry, the pitch-matched width (as measured along their RRL) of the memory cells of directory_RAM 1308 may be half that of the memory cells of TLB_array 604 (also measured along their RRL). Also, the latency assigned to each mismatch stage of compare / equal determiner 1100 may be twice that assigned to each memory cell of directory RAM 1308.

[0088] FIG. 14 is a flow diagram of at least a portion of an exemplary lookup path 1400 of a direct-mapped cache implementing virtual-to-physical address translation with a fully associative TLB (based on a CAM), according to one or more embodiments. Like the exemplary lookup path 1300 of FIG. 13, the lookup path 1400 shown in FIG. 14 may be configured to implement a physically indexed and physically tagged directory. While several logical features of this exemplary embodiment are specifically mentioned, it should be understood that embodiments of the present invention are not limited thereto. Unique to this embodiment is the use of time division multiplexing (TDM) to relax pitch constraints imposed on the serial compare equality determination circuit. Advantageously, the height allocated to the combination of bitwise false compare (i.e., XOR) and propagate (i.e., OR) elements within this TDM circuit 1500, referred to as TDM serial compare equality determination circuit 1500, may be twice the height of the serial compare equality determination circuit 1100 of FIG. 11.

[0089] A consequence of the column-oriented TDM implemented in this design is that the lookup path operating bandwidth can be reduced by a factor of two. The "2-bit read TDM" (column-oriented TDM) circuit 1402 can provide half the physical address width in each of its two associated cycles. Because only half the number of comparisons are performed per cycle, a 2x timing mitigation in the "OR spine" of each TDM serial compare equality determination circuit can be realized. Roughly speaking, such timing mitigation can be necessary to match memory with a fast per-memory cell latency (previously described as the timing budget "T") with logic with a slower stage delay (which can be allocated more time and incorporate more functionality).

[0090] It is important to note that in lookup path 1400, the physical even (cycle 1) and physical odd (cycle 2) address bits are converged to the TDM serial compare equality test 1500. TLB_Even ,Phys TLB_Odd and Phys Dir_Even ,Phys Dir_Odd The signals are provided to a TDM serial compare equality determination circuit 1500 via a "2-bit read TDM" (column-oriented TDM) circuit 1402 and indirectly by the TLB array 604 and directory RAM 608, respectively.

[0091] Like the column-oriented TDM utilized in lookup pathway 1400, careful use of TDM can provide numerous advantages, including, among other benefits: (i) energy savings, (ii) physical pitch matching (i.e., better aspect ratio of logical cell pitch matched to memory cell), (iii) timing mitigation (e.g., 2x, 4x, etc.), (iv) alternative memory array organization / footprint (i.e., row vs. column), and (v) alternative memory array latency. TDM use case examples emerge in subsequent lookup pathway embodiments themselves, which utilize multiple-cycle copy circuit techniques to have waves of computation pass through the circuit to achieve the logical goal of a critical function. With respect to direct memory array interaction, it should be noted that "column-oriented" TDM relating to memory arrays is described in U.S. patent application Ser. No. 17 / 993,543, entitled "Time-Division Multiplexing for Superconducting Memory" ("Reohr 2022"), filed November 23, 2022, the disclosure of which is incorporated herein by reference in its entirety, and that "row-oriented" TDM and "control-based TDM" will be primarily described with respect to Figures 18 and 22.

[0092] 15 is a schematic diagram illustrating at least a portion of an exemplary serial comparison equality determination circuit 1500, according to one or more embodiments. In the exemplary serial comparison equality determination circuit 1500, a combination of the one-cycle-delayed mismatch signal with the current mismatch signal by a cycle-delayed merge circuit 1506 forms an overall mismatch (hit) signal. More specifically, within the bitwise mismatch stage (on the left side of the schematic) of this serial compare equality determination circuit 1500, two waves (two sets of signals passing through the same location on different cycles) associated with one cache lookup access and one portion of the physical address (e.g., a single tag in the lookup path 1400 of a direct-mapped cache shown in FIG. 14) combine and propagate through spine ORs (OR_s) to a cycle-delayed merge circuit 1506 into a single hit signal that is available and sampled on the second of the three cycles of signals associated with (triggered by) the lookup (including parallel accesses of TLB_ARRAY 604 and DIRECTORY_RAM 608). The separate even and odd bit waves enabled by column-oriented TDM propagate down the spine until the individual bit mismatch results are collected and merged by a period-delay mismatch merging circuit 1506, which may include a first one-period delay circuit 1512, a second one-period delay circuit 1507, an OR circuit 1508, and an AnotB circuit 1510, where the AnotB circuit propagates only the merged hit signal (which occurs on the second of the three periods of the signal associated with (triggered by) each lookup).

[0093] Note that the even bit mismatch is available on the first of three cycles, the ORed even and odd bit mismatches are available on the second of three cycles, and the odd bit mismatch is available on the third of three cycles. The second cycle functions as the merging cycle. Specifically for the TDM serial comparison equality determination circuit 1500, "valid" _12 <p1 or p2> serves to generate a hit signal (comparison "out") via the A not B gate 1510 and sample the resulting incorrect comparison. Generally, the cycle delay merge circuit 1506 can perform the merge with parity data generated, for example, by an XOR serial connection chain (useful in the place of a spine OR serial connection chain).

[0094] The TDM serial comparison equality determination circuit 1500 of FIG. 15 shows odd bits to represent its odd circuit topology influence / change: the TDMby2 circuit does not face the rightmost XOR. In other words, PA <n-1> _12 <p0>(of the TLB array 604) and PA <n-1> _12 <p0>(in DIRECTORY_RAM 608) drives XOR (rightmost) 1504. There are only half as many XORs and spine ORs (labeled "OR_s") as other serial compare equality determination circuits (e.g., serial compare equality determination 1100 in FIG. 11).

[0095] 16 is a flow diagram of at least a portion of an exemplary lookup path 1600 of a two-way set-associative cache with a fully associative TLB (based on a CAM) in accordance with one or more embodiments. The lookup path 1600 may be configured to implement virtual-to-physical address translation and may be further configured to implement physically indexed and physically tagged directories. The use of TDM in the lookup path 1600 allows the lookup path 1600 to process requests at half the peak bandwidth of the arrays (TLB_Match 602, TLB_Array 604, and Directory_RAM 1608) and logic.

[0096] Referring to FIG. 16, lookup path 1600 includes directory_RAM 1608, which may be a full directory configured to store physical address bits and cache management bits (e.g., MESI) corresponding to sets 0 and 1. The physical address bits / memory cells of sets 0 and 1 may be interleaved (i.e., staggered) along row lines. In one or more embodiments, the width of the memory cells of directory_RAM 1608 is half that of the TLB_Array(Physical) blocks 1604 included in lookup path 1600. This dimensional reduction in memory cell width is along the read row lines (RRLs) of directory_RAM and that of TLB_Array(Physical). Directory_RAM 1608 also stores index addresses, I0 through I1. N-1 It may receive as input up to

[0097] Operatively coupled to the output of the DIRECTORY_RAM 1608 in the lookup path 1600 is a 2-bit read circuit. The 2-bit read circuit may be a column-oriented TDM circuit (e.g., consistent with the TDM read circuit described in Reohr 2022). The 2-bit read TDM circuit (column-oriented read TDM) 1606 reads the first output bit (PhysDir_0) of the DIRECTORY_RAM 1608. <0> _8-RQL <p0>The serial compare equality determination circuit 1100 may be configured to forward, without substantial delay, the first adjacent output bit of the directory_RAM 1608 (specifically referred to as "PhysDir_1") to the serial compare equality determination circuit 1100. This output bit preferably represents the bit, tag 0, stored in the associated first memory cell. <0> _8-RQLs <p0>The first bit of PhysDir_1 (specifically referred to as "PhysDir_1") may be delayed by one RQL (SFQ) period and then forwarded to the serial compare equality determination circuit 1606 (both actions are performed by the 2-bit read column-oriented TDM circuit 1606). In this way, each tag bit of the two-way set associative directory is stored in a CAM 606 consisting of the physical address, PhysDir_1, retrieved from the TLB (which may be a CAM 606 consisting of TLB_Match 602 and TLB_Array 604 components). TLB , provided for comparison. Phys TLB Two functionally identical copies of the TLB_ARRAY 604, one delayed by an RQL period from the other, may be generated for each TLB access by a read and one-period-delayed read circuit coupled to the output of TLB_ARRAY 604, and the outputs of both TLB_ARRAY 604 and the directory RAM may be skewed by at least one RQL period, so that the signal Phys TLB and Phys Dir_0,1 Note that this is also the case.

[0098] In the case of a TLB match, for the first relevant TLB_ARRAY output RQL cycle (e.g., "n"), the physical address retrieved (i.e., read) from TLB_ARRAY 604 propagates through the respective OR gates of the Read and Read with a 1 Cycle Delay circuit 1604, as indicated by one bit in the Read and Read with a 1 Cycle Delay circuit 1605. This physical address is compared with the tag portion of the Set 0 physical address retrieved from the Directory_RAM 1608. This tag, which corresponds to a portion of the physical address of the line stored in Set 0 and is indexed by the index address obtained in the table formed by Directory_RAM 1608, may be referred to as Tag 0 because it is associated with the Hit 0 output of the serial compare equality determiner, which indicates whether Set 0 of the data cache stores the indexed line.

[0099] In the case of a TLB match at the second related TLB_ARRAY output RQL cycle (n+1), a copy of the physical address retrieved from TLB_ARRAY 604 may be generated (e.g., by a read and one-cycle-delay read circuit) and delayed one RQL cycle. The copy of the physical address is compared with the tag portion of the Set 1 physical address retrieved from Directory_RAM 1608 and further delayed by an RQL cycle by 2-bit read column-oriented TDM circuitry 1606. This tag, which corresponds to a portion of the physical address of the line stored in Set 1 and is obtained in a table formed by Directory_RAM 1608 and indexed by the index address, is referred to as Tag 1 because it is associated with the Hit 1 output of the serial compare equality determination circuit, which indicates whether Set 1 of the data cache stores the indexed line.

[0100] Compared to the exemplary embodiment of FIG. 13, the Hit 0 output may be calculated one RQL cycle before the Hit 1 output in the embodiment shown in FIG. 14. Also, given the two-wave processing that occurs in the serial compare equality test circuit, a fetch or store pretest operation through the cache's lookup path occurs every other cycle. While TDM (column-oriented) may reduce the bandwidth of the lookup path 1600 by half, the need for JTL pass-through may be eliminated, thereby saving comparators. Additionally, and more importantly, for the lookup path 1600, the timing allocated to each spine OR (OR_s) of the serial compare equality test 1100 may be twice that allocated for each memory cell of the directory RAM 1608. Higher speed SFQ memory cells (e.g., as described in Herr2023) may require spine OR logic with the aforementioned relaxed timing allocation.

[0101] 14, for example, in instruction cache applications, the TLB and directory pipelines may be long enough in terms of latency that it is difficult to determine how the instruction stream may diverge to update the program counter (cache operation requester), so having reduced bandwidth may have a less significant impact on performance. It will be apparent to those skilled in the art that spatially, larger lines can be incorporated into the cache.

[0102] FIG. 17 is a flow diagram of at least a portion of an exemplary lookup path 1700 of a two-way set associative cache with a fully associative TLB (based on a CAM) that implements virtual-to-physical address translation, according to one or more embodiments. Like the lookup path 1600 of FIG. 16, the lookup path 1700 may include TLB_MATCH 602 and TLB_ARRAY 604 blocks, and a Read and Read-One-Cycle-Delay block 1710 coupled to TLB_ARRAY 1604. TLB_MATCH 602 and TLB_ARRAY 604 may be configured to provide two accesses of the TLB to the same virtual address, along with two parallel accesses to directory row lines that store the tags of the indexed Set 0 and Set 1 entries. The output generated by TLB_ARRAY 604, Phys TLB , are fed to the serial compare equality determination circuit 1100. Due to the use of TDM in the lookup path 1600, the lookup path 1600 processes requests at half the peak bandwidth of the arrays (TLB_Match 602, TLB_Array 604, and Directory_RAM2 1708) and logic.

[0103] Lookup path 1700 may be configured to implement a physically indexed and physically tagged directory. More specifically, lookup path 1700 may further include a directory, directory_RAM_2 wave 1708, which may be a full directory that stores physical address bits and cache management bits (e.g., MESI) corresponding to Set 0 and Set 1. Directory_RAM_2 wave 1708 may be configured such that one read request triggers two waves of data—TDM data—from the RRL (or, in FIG. 18 , adjacent RRLs) to be retrieved forward from RAM. The physical address bits / memory cells of Set 0 and Set 1 may be stored in separate RRLs.

[0104] Distinguished from the lookup pathway 1600 of FIG. 16, the directory_RAM_2 wave 1708 shown in FIG. 17 may use row-oriented TDM instead of or in addition to the column-oriented TDM described above. Advantageously, row-oriented TDM (enabled on the row lines) allows the same memory cells to be located in both the TLB_array 604 and the directory_RAM_2 wave 1708 because the physical tag bits may be aligned between them. Only one set is read from the directory per cycle for two consecutive cycles related to a single lookup request. The row-oriented TDM configuration of the directory_RAM_2 wave 1708 will be described in more detail herein below in connection with the schematic diagram shown in FIG. 18 and its associated read timing diagram shown in FIG. 19, in accordance with one or more embodiments of the inventive concepts. (It is worth noting that the lookup pathway with control-based read TDM, described with reference to FIG. 22, functions in substantially the same manner as the lookup pathway 1700 of FIG. 17.)

[0105] 18 is a schematic diagram illustrating at least a portion of an exemplary RQL (or SFQ) time division multiplexed memory array 1800 that uses TDM to read data from memory cells (or fixed switch / ROM cells, as known in the art) in the array, in accordance with one or more embodiments of the present invention. The memory array 1800 includes corresponding RRLs (RRLs) in this exemplary embodiment, where the RRLs and RCLs are oriented substantially perpendicular to one another. <0> From RRL <n-1>) perpendicularly along the RCL (RCL <0> From RCL <m-1>) arranged horizontally along a line 1804. Each dashed box represents a set (i.e., collection or grouping) of adjacent memory cells in the array 1800, with the right dashed box representing the memory cells furthest from their respective data outputs and the left dashed box of FIG. 18 representing the memory cells nearest to their respective data outputs. The memory array 1800 further includes a read decoder and driver operatively connected to the corresponding set of memory cells. Data from one memory cell in a given RCL is passed to memory cells in an adjacent RRL of that RCL. Data Output, Output <0> Output from <m-1>Until the last RRL (RRL) in each RCL in the memory array 1800 <n-1>) is generated by the memory cell associated with

[0106] The time-division multiplexed memory array 1800 can be used in conjunction with JTLs and RCLs (i.e., read column lines) based on OR gates. In the exemplary read path associated with the time-division multiplexed array 1800, the controlling signal is a logic "1," and therefore the array read path is assumed to preferably use an OR gate, although embodiments of the inventive concept are not limited to these assignments. For example, it should be understood that in other embodiments where the controlling signal is a logic "0," the read path could use an AND gate instead of an OR gate, as would be apparent to one skilled in the art.

[0107] 19 is a timing diagram conceptually illustrating certain example signals in the example time-division multiplexed memory array 1800 shown in FIG. 18 during a TDM read operation, in accordance with one or more embodiments. For a TDM read operation described in conjunction with the time-division multiplexed memory array 1800 of FIG. 18, the subscript letter attached to a given memory cell indicates the location / address of the memory cell, while the parenthetical indicates the state of the memory cell. (See the four memory cells in the upper right quadrant of FIG. 18. Note that the labels A, B, C, and D associated with the states of the memory cells are unrelated to the cache direction / set labeling that often uses those letters in the prior art.)

[0108] More specifically, as shown in the read timing diagram of FIG. 19, the memory array 1800 of FIG. 18 reads the RRL in the subsequent RQL cycle. <1> Followed by the launch of RRL <0> Triggered by the activation of,its representative output, output <0> and output <1> (All outputs are from 0 to <n-1>Two successive waves of RRL results may be generated as a time-division multiplexed set of data for each RRL and each RCL (which will include up to and including 10 ...

[0109] As an extension of this exemplary embodiment, the circuitry included in the time-division multiplexed memory array 1800 (e.g., the read decoders and drivers, which are implied but not explicitly shown) can be designed to send out multiple waves associated with a multi-row access by simply forwarding the enable signal through at least one period delay element onto the next read row line. Furthermore, the timing between waves can be extended by an integer number of desired RQL periods rather than a single RQL period (labeled "1 period delay") as shown in the schematic diagram.

[0110] Only one final stage decoder and driver 1806 (e.g., "close") connects the first and second RRLs (e.g., RRL <n-1>and drives RRL<N - 2..), and the second RRL is driven by a signal with a cycle delay from the first RRL generated by the one - cycle delay circuit 1804. Thus, the time - division demultiplexed memory array 1800 of FIG. 18 beneficially reduces the number of the final decoder and driver stages, the final - stage decoder and driver 1806, by a factor of two (at least, a factor of two for sending out multiple waves of data from generally integer columns).

[0111] FIGS. 20 and 21 are block diagrams and corresponding write timing diagrams conceptually showing a time - division demultiplexed memory array 2000 and an exemplary write operation related thereto, respectively, according to one or more embodiments. Note that in FIGS. 20 and 21, the write row lines are abbreviated as WRL, and in FIG. 20, the write column lines are abbreviated as WCL.

[0112] Referring to FIG. 20, like the exemplary memory array 1800 shown in FIG. 18, the memory array 2000, in this exemplary embodiment, has corresponding WRLs (from WRL<0> to WRL <n-1>) and the corresponding WCL (WCL <0> From WCL <m-1>20 ) with the WRL and WCL oriented substantially perpendicular to one another. Each dashed box represents a set (i.e., collection or grouping) of adjacent memory cells in the array 2000, with the dashed boxes on the right representing the memory cells furthest from their respective data inputs and the dashed boxes on the left of FIG. 20 representing the memory cells nearest to their respective data inputs. The memory array 2000 further includes a write decoder and driver operatively connected to the corresponding set of memory cells. Data from one memory cell in a given WCL is passed to memory cells in an adjacent WRL of that WCL. Data input, Data_In <0> From Data_In <m-1>until the first WRL (WRL <0> ) is supplied to the associated memory cell.

[0113] An exemplary data input, Data_In, is provided for multiple rows of a memory array (represented by data A, B, C, and D). <0> , Data_In <1> (All inputs are from 0 to <n-1>A single associated write operation of the time division demultiplexed memory array 2000 is described, storing TDM data presented in rows 1 to 4 (including rows 1 to 4). The write demultiplexing is performed in separate, preferably adjacent, rows.

[0114] Only one final stage decoder and driver 2006 (e.g., "close") is connected to the first and second WRLs (e.g., WRL <n-1>and WRL <n-2>) and the second WRL is driven by a period-delayed signal from the first WRL, generated by a one-period delay circuit 2004, the time-division demultiplexed write memory array 2000 of FIG. 20 beneficially reduces the number of final decoder and driver stages, final stage decoder and driver 2006, by a factor of two.

[0115] 21 is a timing diagram conceptually illustrating certain example signals within the example time division demultiplexed memory array 2000 shown in FIG. 20 during a TDM write operation, in accordance with one or more embodiments. For a TDM write operation, as described in conjunction with the time division demultiplexed memory array 2000 of FIG. 20, the subscripts attached to a given memory cell (i.e., Memory_Cell A , Memory_Cell B , Memory_Cell C , and / or Memory_Cell D ) indicates the location / address of the memory cell, while its parenthetical (i.e., A, B, C, and / or D, respectively) indicates the state of the memory cell after it has been written.

[0116] More specifically, as shown in the write timing diagram 2100 of FIG. 21, the memory array 2000 of FIG. 20 operates by switching the write row line WRL <1> followed by the activation of the write row line WRL <0> Its representative input, Data_In, is triggered by the activation of <0> and Data_In <1> (All inputs are from 0 to <m-1>The WRL receives two successive waves of data at its input as a time-division multiplexed set of data for each WRL and each WCL (up to and including the N×M memory array). The ellipses along each WRL and each WCL are intended to represent a larger N×M memory array.

[0117] In the write timing diagram 2100 of Figure 21, before a memory cell is written, it contains an unknown (or previous) state, labeled "X" in Figure 21. A , Memory_Cell B , Memory_Cell C , and Memory_Cell D After being written, they contain their new states, A, B, C, and D, respectively. The subscripts and parentheses are chosen to correspond (be identical) to provide clarity as to which memory cells the TDM write data is directed to. The two waves are written to different rows, A and B in the first wave. <0> and WRLs of C and D in the second wave <1> Note that, , is stored in the associated memory cell.

[0118] As an extension of this exemplary embodiment, the circuitry (e.g., read decoders and drivers) included in the time-division multiplexed memory array 1800 can be designed to send out multiple waves associated with a multi-row access by simply forwarding the enable signal through at least one period delay element onto the next read row line. Furthermore, the timing between waves can be extended by an integer number of desired RQL periods rather than a single RQL period (labeled "1 period delay") as shown in the schematic diagram.

[0119] One subtlety worth mentioning is that while this example embodiment—time division demultiplexed memory array 2000—depicts row-oriented TDM write operations, only row-oriented TDM read operations of the memory array (labeled DIRECTORY_RAM_2 wave 1708 in FIG. 17) need be enabled for cache read operations. For directory write operations, only a single tag needs to be modified to write the directory. However, the row-oriented TDM write approach can be used, for example, to load a new line in data RAM (of a cache) if the line has a distinct index address, allowing it to be stored across two waves separated by at least one RQL period.

[0120] 22 is a flow diagram illustrating at least a portion of an exemplary lookup path 2200 for a two-way set associative cache that implements virtual-to-physical address translation with a fully associative TLB, according to one or more embodiments. Lookup path 2200 represents an alternative to the exemplary approach shown in FIG. 17. In the exemplary embodiment of FIG. 22, instead of using row-oriented TDM circuit 1800 of FIG. 18 (associated lookup of FIG. 17), Phys Dir_0 Holds Tag 0 (Through Way 0) and Phys Dir_1 Such two-wave output for accessing the two portions of the address associated with Tag 1 (Through Way 1), which holds the address, can also be generated through a normal memory array (e.g., RAM) access by making read directory RAM 2208 requests on successive RQL cycles. Similar to the lookup operation 1800 enabled by the technique shown in FIG. 18, the technique 2200 shown in FIG. 22 enables a lookup operation only every other RQL cycle. This alternative technique is a "control-based" version of TDM (control-based TDM) primarily because two full directory RAM 2208 accesses occur for each logical lookup operation, i.e., multiple waves of data can be processed during each functional lookup access. A standard lookup operation can occupy one system cycle (i.e., bandwidth) of RAM throughput. To support the lookup, two requests to the TLB CAM 2206 retrieve data from the same location (e.g., logical address 0).

[0121] Unlike the "page mode" used in standard DRAM, where additional data from a single read access is present in the output latch (associated with the memory cell sense and restore operation) after the read operation so that the data can be fetched in a subsequent cycle (before the output latch / sense amplifier is precharged), two full accesses are now performed for the RAM, independently traversing the read decoder, RRL, memory cell, and RCL.

[0122] As explained with respect to previous figures (e.g., Figures 3A, 3B, and 3C), the output of a RAM read request for a reasonably sized (e.g., 128 RRL x 128 RCL) array is skewed in time across an RQL period, so the term "wave" is used herein to describe the processing of addresses in Figure 22 rather than "period." A "period" or "multiple periods" will have to be specified across ranges. Herein, the integers N and M are also intended to provide an indication of the cumulative latency through each circuit element (i.e., RAM, CAM, and serial compare equality determination).

[0123] "Hit 0" and "Hit 1" can occur as waves N+M and N+M+1, respectively, the former at a particular RQL period while the latter follows one RQL period later, as is evident from the schematic diagram of serial comparison equality determination 1100. Two sets of inputs - (i) applied in combination, Phys Dir_0 and Phys TLB and (ii) applied in combination, Phys Dir_1 and Phys TLB - respectively produce two outputs - (i) Hit 0 and (ii) Hit 1. Within the serial compare equality determination circuit, the skewed outputs from each of the two access sequences converge in time (i.e., merge) at the "Hit" output into two signals in quick succession, occupying two corresponding RQL periods.

[0124] Note that the entries to the directory are labeled "Index Address 0 (+Tag 0)" and "Index Address 0 (+Tag 1)". Although they are different addresses, they are labeled with the "Index Address 0" prefix to remain consistent with existing cache nomenclature and its associated address mapping and memory array access structures. The tag bit can be the low-order bit of the directory (RAM) address and can be "0" for the first access and "1" for the second access.

[0125] Figure 23 shows an example flow diagram of the TLB virtual address match portion of the lookup pathway of a four-way set associative cache that implements virtual (i.e., logical) to physical address translation, according to one or more embodiments. Together, Figures 23 and 24 illustrate the combined overall lookup pathway 2300, 2400 for an example four-way set associative cache having an overall two-way set associative TLB. Due to the inclusion of TDM (e.g., two-wave access per lookup operation—preferably row-oriented TDM) to align the pitch of the two-wave four-way directory RAM 2404 and the two-way TLB_RAM 2402, this lookup pathway operates at half the bandwidth that would otherwise be enabled by its RQL micro-pipeline.

[0126] The combined superconducting set-associative lookup pathways 2300, 2400 in this exemplary embodiment can be configured to implement physically indexed and physically tagged directories as well as virtually indexed and virtually tagged TLBs. The combined lookup pathways 2300, 2400 of an N-way set associative cache (denoted herein as a 4-way set associative cache, easily modified to N-way, where N is an integer greater than 1) include at least one TLB tag array, TLB_TAG_ARRAY_X 2302 and TLB_TAG_ARRAY_Y 2302 (e.g., TLB_TAG_ARRAY 2302), that stores virtual addresses; at least one TLB RAM 2402 that stores corresponding physical addresses; at least one serial compare equality determination circuit 2306 associated with the TLB tag array and that generates two identical results on successive cycles (e.g., shown as "TLB_HIT_X, TLB_HIT_X" in FIG. 23) for comparing the tag portion of the virtual address with the output of the TLB tag array (labeled "Stored_Virtual_Tag"); at least one directory RAM configured for time division multiplexing (DIRECTORY_RAM 2 wave 2404); The TLB 2402 includes at least one serial comparison equality determination circuit 1100 for comparing the RAM 2402 and directory RAM 2404 outputs, at least one AND circuit, and at least one OR circuit, where all serial comparison equality determination circuits complete their bit-wise match evaluation over multiple RQL cycles (e.g., two cycles) of each lookup operation, and the AND OR circuit determines virtual matches (denoted as "TLB_HIT") and director matches (denoted as "HIT"). Phys ") are combined to generate an overall hit signal (denoted "Hit").

[0127] More specifically, the portion of the embodiment of the lookup path 2400 shown in FIG. 24 includes four serial compare equality determination circuits 1100, four AND circuits, and two OR circuits that perform operations on two waves of data for each required lookup operation.

[0128] In conventional methods, the signal appears from the RAM in the same or, at most, the next cycle. The comparison is completed in less than a single cycle. Furthermore, multiple tag matches (i.e., physical address matches) can occur within one wave or multiple waves, as described with reference to FIG. 24. The AND OR logic at the output of the serial compare equality determination circuit 1100 shown in FIG. 24 can ensure that the translated address from the TLB, one of the two physical addresses, is valid and that the directory stores that particular address. This notation is intended to indicate that Hit 0 and Hit 1 are calculated from the first wave of data retrieved from the TLB RAM and directory RAM—specifically, by accessing the first read line of a wave-pipelined pair of read line lines in the directory RAM as described with reference to FIG. 24—while Hit 2 and Hit 3 are calculated from the second wave of data retrieved from the TLB RAM and directory RAM—specifically, by accessing the second read line of a wave-pipelined pair of read line lines in the directory RAM as described with reference to FIG. 24.

[0129] It is important to note that the physical design (layout) of the combined lookup paths 2300, 2400 is specified so that the TLB RAM 2402 (a two-way set associative TLB) can be directly aligned with the directory RAM 2 wave 2404 (a four-way set associative directory). The memory cells of the TLB RAM 2402 can store the PhysTLB_X and PhysTLB_Y bits interleaved along each RRL. The memory cells of the directory RAM 2 wave 2404 can store the PhysTLB_X and PhysTLB_Y bits interleaved along each even RRL. Dir_0 and Phys Dir_1 bits and (ii) the interleaved Phys along each odd RRL Dir_2 and Phys Dir_3 18 )。 With this physical and logical structure, a common (identical) memory cell layout can be advantageously used for all of the following memories: (i) TLB tag array 2302, (ii) TLB RAM 2402, and (iii) directory RAM 2404.

[0130] Figures 25 and 26 collectively illustrate the lookup paths of an exemplary two-way set associative cache having a generally two-way set associative TLB, according to one or more embodiments. In contrast to the exemplary lookup path shown in Figure 24, the exemplary lookup path shown in Figures 25 and 26 can operate at the full bandwidth of the underlying RQL micro-pipeline. Unfortunately, its "hit" rate can be much lower due to its associativity being set half as low (two-way associative in Figure 26 vs. four-way associative in Figure 24).

[0131] Given that the latency of a cache is already large compared to its bandwidth, there is little advantage to be derived in using a full bandwidth cache in all cases where the hit rate was the same, even if they were not.

[0132] Principles according to embodiments of the present disclosure can be used to configure pipelined SFQ memory arrays such that the period during which their output data is available (e.g., from a cache) is a function of (i.e., dependent on) the value of a subset of their address bits (e.g., the most significant address bits), where the value of that subset of address bits can indicate how far the signal generating the output data, associated with the decoded address, must travel primarily within the column of the memory array itself; i.e., the value of the subset of address bits can be coded to represent the distance associated with the signal path between a memory cell and its corresponding output logic. The subset of address bits and their associated row will be referred to herein as a “fixed-delay address” subset. Rather than suppressing the variable pipeline latencies inherent in SFQ, one or more embodiments of the inventive concepts seek to exploit them. These embodiments can be applied not only to memory arrays, but more broadly to interchangeable (i.e., fungible) logic and memories. Thus, one or more embodiments described in more detail below may apply equally to "memory arrays," "logic arrays," and interchangeable arrays. It should be understood that incorporating variable latency arrays may add complexity and area to the design of the entity receiving the data, e.g., a CPU, with significant tradeoffs in performance.

[0133] It should also be understood that the delays of the decoder subsets and the rows within a fixed delay address subset can all be designed to have the same delay regardless of row—padded, flat delay, if necessary. These delay adjustments are generally small when compared to the delay associated with the entire set of fixed delay address subsets.

[0134] For requests into a pipeline with multiple entry points and variable delay lengths, collisions can occur internally within each memory array or on the data output bus, where outputs from multiple memory arrays converge. Such collisions should be avoided to prevent the return of corrupted data. Adding delay to shorter pipeline entry points to ensure identical latency in the pipeline solves the collision problem, but at the expense of performance; applying this technique ensures that all paths through the memory array have the worst-case latency corresponding to the slowest address.

[0135] As a result of enabling a variable latency pipeline in an attempt to improve overall performance by lowering average array access latency, data can and will return out of order. Control logic used to prevent collisions may be configured to account for out-of-order data return, according to one or more embodiments. For example, additional control logic may be configured to track the addresses of arriving data, according to some embodiments. RAM (data RAM, e.g., D-cache, etc.) may handle out-of-order data return, but it may add design complexity to the area of ​​the CPU that receives the data.

[0136] FIG. 27 is a block diagram illustrating at least a portion of an exemplary variable delay pipelined SFQ memory array 2700 in accordance with one or more embodiments. Referring to FIG. 27 , the variable delay pipelined SFQ memory array 2700 includes a plurality of memory cells 2702 and a read decoder and driver 2704 coupled to the memory cells. In this exemplary embodiment, a memory array having 128 RRLs (RRLs 0 through 127) and M read CLs (read CLs 0 through M−1) is assumed, where M is an integer greater than 1. Each RRL is further assumed to be organized into one of four distinct “regions,” where each distinct region has a specified latency between a memory cell and its associated corresponding output logic (i.e., memory output). While four distinct regions are shown in this example, it should be understood that embodiments of the present invention are not limited to this particular arrangement, i.e., the number of regions may be less than four (e.g., two or three) or more than four (e.g., five or more).

[0137] Using four different regions, each region may be assigned 32 RRLs. In this example, it is assumed that the memory cells associated with RRLs 0 through 31 are closest to the output logic and therefore have the shortest latency (i.e., shortest delay) (e.g., 1 delay unit), RRLs 32 through 63 are further from the output logic than RRLs 0 through 31 and therefore have the second shortest latency (e.g., 2 delay units), RRLs 64 through 95 are further from the output logic than RRLs 32 through 63 and therefore have the third shortest latency (e.g., 3 delay units), and RRLs 96 through 131 are further from the output logic and therefore have the longest latency (e.g., 4 delay units), as shown in FIG. 27. Each region may include its own associated last stage decoder and driver circuitry 2704 configured to control the movement of data through the corresponding RRL. Such control may include additional delays and reordering of out-of-order returned data, as described in more detail below. Each column of memory cells and their corresponding last stage decoder and driver circuitry 2704 may be considered a fixed delay address subset.

[0138] Assume that the amount of delay between one fixed-delay address subset and the next can be consistent across all subset values ​​(and, for an exemplary embodiment, is consistent). For example, if there are two address bits and the amount of delay between successive fixed-delay address subsets is one delay unit (e.g., delay may be generally defined herein as N RQL periods, where N is an integer greater than or equal to one), the code points and their associated respective delays may be "00" being the fastest, "01" being one delay slower than the fastest, "10" being two delays slower than the fastest, and "11" being three delays slower than the fastest. In the discussion that follows, it will be shown that the amount of delay between successive fixed-delay address subsets is consistent across subset values, resolving what initially appears to be a contradiction in the previous figure. This discussion includes Figure 27, Table A, Table B, and references to Figures 3A through 4 above, and the labeling conventions (which may be arbitrarily assigned) used in connection with this discussion are also provided. Depending on how many memory cells are included in each column, the array rows may be divided into more or fewer fixed delay address subsets than shown, as previously described. The latency through any path within a fixed delay address subset may be designed to be identical. Only one row is shown for each subset in the exemplary diagram shown in FIG. 27.

[0139] Referring to Figure 27, the bypass signal <0> from <m-1>Note that M, an integer greater than 1, is included to indicate that data on one side of the RAM can be passed to its output on the other side via the SFQ (single flux quantum) column circuitry associated with each memory cell.

[0140] Figures 3A through 3C are intended to show the raw NDRO delay of the array, without the delay padding introduced in all or many of the previous figures to ensure functional operation (depending on where delay is introduced in the path). Unlike the configurations shown in the previous figures, the exemplary circuit shown in Figure 27 "buckets" (i.e., assigns) rows into four fixed-delay address subsets with delays that incrementally vary from 1 to 4 delay units (e.g., 4 RQL periods for the 128-column exemplary array) by adding phase or period delays to almost all final-stage decoder and driver circuits (and / or intermediate decoders) in each subset except those farthest from the memory output. Because of these aforementioned differences, confusion may arise in understanding Figure 27 and Figures 3A, 3B, and 3C collectively; however, this confusion can be resolved when it is understood that Figure 27 has padded delay paths and Figures 3A, 3B, and 3C represent the raw delays of the array.

[0141] By way of example only and without limitation or loss of generality, Table A below contains listed exemplary raw sequence delays obtained from FIGS. 3A, 3B, and 3C. [Table 1]

[0142] Delays can be introduced to convert the raw array of Table A into any fixed-delay address subset of the RAM in Figure 27. In Figure 27, the nearby read row lines are arranged such that each of their delays is one delay (in our example, one RQL period), regardless of their addresses within the rows of this subset. <0> , and the read line <31> up to the last row are packed with decreasing phase delay as their row number increases in the read path to the last row.

[0143] Other rows shown in Table A, read row line <31> , read line <63> , and the read line <127> , are the raw delay values ​​(or close to the raw delay values) corresponding to Figure 27. Given that they are the last rows in the fixed delay address subset, they set / define the overall delay of the entire subset.

[0144] A discussion of Table B follows. Generally, delays can vary among the fixed-delay address subsets. However, in FIG. 27, they are defined to be the same one-cycle difference for simplicity (again, to avoid confusion, their sequence timings represent exemplary raw delays, so no correspondence with FIGS. 3A, 3B, and 3C depicted in Table A should be considered). It should be understood that, in this discussion, the term “far” (or “farthest”) is intended to refer to the maximum signal path distance from a memory cell to a corresponding circuit element (e.g., a row or column output) relative to the signal path distance between the circuit element and other memory cells in the system. Thus, merely by way of illustration, the final stage decoders and drivers of the farthest set may be assigned to the far fixed-delay address subset with high-order address bits “11”; these are the memory cells furthest from their corresponding outputs and have a four-cycle delay. The set of final stage decoders and drivers spanning the mid-to-far range may be assigned to the mid-far fixed delay address subset with high-order address bits "10", which has a delay of 3 cycles. The set of final stage decoders and drivers spanning the proximal to mid range may be assigned to the mid-near fixed delay address subset with high-order address bits "01", which has a delay of 2 cycles. The set of near stage decoders and drivers may be assigned to the near fixed delay address subset with high-order address bits "00", which has a delay of 1 cycle.

[0145] By way of illustration and without limitation or loss of generality, Table B below includes a listing of delays through the exemplary memory array 2700 of FIG. [Table 2]

[0146] Referring to FIG. 27, the following naming conventions may be used, although it should be understood that embodiments of the present invention are not limited to any particular naming conventions. S(row addr<11…>) = slow = "far" fixed delay address subset delay MS(row addr<10…>) = Medium Slow = Delay for the "medium far" fixed delay address subset MF(row addr<01…>) = Medium Fast = "near-medium" fixed latency address subset latency F(row addr<00…>) = Fast = "close" fixed delay address subset delay

[0147] The above discussion establishes the fact that the amount of delay between successive fixed delay address subsets can be made consistent across all subset values.

[0148] The number of address bits used to point to a fixed-delay address subset may depend on the number of such subsets. For example, if four fixed-delay address subsets are used, then two address bits will be required to point to one of the fixed-delay address subsets. To generalize, N address bits may be used to point to two N A fixed-delay address is required to uniquely point to one of the subsets, where N is an integer.

[0149] Before getting into out-of-order access and collisions, it is best to show how the variable delay pipelined SFQ memory array 2700 of FIG. 27 can be used to reduce latency in a cache.

[0150] 28 is a block diagram illustrating at least a portion of an exemplary four-way set associative cache 2800 having a fully associative TLB 602 / 604 with metamorphosis capabilities in accordance with one or more alternative embodiments of the inventive concepts. Referring to FIG. 28, the four-way set associative cache 2800 may include lookup circuitry 2802 operatively coupled to one or more metamorphosis memories 2804. The lookup circuitry 2802 may comprise a fully associative TLB, including at least one TLB_Match 602 (a TLB content-addressable memory holding virtual (i.e., logical) addresses) and at least one TLB Array 604 (a TLB holding physical addresses), at least one serial compare equality determiner 1100 (which may evaluate over multiple RQL cycles), and at least one Directory_RAM_4 2808 (which includes physical address bits and cache management bits, such as MESI to support four sets). More specifically, in the cache 2800, lookup operations may be performed first before the MM 2804 is accessed (the MM may function as the Data RAM 408 of FIG. 4). Such a cache organization saves power and reduces wire congestion, but increases latency in a conventional cache. Advantageously, the latency of hits 0, 1, 2, and 3 may be offset by the variable-delay pipelined SFQ memory array 2700 of FIG. 27.

[0151] All components within the lookup circuitry 2802 are connected to the virtual addresses (V0 to V1) provided to the lookup circuitry 2802. k-1 to, where K is an integer greater than 1) and index addresses (I0 to I N-1 6. The physical addresses stored in the TLB array 604 may be accessed via both parallel and sequential data flow ordering (as previously described in a number of exemplary lookup path embodiments) from receipt of a hit result (e.g., hit 0, 1, 2, and 3) by the lookup circuitry 2802 through N (where N is an integer greater than 1) to generation of a hit result (e.g., hit 0, 1, 2, and 3) output by the lookup circuitry 2802. Copy circuitry 2806 coupled to the output of TLB_array 604 may be configured to generate four copies of the physical address stored in TLB array 604, with each copy of the physical address sent to and presented to the serial compare equality determination circuit 1100 one RQL period at a time for comparison with the physical address output by directory_RAM_4 wave 2808.

[0152] It should be understood that each hit result generated by the lookup circuitry 2802 may differ from one another (identifying a particular set in a directory as a "hit" if the directory stores the particular set). Hits may be delayed by one RQL / SFQ period for each sequential hit output. Thus, Hit 0 may represent the earliest available hit result output, Hit 1 would be available one RQL / SFQ period after Hit 0, Hit 2 would be available two RQL / SFQ periods after Hit 0, and Hit 3 would be available three RQL / SFQ periods after Hit 0. It should also be understood that in this example, there are four hit results generated by the lookup circuitry 2802, and the number of hit results corresponds to the number of different "sets" in the set-associative cache 2800. All sets are organized in the MM 208 (which, for simplicity, may be the data RAM 408 of the cache 400 of FIG. 4). The variable delay pipelined SFQ memory array 2700 of FIG. 27 is divided into four sections of RAM (abbreviated as RAMP), where the latency of each section is fixed and labeled with S, MS, MF, and F suffixes to indicate the latency.

[0153] Utilizing the variable delay pipelined SFQ memory array 2700 of FIG. 27, set 0 data is stored in RAMP_slow 2700_S, which has the longest latency due to its rows being farthest from the output, set 1 data is stored in RAMP_medium_slow 2700_MS, which has a lower latency compared to set 0 data due to its rows being closer to the output, set 2 data is stored in RAMP_medium_fast 2700_MF, which has a lower latency compared to set 1 data due to its rows being closer to the output, and set 3 data is stored in RAMP_fast 2700_F, which has the least latency to the output, although embodiments of the present invention are not limited thereto. For example, if the memory array is divided into six separate regions, the copy circuitry 2806 coupled to the output of TLB_ARRAY 604 may be configured to generate six copies of the physical address stored in TLB_ARRAY 604, with each copy of the physical address being sent to the serial compare equality determination circuit 1100 simultaneously, one RQL period at a time, to generate six hit results (e.g., hits 0, 1, 2, 3, 4, 5).

[0154] 28, the hit results, hit 0, 1, 2, 3, generated as output by lookup circuitry 2802 may be provided to metamorphosis memory 2804. Metamorphosis memory 2804 may include at least one data RAM, which may include, for example, at least a portion of RAMs 2700_S, 2700_MS, 2700_MF, and 2700_N (collectively, RAMs 2700). Each RAM may be associated with a corresponding one of multiple distinct "sets" into which respective RRLs may be organized, each designed to have the same latency. In the example described above with respect to Figure 27, there are four different regions into which the multiple RRLs are organized: slow (RAMP_slow 2700_S), associated with the memory cells (and their corresponding RRLs) furthest from the data output; medium-slow (RAMP_medium_slow 2700_MS), associated with the memory cells (and their corresponding RRLs) next furthest from the data output; medium-fast (RAMP_medium_fast 2700_MF), associated with the memory cells (and their corresponding RRLs) next closest to the data output; and fast (RAMP_fast 2700_F), associated with the memory cells (and their corresponding RRLs) closest to the data output.

[0155] Each RAMP may have a corresponding multiplexer (Mux) 2810 connected to it. Each multiplexer 2810 has at least one full address input, which may contain a corresponding one of the timed hit results, and an index address (I0 through I1). N-1 Hit 0 through Hit 3, which can be logically ANDed with the block offset address (for example, B0 through B1). P-1 up to, where P is an integer greater than 1). Other inputs (not explicitly shown) to multiplexer 2810 may include the MM "operand" (and its associated "operator" location) when it is being used to perform a computation (rather than a store). Multiplexer 2810 may be configured to select a given one of RAMs 2700 for outputting its data to the output of cache 2800 (enabling metamorphic memory—memory capable of performing computations) based on the location of the memory cell and the distance of the output from the memory cell selected by the requested address.

[0156] The exemplary cache 2800 shown in Figure 28 can functionally operate at one-quarter the peak bandwidth of the underlying RQL / SFQ pipeline. Note that by driving the slow (i.e., furthest) portion of the RAM (e.g., 2700_F) with the fast hit result (e.g., hit 0), and similarly driving the fast (i.e., nearest) portion of the RAM (e.g., 2700_N) with the slowest hi result (e.g., hit 3), the latency of data output from cache 2800 can be advantageously configured to be invariant (or at least substantially invariant) with respect to the input address, regardless of where the addressed memory cell physically resides within cache 2800 (e.g., sets 0, 1, 2, 3). This particular invariant cache latency is the lowest available.

[0157] Although not explicitly indicated by the labels shown in FIG. 28, there may be timing sequence operations shown herein. Hits should be picked up with their TDM pulse train. Note that only one hit per cache read operation can be registered for a properly functioning cache 2800. Shown occurring in metamorphosis memory 2804 is that each address feeding multiplexer 2810 may include a timed hit result (e.g., hit 0, 1, 2, or 3), an index address (e.g., I0 through IN-1) that can be logically ANDed with the hit result, and a block offset address (e.g., B0 through BP-1), as previously described. Each hit has a block offset address and index address timed to match the timing of each hit result, so that only one address is propagated to any one portion of RAM 2700 per cache request.

[0158] Next, an introduction will be provided to some concepts that can be fully utilized by the RAM of Figure 27, such as data collisions and out-of-order data return, which will then be further explained in conjunction with their corresponding figures.

[0159] The amount of delay between return data from successive fixed-delay address subset values ​​in a particular request stream can be variable, and how code point decoding maps to speed can be variable. Consider a chain of latches, where the output of each latch feeds the input of the next subsequent latch in the chain (with one important exception, which is an action (i.e., insertion) period). For example, if there are two address bits and the amount of delay between successive subset values ​​is one period. The signal path and address bit assignment through the chain of latches can appear as follows: upstream period staging → action (i.e., insertion) period (address is available to check / set the chain) → "11" slow → D → "10" 1 period fast → D → "01" 2 periods fast → D → "00" 3 periods fast → downstream period staging → valid data, where "D" is the potential delay. Herein, the term "upstream period staging" is intended to refer to a period in which a cache request exists but the corresponding subset of address bits is not yet known. As used herein, the term "downstream cycle staging" is intended to refer to a cycle later in the data stream.

[0160] The three "Ds" in the chain of latches represent the addition of delay periods, e.g., two RQL periods, to create a delay between successive fixed-delay address subsets. (If the delay between successive subsets is more than two, then D represents multiple staging latches. If the delay between successive subsets is one, as in the chain example above, then there is no D latch.) The four "11" through "00" latches represent the four addressing rates assigned to the fixed-delay address subsets in this example, but it should be understood that embodiments of the present invention are not limited to this number of latches or addressing rates. "Downstream period staging" represents the period an address propagates to and through a RAM (data RAM, e.g., D-cache) until the output data bus is valid.

[0161] There will likely be similar chains that contain a multi-bit request tag field that identifies the requestor in some way. Such bits may include a subset of cache address bits associated with each fixed-delay address subset that are used to monitor differences in cache data output timing (i.e., skew). One example of a requestor might be an instruction unit sending an operand fetch request to a cache.

[0162] Almost all of the latches in the chain propagate their value to the next successive latch in the chain, with one exception: the action period. During the action period, the following actions / events can occur: 1) Address bits are decoded to set one of the corresponding latches slower, say by 1 RQL cycle, faster, say by 2 RQL cycles, or faster, say by 3 RQL cycles. '00' is defined in this example as fastest, so it sets the right-most bit, which is the shortest bit in the chain. Similarly, '11' sets the longest bit. 2) Collision is detected: If a bit that was set in the action cycle (see above) is also propagated in, then a collision is detected (see below). 3) An out-of-order ("OOO") request is detected: If a bit that is set in an action cycle is to the right of a bit that is being propagated in, then an out-of-order condition can be detected (see below).

[0163] A description of an exemplary operation of a pipelined SFQ memory array in accordance with one or more embodiments of the inventive concept follows, in which it may be assumed that: (i) there is a RAM array; (ii) there is a requester that sends requests to the RAM; (iii) there is nearby (proximate to the RAM) “RAM logic” that receives the requests, controls RAM access, and returns RAM output data to the requester along with a data valid indication; (iv) the RAM logic may send back a rejected (i.e., “killed”) indication to the requester rather than a data valid indication; (v) there is “requester logic” that generates RAM requests and processes data returned from the RAM using the data valid indication, and also uses the rejected indication to take corresponding action; and (vi) the requester logic may send successive pipelined requests.

[0164] As mentioned above, the period at which RAM output data is available may depend on the value of a subset of RAM address bits (known as the "fixed-delay address subset bits"), where the value of that subset corresponds to how far, in space and / or time, the decoded address must travel through the RAM array from the memory cell to the corresponding output logic. This can add complexity to the design of the requesting logic.

[0165] This may mean that for pipelined requests, collisions on the RAM data output bus may occur that should be avoided to prevent the return of corrupted data. Avoiding such collisions may lead to newer (i.e., subsequent) requests being rejected, so the pipeline may need to be stalled and / or restarted. This also means that the returned data may be out of order. While the RAM logic may be able to handle sending out-of-order data back, this may add complexity to the design of the requesting logic (e.g., reordering logic may be required to correct the order of the returned data). We assume that the RAM logic is configured to inform the requesting logic about out-of-order data return to assist the requesting logic.

[0166] As an example only, assume that the amount of delay between one subset value (a fixed-delay address subset) and the next slowest subset value is consistent across all subset values. For example, if there are two address bits and the amount of delay between successive subset values ​​is one period, then the address code points and representative delays can be assigned as follows: "00" is the fastest, "01" is one period later, "10" is two periods later, and "11" is three periods later. (See Table B above.)

[0167] In general, it should be understood that the number of address bits used can be variable, the amount of delay between successive waves of data (e.g., in a wave pipelining context) associated with fixed-latency address subset bits can be variable, and how decoding of code points maps to different latencies can be variable. Embodiments of the inventive concepts can be configured to accommodate such variations in memory arrays. However, for logical and architectural simplicity, the exemplary embodiment supports four subset addresses corresponding to a fixed latency and two bits, although it should be understood that the inventive concepts are not so limited.

[0168] FIG. 29 is a block diagram conceptually illustrating at least a portion of an exemplary variable-delay pipelined memory array 2900, in accordance with one or more embodiments. As shown in FIG. 29, the memory array 2900 is organized into four subsets of latencies: slow, medium-slow, medium-fast, and fast. Each block 2911, 2913, 2915, and 2917 in the serial chain of blocks represents an RQL periodic chain, including a "propagating" path. For superconducting logic families, such as RQL, propagation is preferably enabled by two-input AND or OR gates connected in series with JTL to form a serial and timed logic chain. Propagation refers to a bit in a serial chain moving from one chain element to the next. It is intended to contrast with a bit in a chain being set from a path outside the chain. As shown, each block 2911, 2913, 2915, 2917 is connected so that the output of one block feeds the input of the next subsequent block in the RQL cycle chain. Block 2911, which is furthest from the output, may be assigned a designation of slow (s), the next block 2913 may be assigned a designation of medium-slow (ms), the next block 2915 may be assigned a designation of medium-fast (mf), and block 2917, which is closest to the array output, may be assigned a designation of fast (f).

[0169] Each block 2911, 2913, 2915, 2917 may be associated with a corresponding action period having an RQL period set / trigger. For example, block 2911 may be associated with action period 2901 configured to perform slow (S) actions, block 2913 may be associated with action period 2903 configured to perform medium-slow (MS) actions, block 2915 may be associated with action period 2905 configured to perform medium-fast (MF) actions, and block 2917 may be associated with action period 2907 configured to perform fast (F) actions.

[0170] By way of example only and without limitation, reference is made to Figure 29, which depicts a chain of RQL cycles, where the output of each RQL cycle feeds the input of the next RQL cycle. The RQL cycles are interrupted by "action cycles" which are described in the following order: Upstream RQL cycle staging → Action cycle → Downstream RQL cycle staging → Valid data

[0171] As may be used herein, the term "upstream RQL cycle staging" is intended to refer to a cycle during which a previous RAM request can exist and reside as a wave of data (in the context of a wave pipelining scheme). The subset address bits of the next (i.e., new) RAM request are not yet known. As may be used herein, the term "downstream RQL cycle staging" is intended to refer to a cycle during which addresses propagate to and through the RAM until the output data bus is valid. As may be used herein, the term "action cycle" may be defined as the first cycle during which subset address bits are available to check / set the chain. In one or more embodiments, the four subset address decode values ​​and their associated corresponding action cycles may be assigned as follows: "11" S = slow, "10" MS = medium slow, "01" MF = medium fast, "00" F = fast The S / MS / MF / F abbreviations are taken from Table B and the text immediately following the table (see also one alternative embodiment shown in Figure 32).

[0172] On the action cycle, there is a new request, sourced from the last "Upstream RQL Cycle Staging" mentioned above, with a corresponding subset address value that maps to one of S / MS / MF / F, which sets the corresponding RQL Cycle Chain bit labeled s / ms / mf / f.

[0173] Continuing with reference to FIG. 29, one way to represent each period and their sets may use the following convention. Specifically, entities with uppercase letters (2901, 2903, 2905, 2907) may represent action periods in which a new request potentially sets the corresponding RQL period chain bit, as indicated by the vertical arrows shown in FIG. 29. Entities with lowercase letters (2911, 2913, 2915, 2917) may represent RQL period chain bits propagating downstream, as indicated by the horizontal arrows shown in FIG. 29. Each vertical and horizontal arrow represents an RQL period. A discussion of an exemplary operation of variable delay pipelined memory array 2900 follows, with the understanding that embodiments of the present invention are not limited to the described operation.

[0174] The 'f' bit gives the start of the "downstream RQL cycle staging" mentioned earlier. There are likely to be similar chains containing multi-bit request tag fields that identify the requestor in some way (e.g., identification bits). Such bits may also contain a subset of RAM address bits that are used to skew RAM data output timing.

[0175] During an action cycle, certain predefined actions may occur, including, for example:

[0176] (1) One of the subset address decodes S, MS, MF, F will set ("turn on" or "enable") the corresponding one of the RQL periods s, ms, mf, f.

[0177] (2) A collision may be detected. If a bit that is set in an action cycle (e.g., a vertical arrow in FIG. 29) is also propagating in (e.g., a horizontal arrow in FIG. 29), then a collision will be detected. For example, in a given RQL cycle, S (2901) sets s (2911), and in the next RQL cycle, both MS (2903) and s (2911) collide with ms (2913). In a collision formula, this may be represented as "s and MS" (collision cycle). In a multi-cycle example, this may be labeled as "S / MS," which would mean S on a given RQL cycle followed by MS on the next RQL cycle.

[0178] (3) Out-of-order requests can be detected. If a bit being set on an action cycle (e.g., a vertical arrow in FIG. 29) is to the right of a bit being propagated in (e.g., a horizontal arrow in FIG. 29), then an out-of-order condition will be detected. For example, in a given RQL cycle, S (2901) sets s (2911); in the next RQL cycle, s (2911) propagates to ms (2913), and MF (2905) sets mf (2915). What has happened here is that the later request jumped ahead of the earlier request because it may have had a subset address value that was two RQL cycles earlier than the earlier request. In an out-of-order equation, this can be represented as "s and MF." In a multi-cycle example, this can be labeled as "S / MF," which means S on a given RQL cycle followed by MF on the next RQL cycle.

[0179] The collision period and out-of-order (OOO) definition functions can be expressed as follows, with reference to the designations used in FIG. 29: Collision period = (s and MS) or (ms and MF) or (mf and F) [1] OOO = (s and MF) or (s and F) or (ms and F) [2]

[0180] A series of examples are provided later in this document that can be used to verify the accuracy of the above expressions [1], [2] of the definitions of collision period and out-of-order, respectively.

[0181] 30 is a block diagram illustrating at least a portion of an exemplary variable delay pipelined memory array 3000 including an added delay element, according to one or more embodiments. The variable delay pipelined memory array 3000 may be implemented in a manner consistent with the exemplary variable delay pipelined memory array 2900 shown in FIG. 29, with additional periods of delay inserted between successive subset values. More specifically, a first delay block (having a delay value d1) 3012 may be inserted between successive subset values ​​3011 and 3013, a second delay block (having a delay value d2) 3014 may be inserted between successive subset values ​​3013 and 3015, and a third delay block (having a delay value d3) 3016 may be inserted between successive subset values ​​3015 and 3017. In one or more embodiments, each of the delay values ​​d1, d2, d3 may be the same (e.g., one RQL period). In some embodiments, two or more of the delay values ​​may be different from one another. However, for the Boolean expressions described herein, the delays (3012, 314, through 3016) are the same.

[0182] As an example of a collision, assume that in a given RQL period, S (3001) sets s (3011), in the second RQL period, s (3011) propagates to d1 (3012), and in the third RQL period, MS (3003) and d1 (3012) both collide with ms (3013). In subsequent collision expressions, this case may be represented as "d1 and MS" (collision period). (Multiple period instances are not included for the "additional period of delay" case.) Similar to that expression, the collision period may be determined as follows: Collision period = (d1 and MS) or (d2 and MF) or (d3 and F)

[0183] As an example of an out-of-order condition, suppose that in a given RQL period, S (3001) sets s (3011); in a second RQL period, s (3011) propagates to d1 (3012); in a third RQL period, d1 (3012) propagates to ms (3013), and MF (3005) sets mf (3015). What has happened in this example is that the later request jumped ahead of the earlier request because it had a subset address value that was four RQL periods earlier than the earlier request. In subsequent out-of-order condition expressions, this can be expressed as "d1 and MF." (Again, multiple-period examples are not included for the "additional period of delay" case.) Somewhat similar to the previous expression [2], the definition of out-of-order can be determined as follows: OOO = (s and MS) or ((s or d1 or ms) and MF) or ((s or d1 or ms or d2 or mf) and F). Other similar examples can be developed for cases where additional delay periods are included.

[0184] The "collision cycle" and "out-of-order" definitions can be generalized using words rather than variables to encompass a variable number of subset address bits, a variable number of delay cycles, and a variable number of subset address decodings. As used in the definitions below, the term "RQL cycle chain" refers to all bits "s" through "f". Collision Period = RQL Period Both sets of chain bits occur simultaneously. Here, the term "both sets" can be defined as the RQL cycle chain propagation and action cycle set. The "propagation" can be either from the previous subset address RQL cycle or from the rightmost previous delayed RQL cycle. An example of propagation from a previous subset address RQL cycle, in FIG. 29, would be S2901 setting s2911 followed by s2911 propagating into MS2913, where S2901 is the previous subset address RQL cycle for MS2903.

[0185] If a delay such as d13012 is multiple RQL periods, then the delay itself will be a chain of latches that propagates values ​​from left to right, just like the horizontal arrow in Figure 30 going to the right. The term "rightmost" refers to the final delay latch in that mini-chain, the one that feeds ms3013.

[0186] The definition of out of order can be expressed in words as follows: OOO = The RQL cycle chain already has at least one upstream bit. Here, the bit is at least two periods upstream (i.e., to the left in Figure 30) of the RQL period stream bit that is set in the action period. The upstream RQL period can be a mixture of the previous subset address RQL period and the delay RQL period.

[0187] If a collision is detected, the RAM read enable for the newer request must be blocked (or otherwise delayed from being serviced) to prevent corruption of the array output data. (For this technique, the array output corruption function becomes the "OR" of the two conflicting data sources.)

[0188] In one or more embodiments, if a collision is detected, the newer request will include a request tag field in its address and will not modify the value of any RQL cycle chain bits. The collision may be reported to the requesting logic, which then disappears, at least from the perspective of the RAM logic. It is then up to the requesting logic to resolve the collision, for example, by recycling (i.e., reissuing) the request. The previous request with which the newer request collided will continue to be processed as if no collision occurred.

[0189] In the action cycle (or one cycle later) and / or in the data valid cycle, the request tag field can be used by the RAM logic to inform the requesting logic as to which requests had collisions or were out of order, or how many addresses skew the cycle the requests had. Other information can alternatively or additionally be provided to the requesting logic.

[0190] The action period of the RAM logic may occur as soon as the received request signal and the corresponding subset of address bits are staged (the term "latched" would be used for conventional CMOS designs). In some embodiments, upstream requesting logic making a RAM request may include its own chain of RQL periods with its own action period faster than the action period of the RAM logic.

[0191] In fact, this arrangement may allow the requesting logic to avoid collisions in the first place, or at least to take action to address collisions sooner when detected. The arrangement may also allow the requesting logic to deal with out-of-order conditions more efficiently. For example, the requesting logic may be configured to choose subset address bits whose values ​​are known earlier with relatively better timing, or to predict subset address values ​​earlier with relatively better accuracy. Presumably, this will result in selecting address bits that have better slow-mode timing (i.e., later timing within a period) if the address bits were coming from, for example, an adder.

[0192] For embodiments in which the requesting logic includes its own RQL cycle chain, the subset of address bits selected to skew the RAM output data timing may be bits that are not modified downstream from the requesting logic. Specifically, these address bits used to skew the RAM output data timing should not be translated physical address bits that the requesting logic is unaware of but the RAM logic is aware of. For example, if the RAM logic were aware of TLB physical address output bits, it would address a RAM being used as a d-cache to avoid synonyms. One example of this would be if some TLB output physical address bits were used as array index bits into directory and cache arrays.

[0193] Some examples used to derive the aforementioned formulas [1], [2] for the definition of collision period and out-of-order are provided below, respectively (the formulas are also copied below for comparison). In the examples shown below, the label designations shown in Figure 29 may be referenced. These examples assume that two address bits are used to select one of the fixed-delay address subsets, but for simplicity, the delay period (d1, d2, or d3 period) is not assumed. In the examples below, the naming convention "x / x" will be used to refer to two action periods in a row setting the "x" RQL period.

[0194] The following examples are not exhaustive, as they include only back-to-back action cycles, as opposed to gap cycles between two action cycles. Specifically, the examples show all terms shown in the unordered and collision tables, except for lowercase terms in the formulas that are sourced from both the action cycle set and the propagation set, where only the action cycle set is described.

[0195] For the column headings, s = slow, and f = fast (i.e., 3 RQL periods faster, as mentioned above). The two middle, unlabeled RQL periods are 1 and 2 RQL periods faster than s, respectively; ms = medium slow, and mf = medium fast. Because looking at the fifth RQL period makes it clearer what is occurring in some of the examples, a fifth column has been added in the following examples to the right of the "f" column. Each sequential row is one period. The propagating latch period bits move from left to right. The nomenclature "set x" appearing to the right of a row means to set "x" RQL period.

[0196] No collision and OOO conditions

number

[0197] No collision and OOO conditions

[0198] For comparison purposes, the previous expression for the collision period [1] is repeated below:

number

[0199] OOO and no collision

[0200] For comparison purposes, the above formula [2] is repeated below for the unordered conditions:

number

[0201] Previously, it was discussed how TDM and / or wave pipelining can be used to make lookup path busing more wireable, where the drawback is that the lookup bandwidth is reduced by half.

[0202] Previously, it was discussed how subset address skew can cause data RAM 408 output bus collisions. A preferred embodiment was to kill the newer of the two requests to avoid the collision and have the requesting unit recycle it. Then, an alternative embodiment proposes to keep the newer of the two requests as an internal d-cache unit requester, with a limited number of such internal requesters, and their associated state machines.

[0203] If the lookup bandwidth is reduced by half, and we start with some of the previous examples for handling subset address skew, we consider the option of avoiding collisions by delaying newer requests by one RQL period. Such a one-period delay would be called a backup.

[0204] For the discussed example, assume, by way of example only, that lookup request results and corresponding action requests are available only on even cycles or only on odd cycles. (Embodiments may function with a minimum of one cycle between lookup request results, without the additional constraint of even (or odd) cycles.) Assume there is only a one-cycle delay between successive subset address values ​​(as in FIG. 29). Also assume that data RAM 408 is running at full bandwidth, even if the associated lookup path is only running at half-width.

[0205] One difference between Figure 29 and Figure 31 is the addition of two diagonal dashed arrows. Since the action cycles in this example embodiment are always two cycles apart, this limits the number of collision cases to two. The cases are as follows: 1) (mf and F), where the case is caused by the periodic sequence MS / g / F, 2) (ms and MF), where the case is caused by the periodic sequence S / g / MF, A second collision (mf and F) potentially follows by adding the periodic sequence / g / F. Here, g represents the gap period (the period between consecutive even or odd periods).

[0206] OOO cases are not discussed, as their detection and handling is not substantially different from the first example of FIG.

[0207] Each of the two foregoing cases will now be discussed in substantial detail with reference to the blocks in FIG. 31 and the corresponding two examples below, in which the format of the two examples is somewhat similar to many of the examples previously shown. First example ((mf and F) = MS / g / F): In period 1, MS(3103) sets ms(3113). In period 2, ms(3113) propagates to mf(3115). At period 3, mf(3115) propagates to f(3117) (The horizontal arrow in Figure 31 and the "1" in the fourth row in the first example below) and F(3107) is about to collide with f(3117) (Vertical arrow in Figure 31).

[0208] Collisions are prevented by blocking RAM read enable for the newer request. So far, the solution matches the first example in FIG. 29. The new aspect is that a backup occurs in response to the newer request: F(3107) backs up in mf(3115) so that it will leave the RQL cycle chain one cycle later than originally expected. The backup is shown in FIG. 31 as a diagonal arrow from F(3107) to mf(3115). The backup is shown in the first example below as a "b" in the fourth row, immediately following the "1" in that row where it collided. The RAM read address of the newer request is staged for one cycle. In cycle 4, mf(3115) propagates to f(3117) ("b" in the fifth row in the first example below). The RAM read enable is turned on for the newer request, and the corresponding staged RAM read address is sent to RAM. In period 5, F(3107) sets f(3117) to verify that no more collisions occur (line 6 in the first example below). Another such check is performed two periods later. Second example ((mf and F) = (ms and MF) followed by S / g / MF / g / F): In period 1, S(3101) is set to s(3111). In period 2, s(3111) propagates to ms(3113). In period 3, ms(3113) propagates to mf(3115) (The horizontal arrow in Figure 31 and the "1" in the fourth row in the second example below) and MF(3105) is about to collide with mf(3115) (vertical arrow in Figure 31).

[0209] Collisions are prevented by blocking RAM read validation for new requests by an appropriate time. So far, the solution matches the first example in Figure 29. The new aspect is that the first backup occurs in response to a newer request: MF (3105) backs up in ms (3113) so that it will leave the RQL cycle chain one cycle later than originally expected. The first backup is shown in Figure 31 as a diagonal arrow from MF (3105) to ms (3113).

[0210] The first backup is shown in the second example below as "b" in the fourth row. The RAM read address of the newer request is staged for one cycle. In cycle 4, mf(3115) propagates to f(3117) and ms(3113) propagates to mf(3115) (where ms was the first backup that occurred in the last cycle, shown as "b" in row 5 of the second example below). At both appropriate times, RAM read enable will be turned on for the first backup request, and the corresponding staged RAM read address is sent to RAM. In cycle 5, mf(3115) propagates to f(3117), and the first backup, shown as the horizontal arrow in Figure 31 and the rightmost "b" in row 6 of the second example below, and F(3107) is about to collide with the first backup to f(3117) (vertical arrow in Figure 31). Collisions are prevented by blocking RAM read validation for new requests for an appropriate amount of time.

[0211] The second backup occurs in response to a newer request: F(3107) backs up in mf(3115) so that it will leave the RQL cycle chain one cycle later than originally expected. The second backup is shown in FIG. 31 as a diagonal arrow from F(3107) to mf(3115). The second backup is shown in the second example below as the leftmost "b" in row 6, where there are successive backups represented by 2b's in that row. The RAM read address of the newer request is staged one cycle. In cycle 6, mf(3115) propagates to f(3117) (the second backup that occurred in the last cycle, shown as the leftmost "b" in row 7 of the second example below). The RAM read enable will be turned on for the second backup request, and the corresponding staged RAM read address will be sent to RAM. In period 7, F(3107) sets f(3117) to verify that no more collisions occur (line 8 in the second example below). Another such check is performed two periods later.

[0212] One reason Figure 31 does not have a diagonal arrow from MS(3103) to s(3111) is that a collision at ms(3113) can only occur if S(3101) is immediately followed by MS(3103). However, this idea that action periods cannot occur in quick succession (there must be a gap period between them) was discussed above.

[0213] The following two examples follow a similar format to the previous example, with at least the following differences: 1) All 4-cycle chain points are labeled (instead of 2), 2) A total of 7 chain points are shown (instead of 5), 3) The case labeling includes g (gap) periods. 4) "b" labeling (backup) is used for backup periodicity and its propagation (instead of "1" labeling), and 5) The case labeling includes a space followed by " / g / F / g / F". This suffix expression is not an important part of the example, rather it puts pressure on the chain to verify that no more avoidable or unavoidable collisions occur.

number

[0214] With reference to Figure 32, the two high-order address bits are decoded and then gated with a request enable (read enable). Below are the gated actions and associated periodic target row addresses, which will be referred to as "fixed delay address request subsets" for each fixed delay address subset. These are used to inject tokens into the "mimicking delay pipeline" of Figure 32, which will be described later.

[0215] Figure 32 shows an alternative embodiment of a control circuit for a variable latency RAM having multiple mimicked delay pipelines and their associated address request entities, individually shown as associated pairs of address request entities and mimicked delay pipelines that collectively not only represent the wave movement progressing in the array / memory they mimic, but also identify the addresses of data exiting the array at any particular cycle. Essentially, when the scheduler recognizes an opening in the RAM and available mimicked delay pipelines and associated address request entities, as will be described with respect to Figure 34, it interposes a token at the associated address input (fixed delay address subset) in the mimicked delay pipeline and records its associated address in the address request entity.

[0216] The labeling of address requestors as A:C should not be confused with the separate / independent labeling of cache direction or set associativity as A:D.

[0217] Figure 33 shows the inputs, outputs, and states of the Address Request entity. The inputs include (1) the read request address, (2) the read request enable, and (3) the valid output data for Address Request N. These are primarily provided by the scheduler of Figure 34, with one exception: the "Valid Output Data Address Request N" is provided from Figure 32. The outputs are simply state attributes provided to the Scheduler entity of Figure 34. The state, or state attributes, may include (1) the request address, (2) more specifically, the state, including (2a) occupied (the previous request has been granted, thus allowing the wave to move through the array), (2b) stalled (the request is waiting for a pipeline opening), and (2c) open / free / available to process another request, and (3) the fixed-latency address subset bit (which is actually part of (1)).

[0218] When valid output data for the Address Request N token is received, the state of the Address Request entity is set to indicate that it is open / free / available to process another request (2c). When Read Request Enable is activated, the request is granted unless that / this particular request must be stalled waiting for a pipeline opening (2b). The scheduler of Figure 34 will only issue requests to Address Request entities that are open / free / available, not those that are occupied or stalled.

[0219] Figure 34 shows the scheduler and injection decision circuit. The injection decision circuit essentially samples the upstream token (i.e., data wave activity) to predetermine whether a downstream token, if interposed, would collide with an existing upstream token. Such sampling can be done for each stage operating between fixed-delay address subsets where data collisions may occur.

[0220] Yet another alternative embodiment exists in which the scheduler only allows in-order retrieval of data, and OOO is prevented.

[0221] It will be understood that although terms such as "first," "second," and the like may be used herein to describe various elements, these elements are not limited by such terms. These terms are used merely to distinguish one element from another and should not be construed as conveying any particular order of elements relative to each other. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or," when used in conjunction with a related list of elements, is intended to include any and all combinations of one or more of the associated listed elements. For example, the phrase "A and / or B" is intended to include element A alone, element B alone, or elements A and B.

[0222] The terminology used herein is merely for the purpose of describing particular embodiments of the inventive concept and is not intended to be limiting of the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that as used herein, the terms "comprises," "comprising," "includes," and / or "comprising" are intended to specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not necessarily exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0223] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be construed as having a meaning consistent with their meaning in the context of the present specification and the related art, and should not be construed in an idealized or overly formal sense unless expressly so defined herein.

[0224] In accordance with the embodiments of the disclosure described herein, when an element, such as a device or circuit, is referred to as being "connected" or "coupled" to another element, it should be understood that the element may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is intended that there are no intervening elements present.

[0225] Relative terms, such as "bottom," "top," "upper," "lower," "horizontal," "lateral," "vertical," "right" (or "rightmost"), or "left" (or "leftmost"), may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. However, it will be understood that these terms are intended to encompass different orientations of a device or structure instead of or in addition to the orientation depicted in the figures.

[0226] As may be used herein, like reference numbers and / or labels are intended to refer to like elements throughout the several views. Thus, the same numbers and / or labels may be described with reference to other drawings even if they are not explicitly stated or described in the corresponding drawing. Furthermore, elements not indicated by reference numbers and / or labels may be described with reference to other drawings.

[0227] In the drawings and specification, there have been disclosed representative embodiments of the invention, and although specific terms may be employed, they are intended to be used in a generic and descriptive sense only and not for purposes of limitation; the scope of the invention will be indicated by the appended claims. < / n-1> < / n-1> < / n> < / n> < / n> < / n>

Claims

1. 1. A time division multiplexed (TDM) lookup circuit for use in a superconducting cache, comprising: at least one superconducting memory configured to function as a directory in the lookup circuit; at least one comparator circuit, the comparator circuit including a first input adapted to receive a first physical address corresponding to a requested data location and a second input adapted to receive a second physical address corresponding to a main memory external to the TDM lookup circuit, the comparator circuit configured to perform at least one comparison process in which the first physical address is compared with the second physical address and an output signal is generated indicating whether a match occurs between the first physical address and the second physical address; Equipped with The time division multiplexed (TDM) lookup circuit, wherein the at least one comparator circuit is configured to perform multiple comparison processes per lookup access period.

2. 2. The time division multiplexing (TDM) lookup circuit of claim 1, further comprising: translation circuitry configured to translate logical addresses into physical addresses, the translation circuitry comprising a translation lookaside buffer (TLB) including TLB matches configured to store logical addresses and a TLB array configured to store physical addresses.

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