Two-level reservation station

Abstract

A method, system, and apparatus for a computing device includes a plurality of processing cores and a reservation station including circuitry configured to coordinate selection of instructions for out-of-order execution on the plurality of processing cores, the reservation station including a wait buffer and a plurality of clusters, wherein when the reservation station predicts that a load instruction will result in a cache miss, the reservation station is configured to execute the load instruction using one of the plurality of clusters and store one or more dependent instructions of the load instruction in the wait buffer, and when execution of the load instruction is completed, the reservation station is configured to retrieve the dependent instructions from the wait buffer and execute the dependent instructions using the plurality of clusters.

Description

[Background technology]

[0001] This specification relates to a device that includes one or more reservation stations (RSVs) that can support out-of-order (OoO) instruction execution in a computing device.

[0002] In modern out-of-order (OoO) processors, instruction throughput (e.g., instructions per cycle (IPC)) typically improves with increasing the size of the OoO window. Reservation Stations (RSVs) are typically one of the components that constrain this window size. Larger RSVs can extract instruction- and memory-level parallelism, which helps improve IPC.

[0003] However, increasing the RSV size creates cycle time challenges and constrains frequency. The wakeup-select timing path, related to the RSV size, is one of the tightest timing paths in modern OoO CPUs and typically constrains the overall CPU frequency. Increasing the RSV size places a strain on each component along the wakeup-select path. For example, increasing the RSV size increases wakeup latency because of increased load on the tag broadcast wiring. The increase in selection latency occurs because more instructions participate in the selection process and it takes time to determine the selection priority among them. Because both IPC and frequency contribute to overall performance, simply increasing the RSV size does not necessarily improve overall performance. Summary of the Invention

[0004] Described herein are systems and methods for implementing RSVs with multiple levels to increase "effective capacity" in a cycle-time friendly manner.

[0005] "RSV clustering" is the process by which an RSV is divided into smaller "clusters" or "groupings," each designed to handle a specific type of instruction. When all instructions are supplied to all clusters, this structure is called a "fully integrated" or "monolithic" RSV. On the other hand, a "fully distributed" or "fragmented" RSV is when instructions are supplied only to designated clusters. Both structures have advantages and disadvantages in terms of IPC and cycle time. The two-level RSV organization presented herein outlines a device that does not rely on a "fully distributed" or "fully integrated" design to gain similar performance benefits offered by each structure.

[0006] This two-level RSV design takes advantage of the fact that RSV is often filled with instructions that miss in the last level cache (LLC) and their dependent instructions. LLC is defined as the last cache before the CPU accesses memory. Typically, it can take many cycles (e.g., over 100) to service an instruction that misses the LLC or its dependent instructions. This can cause a chain reaction that prevents RSV from accepting more new instructions. In other words, the RSV "queue" is occupied by instructions that miss the LLC and their dependent instructions, resulting in RSV being unable to store instructions that could be processed more efficiently.

[0007] To overcome this problem, the system actively predicts which instructions will miss the LLC and attempts to direct the dependent instructions of these instructions to a separate, cycle-efficient structure. In some embodiments, this structure may be referred to as a wait buffer (WB). This WB is a separate structure from the regular RSV clustering. In some embodiments, the RSV is divided into two levels: the first consists of the WB and the second contains one or more RSV clusters. In some embodiments, instructions that are predicted to miss the LLC send their dependent instructions to the level 1 WB rather than passing them directly to a level 2 RSV cluster. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram of an exemplary system implementation. [Figure 2] FIG. 2 is a detailed diagram of an exemplary system implementation. [Figure 3] FIG. 2 is a diagram of an exemplary process by which instructions are processed by an exemplary system implementation. [Figure 4] FIG. 10 is a diagram of an exemplary process by which the estimation logic of the LLC predictor is improved. DETAILED DESCRIPTION OF THE INVENTION

[0009] 1 is a schematic diagram of an exemplary system. System 100 includes a fetch module 102, a decode module 104, a wait buffer (WB) 105, a dispatch module 106, one or more RSVs 108, a reorder buffer 110, a commit module 112, and a store buffer 114. The various "modules" described above may be implemented using various logic circuit components to include AND, OR, NOT, NAND, or XOR gates. Other implementations may choose to use other circuit components.

[0010] The fetch module 102 reads incoming instructions for decoding. The decode module 104 analyzes the received functions to determine their consumers. In some implementations, the output of the decode module 104 is used to determine whether the decoded instruction corresponds to an instruction that is likely to miss the LLC. If it is determined that an instruction is likely to miss the LLC, a bank in the WB 105 is allocated to the instruction's dependent instructions. If the instruction is not likely to miss the LLC or meets the requirements for exiting the WB 105, the instruction is sent to the dispatch module 106, which sends the instruction to the RSV 108. The RSV 108 can take various forms between a fully distributed system and a fully integrated system. The RSV 108 can also use various forms of clustering, where groups of instruction types can be assigned to a specific number of RSVs 108. After being retrieved from the RSV 108, the instructions are processed by the reorder buffer 110 and the commit module 112 before reaching the store buffer 114.

[0011] 2 is a detailed diagram of an exemplary system implementation 200. System 200 includes a decode module 202, an LLC predictor 204, a WB free list 206, a rename module 208, a WB 210, a WB bank 212, a "WB bank ID" 214, a WB multiplexer 216, one or more RSV multiplexers 218, one or more RSV clusters 220, and one or more execution lanes 222.

[0012] The LLC predictor 204 is used to determine which instructions are likely to miss the LLC. In some embodiments, this prediction may occur during the RSV decode module 202. Prior to use, the LLC predictor 204 may undergo initial training regarding which instructions are likely to miss the LLC. If the LLC predictor 204 detects that an instruction will miss the LLC, the instruction reserves a bank 212 in the WB 210 if the WB free list 206 identifies a free bank ID 214 as available. At this point, additional identifiers may be assigned to the instruction, such as a physical register number (PRN) tag and a "BankIDValid." In some embodiments, this process may be handled by the renaming module 208.

[0013] In some implementations, the WB 210 may be divided into a specific number of banks 212. The number of banks 212 may be further divided into multiple entries, each occupied by a single instruction, resulting in a first-in, first-out (FIFO) structure. The FIFO structure allows for bank-level wakeup (i.e., all instructions within the same bank 212) and reduces design complexity. Other implementations within the scope of the claims may use other WB 210 structures or processes.

[0014] When exiting the WB 210, the instruction chain is sent out in a specific format, e.g., a FIFO-based allocation order. In some implementations, this process may be handled by the WB multiplexer 216. Instructions leaving the WB 210 may then be provided to the RSV cluster 220. In implementations where multiple instruction types are handled by the same RSV cluster 220, the instructions may be distributed to the appropriate RSV using the RSV multiplexer 218. Instructions that are ready to execute are then assigned an execution lane 222 by the RSV. In some implementations, individual RSV clusters 220 are configured to handle different instruction types. For example, each RSV cluster may be configured to handle different types of instructions or instruction classes. For example, different RSV clusters 220 may be assigned to handle loads, stores, functional operations, basic mathematical operations, and complex mathematical operations, respectively. Other alternative implementations may use any suitable arrangement of RSV clusters for instruction types or classes.

[0015] 3 is a flowchart of an exemplary process for using a wait buffer for predicted load misses. The exemplary process may be performed by any suitable processor configured to operate in accordance with this specification.

[0016] The LLC predictor may undergo initial training regarding which instructions are likely to miss the LLC (310). In some embodiments, this training may be based on known program counter (PC) data. Training is described in more detail below with reference to FIG. 4. As RSV operates, the predictions used by LLC predictor 204 may be refined to more accurately predict which instructions will miss the LLC. In some embodiments, LLC predictor 204 may include a table with multiple entries, each of which has an N-bit saturation counter. This table may be indexed by various means, including the load instruction address, a hash value of the load instruction address, global load hit / miss history (GLHR), load path history, or other parameters readily obtainable from the PC. This table may be indexed by a combination of the above parameters.

[0017] In embodiments where the GLHR is used, the GLHR may include an "N"-bit shift register that is updated at instruction LLC miss prediction time. If the instruction is predicted to miss the LLC, a "1" is assigned to the GLHR. Alternatively, if the instruction is predicted to hit the LLC, a "0" is assigned to the GLHR. In other embodiments that use load path history to update the LLC predictor 204, this operation may include hashing the PC bits from the previous "N" load instructions.

[0018] Additionally, in multi-core systems where LLC hit / miss information is not readily available, a proxy may be used to train LLC predictor 204. In this case, the number of cycles consumed by instructions at the top of the reorder buffer (ROB) may be used to train LLC predictor 204. A cycle count may be assigned, for example, 50, and if the cycle count exceeds that, the instruction is considered a miss and the respective counter may be incremented. Otherwise, the instruction is considered a hit and the respective counter will be decremented.

[0019] After initial training, LLC predictor 204 decodes instructions during operation and makes predictions about which instructions will miss the LLC (320). If LLC predictor 204 predicts that an instruction will miss the LLC, its dependent instructions are moved to a bank 212 in WB 210 (330). Upon entry into WB 210, the dependent instruction may be assigned a “bank ID” 214 corresponding to its destination logical register number (LRN). This information may be arranged in an easy-to-reference format, such as a lookup table. When a dependent instruction corresponding to the same LRN is found, the bank ID 214 may be used to place the dependent instruction in the same bank in WB 210 as the preceding instruction. If a dependent instruction has multiple preceding instructions that are assigned unique banks in the WB, the system may follow a predetermined response, such as assigning the dependent instruction to the bank 212 in WB 210 with the lowest occupancy.

[0020] The bank ID 214 of each instruction may also be shared with the load store unit (LSU). For example, upon detecting that an instruction is ready to leave the WB 210 because a load instruction has completed, a “wake-up” is sent by the LSU to all dependent instructions in the same bank 212 (340). Additionally, the LSU may perform other actions. For example, the LSU may send an advance warning to the LRN or other component that a wake-up is in progress. The LSU may also trigger an early departure of an instruction chain from the WB 210. When exiting the WB 210, the instruction chain leaves in a specific format, for example, in a FIFO-based allocation order (350). In this method, there is no limit to the number of instruction chains that can be woken up per cycle. Other embodiments within the scope of the claims may utilize different wake-up methods or cause the LSU to perform different actions.

[0021] If multiple instruction chains wake up in the same cycle, the system may control how instructions exit the WB 210 (360) according to a particular arbitration process. In some implementations, a round-robin may be implemented to determine the order. In other implementations, an age-based method in which older instruction banks 212 take priority may be preferred. Furthermore, this age prioritization may be extended to other instructions not assigned to the WB 210, such that instruction chains exiting the WB 210 take priority over instructions exiting directly from decode 202.

[0022] 4 is a flowchart of an example process 400 for improving the accuracy of an LLC predictor. The example process may be performed by any suitable processor configured in accordance with this specification. For example, the processor may perform the example process during instruction execution to continuously improve the LLC predictor.

[0023] Following the initial training of the LLC predictor (410) illustrated in FIG. 3, it may be desirable to refine aspects of the LLC predictor's estimation logic to more accurately identify problematic instructions. In some implementations, a counter may be assigned to each load instruction to form an entry table (420). In some cases, this table may be uniquely indexed based on a hash of the load instruction's PC. Other implementations may choose to use a "tagged" LLC predictor that utilizes a content addressable memory (CAM) structure that performs load instruction tag comparisons. During execution, load instructions are monitored to determine if there is a missing LLC (430).

[0024] Upon detecting (430) that the load instruction missed the LLC, the counter assigned to the load instruction is increased by a constant (440). In some embodiments, this number may be an integer (e.g., "1"). If the load instruction did not miss the LLC, the counter assigned to the load instruction is decreased by a constant (450). In some embodiments, this number may be an integer (e.g., "1"). After the counter for the load instruction has been updated, the system continues execution using the updated counter (460).

[0025] The above is one example implementation for updating the LLC predictor logic. Other implementations may choose different variations of the described process, for example, incrementing the counter in a different manner. Other implementations may choose to use other processes entirely, including using other data available to the LLC predictor 204 from the computing system.

[0026] Embodiments of the subject matter and functional operations described herein can be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware, such as the structures disclosed herein and their structural equivalents, or one or more combinations thereof. Embodiments of the subject matter described herein can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory storage medium, for execution by or to control the operation of a data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random-access or serial-access memory device, or one or more combinations thereof. Alternatively, or in addition, the program instructions can be encoded in an artificially generated transmitted signal, such as a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiver apparatus for execution by a data processing apparatus.

[0027] The term "data processing apparatus" refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or multiple computers. An apparatus may be or further include special-purpose logic circuitry, such as an FPGA (field-programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, an apparatus may also optionally include code that creates an execution environment for a computer program, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0028] A computer program, which may be called or described as a program, software, software application, app, module, software module, script, or code, can be written in any form of programming language, including compiled or interpreted, declarative or procedural, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in part of a file that holds other programs or data, for example, one or more scripts stored in a markup language document, in a single file dedicated to the program, or in multiple cooperating files, for example, files that store one or more modules, subprograms, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a data communications network.

[0029] To say that one or more computer systems are configured to perform particular operations or actions means that the systems have installed thereon software, firmware, hardware, or a combination thereof that, when running, causes the systems to perform the operations or actions. To say that one or more computer programs are configured to perform particular operations or actions means that the one or more programs contain instructions that, when executed by a data processing device, cause the device to perform the operations or actions.

[0030] As used herein, "engine," or "software engine," refers to a software-implemented input / output system that provides an output distinct from the input. An engine may be an encoded block of functionality, such as a library, platform, software development kit ("SDK"), or object. Each engine may be implemented on any suitable type of computing device, e.g., a server, a mobile phone, a tablet computer, a notebook computer, a music player, an e-book reader, a laptop or desktop computer, a PDA, a smartphone, or other fixed or portable device, which includes one or more processors and computer-readable media. Furthermore, two or more of the engines may be implemented on the same computing device or different computing devices.

[0031] The processes and logic flows described herein may be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by special purpose logic circuitry, such as an FPGA or an ASIC, or a combination of special purpose logic circuitry and one or more programmed computers.

[0032] A computer suitable for executing a computer program can be based on a general-purpose or special-purpose microprocessor, or both, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from a read-only memory, a random-access memory, or both. The basic elements of a computer are a central processing unit for performing and executing instructions and one or more memory devices for storing instructions and data. The central processing unit and memory may be supplemented by, or incorporated into, special-purpose logic circuitry. Typically, a computer also includes one or more mass storage devices for storing data, such as magnetic, magneto-optical, or optical disks, or is operably coupled to receive data from or transfer data to them, or both. However, such devices are not required for a computer. Furthermore, a computer can be embedded in other devices, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device, such as a universal serial bus (USB) flash drive, to name a few.

[0033] Computer-readable media suitable for storing computer program instructions and data include all types of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices, magnetic disks such as internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0034] To facilitate user interaction, embodiments of the subject matter described herein can be implemented in a computer that has a display device, such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user, and a keyboard and pointing device, such as a mouse, trackball, or pressure-sensitive display or other input surface, through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user. For example, feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback, and input from the user can be received in any form, such as acoustic input, voice input, or tactile input. Furthermore, a computer can interact with a user by sending and receiving documents to a device used by the user, for example, by sending a web page to a web browser on the user's device in response to a request received from the web browser. A computer may also interact with a user by sending text messages or other types of messages to a personal device (e.g., a smartphone running a messaging application) and then receiving a reply message from the user.

[0035] In addition to the above embodiments, the following embodiments are also innovative.

[0036] Embodiment 1 is a computing device, a plurality of processing cores; a reservation station comprising a wait buffer, a plurality of clusters, and circuitry configured to coordinate selection of instructions for out-of-order execution among the plurality of processing cores, the reservation station comprising: predicting that the load instruction will result in a cache miss; When a load instruction is predicted to result in a cache miss, i) executing the load instruction using one of the plurality of clusters, and ii) storing one or more dependent instructions of the load instruction in the wait buffer; Upon completion of execution of the load instruction, i) retrieving one or more of the dependent instructions from the queue buffer, and ii) executing the one or more dependent instructions using the plurality of clusters; A computing device configured to:

[0037] Embodiment 2 is the computing device of embodiment 1, wherein the wait buffer comprises a plurality of banks, and storing the one or more dependent instructions of the load instruction includes storing all dependent instructions of the load instruction in the same bank of the wait buffer.

[0038] Embodiment 3 is the computing device of embodiment 2, wherein each bank entry of the wait buffer comprises a logical register number, a physical register number, a bank ID, and a valid value.

[0039] Example 4 is the computing device of example 3, wherein each bank is organized as a first-in, first-out queue.

[0040] Embodiment 5 is a computing device described in any one of embodiments 1 to 4, wherein the reservation station further comprises a prediction circuit configured to generate a prediction of whether the load instruction will result in a cache miss.

[0041]

[0013] Embodiment 6 is a computing device as recited in embodiment 5, wherein the prediction circuitry comprises a counter incremented by a global load hit / miss history.

[0042] Embodiment 7 is the computing device of embodiment 5, wherein the prediction circuitry comprises a number of cycles consumed by an instruction at the head of a reorder buffer.

[0043] Embodiment 8 is the computing device of embodiment 5, wherein the prediction circuit comprises a hash load.

[0044] Embodiment 9 is the computing device according to any one of embodiments 1 to 8, wherein the cache miss is a miss in a last level cache of the computing device.

[0045] Embodiment 10 is a computing device described in any one of embodiments 1 to 9, wherein two or more clusters of the plurality of clusters are dedicated to executing different combinations of instruction types.

[0046]

[0023] Embodiment 11 is the computing device of embodiment 10, wherein the first cluster is dedicated to executing simple instructions and branch instructions that execute in a single cycle.

[0047]

[0023] Embodiment 12 is the computing device of embodiment 11, wherein the second cluster is dedicated to executing simple instructions and multi-cycle instructions.

[0048] Embodiment 13 is a computing device described in any one of embodiments 1 to 12, wherein the reservation station is configured to perform bank-level arbitration when multiple banks are activated in the same clock cycle.

[0049]

[0023] Embodiment 14 is a method performed by a computing device comprising a plurality of processing cores and a reservation station comprising a wait buffer, a plurality of clusters, and circuitry configured to coordinate selection of instructions for out-of-order execution on the plurality of processing cores, the method comprising: predicting, by the reservation station, that a load instruction will result in a cache miss; When a load instruction is predicted to result in a cache miss, i) executing the load instruction using one of the plurality of clusters, and ii) storing one or more dependent instructions of the load instruction in the wait buffer; Upon completion of execution of the load instruction, i) retrieving one or more of the dependent instructions from the queue buffer, and ii) executing the one or more dependent instructions using the plurality of clusters; Includes.

[0050] Embodiment 15 is the method of embodiment 14, wherein the wait buffer comprises multiple banks, and storing the one or more dependent instructions of the load instruction includes storing all dependent instructions of the load instruction in the same bank of the wait buffer.

[0051]

[0023] Embodiment 16 is the method of embodiment 15, wherein each bank entry of the wait buffer comprises a logical register number, a physical register number, a bank ID, and a valid value.

[0052] Example 17 is the method of example 16, wherein each bank is organized as a first-in, first-out queue.

[0053] An eighteenth embodiment is a method according to any one of the fourteenth to seventeenth embodiments, wherein the reservation station further comprises a prediction circuit configured to generate a prediction of whether the load instruction will result in a cache miss.

[0054]

[0023] Example 19 is the method of example 18, wherein the prediction circuitry comprises a counter incremented by a global load hit / miss history.

[0055] Embodiment 20 is directed to one or more non-transitory computer storage media encoded with computer program instructions that, when executed by one or more computers, cause the one or more computers to: predicting, by a reservation station, that a load instruction will result in a cache miss; When a load instruction is predicted to result in a cache miss, i) executing the load instruction using one of a plurality of clusters, and ii) storing one or more dependent instructions of the load instruction in a wait buffer; Upon completion of execution of the load instruction, i) retrieving one or more of the dependent instructions from the queue buffer, and ii) executing the one or more dependent instructions using the plurality of clusters; and one or more non-transitory computer storage media that cause the computer to perform operations including:

[0056] While the specification contains many specific implementation details, these should not be construed as limiting the scope of any invention or the scope of patentable subject matter, but rather as descriptions of features that may be unique to particular embodiments of a particular invention. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features of the invention that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and originally claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to subcombinations or variations of the subcombination.

[0057] Similarly, while acts are shown in a particular order in the figures, this should not be understood as requiring that such acts be performed in the particular order or sequential order shown, or that all of the acts shown be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated into a single software product or packaged into multiple software products.

[0058] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain cases, multitasking and parallel processing may be advantageous.

Claims

1. a plurality of processing cores; a reservation station comprising a wait buffer, a plurality of clusters, and circuitry configured to coordinate selection of instructions for out-of-order execution among the plurality of processing cores, the reservation station comprising: predicts that the load instruction will result in a cache miss, When a load instruction is predicted to result in a cache miss, i) executes the load instruction using one of the plurality of clusters, and ii) stores one or more dependent instructions of the load instruction in the wait buffer; a computing device configured to, upon completion of execution of the load instruction, i) retrieve one or more of the dependent instructions from the waiting buffer, and ii) execute the one or more dependent instructions using the plurality of clusters.

2. 2. The computing device of claim 1, wherein the wait buffer comprises a plurality of banks, and wherein storing the one or more dependent instructions of the load instruction comprises storing all dependent instructions of the load instruction in the same bank of the wait buffer.

3. The computing device of claim 2 , wherein each bank entry of the wait buffer comprises a logical register number, a physical register number, a bank ID, and a valid value.

4. The computing device of claim 3 , wherein each bank is organized as a first-in, first-out queue.

5. 5. The computing device of claim 1, wherein the reservation station further comprises a prediction circuit configured to generate a prediction of whether the load instruction will result in a cache miss.

6. The computing device of claim 5 , wherein the prediction circuitry comprises a counter incremented by a global load hit / miss history.

7. 6. The computing device of claim 5, wherein the prediction circuit comprises a number of cycles taken by an instruction at the head of a reorder buffer.

8. The computing device of claim 5 , wherein the prediction circuit comprises a hash load.

9. The computing device of any preceding claim, wherein the cache miss is a miss in a last level cache of the computing device.

10. A computing device according to any preceding claim, wherein two or more of the plurality of clusters are dedicated to executing different combinations of instruction types.

11. 11. The computing device of claim 10, wherein the first cluster is dedicated to executing simple instructions and branch instructions that execute in a single cycle.

12. 12. The computing device of claim 11, wherein the second cluster is dedicated to executing simple and multi-cycle instructions.

13. 13. The computing device of claim 1, wherein the reservation station is configured to perform bank-level arbitration when multiple banks are activated in the same clock cycle.

14. 1. A method performed by a computing device comprising: a plurality of processing cores; and a reservation station comprising a wait buffer, a plurality of clusters, and circuitry configured to coordinate selection of instructions for out-of-order execution on the plurality of processing cores, the method comprising: predicting, by the reservation station, that a load instruction will result in a cache miss; When a load instruction is predicted to result in a cache miss, i) executing the load instruction using one of the plurality of clusters, and ii) storing one or more dependent instructions of the load instruction in the wait buffer; Upon completion of execution of the load instruction, i) retrieving one or more of the dependent instructions from the queue buffer, and ii) executing the one or more dependent instructions using the plurality of clusters; A method comprising:

15. 15. The method of claim 14, wherein the wait buffer comprises a plurality of banks, and wherein storing the one or more dependent instructions of the load instruction comprises storing all dependent instructions of the load instruction in the same bank of the wait buffer.

16. 16. The method of claim 15, wherein each bank entry of the wait buffer comprises a logical register number, a physical register number, a bank ID, and a valid value.

17. 17. The method of claim 16, wherein each bank is organized as a first-in, first-out queue.

18. The method of any one of claims 14 to 17, wherein the reservation station further comprises a prediction circuit configured to generate a prediction of whether the load instruction will result in a cache miss or not.

19. 20. The method of claim 18, wherein the prediction circuitry comprises a counter incremented by a global load hit / miss history.

20. One or more non-transitory computer storage media encoded with computer program instructions that, when executed by one or more computers, cause the one or more computers to: predicting, by a reservation station, that a load instruction will result in a cache miss; When a load instruction is predicted to result in a cache miss, i) executing the load instruction using one of a plurality of clusters, and ii) storing one or more dependent instructions of the load instruction in a wait buffer; Upon completion of execution of the load instruction, i) retrieving one or more of the dependent instructions from the queue buffer, and ii) executing the one or more dependent instructions using the plurality of clusters; One or more non-transitory computer storage media that cause operations to be performed, including:

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