Method for manufacturing a resistive layer

Abstract

The present invention relates to a method for manufacturing a stack, including providing an initial stack comprising a base plate substrate primarily of a first material and a first insulating layer comprising an array of walls of a first insulating material separated by trenches, filling the trenches with a second insulating material to thereby form a second insulating layer, and forming a semiconducting film on the second insulating layer.

Description

[Technical Field]

[0001] The present invention relates to the manufacture of resistive layers, and more particularly to the manufacture of substrates comprising a semiconducting layer resting on an insulating layer, such as SOI (Silicon on Insulator) substrates, which have particularly advantageous applications, for example, in the field of radio frequency (RF) components. [Background technology]

[0002] To improve the performance of microelectronic components, and more particularly RF components, a major development focus is on improving SOI-type substrates. In particular, it is common to provide a high-resistivity base (or base plate) to support signal integrity and to insert a layer for trapping free carriers between the base and the buried oxide, commonly called BOX. The function of this trapping layer is to form a quasi-insulator, which in particular has an ultra-high electrical resistivity and does not vary with bias (Fermi level pinning).

[0003] Additionally, in the field of radio frequencies, it is desirable to have a substrate that allows signal integrity to be independent of the operating temperature of the device, for example, to produce communicating objects that are exposed to a wide range of variable temperatures. As an example, some devices can be exposed to temperatures ranging from -75°C to 200°C.

[0004] Several trap layers have been investigated in the past.

[0005] The most common trapping layers are made from undoped polycrystalline silicon (poly-Si). The large number of defects present at the grain boundaries of this material ensures the trapping function, resulting in resistivities of up to 10 kΩ.cm, or 100 Ω.m. The performance of these types of trapping layers has been investigated, among other things, in the document "RF Performance of a Commercial SOI Technology Transferred Onto a Passivated High-Rate Silicon Substrate," by Dimitri Lederer and Jean-Pierre Raskin, IEEE Trans. Electr. Dev., Vol. 55, No. 7, July 2008. This solution, however, does not provide sufficient stability of the electrical resistivity with respect to temperature fluctuations, impairing device performance. The electrical resistivity of an assembly consisting of a high-resistivity silicon base and a poly-Si trapping layer actually varies significantly with temperature.

[0006] The other capture layer is made of porous silicon. The use of this insulating material allows for linearity that is slightly dependent on the ambient environment for certain porosity conditions. These conditions are investigated in the paper "Small- and Large-Signal Performance Up to 175°C of Low-Cost Porous Silicon Substrate for RF Applications," M. Rack et al., IEEE Trans. Electr. Dev. 2018. However, this material has two major disadvantages: a high thermal resistivity that limits the power that can be dissipated, and low mechanical stiffness that makes its integration on SOI substrates and its use in foundries difficult.

[0007] A third solution is disclosed in particular in the document US Pat. No. 7,067,890 (B2). It consists in the formation in a silicon substrate of an array of walls 2 separated by trenches 3 (FIG. 9A), followed by the oxidation of these walls 2 until they coalesce (FIG. 9B). In the document, the width of the walls l m The width of trench 3 is l tThe optimal relationship relating: 0.46*l t =0.53l m This method is suitable for locally very thick oxides (10 μm = 10 -5 This allows obtaining a thermal conductivity of around 1 W / mK. The mechanical strength of the assembly thus obtained is better than that of the porous silicon capture layer. However, the thermal conductivity of the oxide is of the same order of magnitude (around 1 W / mK) as that of porous silicon (around 0.5 W / mK), the latter of which is lower than that of silicon (close to 140 W / mK). The same problems of dissipating power as described for porous silicon layers therefore also arise within the scope of this solution. Moreover, the production of thick oxides by the method described in document US Pat. No. 7,067,890 (B2) is extremely sensitive to variations in the dimensions of the walls 2 and of the trenches 3. The ratio l t / l m If the ratio l is greater than 0.53 / 0.46, an empty space will remain in the trench 3 after the complete oxidation of the wall 2, which is not favorable for heat release. t / l m If is less than 0.53 / 0.46, the trench 3 will be filled before full oxidation of the walls, leaving unoxidized silicon areas in the layer and sacrificing RF performance. Furthermore, this solution is not stable enough against temperature fluctuations. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] US Patent No. 7067890(B2) [Non-patent literature]

[0009] [Non-Patent Document 1] "RF Performance of a Commercial SOI Technology Transferred Onto a Passivated High-Rate Silicon Substrate," Dimitri Lederer and Jean-Pierre Raskin, IEEE Trans. Electr. Dev., Vol. 55, No. 7, July 2008. [Non-patent document 2] “Small- and Large-Signal Performance Up To 175℃ of Low-Cost Porous Silicon Substrate for RF Applications”, M. Rack et al., IEEE Trans. Electr. Dev. 2018 Summary of the Invention [Problem to be solved by the invention]

[0010] The present invention therefore aims to propose a simple solution that makes it possible to limit at least some of the disadvantages of known solutions, for example making it possible to obtain a buried insulating layer that has good mechanical strength, good thermal resistivity and a limited thermal expansion contrast with the substrate.

[0011] Other objects, features and advantages of the present invention will become apparent upon consideration of the following description and accompanying drawings, and it will be understood that other advantages may be incorporated. [Means for solving the problem]

[0012] To achieve the above-mentioned object, a first aspect of the present invention relates to a method for manufacturing a stack, comprising the following steps: a. At least one initial stack: i. a base plate substrate whose main component is a base material having a thermal expansion coefficient referred to as base α; ii. a first insulating layer resting on the base plate substrate, the first insulating layer being primarily composed of a first insulating material, the first insulating material having a first thermal conductivity λ1 and a first thermal expansion coefficient α1, the first insulating layer comprising an array of trenches; and providing at least one initial stack, Includes. The method comprises at least the following steps: b. filling the trench with a second insulating material having a second thermal conductivity λ2 and a second coefficient of expansion α2, thereby forming a second insulating layer, the second thermal conductivity λ2 being different from the first thermal conductivity λ1, and α1 and α2 being greater than 0.3 ppm / K; c. forming a semiconducting film above the second insulating layer; It is characterized by also including.

[0013] The buried insulating layer is in this case constituted in particular by a first insulating layer and a second insulating layer.

[0014] The use of a second insulating material allows the selection of the base plate substrate without being limited by the thermal conductivity, electrical resistivity, and / or thermal expansion values ​​that the material can provide. In particular, using a second insulating material with a thermal conductivity greater than that of the first insulating material allows the power dissipated by the buried insulating layer to be optimized. It is also possible to use a material whose average thermal expansion coefficient is close to that of the base plate material. In this sense, the use of several materials to create the buried insulating layer allows the achievement of physical properties that would be impossible to achieve by limiting the base plate substrate to one single material that must guarantee both the role of electrical insulator and thermal conductor.

[0015] A solution consisting of depositing a thick layer of an insulator, such as silicon nitride (Si3N4), having a thermal conductivity greater than that of the base plate substrate would be limited by the difference in coefficient of thermal expansion (CTE) between the silicon base plate substrate and the nitride layer (and most high thermal conductivity insulators), which could cause unacceptable deformation during thermal processing steps associated with manufacturing or using the substrate.

[0016] Furthermore, the wall array structure provides the layer with good mechanical strength, thus minimizing deformation of the layer compared to a continuous layer of one single material. This advantage is particularly interesting when the method is used to form a monolithic insulating layer. This is conveyed in this context by the arrow, which is lower than when the buried insulating layer is composed of a conventional continuous layer.

[0017] Another object of the invention relates to a microelectronic device comprising a stack of layers, said stack comprising, from the bottom surface of the stack: a. a base plate substrate; b. A buried insulating layer comprising: i. a first insulating layer having a plurality of walls, the first insulating layer being primarily composed of a first insulating material, the first insulating material having a first thermal conductivity λ1 and a first coefficient of expansion α1; ii. a second insulating layer whose main component is a second insulating material and which extends at least into the trench separating the walls, the second insulating material having a second thermal conductivity λ2 and a second expansion coefficient α2, the second thermal conductivity λ2 being different from the first thermal conductivity λ1, preferably 0.6≦I(α2+α1) / 2αI≦1.7, and α1 and α2 being greater than 0.3 ppm / K; a buried insulating layer comprising: c. Semiconductive film Equipped with.

[0018] By microelectronic devices, this is meant any kind of device produced by microelectronic means, these devices in particular including micromechanical or electromechanical devices (MEMS, NEMS, etc.) as well as optical or optoelectronic devices (MOEMS, etc.), in addition to devices of purely electronic purpose.

[0019] This can be a device intended to ensure electronic, optical, mechanical functionality, etc. It can also be an intermediate product intended solely for the production of another microelectronic device. The method and device according to the invention are particularly advantageous for forming devices for radio frequency (RF) applications.

[0020] The objects, goals, as well as features and advantages of the present invention will be best apparent from the following detailed description of one embodiment of the present invention, illustrated by the accompanying drawings. [Brief explanation of the drawings]

[0021] [Figure 1A] 1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, more particularly illustrating steps of forming an initial stack as shown in FIG. 1E, from which other steps are performed to achieve a stack according to the present invention, and illustrating the preparation of a substrate. [Figure 1B] 1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, more particularly illustrating steps of forming an initial stack as shown in FIG. 1E, from which other steps are performed to achieve the stack according to the present invention, and illustrating deposition of a lithography mask on a substrate. [Figure 1C]1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, more particularly illustrating steps of forming an initial stack as shown in FIG. 1E, from which other steps are performed to achieve the stack according to the present invention, and representing the formation of trenches in a substrate through a lithography mask, resulting in the formation of an array of walls in the substrate. [Figure 1D] 1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, more particularly illustrating steps of forming an initial stack as shown in FIG. 1E, from which other steps are performed to achieve the stack according to the present invention, and illustrating removal of a lithography mask. [Figure 1E] 1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, more particularly illustrating steps of forming an initial stack as shown in FIG. 1E, from which other steps are performed to achieve a stack according to the present invention, and illustrating steps of converting the material constituting the walls made from a first insulator, thereby forming a first insulating layer. [Figure 1F] 1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, illustrating steps of forming an initial stack as shown in FIG. 1J, from which other steps are performed to achieve a stack according to the present invention, and illustrating the preparation of a base plate substrate. [Figure 1G] Illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, illustrating steps of forming an initial stack as shown in FIG. 1J, from which other steps are performed to achieve a stack according to the present invention, illustrating the formation of a first initial insulating layer on a base plate substrate. [Figure 1H]1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, illustrating steps of forming an initial stack as shown in FIG. 1J, from which other steps are performed to achieve the stack according to the present invention, illustrating deposition of a lithography mask on a first initial insulating layer. [Figure 1I] 1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, illustrating steps of forming an initial stack as shown in FIG. 1J, from which other steps are performed to achieve a stack according to the present invention, and illustrating the formation of trenches in a first initial insulating layer through a lithographic mask, resulting in the formation of an array of walls in the first initial insulating layer. [Figure 1J] 1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, illustrating steps of forming an initial stack as shown in FIG. 1J, from which other steps are performed to achieve the stack according to the present invention, illustrating removal of a lithography mask. [Figure 1K] 1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, depicting the step of filling a trench with a second insulating material, thereby forming a second insulating layer. [Figure 1L] 1 illustrates steps of a first example of a method for forming a stack according to one embodiment of the present invention, illustrating steps of forming a semiconducting film on a first insulating layer and a second insulating layer. [Figure 2A] 10 illustrates another example of creating trenches in a base plate substrate implementing nano-printing technology, depicting the deposition of a printable resin layer onto the base plate substrate. [Figure 2B] 10 illustrates another example of creating trenches in a base plate substrate implementing nano-printing technology, illustrating using a mold to press the mold into the printable resin, and printing a pattern into the printable resin by UV treatment. [Figure 2C] 10 illustrates another example of creating trenches in a base plate substrate implementing nano-printing technology, illustrating removal of a mold. [Figure 2D] 10 illustrates another example of creating trenches in a base plate substrate implementing nano-printing technology, illustrating etching of certain zones of a printable resin layer to form a desired etching mask. [Figure 2E] 10 illustrates another example of creating trenches in a base plate substrate implementing nano-printing technology, depicting the formation of trenches in the base plate substrate through an etching mask. [Figure 3A] FIG. 1 illustrates another example of one embodiment of a trench in a base plate substrate implementing a technique for self-assembling block copolymers, representing the deposition of a copolymer layer onto the base plate substrate, with the blending of diagonal and dotted lines illustrating the fact that this layer initially comprises two mixed and random copolymers. [Figure 3B] FIG. 1 illustrates another example of an embodiment of a trench in a base plate substrate implementing a technique for self-assembling block copolymers, illustrating processing steps that allow the copolymers to be aligned by an alternating sequence of blocks each comprising only one of the two copolymers. [Figure 3C] 1 illustrates another example of an embodiment of a trench in a base plate substrate implementing a technique for self-assembling block copolymers, illustrating the selective removal of one of the two copolymers relative to the other to form an etch mask. [Figure 3D] 1 illustrates another example of one embodiment of a trench in a base plate substrate implementing a technique for self-assembling block copolymers, depicting the formation of a trench in the base plate substrate through an etching mask. [Figure 4] 10 depicts an optional step according to one embodiment of the present invention of depositing a continuous layer of predominantly the second insulating material on the second insulating layer and the first insulating layer. [Figure 5] 10 depicts an optional step according to one embodiment of the present invention of depositing a third insulating layer onto a continuous layer primarily composed of a second insulating material. [Figure 6A] 10 illustrates another example of an embodiment of the step of forming a semiconducting film, depicting the injection of a layer enriched with a gas element into the semiconducting layer. [Figure 6B] 10 depicts another example of an embodiment of the step of forming a semiconductive film, illustrating bonding of a semiconductive layer to a stack. [Figure 6C] 10 illustrates another example of an embodiment of the step of forming a semiconductive film, illustrating cutting the semiconductive layer at a layer enriched in a gas element to form the semiconductive film. [Figure 6D] 10 illustrates another example of one embodiment of the step of forming a semiconductive film, illustrating the resulting stack after the step of cutting the semiconductive layer. [Figure 7] 1 illustrates a stack according to one embodiment of the present invention, in which a semiconducting film is deposited directly onto a second insulating layer. [Figure 8] 1 illustrates a stack according to one embodiment of the present invention, in which a semiconducting film is deposited, primarily directly onto a continuous layer of a second insulating material. [Figure 9A] 1 illustrates a method for obtaining a thick oxide layer according to the prior art. [Figure 9B] 1 illustrates a method for obtaining a thick oxide layer according to the prior art. DETAILED DESCRIPTION OF THE INVENTION

[0022] The drawings are given by way of example and not by way of limitation of the invention. They constitute a schematic representation of principles intended to facilitate understanding of the invention and are not necessarily to scale in practical application. In particular, the thicknesses of different layers and films do not represent reality.

[0023] Before commencing a detailed discussion of embodiments of the present invention, optional features are described below, which can optionally be used in conjunction or alternatively.

[0024] Preferably, the first insulating layer consists entirely of the first insulating material.

[0025] Advantageously, the first insulating material and the second insulating material are distinct from the base material.

[0026] After conversion, the trench extends through the thickness of the first insulating layer.

[0027] Preferably, the first insulating layer has a lower surface and lies completely below the bottom of the trench.

[0028] According to an advantageous embodiment, 0≦2*|(α2-α1)| / (α2+α1)≦1.8 and 0≦|(α-α1)| / α≦2.1. Thus, the thermal expansion coefficients of the first insulating layer and the second insulating layer, on the one hand, and the first insulating layer and the base plate substrate, on the other hand, are very close to each other. This makes it possible to avoid too large a difference in the thermal expansion coefficients between the materials of the layers in contact with the main components. This makes it possible to reduce or even avoid mechanical deformations that may occur during temperature fluctuations. This gives the stack better robustness and better structural quality.

[0029] According to one example, 0.6≦|(α2+α1) / 2α|≦1.7. This again makes it possible to guarantee a certain proximity of the thermal expansion coefficient values ​​of the different materials of the stack. This makes it possible to reduce or even avoid mechanical deformations that may occur during temperature fluctuations. This gives the stack better robustness and better structural quality.

[0030] According to one example, k1≦|(λ2−λ1) / λ1|, where 0.3≦k1.

[0031] According to one embodiment, the second thermal conductivity λ2 is strictly greater than the first thermal conductivity λ1 (λ2>λ1).

[0032] According to one example, one of the first thermal expansion coefficient α1 and the second thermal expansion coefficient α2 is greater than α, and / or the other of the first thermal expansion coefficient α1 and the second thermal expansion coefficient α2 is smaller than α.

[0033] According to one example, the first insulating material has a first Young's modulus E1 and the second insulating material has a second Young's modulus E2, where E1≠E2, preferably m1≦|(E2−E1) / E1|, where 0.03≦m1, and E1 and E2 are greater than 50 GPa.

[0034] According to one example, preparing the initial stack comprises the following steps: a. providing at least one initial substrate having a top surface, the main component of which is, preferably consisting of, a base material; b. forming an initial array of trenches in the initial substrate from the top surface, with base material remaining between the trenches to form initial walls; c. converting at least the base material on at least one portion of the initial substrate comprising an initial array of initial walls made from a first insulating material to form a resulting first insulating layer comprising an array of walls separated by trenches; Includes.

[0035] According to one example, the step of transforming at least the base material on at least one portion of the initial substrate comprises oxidizing the base material separating the trenches from one another.

[0036] According to one example, the step of forming the initial array of initial walls comprises the implementation of at least one technique from among lithography, nanoprinting, block copolymer self-assembly and laser processing.

[0037] According to one embodiment, the step of preparing the initial stack comprises the following steps: a. providing a base plate substrate; b. forming a first initial insulating layer overlying the base plate substrate, the first initial insulating layer being primarily composed of a first insulating material; c. forming an array of trenches in the first initial insulating layer, thereby forming a first insulating layer; Includes.

[0038] According to one example, the step of forming the array of walls comprises the implementation of at least one technique from among lithography, nanoprinting, block copolymer self-assembly and laser processing.

[0039] According to one embodiment, the method further includes, prior to the step of forming the semiconducting film, a step of continuously forming a continuous layer whose main component is a second insulating material, preferably made from the second insulating material, directly covering the second insulating layer. According to one example, the continuous layer is insulating. The continuous layer preferably also covers the walls separating the trenches. The continuous layer can optionally be formed simultaneously with the second insulating layer, for example during simultaneous deposition, preferably conformal deposition, on the sides and top of the walls separating the trenches. This optional layer improves the electrical resistivity of the stack. It also makes it possible to ensure good cohesion of the different layers provided in the buried insulating layer. According to one example, the continuous layer can be considered as a fourth layer.

[0040] According to one embodiment, the method further comprises forming a third insulating layer below the semiconducting film. The third insulating layer therefore preferably covers the walls separating the trenches. This optional layer improves the electrical resistivity of the stack. It can also be useful for the purpose of planarization of the buried insulating layer and the quality of its interface with the semiconducting film.

[0041] According to one embodiment, the walls separating the trenches have a wall width l m ', and the trench has a trench width l t ' and the ratio l t ' / l m ' is between 0.3 and 3, preferably between 0.5 and 1.5. t ' and l m' is preferably 0.7≦|(l t '*α2+l m '*α1) / ((l t '+l m ')*α)|≦1.3.

[0042] According to one example, the trench has a depth e t ' and e t is between 5 and 20 μm, preferably between 8 and 15 μm.

[0043] According to one example, l m ' is between 0.5 μm and 4 μm, preferably between 0.8 μm and 1.5 μm.

[0044] According to one example, l t ' is between 0.25 μm and 4 μm, preferably between 0.4 μm and 0.8 μm.

[0045] According to one example, the second insulating material is made of or consists mainly of one of the following: Al2O3, AlN, SiC, Si3N4, BeO, silicon oxynitride and BN.

[0046] According to one example, the semiconducting film is mainly composed of one of Si and its alloys, Ge and its alloys, SiC, InAs, InSb, InGaAs, GaN, AlGaN, InGaN, GaAs, and InP.

[0047] According to one example, the third insulating layer is mainly composed of one of SiO2, AlN, HFSiON, and Al2O3.

[0048] According to one embodiment of the device, the buried insulating layer further comprises a continuous layer consisting primarily of the second insulating material directly overlying the second insulating layer.

[0049] According to one embodiment, the buried insulating layer further comprises a third insulating layer overlying the second insulating layer.

[0050] It is specified that within the scope of the present invention, the terms "on," "resting," "covering," "underlying," "opposite," and their equivalents do not necessarily mean "in contact with." Thus, for example, depositing, transferring, bonding, combining, or applying a first layer to a second layer does not necessarily mean that the two layers are in direct contact with each other, but rather that the first layer at least partially covers the second layer, either by being in direct contact with it or by being separated from it by at least one other layer or at least one other element.

[0051] A layer can consist of one above the other of the same material or of several sublayers of different materials.

[0052] By a substrate, layer, or device "based on" a material M, this means a substrate, layer, or device comprising only this material M, or this material M and optionally other materials, such as alloying, impurity, or doping elements. Thus, a material based on III-N materials can consist of III-N materials with added dopants. Similarly, a GaN-based layer typically comprises GaN and an AlGaN or InGaN alloy.

[0053] The term "III-V material" refers to semiconductors composed of one or more elements from columns III and V of Mendeleev's periodic table. Column III elements include boron, gallium, aluminum, and indium. Column V includes, for example, nitrogen, arsenic, antimony, and phosphorus.

[0054] Electrical resistivity is 1 kg (10 3 ) ohm-meter (1 kΩm) or greater, preferably 10 kΩm or greater, is considered an insulator.

[0055] The abbreviation "ppm" means "parts per million." This term is used to refer to a concentration of 10 -6 , i.e., a fraction equal to one millionth.

[0056] By "selective etch with respect to" or "etch with selectivity with respect to," it is meant an etch configured to remove material or layer A with respect to material or layer B, where the etch rate of material A is greater than the etch rate of material B. Selectivity is the ratio between the etch rate of material A to the etch rate of material B. The selectivity between A and B is referred to as SA:B.

[0057] The expression "stability of electrical resistivity with respect to temperature" (or "stability of applied electric field") can correspond to the maintenance of resistivity above a given threshold, for example 10 kΩ.cm, independent of temperature (or applied electric field).

[0058] A preferably orthonormal system is represented in Figure 1A, with axes x, y, z. This system is applicable by extension to other figures.

[0059] In this patent application, thickness is preferably referred to in relation to a layer, and height is preferably referred to in relation to a structure or device. Thickness is measured in a direction perpendicular to the main extension plane of the layer, and height is measured perpendicular to the base plane XY. Thus, a layer, if it extends mainly along the plane XY, typically has a thickness along z, and a protruding element, e.g., an insulating trench, has a height along z. The relative terms "above", "below", and "underneath" preferably refer to positions taken along the direction z.

[0060] Within the scope of the present invention, the term "array" includes any distribution of walls separated by trenches. The array may or may not have a regular step. It may extend over the entire surface of the first insulating layer or over only a portion of its surface.

[0061] The steps of the method as claimed can be broadly extended and optionally carried out in several substeps.

[0062] An example of a production method will now be described with reference to Figures 1A to 1L. The method makes it possible to obtain a stack 1, illustrated in Figure 1L, comprising a base plate substrate 100', an insulating layer 1000 such as a buried oxide, and a semiconducting film 400'. The insulating layer 1000 comprises, in this embodiment, a first insulating layer 130' and a second insulating layer 200, which themselves comprise a plurality of walls 150' separated by trenches 120'.

[0063] The production method first consists of preparing an initial stack as illustrated in Figures 1E and 1J. This stack comprises, in particular, a base plate substrate 100' of a first material, considered as the base material, and a first insulating layer 130' comprising an array 150' of trenches 120' separated by walls 110'. Two embodiments for producing this initial stack will now be described.

[0064] The first of these two embodiments will be described first with reference to Figures 1A to 1E. As illustrated in Figure 1A, in this embodiment, the first step consists of preparing a substrate 100, the main component of which is a base material that can be converted into an insulating material, referred to as the first insulating material. Preferably, the substrate 100 is monocrystalline silicon or polycrystalline silicon based. In general, any semiconductor that can be made insulating by oxidation can be considered. It is also possible to choose a material that can be converted into an insulator by ion bombardment. There are therefore many possible materials, making it possible to have the option of using low-cost materials in particular.

[0065] The initial substrate 100 has a top surface 101 and a bottom surface 102 that both extend primarily in a plane parallel to the Cartesian plane XY. Along the direction Z, it has a thickness e 100 For example, e 100 is between 300 μm and 1000 μm.

[0066] The second step of this embodiment consists of forming in the initial substrate 100 an initial array 150 of initial walls 110 separated by initial trenches 120, as illustrated in Figure 1D. The initial walls 110 have a width l measured in the direction X. m The initial trench 120 has a width l measured in the direction X. t and the depth e measured in the direction Z t The initial wall 110 therefore extends from its upper surface 101 into the initial substrate 100 at a depth e t It stretches up to.

[0067] The initial walls 110 and the initial array 150 of initial trenches 120 can be achieved from all of the top surface 101 of the initial substrate 100. It can also be achieved from only a part of this top surface 101. In a stack 1 produced according to this latter embodiment, the part of the top surface 101 without the initial trenches 120 can be used to electrically connect the semiconducting film 400′ to the substrate 100.

[0068] The initial walls 110 and the initial trenches 120 can be formed in various ways. For example, lithography techniques, such as photolithography, can be used. In this embodiment, a photosensitive resin layer is deposited on the upper surface 101 of the initial substrate 100. Openings are then created in the photosensitive resin by exposure through a photolithography mask and subsequent development. These openings are the origin of the initial trenches 120 that will be formed. At the scale of the stack 1, they typically form parallel lines extending primarily in the direction Y. However, during integration of the stack 1 into a microelectronic device, these lines advantageously do not have a preferred direction relative to the device scale. In this way, the thermal expansion coefficient of the insulating layer 1000 is substantially that of the base plate substrate 100′ in all directions of its plane. The photosensitive resin layer etched in this way forms the etching mask 10, as shown in FIG. 1B. The initial trenches 120 are then formed by etching through the etching mask 10. For example, if the base plate substrate 100 is monocrystalline silicon or polycrystalline based, it is possible to implement the Bosch method, which is preferred for producing high form factor structures such as the walls 110. This method alternates between sulfur hexafluoride (SF6)-based plasma etching and fluorocarbon chemistry (C4F8, C2F6, CF4 or also CHF3-Ar)-based passivation.

[0069] It is possible, but not necessary, to deposit a masking layer between the upper surface 101 of the substrate 100 and the photosensitive resin layer. The masking layer is typically silicon dioxide-based. Preferably, it has a thickness greater than 0.5 μm, preferably greater than 0.8 μm. In this embodiment, after developing the photosensitive resin through its entire thickness, the masking layer is etched through the photosensitive resin layer to obtain a hard mask from which the initial walls 110 will be formed. The etching of the hard mask and the etching of the initial trench 120 can be carried out successively by different methods or, advantageously, during one and the same etching method. The Bosch method described above can in particular be used for etching the silicon dioxide hard mask simultaneously with the etching of the initial trench 120.

[0070] In any case, etching of the trench can be followed by a step to remove potential etch residues.

[0071] It should be noted that the etching mask 10 can also be formed by other lithographic techniques, such as electron lithography, double exposure lithography or even extreme ultraviolet lithography.

[0072] Furthermore, the initial trench 120 can be achieved other than by lithography.

[0073] For example, the step of forming the initial trenches can include a nano-printing step. This embodiment is illustrated in FIGS. 2A to 2E. FIG. 2A illustrates the deposition of a printable resin layer 20 on the upper surface 101 of an initial substrate 100. This printable resin layer 20 has an upper surface 21 and a lower surface 22 extending mainly in the Cartesian plane XY, with the lower surface 22 being in contact with the upper surface 101 of the initial substrate 100. FIG. 2B illustrates the step of printing a pattern into the printable resin layer 20 using a mold 25. The mold 25 is leveled and pressed against the upper surface 21 of the printable resin layer 20 and subjected to an ultraviolet (UV) treatment, represented in FIG. 2B by all parallel arrows pointing towards the upper surface 21, to harden the printable resin according to the desired pattern. The printable resin layer 20 is then etched to expose only certain zones of the upper surface 101 of the initial substrate 100. Finally, initial trenches 120 are formed in the baseplate substrate by etching through the remaining areas of the printable resin layer 20 .

[0074] Another lithographic alternative is illustrated in Figures 3A-3D. First, a copolymer layer 30 is deposited on the upper surface 101 of an initial substrate 100 (Figure 3A). This layer 30 comprises an initially disordered mixture of a first polymer and a second polymer. As illustrated in Figure 3B, the copolymer layer 30 then undergoes a treatment that allows the first polymer and the second polymer to be aligned in an alternating sequence between blocks 31 of the first polymer and blocks 32 of the second polymer. One of the two polymers is then selectively removed relative to the other to expose a zone of the upper surface 101 of the initial substrate 100, as illustrated in Figure 3C. Etching is then performed through the remaining polymer blocks to form an initial trench 120.

[0075] Lithography can also be replaced by deposition of a layer on the initial substrate 100 followed by laser treatment of this layer to form an array of ripples that can then be etched to again form an etching mask.

[0076] One advantage of the last three embodiments described for forming the array 150 of initial walls 110 and initial trenches 120 is that they avoid the use of lithography equipment. In any case, etching of the initial trenches 120 can be performed by any one of the etching methods described above.

[0077] The third step of this embodiment is represented by the transition from FIG. 1D to FIG. 1E. This is the conversion of the base material constituting the initial walls 110, and optionally the portion of the initial substrate 100 directly below the initial walls 110, into a first insulator. This conversion allows the formation of a first insulating layer 130' comprising an array 150' of walls 110' and trenches 120'. Therefore, the height of the first insulating layer 130', measured along axis Z, is equal to or greater than the depth of the trenches 120'. Therefore, after conversion, the trenches 120' thus extend within the thickness of the first insulating layer 130'. Preferably, they do not extend into the unconverted portion of the initial substrate 100. The height of the first insulating layer 130' is typically constant. The first insulating layer 130' therefore typically has a lower surface 132' extending primarily in a plane parallel to plane XY. The lower surface 132 ′ of the first insulating layer 130 ′ is located along the axis Z between the lower surface 102 and the upper surface 101 of the initial substrate 100 .

[0078] The lower surface 132' of the first insulating layer 130' is located completely below the bottom 122' of the trench 120'.

[0079] The conversion step typically involves an oxidation step, conventionally wet oxidation. For example, this step allows the silicon initial wall 110 to be converted into a silica wall 110'. The conversion step can also include an ion bombardment step. This ion bombardment can be, for example, based on carbon, oxygen, and / or nitrogen ions, with a dose that allows reaching an atomic concentration of a few percent to result in a material with grains smaller than 10 nm after rapid annealing above 1000°C for less than 1 second with a ramp of at least 50°C / s. This ion bombardment can be preceded by a conventional Si+ ion bombardment that allows amorphizing the wall to promote its transformation by implantation of one of the species mentioned above (carbon, oxygen, and / or nitrogen).

[0080] The first insulating material has the following parameters: a first thermal conductivity λ1, a first electrical resistivity ρ1, a first Young's modulus E1, and a first thermal expansion coefficient α1.

[0081] The thermal conductivity of a material is measured in Wm -1 .K -1 It can be evaluated, for example, by the so-called 3ω method.

[0082] The thermal expansion coefficient of a material is expressed in K units of the International System of Units. -1 It can be measured, for example, by dilatometry: the length or thickness of the sample is measured while the sample is subjected to known temperature variations.

[0083] The values ​​of the dimensions characterizing the geometry of the array can be modified during the transformation of the initial wall 110 into the wall 110'. Thus, new dimensions are now defined for the array 150'. The wall 110' has a width l measured in the direction X. m The trench 120′ has a width l measured in the direction X. t ' and the depth e measured in the direction Z t The wall 110' thus extends from its upper surface 101 into the substrate 100 to a depth e t ' stretches to.

[0084] Width of wall 110'l m ', width of trench 120'l t ' and the depth of trench 120' e t The depth e of the trench 120' is determined in accordance with the functional requirements of the systems supported by the stack 1, in particular their operating frequencies, losses that can be tolerated in these systems, and also diaphony. t ' is typically between 5 and 20 μm. In addition, it is advantageous to m The width l of the wall 110' is at least five times larger than the width l of the wall 110', and preferably ten times larger than the width l of the wall 110'. m The width l of trench 120' is typically between 0.5 and 4 μm. t The width l of the wall 110' is typically between 0.25 and 4 μm. m ' and the width l of the trench 120' t ' are advantageously substantially equal. They are preferably respectively l m ' and l t The thermal expansion coefficients α1 and α2 of the first and second insulators, weighted by ', are chosen to be between 0.7*α and 1.3*α, and preferably substantially equal to the thermal expansion coefficient of the base α. For example, it is possible to proceed as follows to size the walls 110' and trench 120': a. selecting a first insulating material and a second insulating material that will fill the trench 120'; b. The above relationship: 0.7≦|(l t '*α2+l m '*α1) / ((l t '+l m Fixing the ratio between the width of the wall 110′ and the width of the trench 120′ so that |′)*α)|≦1.3 is satisfied; c. The relative dielectric constants of the first and second insulating materials and the trench depth e t depth e so that the ratio between t For example, it is 7 / 15μm -1The equivalent relative permittivity is l m ' and l t is the average of the relative dielectric constants of the first and second insulating materials, weighted by '. dl t ' and e t The aspect ratio between the trench and the lattice length is such that the trench can be easily filled. t 'Choose a width value. For example, around 1 / 10 t ' / e t '. Then from this m ' is inferred.

[0085] After conversion of the initial array 150 into the insulating array 150', the initial stack depicted in FIG. 1E is obtained. In particular, the unconverted portion of the initial substrate 100 corresponds to the baseplate substrate 100' provided in the initial stack depicted in FIG. 1E. The lower surface 132' of the first insulating layer 130' is aligned with the upper surface 101' of the baseplate substrate 100'. The first insulating layer 130' therefore extends entirely above the upper surface 101' of the baseplate substrate 100'. Like the lower surface 132' of the first insulating layer 130', the upper surface 101' of the baseplate substrate 100' extends primarily in a plane parallel to the plane XY.

[0086] A second embodiment of the step of preparing the initial stack will now be described with respect to Figures 1F-1J.

[0087] As illustrated in Figure 1F, in this embodiment, the first step consists of providing a baseplate substrate 100' having an upper surface 101' and a lower surface 102' that both extend primarily in a plane parallel to the Cartesian plane XY.

[0088] A first initial insulating layer 130 is then deposited on the upper surface 101' of the baseplate substrate 100'.

[0089] The second step of this embodiment consists of forming in the first initial insulating layer 130 an array 150' of walls 110' separated by trenches 120', as illustrated in Figures 1H and 1I. The trenches 120' are formed within the thickness of the first initial insulating layer 130. Preferably, the trenches do not extend into the base plate substrate 100'. In the first initial insulating layer 130, an array 150' of walls 110' has been formed, which corresponds to the first insulating layer 130' described above.

[0090] The formation of the walls 110' and trenches 120' can be achieved by implementing any of the techniques described above for the formation of the initial walls 110 and initial trenches 120, or even several of them: lithography (photolithography, electron lithography, double exposure lithography, extreme ultraviolet lithography), nanoprinting, selective application and removal of block copolymers, or even laser processing. Common to all these techniques, the final etching of the trenches 120' must be adapted to the properties of the first insulating material. Thus, in this embodiment, for example, the following chemistries can be used (in brackets, the material considered for the first insulating material): BCl3-Ar (for AlN, BeO), O2-SF6 (for SiC), CHF3 (for SiON), and O2-CF4 (for BN and Al2O3).

[0091] In this embodiment, no conversion step is required. The dimensions of the array after etching are therefore the dimensions l mentioned above. t ',l m ',e t ', the sizing characteristics of which have already been described.

[0092] After removal of the etching mask used during the step of forming the array 150, an initial stack is obtained as illustrated in Figure 1J, which is similar to that obtained by implementing the first embodiment of the preparation of this initial stack (Figure 1E). The subsequent steps of the method will now be described with reference to Figures 1K, 1L and 4 to 8.

[0093] 1K, the trench 120′ is filled with a second insulating material, resulting in the formation of a second insulating layer 200. This second insulating layer 200 is formed from multiple regions, each extending into the trench 120. It has a thickness e measured along the direction Z. 200 The thickness e of the second insulating layer 200 200 is preferably the depth e of the trench 120′. t In the present case of forming the second insulating layer 200 by conformal deposition, a secondary thickness of the second insulating material can be defined and deposited from the side of the array of walls 110′. This secondary thickness, measured in the plane XY, is equal to l t ' / 2. In fact, in trench 120', the growth fronts starting from the sides of wall 110' surrounding trench 120' join together when the secondary thickness is equal to half the width of trench 120'. This secondary thickness of second insulating layer 200 is preferably between 5 and 20 μm.

[0094] The fact that the second insulating layer 200 is formed in the trenches 120' of the first insulating layer 130' gives the assembly good mechanical strength. More specifically, the array structure of the first insulating layer 130' and the complementary shape of the second insulating layer 200 make it possible to obtain better mechanical strength of the single stack of planar layers of the first insulating material and of the second insulating material.

[0095] The second insulating material has the following parameters: a second thermal conductivity λ2, a second electrical resistivity ρ2, a second Young's modulus E2, and a second thermal expansion coefficient α2. The width of the trench 120' and the wall 110', the first thermal expansion coefficient α1, and the second thermal expansion coefficient α2 are advantageously such that the thermal expansion coefficient of the assembly composed of the first insulating layer 130' and of the second insulating layer 200 in the direction X is substantially close to that of the base plate substrate 100'.

[0096] The second insulating material preferably has a high thermal conductivity λ2. It can be, for example, Al2O3, AlN, SiC, Si3N4, BeO or even BN. These insulators have particularly good thermal conductivity, and SiO2 can typically be used as the first insulator. In practice, it is advantageously provided that the thermal conductivity λ2 of the second insulating material is greater than the thermal conductivity λ1 of the first insulator.

[0097] The deposition of the second insulating material in the converted trench 120' is preferably carried out by a method that makes it possible to achieve high conformality, for example by LPCVD (Low Pressure Chemical Vapor Deposition) or by ALD (Atomic Layer Deposition).

[0098] Advantageously, but optionally, after the step of depositing the second insulating layer 200, there is provided the deposition of a continuous layer 250 of a second insulating material predominantly on the second insulating layer 200. The continuous layer 250 of a second insulating material predominantly extends in particular in vertical alignment with the array 150'. More particularly, it covers the upper portions 111' of the converted walls 110'. It has a thickness e of the second insulating layer. 200 Advantageously, second insulating layer 200 completely fills trench 120', and continuous layer 250 does not extend into converted trench 120'. Continuous layer 250 and second insulating layer 200 thereby form a continuous assembly primarily composed of the second insulating material. This optional step is illustrated in FIG. 4. In this embodiment, buried insulating layer 1000 comprises first insulating layer 130', second insulating layer 200, and continuous layer 250.

[0099] Advantageously, but optionally, after the step of depositing the second insulating layer 200, the thickness e measured along the direction Z 300The third insulating layer 300 has a top surface 301 extending primarily in the orthogonal plane XY. This third insulating layer 300 is deposited on the second insulating layer 200 or on the continuous layer 250, if such a layer is deposited. It is mainly composed of a third insulating material, which can optionally be the same as the first insulator. For example, it can be silica-based. The third insulator has the following parameters: a third thermal conductivity λ3, a third electrical resistivity ρ3, a third Young's modulus E3, and a third thermal expansion coefficient α3.

[0100] In this embodiment, the insulating layer 1000 comprises a first insulating layer 130', a second insulating layer 200, a third insulating layer 300 and optionally a continuous layer 250, as depicted in FIG.

[0101] The method can include an optional step of planarizing the buried insulating layer 1000 after depositing the second insulating layer 200 and any other optional insulating layers. This can be performed using a chemical mechanical planarization (CMP) step from the top surface 1001 of the buried insulating layer 1000. In the case where a third insulating layer 300 is deposited on the second insulating layer 200, the planarization of the buried insulating layer 1000 can be performed to a thickness e 300 is advantageously greater than twice, and preferably four times, the maximum roughness of the surface of the underlying layer of second insulating material. This avoids the roughness of this surface being transferred to the upper surface 301 of the third insulating layer 300. In any case, the CMP step aims to remove a surface roughness greater than twice, and preferably substantially equal to three times, the maximum roughness of the upper surface 1001 of the buried insulating layer 1000.

[0102] Planarization can alternatively be obtained by proceeding with a planarizing deposition onto the upper surface 1001 of the buried insulating layer 1000. For example, this can be a hydrogen silsesquioxane (HSQ) deposition.

[0103] This optional step is intended to prepare the upper surface 1001 of the buried insulating layer 1000, particularly in the step of providing the semiconductive film 400' to be described below, particularly when the semiconductive film 400' is provided by bonding.

[0104] The fifth step is depicted in Figure 1L. It consists of forming a semiconducting film 400' on the buried insulating layer 1000. More specifically, the semiconducting film 400' can directly cover the second insulating layer 200, the continuous layer 250 mainly of the second insulating material, or also the third insulating layer 300, depending on whether optional layers have been previously deposited on the second insulating layer.

[0105] The semiconducting film 400' can be, for example, Si-based or based on III-V materials such as InP, GaAs or also GaN, which are commonly used to produce RF devices.

[0106] According to one embodiment of the present method, forming the semiconducting film 400' includes implementing a Smart Cut™ type method, one embodiment of which is illustrated in Figures 6A-6D.

[0107] 6A illustrates the preparation of a semiconducting layer 400 having an upper surface 401 and a lower surface 402, both of which extend primarily in an orthogonal plane XY. This figure illustrates the implantation of light ions into the semiconducting layer 400 from its upper surface 401 to form an implantation zone 500. The semiconducting layer 400 thus defines a semiconducting film 400' between its upper surface 401 and the implantation zone 500. The implantation zone 500 advantageously extends parallel to the upper surface 401 and to the lower surface 402 of the semiconducting layer 400.

[0108] 6B, the semiconducting layer 400 is then bonded at its upper surface 401 to the upper surface 1001 of the buried insulating layer 1000. The implementation of the optional step of planarizing the buried insulating layer 1000 described above makes it possible to improve the quality of the bonding interface between the semiconducting film 400′ and the upper surface 1001 of the buried insulating layer 1000.

[0109] After the bonding step, the semiconducting layer 400 is subjected to a treatment that allows weakening in its implanted zones in the gas element. As shown in FIG. 6C, the semiconducting layer 400 can then be cut. A semiconducting film 400' of the same material as the semiconducting layer 400 thus remains on the buried insulating layer, its thickness along Z e 400 depends on the implantation thickness of the implanted zone 500 in the semiconducting layer 400. The semiconducting film 400' is therefore transferred to the stack 1. The stack 1 thus obtained is represented in FIG. 6D. More specifically, this figure illustrates the stack 1 obtained in an embodiment whose main component includes the optional step of depositing a continuous layer 250 of a second insulating material and of depositing a third insulating layer 300.

[0110] It is also conceivable to bond the semiconducting layer 400 to the upper surface 1001 of the buried insulating layer 1000 at its lower surface 402. The semiconducting film 400' is then defined between the implanted zone 500 and the lower surface 402. Other embodiments of the Smart Cut® method can be implemented. For example, a semiconducting material can be selected for the material of the base plate substrate 100'. Implanting light ions to form an implanted zone can then be performed, for example, through the buried insulating layer 1000 into the base plate substrate 100'. It is then possible to proceed with bonding the handle to the buried insulating layer (and thus to the second insulating layer 200, or to the continuous layer 250 mainly composed of the second insulating material, or to the third insulating layer 300). Like the semiconducting layer 400 in the above-described embodiment, the base plate substrate 100' can then be cut at the transferred layer of light ions to obtain the semiconducting film. The handle can then be polished to form the substrate for the final structure.

[0111] The method that can be used to provide the semiconducting film 400' on the buried insulating layer 1000 is, however, not limited to the just described Smart Cut® method: any other thin film transfer technique can be envisaged.

[0112] For example, it is possible to bond a semiconductive layer 400 to the upper surface 1001 of the buried insulating layer 1000, then finish by a honing step, optionally a CMP polishing step, and proceed with etching from its lower surface 402 to thin this layer until a semiconductive film 400' is obtained.

[0113] According to another embodiment, the semiconducting film is formed in a fuse layer, which is itself deposited on a transparent material. The semiconducting film 400' is bonded to the upper surface 1001 of the buried insulating layer 1000 by direct bonding on the surface facing the fuse layer. The fuse layer is then exposed to light to degrade it and separate it from the semiconducting film 400'.

[0114] According to another embodiment, the semiconducting film 400' is epitaxially grown on the surface of the semiconducting layer in the weakened zone, for example by porosification. The semiconducting film 400' is then bonded with its face facing the weakened zone to the upper surface 1001 of the buried insulating layer 1000. The transfer is then carried out by mechanical separation in the weakened layer, for example by slide insertion or by water jet.

[0115] Figures 7 and 8 respectively represent a device that can be obtained by the method according to the invention when no optional layers are deposited and when only one continuous layer 250 mainly composed of a second insulating material is optionally deposited.

[0116] The proposed method is particularly advantageous for RF applications, in which case the semiconducting film 400' would preferably be InP, GaAs or GaN based.

[0117] The present invention is not limited to the embodiments described above, but extends to all embodiments encompassed by its scope. [Explanation of symbols]

[0118] 1 stack 10 Etching mask 20 printable resin layers 21 Top surface of printable resin layer 22 Bottom surface of printable resin layer 25 Nanoprinting Mold 30 polymer layers 31 First polymer block 32 Second polymer block 100 initial board 101 Top surface of initial board 102 Underside of initial board 100' base plate board 101' Top surface of base plate 102' Bottom surface of base plate 110 Wall 110' converted wall 111' Top of the oxidized wall 120 Trench 120' converted trench 122' Bottom of the Trench 130 First initial insulating layer 131 top surface of first initial insulating layer 132 Lower surface of first initial insulating layer 130' First insulating layer 132' Lower surface of first insulating layer 150 Wall Array 150' Oxidized Wall Array 200 Second insulating layer 201 Upper surface of second insulating layer 250 A continuous layer of a second insulating material as the main component 300 Third insulating layer 301 Top surface of third insulating layer 400 Semiconductive layer 401 Top surface of semiconductive layer 402 Underside of semiconductive layer 400' Semiconductive film 500 injection zones 1000 buried insulating layer 1001 Top surface of buried insulating layer

Claims

1. A method for manufacturing a stack (1), comprising: At least the initial stack, i. a base plate substrate (100') whose main component is a base material having a coefficient of thermal expansion referred to as base coefficient of thermal expansion α, said base plate substrate (100') having an upper surface (101') and a lower surface (102') both extending primarily in plane XY; ii. a first insulating layer (130') on the top surface (101') of the base plate substrate (100'), the first insulating layer (130') being mainly composed of a first insulating material, the first insulating material having a first thermal conductivity λ １ and a first thermal expansion coefficient α １ a first insulating layer (130') comprising an array (150') of trenches (120'); providing at least an initial stack, 10. A method comprising the steps of: Second thermal conductivity λ ２ and a second thermal expansion coefficient α ２ filling the trench (120') with a second insulating material having a second thermal conductivity λ ２ is the first thermal conductivity λ １ Unlike α １ and α ２ is greater than 0.3 ppm / K; forming a semiconducting film (400') above the second insulating layer (200); A method for manufacturing a stack (1), characterized in that it also comprises

2. 0≦2*|(α ２ -α １ ) | / (α ２ +α １ )≦1.8, and 0≦|(α−α １ 2. A method for manufacturing a stack (1) according to claim 1, wherein α≦2.

1.

3. k １ ≦|(λ ２ -λ １ ) / λ １ |, where 0.3≦k １ 3. A method for manufacturing a stack (1) according to claim 1 or 2, wherein

4. The second thermal conductivity λ ２ is the first thermal conductivity λ １ 4. A method for manufacturing a stack (1) according to any one of claims 1 to 3, wherein the thickness of the stack (1) is strictly greater than .

5. The first thermal expansion coefficient α １ and the second thermal expansion coefficient α ２ is greater than α, and the first thermal expansion coefficient α １ and the second thermal expansion coefficient α ２ 5. A method for manufacturing a stack (1) according to any one of claims 1 to 4, wherein the other of

6. The first insulating material has a first Young's modulus E １ and the second insulating material has a second Young's modulus E ２ where E １ ≠E ２ , preferably m １ ≦|(E ２ -E １ ) / E １ |, where 0.03≦m １ So, E １ and E ２ 6. A method for manufacturing a stack (1) according to any one of claims 1 to 5, wherein the modulus of elasticity is greater than 50 GPa.

7. The step of preparing the initial stack comprises the following steps: providing at least one initial substrate (100) whose main component is, and preferably consists of, said base material and which has a top surface (101); forming an initial array (150) of initial trenches (120) in said initial substrate (100) from said top surface (101); converting said base material of at least one portion of said initial substrate (100) into said first insulating material, thereby forming said first insulating layer (130'); A method for manufacturing a stack (1) according to any one of claims 1 to 6, comprising:

8. 8. The method for manufacturing a stack (1) according to claim 7, wherein the step of converting the base material of at least one portion of the initial substrate (100) comprises oxidation of the base material separating the initial trenches (120) from each other.

9. The step of preparing the initial stack comprises the following steps: providing the base plate substrate (100'); forming a first initial insulating layer (130) on the base plate substrate (100'), the first initial insulating layer (130) being primarily composed of the first insulating material; After said step of forming a first initial insulating layer (130), forming said array (150') of trenches (120') in said first initial insulating layer (130), thereby forming said first insulating layer (130'); A method for manufacturing a stack (1) according to any one of claims 1 to 6, comprising:

10. 10. The method for manufacturing a stack (1) according to any one of claims 1 to 9, further comprising the step of forming a continuous layer (250) mainly of the second insulating material directly covering the second insulating layer (200) before the step of forming the semiconducting film.

11. 11. The method for manufacturing a stack (1) according to any one of claims 1 to 10, further comprising the step of forming a third insulating layer (300) below the semiconducting film (400') of a third insulating material having a main component distinct from the second insulating material.

12. The first insulating material remaining between successive trenches forms walls (110'), each wall (110') having a wall width l ｍ ', and the trench (120') has a trench width l ｔ ' and the ratio l ｔ ' / l ｍ ' is between 0.3 and 3, preferably between 0.5 and 1.5, and preferably 0.7≦|(l ｔ '*α ２ +l ｍ '*α １ ) / ((l ｔ '+l ｍ 12. A method for manufacturing a stack (1) according to any one of claims 1 to 11, wherein |α′*α)|≦1.

3.

13. The trench (120') has a depth e ｔ ', and e ｔ 13. A method for manufacturing a stack (1) according to any one of claims 1 to 12, wherein ' is between 5 μm and 20 μm, preferably between 8 μm and 15 μm.

14. The second insulating material is Al ２ O ３ , AlN, SiC, Si ３ N ４ 14. A method for manufacturing a stack (1) according to any one of claims 1 to 13, wherein the stack (1) is made of or is mainly composed of one of the following: BeO, silicon oxynitride and BN.

15. 15. A method for manufacturing a stack (1) according to any one of claims 1 to 14, wherein the first insulating layer consists entirely of the first insulating material.

16. 16. A method for manufacturing a stack (1) according to any one of claims 1 to 15, wherein the first insulating material and the second insulating material are each separate from the base material.

17. A microelectronic device comprising a stack of layers (1), said stack (1) comprising: a base plate substrate (100') having an upper surface (101') and a lower surface (102'), both of which extend primarily in plane XY; a buried insulating layer (1000), a first insulating layer (130') whose main component is a first insulating material and which comprises a plurality of walls (110'), said first insulating material having a first thermal conductivity λ1 and a first thermal expansion coefficient α1, said first insulating layer (130') resting on said top surface (101') of said base plate substrate (100'); a second insulating layer (200) consisting essentially of a second insulating material and extending at least into the trenches (120') separating the walls (110'), the second insulating material having a second thermal conductivity λ2 and a second thermal expansion coefficient α2, the second thermal conductivity λ2 being different from the first thermal conductivity λ1, and α1 and α2 being greater than 0.3 ppm / K; Preferably, a third insulating layer (300) resting on the second insulating layer (200); a buried insulating layer (1000) comprising: Semiconductive film (400') A microelectronic device comprising a stack of layers (1), comprising:

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