Gate driving circuit and display panel

Abstract

This application discloses a gate driving circuit and a display panel, the gate driving circuit including a plurality of stage circuits, each of which includes an input module, a first output module, a second output module, a voltage regulator module, and a first driving control module, the voltage regulator module including a first transistor whose gate receives a clock signal, when the gate driving circuit operates in a low power mode, the clock signal turns on the first transistor to reduce the rate of the clock signal, thereby reducing the power consumption of the gate driving circuit.

Description

[Technical Field]

[0001] The present application relates to the field of display technology, and more particularly to gate driving circuits and display panels. [Background technology]

[0002] In a display panel, a gate driving circuit is usually used to provide corresponding gate driving signals to different transistors, and the gate driving circuit includes multiple stage circuits, and each stage circuit outputs a gate driving signal of a corresponding stage.

[0003] In the prior art, to reduce the power consumption of the stage circuit, the operation modes of the gate circuit include a normal mode and a low-power mode, and in the low-power mode, the rates of multiple input signals to the stage circuit are reduced compared to the normal mode, for example, the rates of the start signal (STV) and clock signal (CK) are reduced. However, when the rate of the clock signal is reduced, the control node that controls the output of the control stage circuit is in a floating state, and the voltage of the control node may leak, causing an abnormality in the display panel. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a gate driving circuit and a display panel, which solves the technical problem in the prior art that, in a low power mode, the rate of the clock signal is reduced, causing the control node that controls the output of the control stage circuit to be in a floating state, resulting in a voltage leak from the control node and causing an abnormality in the display panel. [Means for solving the problem]

[0005] In a first aspect, the present application provides a gate driving circuit, the gate driving circuit including a plurality of cascaded stage circuits, the stage circuit including: an input module for receiving an initial signal or a stage transmission signal output by another stage circuit and controlling a voltage of a second node; a first output module for outputting a first gate driving signal according to a potential of a third node and a potential of a fourth node; a second output module for outputting a second gate driving signal according to the potential of the second node; a voltage regulator module electrically connected to a first power line and a second power line, the voltage regulator module transmitting a voltage of the first power line or a voltage of the second power line to the second node according to a voltage of the fourth node; and a first driving control module for controlling the voltage of the fourth node according to the voltage of the second node, wherein the voltage regulator module includes a first transistor, the gate of which is used to receive a clock signal; an operation mode of the gate driving circuit including a low power mode, wherein when the gate driving circuit is in the low power mode, the clock signal is a first voltage, and the first voltage turns on the first transistor.

[0006] In one embodiment, the first transistor is an N-channel thin film transistor, and the first voltage is at a high level.

[0007] In one embodiment, the first transistor is a double-gate indium gallium zinc oxide thin film transistor, and a first gate of the first transistor and a second gate of the first transistor are both used to receive a clock signal.

[0008] In one embodiment, the voltage regulator module further includes a second transistor, a gate of the second transistor electrically connected to the fourth node, one of a source or a drain of the second transistor electrically connected to the first power supply line, the other of the source or the drain of the second transistor electrically connected to one of a source or a drain of the first transistor, and the other of the source or the drain of the first transistor electrically connected to the second node, wherein the channel types of the first transistor and the second transistor are different.

[0009] In one embodiment, when the gate drive circuit is in a low power mode, the voltage at the fourth node turns on the second transistor to transfer the voltage of the first power rail to one of the source or drain of the first transistor.

[0010] In one embodiment, the voltage regulator module further includes a third transistor, one of a source or a drain of the third transistor electrically connected to the second power supply line, the other of the source or the drain of the third transistor electrically connected to the second node, and a gate of the third transistor electrically connected to the fourth node.

[0011] In one embodiment, when the gate drive circuit is in a low power mode, the voltage at the fourth node turns off the third transistor.

[0012] In one embodiment, the third transistor is a double-gate indium gallium zinc oxide thin film transistor, and a first gate of the third transistor and a second gate of the third transistor are both electrically connected to the fourth node.

[0013] In one embodiment, the stage circuit further includes a reset module that controls the voltage of the second node based on a reset signal.

[0014] In one embodiment, the reset module includes a fourth transistor, one of a source or a drain of the fourth transistor is electrically connected to the first power supply line, the other of the source or the drain of the fourth transistor is electrically connected to the second node, and the gate of the fourth transistor receives the reset signal.

[0015] In one embodiment, in a first frame in which the gate driving circuit operates, the reset signal controls the fourth transistor to turn on before the pulse of the start signal arrives, and transmits the voltage of the first power line to the second node.

[0016] In one embodiment, the first drive control module is electrically connected to the second node and the fourth node, and the first drive control module outputs a voltage to the fourth node that is in phase with the voltage of the second node.

[0017] In one embodiment, the first drive control module includes a fifth transistor and a sixth transistor, one of the source or drain of the fifth transistor is electrically connected to the first power supply line, the other of the source or drain of the fifth transistor is electrically connected to the fourth node, one of the source or drain of the sixth transistor is electrically connected to a third power supply line, the other of the source or drain of the sixth transistor is electrically connected to the fourth node, and the gate of the fifth transistor and the gate of the sixth transistor are electrically connected to the second node.

[0018] Here, the fifth transistor is a P-channel thin film transistor, and the sixth transistor is an N-channel thin film transistor.

[0019] In one embodiment, the sixth transistor is a double-gate transistor, and a first gate of the sixth transistor and a second gate of the sixth transistor are both electrically connected to the second node.

[0020] In one embodiment, when the gate drive circuit is in a low power mode, the sixth transistor is turned on to output the voltage of the third power supply line to the fourth node.

[0021] In one embodiment, the stage circuit further includes a second drive control module, the second drive control module is electrically connected between the second node and the third node, a control terminal of the second drive control module is electrically connected to a drive control line, and the second drive control module is used to control the conduction between the second node and the third node.

[0022] In one embodiment, the second drive control module is used to remove a first pulse where the second node appears in a frame, and to retain a second pulse where the second node appears in the same frame.

[0023] In a second aspect, the present application provides a display panel, the display panel including a pixel circuit and the gate driving circuit according to at least one of the above embodiments, the pixel circuit including a writing transistor for controlling the input of a data signal and a compensation transistor for controlling the input of the data signal to the gate of the driving transistor, an output terminal of the first output module electrically connected to the gate of the writing transistor, and an output terminal of the second output module electrically connected to the gate of the compensation transistor. [Effects of the Invention]

[0024] By electrically connecting the voltage regulator module to the second node, when the gate driver circuit is in a low-power mode, the first transistor can be turned on to maintain the potential of the second node. As a result, when the clock signal has a low rate, the potential of the second node is not reduced due to leakage current, and the potential of the second node can be maintained at a high potential. Therefore, the gate driver circuit provided in this embodiment reduces the clock signal rate, thereby reducing the power consumption of the gate driver circuit and preventing display abnormalities. This solves the problem of the prior art, where a slow clock signal rate causes abnormal output from the stage circuit, resulting in display failure on the display panel. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a structural schematic diagram showing a gate driving circuit of the prior art; [Figure 2] 2 is a timing diagram showing some signals in the gate drive circuit shown in FIG. 1. [Figure 3] 1 is a structural schematic diagram showing a gate driving circuit according to an embodiment of the present application; [Figure 4] 4 is a timing diagram showing some signals in the gate drive circuit shown in FIG. 3. [Figure 5] 2 is a timing diagram showing some signals in the gate drive circuit shown in FIG. 1. [Figure 6] 4 is a timing diagram showing some signals in the gate drive circuit shown in FIG. 3. [Figure 7] FIG. 4 is a timing diagram illustrating the gate drive circuit shown in FIG. [Figure 8] 8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in the first stage of FIG. 7. [Figure 9] 8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in a second stage of FIG. 7. [Figure 10] 8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in a third stage of FIG. 7. [Figure 11]8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in a fourth stage of FIG. 7. [Figure 12] 8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in a fifth stage of FIG. 7. [Figure 13] 8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in a sixth stage of FIG. 7. [Figure 14] 8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in a seventh stage of FIG. 7. [Figure 15] 8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in an eighth stage of FIG. 7. [Figure 16] 8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in a ninth stage of FIG. 7. [Figure 17] 8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in a tenth stage of FIG. 7. [Figure 18] 8 is a schematic diagram showing the gate drive circuit shown in FIG. 3 in the eleventh stage of FIG. 7. [Figure 19] 4 is a structural schematic diagram showing a cascade connection between different stage circuits in the gate drive circuit shown in FIG. 3. FIG. [Figure 20] 1 is a structural schematic diagram showing a display panel according to an embodiment of the present application; [Figure 21] 21 is a structural schematic diagram showing a pixel circuit in the display panel shown in FIG. 20. [Figure 22] 22 is a timing diagram illustrating the pixel circuit shown in FIG. 21. DETAILED DESCRIPTION OF THE INVENTION

[0026] It should be understood that the examples described herein are merely illustrative of the present application and are not intended to be limiting of the present application.

[0027] 1 and 2, Fig. 1 is a structural schematic diagram of a conventional gate driver circuit, which includes at least one of an input module 10, a second driver control module 70, a first driver control module 50, a first output module 20, a second output module 30, and a voltage regulator module 40.

[0028] Here, the first output module 20 outputs a first gate driving signal, and the second output module 30 outputs a second gate driving signal. Here, for a detailed description of the gate driving circuit, please refer to the related description below.

[0029] In order to reduce the power consumption of the stage circuit, in the low power mode, the rates of a number of input signals to the stage circuit are reduced, for example, the rates of the start signal (STV) and clock signals (CK, XCK) are reduced.

[0030] However, the inventors discovered during application that a decrease in the rate of the clock signal would cause abnormalities in the display panel. As shown in Figure 2a, when the clock signal is in a high potential state for a long time, transistor T2 and the first transistor T4 are both off, and node K is in a floating state. Due to the leakage current of transistor T2, the voltage of node K cannot be maintained for a long time. Therefore, node K is leaked by transistor T2, and the voltage of node K continues to decrease. When the voltage of node K decreases to a certain level, Vgs of transistor T3 decreases and eventually reaches a critical value that turns on transistor T3. After transistor T3 is turned on, point P is high, and transistor T14 is turned on, pulling node K to a low level, ultimately turning on transistor T9 and outputting the second gate drive signal, resulting in an output abnormality.

[0031] In other words, in the gate drive circuit shown in FIG. 1, if the rate of the clock signal decreases, the above-mentioned problem may occur. In other words, if the rate of the clock signal decreases, the output of the stage circuit will become abnormal, causing display problems on the display panel.

[0032] Therefore, this embodiment provides a gate driving circuit, and referring to Figures 1 to 22, as shown in Figure 3, this gate driving circuit includes a plurality of stage circuits, and each stage circuit includes at least one of an input module 10, a first output module 20, a second output module 30, a first drive control module 50 and a voltage regulator module 40.

[0033] The input module 10 receives an initial signal or a stage transmission signal output by another stage circuit and controls the voltage of the second node K. The first output module 20 outputs a first gate driving signal based on the potential of the third node Q and the potential of the fourth node P. The second output module 30 outputs a second gate driving signal based on the potential of the second node K. The voltage regulator module 40 is electrically connected to the first power line and the second power line and transmits the voltage of the first power line or the voltage of the second power line to the second node K based on the voltage of the fourth node P. The first drive control module 50 controls the voltage of the fourth node P based on the voltage of the second node K.

[0034] The voltage regulator module 40 includes a first transistor T4, the gate of which is used to receive a clock signal, and the operation mode of the gate driver circuit includes a low-power mode, and when the gate driver circuit is in the low-power mode, the clock signal is a first voltage, which turns on the first transistor.

[0035] As can be seen, the gate drive circuit provided in this embodiment electrically connects the voltage regulator module 40 to the second node K, thereby turning on the first transistor T4 to maintain the potential of the second node K when the gate drive circuit is in a low power mode. As a result, when the clock signal has a low rate, the potential of the second node K does not drop due to leakage current, and the potential of the second node K can be maintained at a high potential. Therefore, the gate drive circuit provided in this embodiment reduces the rate of the clock signal, thereby reducing the power consumption of the gate drive circuit and preventing display abnormalities. This solves the problem of the prior art, in which a slow clock signal rate causes abnormal output from the stage circuit, resulting in display problems on the display panel.

[0036] In one embodiment, the first transistor T4 is an N-channel thin film transistor, the clock signal includes a first clock signal (XCK), the gate of the first transistor T4 is used to receive the first clock signal, and when the gate drive circuit is in a low power mode, the voltage of the first clock signal is a first voltage, the first voltage is at a high level, and the first transistor T4 is turned on.

[0037] Specifically, the first transistor is a double-gate indium gallium zinc oxide thin film transistor, and a first gate of the first transistor and a second gate of the first transistor are both used to receive a first clock signal.

[0038] In addition, when the first clock signal maintains a high potential state at a low rate, the gate driver circuit in this embodiment maintains the potential of the second node K by the first transistor T4 in the voltage regulator module 40, thereby reducing the rate of the clock signal and preventing the gate driver circuit from abnormal output. Therefore, in this application, by maintaining the clock signal at a high potential at a low rate, the power consumption of the gate driver circuit can be reduced.

[0039] In one embodiment, the first transistor T4 is a P-channel thin film transistor, and when the gate drive circuit is in a low power mode, the voltage of the first clock signal is a first voltage, the first voltage is at a low level, and the first transistor T4 is turned on.

[0040] In addition, when the first clock signal maintains a low potential state at a low rate, the gate driver circuit in this embodiment maintains the potential of the second node K by the first transistor T4 in the voltage regulator module 40, thereby reducing the rate of the clock signal and preventing the gate driver circuit from abnormal output. Therefore, in this application, by maintaining the clock signal at a high potential at a low rate, the power consumption of the gate driver circuit can be reduced.

[0041] In one embodiment, the first drive control module 50 is electrically connected to the second node K and the fourth node P, and is used to control the voltage of the fourth node P based on the voltage of the second node K. Here, the input terminal of the first drive control module 50 is electrically connected to the output terminal of the input module 10, and the output terminal of the first drive control module 50 is electrically connected to the fourth node P.

[0042] The voltage regulator module 40 is electrically connected to the second node K, the first power line, and the second power line, and the voltage regulator module 40 is used to maintain the potential of the second node K at the potential of the first power line or the potential of the second power line based on the first clock signal and the potential of the fourth node P.

[0043] In one embodiment, the first driving control module 50 includes a fifth transistor T3 and a sixth transistor T1, one of the source or drain of the fifth transistor T3 is electrically connected to the first power supply line, the other of the source or drain of the fifth transistor T3 is electrically connected to one of the source or drain of the sixth transistor T1 and a fourth node P, the other of the source or drain of the sixth transistor T1 is electrically connected to the third power supply line, and the output terminal of the input module 10 is electrically connected to the gate of the fifth transistor T3, the first gate of the sixth transistor T1, and the second gate of the sixth transistor T1.

[0044] The fifth transistor T3 is a P-channel thin film transistor, and the sixth transistor T1 is a double-gate N-channel thin film transistor, which improves the dynamic performance of the fifth transistor T3 and the sixth transistor T1, thereby improving the dynamic performance of the first drive control module 50.

[0045] The voltage regulator module 40 includes a first transistor T4 and a second transistor T5, one of the source or drain of the first transistor T4 is electrically connected to the output terminal of the input module 10 and the second node K, the gate of the first transistor T4 is electrically connected to the first clock line to receive the first clock signal, the other of the source or drain of the first transistor T4 is electrically connected to one of the source or drain of the second transistor T5, the other of the source or drain of the second transistor T5 is electrically connected to the first power supply line, and the gate of the second transistor T5 is electrically connected to the output terminal of the first drive control module 50 and the fourth node P.

[0046] Furthermore, the voltage regulator module 40 can maintain the second node K at a high potential based on the potential of the fourth node P and the potential of the first clock line, that is, when the fourth node P is at a low potential, the first power line can control the potential of the second node K to the potential of the first power signal PVGH.

[0047] In one embodiment, the voltage regulator module 40 further includes a third transistor T14, one of the source or drain of the third transistor T14 is electrically connected to the second power supply line, the other of the source or drain of the third transistor T14 is electrically connected to the second node K, and the gate of the third transistor T14 is electrically connected to the fourth node P.

[0048] Furthermore, the voltage regulator module 40 can maintain the potential of the second node K at a low potential based on the potential of the fourth node P, that is, when the fourth node P is at a high potential, the second power line can control the potential of the second node K to the potential of the second power signal VGL.

[0049] Here, the third transistor T14 is an N-channel thin film transistor and a double-gate thin film transistor, which can not only improve the controllability of the current passing through it but also reduce the drift amplitude of the threshold voltage.

[0050] In one embodiment, the sixth transistor T1, the first transistor T4 and the third transistor T14 may all be indium gallium zinc oxide thin film transistors.

[0051] In one embodiment, the gate drive circuit further includes a second drive control module 70. The second drive control module 70 is electrically connected between the second node K and the third node Q. The input terminal of the second drive control module 70 is electrically connected to the output terminal of the input module 10, and the control terminal of the second drive control module 70 is electrically connected to the drive control line.

[0052] The input terminal of the second output module 30 is electrically connected to the output terminal of the input module 10, and the output terminal of the second output module 30 is electrically connected to the positive pulse gate drive line of the Nth stage, and the number of positive pulses output by the positive pulse gate drive line of the Nth stage in one frame is greater than the number of negative pulses output by the negative pulse gate drive line of the Nth stage in one frame.

[0053] The positive pulse gate drive line of the Nth stage, i.e., the second gate drive line, is used to transmit the positive pulse gate drive signal Nout[N] of the Nth stage, i.e., the second gate drive signal, and the second gate drive signal can be used as the stage transmission signal of the stage circuit. The negative pulse gate drive line of the Nth stage, i.e., the first gate drive line, is used to transmit the negative pulse gate drive signal Pout[N] of the Nth stage, i.e., the first gate drive signal.

[0054] In addition, the gate driving circuit provided in this embodiment can not only output a second gate driving signal with a larger number of pulses through the input module 10 and the second output module 30, but also select the second gate driving signal as a stage transmission signal between different stage circuits, and can output a first gate driving signal with a smaller number of pulses through the input module 10, the second driving control module 70, the first driving control module 50, and the first output module 20, thereby meeting the pulse duration, number, etc. requirements of the gate driving signal in one frame of the corresponding pixel circuit, and driving the pixel circuit to achieve image quality display.

[0055] In one embodiment, the second drive control module 70 includes a transistor T11, one of the source and drain of which is electrically connected to the output terminal of the input module 10, the other of which is electrically connected to the control terminal of the first output module 20, and the gate of the transistor T11 is electrically connected to a drive control line. Here, the transistor T11 is a P-channel thin film transistor. The drive control line is used to transmit a drive control signal RST.

[0056] The output terminal of the input module 10 is the second node K. One of the control terminals of the first output module 20 is the third node Q. The other of the source or drain of the transistor T11 is the node W. The second drive control module 70 is used to reduce the double pulse appearing at the second node K in one frame to a single pulse appearing at the third node Q in one frame. Specifically, it removes the first pulse appearing at the second node K in one frame and retains the second pulse appearing in the same frame.

[0057] In addition, this embodiment is advantageous in ensuring the output stability of the negative pulse gate drive signal Pout[N] of the Nth stage, and avoids the coupling pull-down phenomenon that occurs before the negative pulse arrives.

[0058] In one embodiment, the second drive control module 70 further includes a first capacitor C2, one end of which is electrically connected to the gate of the transistor T11, and the other end of which is electrically connected to the other of the source or drain of the transistor T11.

[0059] In addition, this embodiment is advantageous in further improving the output stability of the negative pulse gate driving signal Pout[N] of the Nth stage.

[0060] The output terminal of the input module 10 is the second node K. The control terminal of the first output module 20 is the third node Q. The other of the source or drain of the transistor T11 is the node W. The second drive control module 70 is used to reduce the double pulse appearing at the second node K in one frame to a single pulse appearing at the third node Q in one frame. Specifically, the second node K removes the first pulse appearing in one frame and retains the second pulse appearing in the same frame.

[0061] In one embodiment, the first output module 20 includes a transistor T6 and a second capacitor C1, the gate of the transistor T6 is electrically connected to one of the source or drain of the transistor T11, the source or drain of the transistor T6 is electrically connected to the second clock line, the other of the source or drain of the transistor T6 is electrically connected to the negative pulse gate drive line of the N stage, one end of the second capacitor C1 is electrically connected to the gate of the transistor T6, and the other end of the second capacitor C1 is electrically connected to the other of the source or drain of the transistor T6, where the capacitance ratio between the first capacitor C2 and the second capacitor C1 is greater than or equal to 0.5.

[0062] In addition, this embodiment is advantageous in that the capacitance ratio between the first capacitor C2 and the second capacitor C1 is set to further ensure the output stability of the negative pulse gate driving signal Pout[N] of the Nth stage, and avoid the coupling pull-down phenomenon that occurs before the arrival of the negative pulse.

[0063] Specifically, the capacitance of the first capacitor C2 may be 50 fF or more, and the capacitance of the second capacitor C1 may be 100 fF or more. In some embodiments, the transistor T6 may be a P-channel thin film transistor.

[0064] In one embodiment, the first output module 20 includes a transistor T7, one of the source or drain of the transistor T7 is electrically connected to the first power supply line, the other of the source or drain of the transistor T7 is electrically connected to the negative pulse gate drive line of the Nth stage, and the gate of the transistor T7 is electrically connected to the output terminal of the first drive control module 50, i.e., the fourth node P.

[0065] In addition, the transistor T7 may be a P-channel thin film transistor. The first output module 20 and the second output module 20 cooperate to modulate the desired negative pulse gate driving signal Pout[N] of the Nth stage.

[0066] In one embodiment, the input module 10 includes a transistor T2, a transistor T13, and a transistor T12. One of the source and drain of the transistor T13 is electrically connected to the third power supply line, the other of the source and drain of the transistor T13 is electrically connected to the input terminal of the input module 10, the first gate of the transistor T13 is electrically connected to the start control line or the positive pulse gate driving line of the NY stage, and the first gate of the transistor T13 is electrically connected to the second gate of the transistor T13, and the transistor T13 is an N-channel thin film transistor. One of the source or drain of transistor T12 is electrically connected to the first power supply line, the other of the source or drain of transistor T12 is electrically connected to the other of the source or drain of transistor T13, the gate of transistor T12 is electrically connected to the first gate of transistor T13, transistor T12 is a P-channel thin film transistor, one of the source or drain of transistor T2 is electrically connected to the output terminals of transistors T13 and T12, the other of the source or drain of transistor T2 is electrically connected to the input terminal of second drive control module 70, and the gate of transistor T2 is electrically connected to the first clock line. In some embodiments, transistor T2 may be a P-channel thin film transistor.

[0067] In addition, the input module 10 in this embodiment not only has an objective inversion function, that is, the input signal and the output signal are inverted in potential at the same time, so that the positive pulse gate driving signal Nout[N] of the Nth stage functions as a stage transmission signal between the stage circuits; otherwise, the stage transmission between the circuits of each stage cannot be realized, and the gate driving circuit cannot normally supply the corresponding gate driving signal.

[0068] In one embodiment, the second output module 30 includes a P-channel transistor T9 and an N-channel transistor T10, where a first electrode of the transistor T9 is electrically connected to the fourth power supply line and a gate of the transistor T9 is electrically connected to a second node K. The first electrode of the transistor T10 is electrically connected to a second electrode of the transistor T9 to output a second gate drive signal, and the gate of the transistor T10 is electrically connected to the gate of the transistor T9.

[0069] In one embodiment, the gate of the transistor T10 includes a first gate and a second gate, and the second node K is electrically connected to the first gate of the transistor T10 and the second gate of the transistor T10.

[0070] In addition, the transistor T10 in this embodiment may be a double-gate thin film transistor, which can not only increase the controllability of the current passing through the body but also reduce the threshold voltage drift amplitude, where the transistor T10 is an indium gallium zinc oxide thin film transistor.

[0071] Here, the first power line is used to transmit a first power signal PVGH, which can control whether an N-channel thin film transistor is turned on or whether a P-channel thin film transistor is turned off. The second power line is used to transmit a second power signal NVGL, which can control whether a P-channel thin film transistor is turned on or whether an N-channel thin film transistor is turned off. The third power line is used to transmit the third power signal PVGL, and the fourth power line is used to transmit the fourth power signal NVGH.

[0072] In one embodiment, the third power signal PVGL is less than the second power signal NVGL so that when the third transistor T14 is in the off state, it is more completely turned off.

[0073] In one embodiment, the second output module 30 outputs a second gate driving signal according to the potential of the second node K, and the number of pulses in one frame of the second gate driving signal is greater than the number of pulses in one frame of the first gate driving signal.

[0074] The transistor T9 is a P-channel thin film transistor, and the transistor T10 is a double-gate N-channel thin film transistor, which improves the dynamic performance of the transistors T9 and T10, thereby improving the dynamic performance of the second output module 30.

[0075] The positive pulse gate drive line of the Nth stage is used to transmit the positive pulse gate drive signal Nout[N] of the Nth stage. The negative pulse gate drive line of the Nth stage is used to transmit the negative pulse gate drive signal Pout[N] of the Nth stage. The first clock line is used to transmit the first clock signal XCK. The second clock line is used to transmit the second clock signal CK. The start control line is used to transmit the start control signal STV. The positive pulse gate drive line of the NY stage is used to transmit the positive pulse gate drive signal Nout[NY] of the NY stage. The positive pulse gate drive line of the NX stage is used to transmit the positive pulse gate drive signal Nout[NX] of the NX stage. The drive control line is used to transmit the drive control signal RST.

[0076] In one embodiment, the second driving control module 70 further includes a leakage prevention transistor T8, one of the source or drain of the leakage prevention transistor T8 is electrically connected to the other of the source or drain of the transistor T11, the other of the source or drain of the leakage prevention transistor T8 is electrically connected to the control terminal of the first output module 20, and the gate of the leakage prevention transistor T8 is electrically connected to the leakage prevention signal line to receive the leakage prevention signal.

[0077] Here, the leakage prevention signal line may be the positive pulse gate drive line N[nX], specifically, the positive pulse gate drive line of the N-2th stage, and the leakage prevention signal is the positive pulse gate drive signal N[n-2] of the N-2th stage.

[0078] As shown in FIG. 5c, when the first clock signal XCK of the transistor T2 is not activated, the second node K is in a floating state, and when the second node K is randomly in a low level state, the second output module 30 outputs a high level, which causes a series of stage transmission reactions and results in output abnormalities of the first frame in all rows.

[0079] To solve the above problem, in one embodiment, the Nth stage circuit further includes a reset module 60, which controls the voltage of the second node according to a reset signal control. The reset module 60 includes a fourth transistor T15, one of the source or drain of the fourth transistor T15 is electrically connected to the first power supply line, the other of the source or drain of the fourth transistor T15 is electrically connected to the second node, and the gate of the fourth transistor T15 receives the reset signal control.

[0080] Here, the reset signal control is turned on only once every time the gate driver circuit is energized, i.e., turns on the fourth transistor T15 and raises the potential of the second node K to a high potential, and at this time, the start signal STV, the first clock signal XCK, the second clock signal CK, the leakage prevention signal N[n-2], and the drive control signal RST have not yet started transmitting.

[0081] As can be seen, the reset module 60 ensures that the second node K is at a high level whenever the gate driver circuit is energized, so that the above-mentioned abnormal output situation does not occur, as shown in FIG. 6d.

[0082] The operation process of the above stage circuit in one frame may include the following steps, as shown in FIG.

[0083] In the first stage S1, as shown in FIGS. 7 and 8, the start control signal STV, the drive control signal RST, the first clock signal XCK, and the leakage prevention signal N[n-2] are all at low potential, the second clock signal CK is at high potential, the first node O, the second node K, and the third node Q are all at high potential, the fourth node P is at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential.

[0084] In the second stage S2, as shown in FIGS. 7 and 9, the start control signal STV, the second clock signal CK, and the leakage prevention signal N[n-2] are all at low potential, the drive control signal RST and the first clock signal XCK are at high potential, the first node O, the second node K, and the third node Q are all at high potential, the fourth node P is at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential.

[0085] In the third stage S3, as shown in FIGS. 7 and 10, the start control signal STV, the first clock signal XCK, and the leakage prevention signal N[n-2] are all at low potential, the drive control signal RST and the second clock signal CK are all at high potential, the first node O, the second node K, and the third node Q are all at high potential, the fourth node P is at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential.

[0086] In the fourth stage S4, as shown in FIGS. 7 and 11, the drive control signal RST and the start control signal STV are at low potentials, the first clock signal XCK, the second clock signal CK, and the leakage prevention signal N[n-2] are all at high potentials, the first node O, the second node K, and the third node Q are all at high potentials, the fourth node P is at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential.

[0087] In the fifth stage S5, as shown in FIGS. 7 and 12, the drive control signal RST and the first clock signal XCK are all at low potential, the start control signal STV, the second clock signal CK and the leakage prevention signal N[n-2] are all at high potential, the third node Q and the fourth node P are all at high potential, the first node O and the second node K are all at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at high potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential.

[0088] In the sixth stage S6, as shown in FIGS. 7 and 13, the start control signal STV, the first clock signal XCK, the second clock signal CK, and the drive control signal RST are all at high potential, the leakage prevention signal N[n-2] is at low potential, the third node Q and the fourth node P are all at high potential, the first node O and the second node K are at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at high potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential.

[0089] In the seventh stage S7, as shown in FIGS. 7 and 14, the start control signal STV, the first clock signal XCK, and the leakage prevention signal N[n-2] are all at low potential, the second clock signal CK and the drive control signal RST are all at high potential, the fourth node P is at low potential, the first node O, the second node K, and the third node Q are at high potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential.

[0090] In the eighth step S8, as shown in FIGS. 7 and 15, the start control signal STV, the first clock signal XCK, and the leakage prevention signal N[n-2] are all at high potential, the drive control signal RST is at low potential, the first node O and the fourth node P are at low potential, the third node Q and the second node K are all at high potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential.

[0091] In the ninth stage S9, as shown in FIGS. 7 and 16, the drive control signal RST and the first clock signal XCK are all at low potential, the start control signal STV, the second clock signal CK and the leakage prevention signal N[n-2] are all at high potential, the first node O and the second node K are at low potential, the fourth node P and the third node Q are all at high potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at high potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential.

[0092] In the tenth step S10, as shown in FIGS. 7 and 17, the start control signal STV, the drive control signal RST, the second clock signal CK, and the leakage prevention signal N[n-2] are all at low potential, the first clock signal XCK is at high potential, the first node O and the fourth node P are at high potential, the third node Q and the second node K are at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at high potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at low potential.

[0093] In the eleventh step S11, as shown in FIGS. 7 and 18, the start control signal STV, the drive control signal RST, the first clock signal XCK, and the leakage prevention signal N[n-2] are all at low potential, the second clock signal CK is at high potential, the fourth node P is at low potential, the first node O, the third node Q, and the second node K are at high potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential.

[0094] It should be noted that the "X" in FIGS. 8 to 18 indicates that the transistor covered by it is in the OFF state, and that the transistor not covered by the "X" is in the ON state.

[0095] 7, the positive pulse gate driving signal Nout[N] of the Nth stage has a first positive pulse and a second positive pulse sequentially in one frame, and the negative pulse gate driving signal Pout[N] of the Nth stage has a first negative pulse in one frame.

[0096] In one frame, the duration of the second positive pulse is longer than the duration of the first negative pulse, and the duration of the first negative pulse is within the duration of the second positive pulse.

[0097] 19 is a structural schematic diagram showing the cascade connection between different stage circuits in the gate driving circuit shown in FIG. 3, where, from top to bottom, there are a first stage circuit 101, a second stage circuit 102, a third stage circuit 103, a fourth stage circuit 104, a fifth stage circuit 105, a sixth stage circuit 106, etc. A first clock line is electrically connected to each stage circuit, and a second clock line is also electrically connected to each stage circuit.

[0098] Here, the first stage circuit 101 outputs a first stage negative pulse gate drive signal Pout[1] and a first stage positive pulse gate drive signal Nout[1] corresponding to the first stage negative pulse gate drive line and the first stage positive pulse gate drive line, respectively.

[0099] The second stage circuit 102 outputs a second stage negative pulse gate drive signal Pout[2] and a second stage positive pulse gate drive signal Nout[2] via a second stage negative pulse gate drive line and a second stage positive pulse gate drive line, respectively.

[0100] The third stage circuit 103 outputs a third stage negative pulse gate drive signal Pout[3] and a third stage positive pulse gate drive signal Nout[3] via a third stage negative pulse gate drive line and a third stage positive pulse gate drive line, respectively.

[0101] The fourth stage circuit 104 outputs a fourth stage negative pulse gate drive signal Pout[4] and a fourth stage positive pulse gate drive signal Nout[4] via the fourth stage negative pulse gate drive line and the fourth stage positive pulse gate drive line, respectively.

[0102] The fifth stage circuit 105 outputs a fifth stage negative pulse gate drive signal Pout[5] and a fifth stage positive pulse gate drive signal Nout[5] via the fifth stage negative pulse gate drive line and the fifth stage positive pulse gate drive line, respectively.

[0103] The sixth stage circuit 106 outputs a sixth stage negative pulse gate drive signal Pout[6] and a sixth stage positive pulse gate drive signal Nout[6] through a sixth stage negative pulse gate drive line and a sixth stage positive pulse gate drive line, respectively. The other stage circuits can be subsequently inferred.

[0104] The input terminal (IN) of the input module 10 in the first stage circuit 101 is electrically connected to the start control line and receives the start control signal STV. In other stage circuits, the input terminals (IN) of the input module 10 all receive the positive pulse gate drive signal of the previous stage. For example, in the second stage circuit 102, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal Nout[1] of the first stage; in the third stage circuit 103, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal Nout[2] of the second stage; in the fourth stage circuit 104, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal Nout[3] of the third stage; in the fifth stage circuit 105, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal Nout[4] of the fourth stage; and in the sixth stage circuit 106, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal Nout[5] of the fifth stage. The rest can be further explained by analogy. As can be appreciated, multiple stage circuits can be cascaded at other intervals, and this application will not discuss this further.

[0105] In the fifth stage circuit 105, the control terminal of the second driving control module 70 (transistor T8) receives the third stage positive pulse gate driving signal Nout[3], in the sixth stage circuit 106, the control terminal of the second driving control module 70 receives the fourth stage positive pulse gate driving signal Nout[4], and so on. Wherein, X can be 3, 4, 5, 6, 7, etc., and here, X=2 is taken as an example.

[0106] Note that, since the output terminals of some stage circuits are connected to dummy pixels or suspended, it is not the pixel circuits in the Nth row that are connected to each output terminal of the Nth stage circuit, but rather it is necessary to determine which row the connected pixel circuits are in based on the number of stage circuits connected to dummy pixels or the number of suspended stage circuits.

[0107] The upper diagram in Figure 20 is a structural schematic diagram showing a display panel of the prior art, in which the gate drive circuits used to supply the light-emitting control signal EM, the gate drive signal Nscan1, and the gate drive signal Pscan are arranged on the left side (non-display area or bezel area) of the display area (AA area), and the gate drive circuits used to supply the gate drive signal Pscan and the gate drive signal Nscan2 are arranged on the right side (non-display area or bezel area) of the display area (AA area).

[0108] Here, each gate drive signal Pscan drives one row of pixel circuits. The gate drive signals Nscan1 and Nscan2 operate in the same manner as the gate drive signal Pscan, but each gate drive signal Nscan1 / Nscan2 must drive two rows of pixel circuits. In actual operation, to achieve a narrower bezel, the gate drive circuit used to output the gate drive signal Nscan1 and the gate drive circuit used to output the gate drive signal Nscan2 are both configured for single-sided driving, which results in a deterioration in the driving capabilities of the two gate drive circuits and an increase in power consumption.

[0109] Therefore, in this embodiment, the gate drive circuit shown in Figure 3 is arranged to be driven on both sides as shown in the bottom diagram of Figure 20, that is, the gate drive circuits shown in Figure 3 are arranged on both sides of the AA region, and the corresponding gate drive signals are input to both ends of each gate drive line simultaneously, which not only improves the driving capabilities of the Nth stage negative pulse gate drive signal Pout[N] and positive pulse gate drive signal Nout, but also reduces power consumption and the bezel space required, which is advantageous for developing a narrower bezel design.

[0110] Here, the positive pulse gate driving signal Nout includes a positive pulse gate driving signal Nout[N] of the Nth stage and a positive pulse gate driving signal Nout[NL] of the NLth stage, where L may be an integer equal to or greater than 1, such as 2, 3, 4, 5, 6, etc.

[0111] In one embodiment, this embodiment provides a display panel, which includes the gate driving circuit and pixel circuits according to at least one of the above embodiments, and a row of pixel circuits is electrically connected to an N stage positive pulse gate driving line and an N stage negative pulse gate driving line.

[0112] As can be seen, the display panel provided by this embodiment includes the gate driving circuit of at least one of the above embodiments, and similarly, by electrically connecting the voltage regulator module 40 to the second node K, the voltage regulator module 40 can control the potential of the fourth node P based on the potential of the second node K to maintain the potential of the second node K, so that when the clock signal has a low rate, the potential of the second node K will not drop due to leakage current and can be maintained. Therefore, the gate driving circuit provided by this embodiment reduces the rate of the clock signal, thereby reducing the power consumption of the gate driving circuit and preventing display abnormalities, and thus solving the problem of the prior art that when the clock signal rate is low, the output of the stage circuit becomes abnormal, causing display problems on the display panel.

[0113] 21 is a structural schematic diagram showing a pixel circuit in the display panel shown in FIG. 20. As can be seen, the gate driving circuit shown in FIG. 3 can supply a positive pulse gate driving signal Nout[N] of the Nth stage, a positive pulse gate driving signal Nout[NL] of the NLth stage, and a negative pulse gate driving signal Pout[N] of the Nth stage corresponding to the pixel circuit shown in FIG.

[0114] The pixel circuit shown in FIG. 21 may include at least one of a write transistor T2P, a drive transistor T1P, a first light-emitting control transistor T5P, a second light-emitting control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light-emitting element D1, a storage capacitor Cst, and a bootstrap capacitor Cboost.

[0115] The first power supply line is electrically connected to the first pole of the first light-emitting control transistor T5P and one end of the storage capacitor Cst. The second pole of the first light-emitting control transistor T5P is electrically connected to the first pole of the driving transistor T1P and the first pole of the writing transistor T2P. The second pole of the driving transistor T1P is electrically connected to the first pole of the compensation transistor T3P and the first pole of the second light-emitting control transistor T6P. The second pole of the second light-emitting control transistor T6P is electrically connected to the first pole of the second initialization transistor T7P and the anode of the light-emitting element D1, and the cathode of the light-emitting element D1 is electrically connected to the second power supply line. The light-emitting control line is electrically connected to the gate of the first light-emitting control transistor T5P and the gate of the second light-emitting control transistor T6P. The second pole of the writing transistor T2P is electrically connected to the data line, and the gate of the writing transistor T2P is electrically connected to the negative pulse gate driving line (first gate driving line) of the Nth stage and one end of the bootstrap capacitor Cboost. The second electrode of the second initialization transistor T7P is electrically connected to the second initialization line, and the gate of the second initialization transistor T7P is electrically connected to the third gate drive line. The second electrode of the compensation transistor T3P is electrically connected to the gate of the drive transistor T1P, and the gate of the compensation transistor T3P is electrically connected to the positive pulse gate drive line (second gate drive line) of the Nth stage. The gate of the drive transistor T1P is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor Cboost, and the first electrode of the first initialization transistor T4P. The second electrode of the first initialization transistor T4P is electrically connected to the first initialization line, and the gate of the first initialization transistor T4P is electrically connected to the positive pulse gate drive line (second gate drive line) of the N-th stage. The first electrode of the third initialization transistor T8P is electrically connected to the first electrode of the driving transistor T1P, the second electrode of the third initialization transistor T8P is electrically connected to the third initialization line, and the gate of the third initialization transistor T8P and the gate of the second initialization transistor T7P share the third gate driving line.

[0116] The second initialization line may be replaced with the first initialization line, which reduces the number of wires required for the pixel circuit by one, and is advantageous for increasing the density of pixel circuits in the display panel.

[0117] Here, the first electrode may be either the source or the drain, and the second electrode may be the other of the source or the drain. For example, if the first electrode is the source, the second electrode is the drain. Or, if the first electrode is the drain, the second electrode is the source.

[0118] Here, the first power supply line is used to transmit a positive power supply signal VDD, and the second power supply line is used to transmit a negative power supply signal VSS, and the potential of the positive power supply signal VDD is higher than the potential of the negative power supply signal VSS. The data line is used to transmit a data signal Data. The light-emitting control line is used to transmit a light-emitting control signal EM. The first initialization line is used to transmit a first initialization signal Vi1. The second initialization line is used to transmit a second initialization signal Vi2. The third initialization line is used to transmit a third initialization signal Vi3. The first gate drive line is used to transmit a negative pulse gate drive signal Pout[N] of the Nth stage. The positive pulse gate drive line (second gate drive line) of the Nth stage is used to transmit a positive pulse gate drive signal Nout[N] of the Nth stage. The positive pulse gate drive line (second gate drive line) of the NLth stage is used to transmit a positive pulse gate drive signal Nout[NL] of the NLth stage. The third gate driving line is used to transmit the gate driving signal Pscan2.

[0119] As shown in FIG. 22, the operation timing of one frame of the pixel circuit shown in FIG. 21 is such that, under common driving of the negative pulse gate drive signal Pout[N] of the Nth stage, the gate drive signal Pscan2, the positive pulse gate drive signal Nout[NL] of the NLth stage, the positive pulse gate drive signal Nout[N] of the Nth stage, and the light emission control signal EM, the pixel circuit shown in FIG. 21 can perform normal display.

[0120] Here, the negative pulse gate drive signal Pout[N] of the Nth stage, the positive pulse gate drive signal Nout[NL] of the NLth stage, and the positive pulse gate drive signal Nout[N] of the Nth stage can be supplied by the gate drive circuit shown in FIG. 3.

[0121] Those skilled in the art will appreciate that there are variations in the specific embodiments and scope of application in light of the concept of the present application, but in summary, it should be understood that the description in this specification is not intended to limit the present application.

Claims

1. a plurality of cascaded stage circuits, the stage circuits comprising: an input module for receiving an initial signal or a stage transmission signal output by another stage circuit to control the voltage of the second node; a first output module that outputs a first gate driving signal based on the potential of the third node and the potential of the fourth node; a second output module that outputs a second gate driving signal based on the potential of the second node; a voltage regulator module electrically connected to the first power supply line and the second power supply line, and configured to transmit a voltage of the first power supply line or a voltage of the second power supply line to the second node based on a voltage of the fourth node; a first drive control module that controls the voltage of the fourth node based on the voltage of the second node; wherein the voltage regulator module includes a first transistor, a gate of the first transistor is used to receive a clock signal, an operation mode of the gate drive circuit includes a low power mode, when the gate drive circuit is in the low power mode, the clock signal is a first voltage, and the first voltage turns on the first transistor; Gate drive circuit.

2. the first transistor is an N-channel thin film transistor, and the first voltage is at a high level; 2. The gate drive circuit of claim 1.

3. the first transistor is a double-gate indium gallium zinc oxide thin film transistor, and a first gate of the first transistor and a second gate of the first transistor are both used to receive a clock signal; 3. The gate drive circuit according to claim 2.

4. the voltage regulator module further includes a second transistor, a gate of the second transistor electrically connected to the fourth node, one of a source or a drain of the second transistor electrically connected to the first power supply line, the other of the source or the drain of the second transistor electrically connected to one of the source or the drain of the first transistor, and the other of the source or the drain of the first transistor electrically connected to the second node; wherein the first transistor and the second transistor have different channel types; 3. The gate drive circuit according to claim 2.

5. When the gate drive circuit is in a low power mode, the voltage at the fourth node turns on the second transistor, transmitting the voltage at the first power supply line to one of the source or drain of the first transistor.

5. The gate drive circuit according to claim 4.

6. the voltage regulator module further includes a third transistor, one of a source or a drain of the third transistor electrically connected to the second power supply line, the other of the source or the drain of the third transistor electrically connected to the second node, and a gate of the third transistor electrically connected to the fourth node; 2. The gate drive circuit of claim 1.

7. When the gate drive circuit is in a low power mode, the voltage at the fourth node turns off the third transistor.

7. The gate drive circuit of claim 6.

8. the third transistor is a double-gate indium gallium zinc oxide thin film transistor, and a first gate of the third transistor and a second gate of the third transistor are both electrically connected to the fourth node; 8. The gate drive circuit of claim 7.

9. The stage circuit further includes a reset module that controls the voltage of the second node based on a reset signal; 2. The gate drive circuit of claim 1.

10. the reset module includes a fourth transistor, one of a source or a drain of the fourth transistor is electrically connected to the first power line, the other of the source or the drain of the fourth transistor is electrically connected to the second node, and a gate of the fourth transistor receives the reset signal; 10. The gate drive circuit of claim 9.

11. In a first frame in which the gate driving circuit operates, the reset signal controls the fourth transistor to be turned on before a pulse of a start signal arrives, and transmits the voltage of the first power supply line to the second node.

11. The gate drive circuit of claim 10.

12. the first drive control module is electrically connected to the second node and the fourth node, and the first drive control module outputs a voltage to the fourth node that is in phase with the voltage of the second node; 3. The gate drive circuit according to claim 2.

13. the first drive control module includes a fifth transistor and a sixth transistor, one of a source or a drain of the fifth transistor is electrically connected to the first power supply line, the other of the source or the drain of the fifth transistor is electrically connected to the fourth node, one of a source or a drain of the sixth transistor is electrically connected to a third power supply line, the other of the source or the drain of the sixth transistor is electrically connected to the fourth node, and a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the second node; wherein the fifth transistor is a P-channel thin film transistor, and the sixth transistor is an N-channel thin film transistor.

13. The gate drive circuit of claim 12.

14. the sixth transistor is a double-gate transistor, and a first gate of the sixth transistor and a second gate of the sixth transistor are both electrically connected to the second node; 14. The gate drive circuit of claim 13.

15. When the gate drive circuit is in a low power mode, the sixth transistor is turned on to output the voltage of the third power supply line to the fourth node.

15. The gate drive circuit of claim 14.

16. the stage circuit further includes a second drive control module, the second drive control module is electrically connected to the second node and the third node respectively, a control terminal of the second drive control module is electrically connected to a drive control line, and the second drive control module is used to control conduction between the second node and the third node; The gate drive circuit according to any one of claims 1 to 14.

17. The second drive control module is used to remove a first pulse of the second node appearing in one frame and to retain a second pulse of the second node appearing in the same frame.

17. The gate drive circuit of claim 16.

18. the second driving control module includes a transistor, one of the source or drain of the transistor is electrically connected to the output terminal of the input module, the other of the source or drain of the transistor is electrically connected to the control terminal of the first output module, and the gate of the transistor is electrically connected to the driving control line, where the transistor is a P-channel thin film transistor, and the driving control line is used to transmit a driving control signal; 17. The gate drive circuit of claim 16.

19. the second drive control module further includes a first capacitor, one end of the first capacitor being electrically connected to the gate of the transistor, and the other end of the first capacitor being electrically connected to the other of the source and drain of the transistor; 18. The gate drive circuit of claim 17.

20. a pixel circuit including a write transistor that controls input of a data signal, and a compensation transistor that controls the data signal and inputs it to the gate of a drive transistor; and a gate drive circuit according to any one of claims 1 to 19, an output terminal of the first output module electrically connected to the gate of the write transistor, and an output terminal of the second output module electrically connected to the gate of the compensation transistor; Display panel.

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