Flexible circuit board, COF module, and electronic device including the same

Abstract

A flexible circuit board according to an embodiment includes a substrate having a first surface and a second surface opposite the first surface, a first circuit pattern disposed on the first surface, a second circuit pattern disposed on the first surface and the second surface, and a third circuit pattern disposed on the first surface and the second surface, wherein the second circuit pattern includes a first via and a second wiring portion, and the third circuit pattern includes a second via and a third wiring portion, wherein the first via and the second via include a via land and a via hole formed in the via land, and at least one of the first via and the second via defines a first distance between the via lands, a second distance between the via land and the second wiring portion or the third wiring portion adjacent to the via land, and a third distance between a side surface of the via land and the via hole, and at least one of the first distance, the second distance, and the third distance is greater than the width of the wiring portion.

Description

[Technical Field]

[0001] The embodiments relate to flexible circuit boards, COF modules, and electronic devices including the same. [Background technology]

[0002] Recently, various electronic products have become thinner, smaller, and lighter, and accordingly, various researches are being conducted to mount semiconductor chips at high density in a narrow area of ​​the electronic products.

[0003] COF (Chip On Film) includes a flexible substrate. Therefore, the COF can be applied to flexible displays. For example, the COF can be applied to various wearable electronic devices. Furthermore, the COF method can realize a fine pitch. This allows for a high-resolution display with an increased number of pixels.

[0004] The COF is a method of mounting a semiconductor chip on a thin film-shaped flexible circuit board. For example, the semiconductor chip can be an integrated circuit (IC) chip or a large scale integrated circuit (LSI) chip.

[0005] The chip may be connected to an external circuit board and a display panel via a circuit pattern. For example, pads may be disposed on one end and the other end of the circuit pattern. One of the pads may be electrically connected to a terminal of the chip. The other pad may be connected to a terminal of the circuit board and a terminal of the display panel. This electrically connects the chip, the circuit board, and the display panel via the COF. This allows signals to be transmitted to the display panel via the circuit pattern.

[0006] The flexible circuit board includes a plurality of circuit patterns that connect the chip, the circuit board, and the display panel, and signals can be transmitted to the chip, the circuit board, and the display panel via the circuit patterns.

[0007] The circuit pattern may be disposed on one or both sides of the substrate. When the circuit pattern is disposed on both sides of the substrate, the circuit patterns on both sides are connected through vias.

[0008] If the vias are misaligned, the circuit patterns on both sides of the substrate may short out, which may reduce the reliability of the flexible circuit board.

[0009] Therefore, there is a need for a flexible circuit board, a COF module, and an electronic device including the same, each having a new structure that can solve the above problems. Summary of the Invention [Problem to be solved by the invention]

[0010] Embodiments provide flexible circuit boards, COF modules, and electronic devices containing the same with improved reliability. [Means for solving the problem]

[0011] A flexible circuit board according to an embodiment includes a substrate including a first surface and a second surface opposite to the first surface, a first circuit pattern disposed on the first surface, a second circuit pattern disposed on the first surface and the second surface, and a third circuit pattern disposed on the first surface and the second surface, wherein the second circuit pattern includes a first via and a second wiring portion, and the third circuit pattern includes a second via and a third wiring portion, wherein the first via and the second via include a via land and a via hole formed in the via land, and at least one of the first via and the second via defines a first distance between the via lands, a second distance between the via land and the second wiring portion or the third wiring portion adjacent to the via land, and a third distance between a side surface of the via land and the via hole, and at least one of the first distance, the second distance, and the third distance is greater than the width of the wiring portion. [Effects of the Invention]

[0012] A flexible circuit board according to an embodiment includes vias. Circuit patterns on a first surface and a second surface are connected by the vias. The vias are disposed on the first surface and the second surface, respectively. The vias include a plurality of via lands and via holes within the via lands.

[0013] The via land is spaced apart at a set interval. The via land is spaced apart from a wiring portion of the circuit pattern at a set interval. The via land and the via hole are spaced apart at a set interval.

[0014] This prevents the via holes inside the via lands from shifting, and therefore prevents the alignment of the vias on the first and second surfaces from shifting.

[0015] This improves the electrical connection characteristics of the flexible circuit board.

[0016] The via land includes a plurality of corners. At least one corner includes a curved surface. The intervals between the via lands where the curved surface is formed are wider than other intervals. Furthermore, the intervals between the via lands where the curved surface is formed and the wiring portion are wider than other intervals.

[0017] This prevents adjacent via lands from being connected to each other when the via lands and the wiring portions are patterned, and also prevents adjacent via lands and wiring portions from being connected to each other.

[0018] Therefore, the reliability of the flexible circuit board is improved. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 2 is a top view of a flexible circuit board according to an embodiment. [Figure 2] FIG. 2 is a bottom view of the flexible circuit board according to the embodiment. [Figure 3] FIG. 2 is an enlarged view of region A in FIG. [Figure 4] FIG. 2 is an enlarged view of region B in FIG. [Figure 5] FIG. 3 is an enlarged view of region C in FIG. 2. [Figure 6] FIG. 3 is an enlarged view of region D in FIG. 2. [Figure 7] FIG. 2 is an enlarged view of region E in FIG. [Figure 8] FIG. 2 is an enlarged view of region F in FIG. [Figure 9] FIG. 2 is an enlarged view of region G in FIG. [Figure 10] 1A and 1B are diagrams for explaining a COF module according to an embodiment. [Figure 11] FIG. 4 is a cross-sectional view taken along the line AA′ in FIG. 3. [Figure 12] FIG. 4 is a cross-sectional view taken along the line AA′ in FIG. 3. [Figure 13] FIG. 10 is a top view of a flexible circuit board according to another embodiment. [Figure 14] FIG. 10 is a bottom view of a flexible circuit board according to another embodiment. [Figure 15]FIG. 14 is an enlarged view of region A in FIG. [Figure 16] FIG. 15 is an enlarged view of region B in FIG. [Figure 17] FIG. 14 is an enlarged view of region C in FIG. [Figure 18] FIG. 15 is an enlarged view of region D in FIG. [Figure 19] FIG. 18 is a cross-sectional view taken along the line BB′ of FIG. 17. [Figure 20] FIG. 14 is another enlarged view of the region C in FIG. [Figure 21] FIG. 14 is another enlarged view of the region C in FIG. [Figure 22] FIG. 14 is another enlarged view of the region C in FIG. [Figure 23] FIG. 14 is another enlarged view of the region C in FIG. [Figure 24] 10A and 10B are diagrams for explaining the connection between the COF module according to the embodiment and other members. [Figure 25] 1A and 1B are diagrams illustrating an electronic device including a flexible circuit board according to an embodiment. [Figure 26] 1A and 1B are diagrams illustrating an electronic device including a flexible circuit board according to an embodiment. [Figure 27] 1A and 1B are diagrams illustrating an electronic device including a flexible circuit board according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical concept of the present invention is not limited to the described embodiments and may be realized in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0021] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the examples of the present invention are to be interpreted as meanings that would be commonly understood by a person of ordinary skill in the art to which the present invention belongs, and commonly used terms, such as those defined in dictionaries, may be interpreted in light of the contextual meaning of the relevant art.

[0022] Furthermore, terms used in the examples of the present invention are intended to describe the examples and are not intended to limit the present invention. In this specification, the singular form can also include the plural form unless otherwise specified in the phrase, and when it is stated as "A and (and) at least one (or more) of B and C," it can include one or more of all possible combinations of A, B, and C.

[0023] Furthermore, when describing components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. are used only to distinguish the component from other components, and the terminology does not determine the essence, order, or procedure of the component.

[0024] Furthermore, when a component is described as being "coupled," "coupled," or "connected" to another component, it includes not only cases where the component is directly coupled, coupled, or connected to the other component, but also cases where the component is "coupled," "coupled," or "connected" by other components between the component and the other component.

[0025] Furthermore, when described as being formed or disposed "above or below" each component, "above" or "below" includes not only the case where the two components are in direct contact with each other, but also the case where one or more other components are formed or disposed between the two components.

[0026] Furthermore, when it is expressed as "upper" or "lower," it can mean not only the upper direction but also the lower direction based on one component.

[0027] In the following description, the first direction 1D can be defined as the width direction of the flexible circuit board, and the second direction 2D can be defined as the length direction of the flexible circuit board.

[0028] Hereinafter, a flexible circuit board, a COF module, and an electronic device including the same according to embodiments will be described with reference to the drawings.

[0029] 1 to 6, the flexible circuit board 1000 includes a substrate 100, a circuit pattern, and a protective layer.

[0030] The substrate 100 includes a first surface 1S and a second surface 2S opposite to the first surface 1S. The circuit pattern and the protective layer are disposed on the first surface 1S and the second surface 2S.

[0031] The substrate 100 includes a cut line CL. The flexible circuit board 1000 is cut along the cut line CL. For example, after the circuit pattern, the protective layer, and the chip are arranged on the substrate 100, the substrate 100 can be cut along the cut line CL. In this way, the flexible circuit board 1000 is manufactured into the COF module 2000.

[0032] The base material 100 includes an effective area AA and a non-effective area UA. The effective area AA and the non-effective area UA are separated by the cut line CL. The effective area AA is the area inside the cut line CL. The non-effective area UA is the area outside the cut line CL.

[0033] The circuit pattern, the protective layer, and the chip are disposed on the effective area AA. Dummy patterns DP and sprocket holes SH are disposed on the non-effective area UA. The strength of the substrate 100 is improved by the dummy patterns, thereby preventing the flexible circuit board 1000 from warping. The flexible circuit board 1000 is wound and unwound in a roll-to-roll manner using the sprocket holes SH.

[0034] The substrate 100 includes a chip mounting area CHA. The chip mounting area CHA is arranged on the first surface 1S. The chip mounting area CHA is arranged inside the effective area AA. The chip is arranged on the chip mounting area CHA. Furthermore, the pad portion of the circuit pattern is arranged inside the chip mounting area CHA. Furthermore, the protective layer is not arranged on the chip mounting area CHA.

[0035] The substrate 100 may include a ductile material. For example, the substrate 100 may include polyimide (PI). However, examples are not limited thereto. The substrate 100 may include a polymer material such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). This allows the flexible circuit board to be used in a variety of electronic devices, including curved display devices.

[0036] The substrate 100 may have a thickness of 20 μm to 100 μm. For example, the substrate 100 may have a thickness of 25 μm to 50 μm. For example, the substrate 100 may have a thickness of 30 μm to 40 μm. If the thickness of the substrate 100 exceeds 100 μm, the thickness of the flexible circuit board may increase, thereby reducing the flexibility of the flexible circuit board. Furthermore, if the thickness of the substrate 100 is less than 20 μm, the strength of the substrate may decrease. Therefore, when mounting the chip on the flexible circuit board, the substrate 100 may be damaged by heat and pressure transferred to the substrate 100.

[0037] The circuit pattern and the protective layer are disposed on the substrate 100. For example, the circuit pattern and the protective layer may be disposed on the active area AA and the non-active area UA.

[0038] The circuit patterns may include a first circuit pattern 210, a second circuit pattern 220, a third circuit pattern 230, and a fourth circuit pattern 240. In addition, the protective layer may include a first protective layer 310 and a second protective layer 320.

[0039] 1 and 3, the first circuit pattern 210 is disposed on the first surface 1S. The first circuit pattern 210 includes a first wiring portion 211, a first pad portion 212a, and a second pad portion 212b. The first wiring portion 211, the first pad portion 212a, and the second pad portion 212b may include the same material. The first wiring portion 211, the first pad portion 212a, and the second pad portion 212b may be integrally formed.

[0040] The first pad portion 212a is disposed within the chip mounting area CHA, and is connected to the terminals of the chip, thereby connecting the first circuit pattern 210 to the chip.

[0041] The second pad portion 212b is disposed outside the chip mounting area CHA and is connected to a terminal of a circuit board, thereby connecting the first circuit pattern 210 to the circuit board.

[0042] The second pad portion 212b may include a first test pad portion. The first circuit pattern 210 is tested before the circuit board and the second pad portion 212b are connected. For example, the first test pad portion can be used to check whether the first circuit pattern has an open circuit or a short circuit.

[0043] The first wiring part 211 is disposed between the first pad part 212a and the second pad part 212b. The first wiring part 211 connects the first pad part 212a and the second pad part 212b. This connects the chip and the circuit board. Therefore, signals generated from the chip are transmitted to the circuit board.

[0044] The first protective layer 310 is disposed on the first circuit pattern 210. The first protective layer 310 is disposed on an area excluding the first pad portion 212a and the second pad portion 212b.

[0045] 1, 2, 4, and 5, the second circuit pattern 220 is disposed on the first surface 1S and the second surface 2S. The second circuit pattern 220 includes second wiring portions 221a and 221b, a third pad portion 222a, a fourth pad portion 222b, and a first via V1. The second wiring portions 221a and 221b, the third pad portion 222a, and the fourth pad portion 222b may include the same material. Additionally, the second wiring portions 221a and 221b, the third pad portion 222a, and the fourth pad portion 222b may be integrally formed.

[0046] The third pad portion 222a is disposed on the first surface 1S. The third pad portion 222a is disposed within the chip mounting area CHA. As a result, the third pad portion 222a is connected to the terminal of the chip. As a result, the second circuit pattern 220 and the chip are connected to each other.

[0047] The fourth pad portion 222b is disposed on the second surface 2S and is connected to a terminal of a display panel, thereby connecting the second circuit pattern 220 to the display panel.

[0048] The second wiring portion includes a 2-1 wiring portion 221a and a 2-2 wiring portion 221b. The 2-1 wiring portion 221a is disposed on the first surface 1S. The 2-2 wiring portion 221b is disposed on the second surface 2S. The second wiring portion connects the third pad portion 222a and the fourth pad portion 222b. The 2-1 wiring portion 221a is connected to the third pad portion 222a. In addition, the 2-2 wiring portion 221b is connected to the fourth pad portion 222b.

[0049] This connects the chip to the display panel, allowing signals generated by the chip to be transmitted to the display panel.

[0050] The first protective layer 310 and the second protective layer 320 are disposed on the second circuit pattern 220. The first protective layer 310 is disposed on the second circuit pattern 220 on the first surface 1S. The second protective layer 320 is disposed on the second circuit pattern 220 on the second surface 2S. The first protective layer 310 and the second protective layer 320 are disposed on an area excluding the third pad portion 222a and the fourth pad portion 222b.

[0051] The 2-1 wiring portion 221a and the 2-2 wiring portion 221b are connected to each other. The 2-1 wiring portion 221a and the 2-2 wiring portion 221b are connected to each other through the first via V1. The first via V1 penetrates the base material 100. The first via V1 is disposed on the first surface 1S and the second surface 2S. The first via V1 on the first surface 1S and the first via V1 on the second surface 2S are disposed at corresponding positions.

[0052] The first via V1 includes a first via land VL1 and a first via hole VH1. The first via hole VH1 is formed inside the first via land VL1. A conductive material is disposed in the first via hole VH1. This electrically connects the 2-1 wiring portion 221a and the 2-2 wiring portion 221b.

[0053] The second circuit pattern 220 may include a second test pad portion TP2. The second test pad portion TP2 may be disposed on the second surface 2S. The second test pad portion TP2 may be disposed on the non-effective area UA. A second passivation layer 320 is not disposed on the second test pad portion TP2. The second test pad portion TP2 may be connected to the 2-2 wiring portion 221b. The second test pad portion TP2 may be integrally formed with the 2-2 wiring portion 221b.

[0054] Before connecting the display panel to the fourth pad portion 222b, the second circuit pattern 220 may be tested. For example, the second test pad portion TP2 may be used to check for open and short circuits in the second circuit pattern.

[0055] 1, 2, 3, and 6, the third circuit pattern 230 is disposed on the first surface 1S and the second surface 2S. The third circuit pattern 230 includes a third wiring portion 231, a fifth pad portion 232a, a sixth pad portion 232b, and a second via V2. The third wiring portion 231, the fifth pad portion 232a, and the sixth pad portion 232b may include the same material. The third wiring portion 231, the fifth pad portion 232a, and the sixth pad portion 232b may be integrally formed.

[0056] The fifth pad portion 232a is disposed on the first surface 1S. The fifth pad portion 232a is disposed within the chip mounting area CHA. As a result, the fifth pad portion 232a is connected to the terminal of the chip. As a result, the third circuit pattern 230 and the chip are connected to each other.

[0057] The sixth pad portion 232b is disposed on the second surface 2S and is connected to a terminal of the display panel, thereby connecting the third circuit pattern 230 to the display panel.

[0058] The third wiring part 231 connects the fifth pad part 232a and the sixth pad part 232b, thereby connecting the chip to the display panel, and thus transmitting signals generated from the chip to the display panel.

[0059] The second protective layer 320 is disposed on the third circuit pattern 230. The second protective layer 320 is disposed on the third circuit pattern 230 on the second surface 2S. The second protective layer 320 is disposed on an area excluding the fifth pad portion 232a and the sixth pad portion 232b.

[0060] The fifth pad portion 232a and the third wiring portion 231 are connected to each other. The fifth pad portion 232a and the third wiring portion 231 are connected to each other through the second via V2. The second via V2 is disposed on the first surface 1S and the second surface 2S. The second via penetrates the base material 100. The second via V2 on the first surface 1S and the second via V2 on the second surface 2S are disposed at corresponding positions.

[0061] The second via V2 includes a second via land VL2 and a second via hole VH2. The second via hole VH2 is formed inside the second via land VL2. A conductive material is disposed in the second via hole VH2. Thus, the fifth pad portion 232a and the third wiring portion 231 are electrically connected.

[0062] The third circuit pattern 230 may include a third test pad portion TP3. The third test pad portion TP3 may be disposed on the second surface 2S. The third test pad portion TP3 may be disposed on the non-effective area UA. The second passivation layer 320 is not disposed on the third test pad portion TP3. The third test pad portion TP3 may be connected to the third wiring portion 231. The third test pad portion TP3 may be integrally formed with the third wiring portion 231.

[0063] Before connecting the display panel to the sixth pad portion 232b, the third circuit pattern 230 may be tested. For example, the third circuit pattern 230 may be checked for open and short circuits via the third test pad portion TP3.

[0064] 1, 7, and 8, the fourth circuit pattern 240 is disposed on the first surface 1S and the second surface 2S. The fourth circuit pattern 240 includes fourth wiring portions 241a and 241b, a seventh pad portion 242a, an eighth pad portion 242b, and a third via V3. The fourth wiring portions 241a and 241b, the seventh pad portion 242a, and the eighth pad portion 242b may include the same material. Additionally, the fourth wiring portions 241a and 241b, the seventh pad portion 242a, and the eighth pad portion 242b may be integrally formed.

[0065] The seventh pad portion 242a is disposed on the first surface 1S. The seventh pad portion 242a is disposed adjacent to the first pad portion 212a. The seventh pad portion 242a is connected to a terminal of the circuit board. Thus, the fourth circuit pattern 220 and the circuit board are connected to each other.

[0066] The eighth pad portion 242b is disposed on the second surface 2S and is connected to a terminal of the display panel, thereby connecting the fourth circuit pattern 240 to the display panel.

[0067] The fourth wiring portion includes a 4-1 wiring portion 241a and a 4-2 wiring portion 241b. The 4-1 wiring portion 241a is disposed on the first surface 1S. The 4-2 wiring portion 241b is disposed on the second surface 2S. The fourth wiring portion connects the seventh pad portion 242a and the eighth pad portion 242b. The 4-1 wiring portion 241a is connected to the seventh pad portion 242a. The 4-2 wiring portion 241b is connected to the eighth pad portion 242b.

[0068] This connects the circuit board and the display panel, allowing the circuit board and the display panel to exchange signals with each other.

[0069] The first protective layer 310 and the second protective layer 320 are disposed on the fourth circuit pattern 240. The first protective layer 310 is disposed on the fourth circuit pattern 240 on the first surface 1S. The second protective layer 320 is disposed on the fourth circuit pattern 240 on the second surface 2S. The first protective layer 310 and the second protective layer 320 are disposed on an area excluding the seventh pad portion 242a and the eighth pad portion 242b.

[0070] The 4-1 wiring portion 241a and the 4-2 wiring portion 241b are connected to each other. The 4-1 wiring portion 241a and the 4-2 wiring portion 241b are connected to each other via the third via V3. The third via V3 is disposed on the first surface 1S and the second surface 2S. The third via V3 penetrates the base material 100. The third via V3 on the first surface 1S and the third via V3 on the second surface 2S are disposed at corresponding positions.

[0071] The third via V3 includes a third via land VL3 and a third via hole VH3. The third via hole VH3 is formed inside the third via land VL3. A conductive material is disposed in the third via hole VH3. This electrically connects the 4-1 wiring portion 241a and the 4-2 wiring portion 241b.

[0072] The circuit patterns 210, 220, 230, and 240 may include a metal material with excellent electrical conductivity. Specifically, the circuit patterns 210, 220, 230, and 240 may include copper (Cu). However, the embodiment is not limited thereto. The circuit patterns 210, 220, 230, and 240 may include copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), or molybdenum (Mo). They may also include at least one metal selected from the group consisting of gold (Au), titanium (Ti), and alloys thereof.

[0073] The first protective layer 310 and the second protective layer 320 may include a solder paste, which may include a thermosetting resin, a thermoplastic resin, a filler, a hardener, or a hardening accelerator.

[0074] As described above, the flexible circuit board 1000 includes a plurality of vias, including the first via V1, the second via V2, and the third via V3.

[0075] The via land and the via hole may have a predetermined size. The via land may have a predetermined distance. The via land and the wiring portion may have a predetermined distance. As a result, the flexible circuit board may have improved reliability, alignment characteristics, and process efficiency.

[0076] The vias and wiring portions of the flexible circuit board according to the embodiment will be described with reference to Figures 9 and 10. For convenience of explanation, Figure 9 focuses on the first via. The following description also applies to the second and third vias.

[0077] 9, the first via land VL1 has a first length L1 and a second length L2. The first length L1 is the length in a first direction D1. The second length L2 is the length in a second direction D2. The first length L1 and the second length L2 may be the same or similar.

[0078] The first length L1 and the second length L2 have a set size, for example, the first length L1 and the second length L2 may be 60 μm to 80 μm, 65 μm to 80 μm, or 67 μm to 75 μm.

[0079] If the first length L1 and the second length L2 are less than 60 μm, the area of ​​the first via land VL1 is reduced. This makes it difficult to form the first via hole VL1 inside the first via land VL1. This may cause the position or size of the first via hole VH1 to change. This reduces the alignment characteristics of the first via hole VL1.

[0080] When the first length L1 and the second length L2 exceed 80 μm, the area of ​​the first via land VL1 increases, thereby increasing the bezel area of ​​a display panel connected to the COF module 2000.

[0081] 10, the COF module 2000 includes a first region 1A and a second region 2A. The first region 1A is a region where the vias V1, V2, and V3 are not arranged. The second region 2A is a region where the first via V1 and the third via V3 are arranged.

[0082] The COF module 2000 and the display panel 4000 are connected in the second region 2A. The COF module 2000 is bent in the first region 1A. That is, the COF module 2000 is bent in a region where the vias V1, V2, and V3 are not arranged. As a result, the second region 2A becomes a bezel region of the display panel 4000. Therefore, if the area of ​​the first via land VL1 increases, the bezel region of the display panel 4000 can increase. As a result, the effective area of ​​the display panel 4000 can be reduced.

[0083] The first via hole VH1 has a first width W1. The first width W1 has a set size. For example, the first width W1 may be 20 μm to 30 μm, 22 μm to 28 μm, or 23 μm to 27 μm.

[0084] If the first width W1 is less than 20 μm, the alignment characteristics of the first via hole VH1 are degraded, which in turn degrades the connection characteristics of the first wiring portion 221 on the first surface 1S and the second surface 2S.

[0085] If the first width W1 exceeds 30 μm, it becomes difficult to form the first via hole VL1 inside the first via land VL1, which may cause the position or size of the first via hole VH1 to change, thereby degrading the alignment characteristics of the first via hole VL1.

[0086] The plurality of first via lands VL1 have a first interval G1. The first via land VL1 and the first wiring portion 221 have a second interval G2. The first via hole VH1 and the first via land VL1 have a third interval G3.

[0087] The first distance G1, the second distance G2, and the third distance G3 may be different from the second width W2 of the first wiring portion 221. For example, the first distance G1, the second distance G2, and the third distance G3 may be greater than the second width W2.

[0088] For example, the first gap G1 may be 1.1 times, 1.5 times, 2 times, 2.5 times, or 3 times or more the second width W2. As an example, the first gap G1 may be more than 1 to 5 times the second width W2. By setting the first gap G1 within this range, the distance between the first via lands VL1 can be sufficiently secured. This prevents adjacent first via lands VL1 from being connected during processing.

[0089] The second gap G2 may be 1.1, 1, 5, or 2 times or more the second width W2. For example, the second gap G2 may be more than 1 to 3 times the second width W2. Since the second gap G2 is set within this range, a sufficient distance between the first wiring portions 221 can be ensured. This prevents adjacent first wiring portions 221 from being connected together during processing.

[0090] The third distance G3 may be 1.1 times, 1.5 times, 2 times, 2.5 times, or 3 times or more the second width W2. For example, the third distance G3 may be more than 1 to 5 times the second width W2. Since the third distance G3 is set within this range, the first via hole VH1 can be formed with a sufficient area. This improves the alignment characteristics of the first via hole VH1. Furthermore, the first via hole VH1 can be easily formed.

[0091] The first interval G1 and the second interval G2 may be different. Specifically, the first interval G1 may be larger than the second interval G2. For example, the first interval G1 may be more than 1 time the second interval G2. Specifically, the first interval G1 may be 1.1 times, 1.5 times, 2 times, or 3 times or more the second interval G2. For example, the first interval G1 may be 1.1 to 5 times the second interval G2.

[0092] For example, the first gap G1 may be 12 μm or more. Specifically, the first gap G1 may be 12 μm to 30 μm, 13 μm to 25 μm, or 14 μm to 20 μm.

[0093] The second gap G2 may be less than 12 μm. More specifically, the second gap G2 may be 3 μm to 11 μm or 5 μm to 10 μm.

[0094] Since the first distance G1 is set within the above range, the process efficiency of the first via land VL1 can be improved. The first via land VL1 is disposed with an area larger than that of the first wiring portion 221.

[0095] For example, when forming the first via land VL1, the first via land VL1 is plated over a larger area than the first wiring portion 221. Therefore, a DFR (Dry Film Resist) pattern between the via lands VL1 may be damaged during the plating process, which may reduce the process efficiency of the first via land VL1.

[0096] Therefore, the first gap G1 is formed to have a sufficient size, thereby improving the process efficiency of the flexible circuit board 1000.

[0097] The first via land VL1 includes a plurality of corners. The corners may have curved surfaces. The first via land VL1 includes at least one curved surface having a first radius of curvature R1. For example, the corners may include one or two corners connected to the first wiring portion 221. Alternatively, the corners may include two or three corners not connected to the first wiring portion 221. At least one corner not connected to the first wiring portion 221 includes at least one curved surface. Also, the curved surface has the first radius of curvature R1.

[0098] As a result, a region where the interval between the first via lands VL1 varies is formed. Also, a region where the interval between the first via land VL1 and the first wiring portion 221 varies is formed. That is, the first interval G1 is larger at the corners of the first via land VL1. Also, the second interval G2 is larger at the corners of the first via land VL1.

[0099] Specifically, the first via lands VL1 adjacent to each other at the corner have a fourth distance G4 therebetween. Also, the first via lands VL1 adjacent to each other at the corner and the first wiring portion have a fourth distance G4 therebetween. The fourth distance G4 may be greater than the first distance G1 and the second distance G2.

[0100] Therefore, the corners can be easily patterned. That is, the first distance G1 and the second distance G2 are large at the corners where the patterning directions are different. This prevents adjacent first via lands VL1 from being connected to each other during the process. Also, the first via land VL1 and the first wiring portion 221 from being connected to each other.

[0101] The first via hole VH1 is formed in a circular shape having a second radius of curvature R2.

[0102] The first curvature radius R1 and the second curvature radius R2 may be different. Specifically, the first curvature radius R1 may be larger than the second curvature radius R2. That is, the curvature of the corner portion is smaller than the curvature of the first via hole VH1. For example, the first curvature radius R1 may be 30 μm or less. Specifically, the first curvature radius R1 may be 1 μm to 30 μm, 5 μm to 25 μm, or 10 μm to 20 μm.

[0103] The first via hole VH1 and the corner are spaced apart by a fifth distance G5.

[0104] The fourth interval G4 and the fifth interval G5 may be different. Specifically, the fifth interval G5 may be larger than the fourth interval G4.

[0105] Furthermore, the third interval G3 and the fifth interval G5 may be different from each other. Specifically, the fifth interval G5 may be larger than the third interval G3.

[0106] Therefore, the process of aligning the vias is facilitated, improving the reliability of the flexible circuit board.

[0107] Figures 11 and 12 are diagrams for explaining the layer structure of the circuit pattern. Figures 9 and 10 will be explained using the first circuit pattern as an example.

[0108] 11, the first circuit pattern is formed in multiple layers. Specifically, the first wiring portion 211, the first pad portion 212a, and the second pad portion 212b include a buffer layer 205, a metal layer 201, and an adhesive layer 203.

[0109] The buffer layer 205 may include multiple layers. Specifically, the buffer layer 205 includes a first buffer layer 205a and a second buffer layer 205b. The first buffer layer 205a is disposed on the substrate 100. The second buffer layer 205b is disposed on the first buffer layer 205a.

[0110] The first buffer layer 205a includes a material that has good adhesion to the substrate 100. For example, the first buffer layer 205a may include nickel (Ni). The second buffer layer 205b includes a material that has good adhesion to the first circuit pattern. For example, the second buffer layer 205b may include chromium (Cr).

[0111] The buffer layer 205 may have a thickness in the nanometer range, for example, 20 nm or less.

[0112] The buffer layer 205 improves the adhesion between the substrate 100 and the first circuit pattern.

[0113] The metal layer 201 is disposed on the buffer layer 205. Specifically, the metal layer 201 is disposed on the second buffer layer 205b. The metal layer 201 includes a metal material. For example, the metal layer 201 may include copper (Cu).

[0114] The metal layer 201 may be formed by electrolytic plating using the buffer layer as a seed layer, that is, the metal layer 201 may be a plating layer.

[0115] The thickness of the metal layer 201 may be 10 μm to 30 μm.

[0116] The bonding layer 203 is disposed on the metal layer 201 .

[0117] The bonding layer 203 is disposed on the side and top surfaces of the metal layer 201. For example, the bonding layer 203 may be disposed while enveloping the metal layer 201.

[0118] The bonding layer 203 includes a metal, for example, tin (Sn).

[0119] The bonding layer 203 may have a thickness of 0.3 μm to 0.7 μm. The tin content of the bonding layer 203 may increase as it extends from the lower surface to the upper surface.

[0120] That is, the bonding layer 203 contacts the metal layer 201. Therefore, the tin content increases from the bottom surface of the bonding layer 203 toward the top surface thereof, and the copper content decreases from the bottom surface of the bonding layer 203 toward the top surface thereof.

[0121] Therefore, pure tin may remain in a thickness range of 0.1 μm to 0.3 μm from the top surface of the bonding layer 203.

[0122] The pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel by the bonding layer 203. For example, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer melts. Pure tin remains on the upper surface of the bonding layer. Therefore, the pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel.

[0123] 12, the metal layer 201 may include a first metal layer 201a and a second metal layer 201b. The first metal layer 201a is disposed on the buffer layer 205. The second metal layer 201b is disposed on the first metal layer 201a.

[0124] The thickness of the first metal layer 201a may be less than the thickness of the second metal layer 201b.

[0125] For example, the thickness of the first metal layer 201a may be 0.7 μm to 2 μm, and the thickness of the second metal layer 201b may be 10 μm to 25 μm.

[0126] The first metal layer 201a and the second metal layer 201b may include the same metal material, for example, copper (Cu).

[0127] The first metal layer 201a and the second metal layer 201b may be formed by a plating process. For example, the first metal layer 201a may be thinly formed on the buffer layer 205. Then, the second metal layer 201b may be formed using the first metal layer 201a as a seed layer.

[0128] The bonding layer 203 may include the first bonding layer 203a and the second bonding layer 203b.

[0129] The first bonding layer 203a is disposed on the metal layer 201. In particular, the first bonding layer 203a is disposed on the first wiring portion 211, the first pad portion 212a, and the second pad portion 212b.

[0130] The second bonding layer 203b is disposed on the first bonding layer 203a. Specifically, the second bonding layer 203b is disposed on the first pad portion 212a and the second pad portion 212b.

[0131] Therefore, the first wiring portion 211 includes the buffer layer 205, the metal layer 201, and the first bonding layer 203a. Also, the first pad portion 212a and the second pad portion 212b include the buffer layer 205, the metal layer 201, the first bonding layer 203a, and the second bonding layer 203b.

[0132] Therefore, the layer structure of the first wiring portion 211 is different from the layer structures of the first pad portion 212a and the second pad portion 212b.

[0133] The first bonding layer 203a and the second bonding layer 203b contain a metal. In particular, the first bonding layer 203a and the second bonding layer 203b may contain tin (Sn).

[0134] The first bonding layer 203a and the second bonding layer 203b are disposed with different thicknesses, specifically, the thickness of the second bonding layer 203b is greater than the thickness of the first bonding layer 203a.

[0135] For example, the first bonding layer 203a has a thickness of 0.02 μm to 0.06 μm, and the second bonding layer 203b has a thickness of 0.2 μm to 0.6 μm.

[0136] Therefore, the thickness of the first wiring part 211 is reduced, and therefore, cracks in the first wiring part 211 can be prevented when the flexible circuit board is bent.

[0137] The thickness of the first circuit pattern may be 2 μm to 25 μm. More specifically, the thickness of the first circuit pattern may be 5 μm to 20 μm. More specifically, the thickness of the first circuit pattern may be 7 μm to 15 μm.

[0138] If the thickness of the first circuit pattern is less than 2 μm, the resistance of the first circuit pattern may increase, and if the thickness of the first circuit pattern is more than 25 μm, it may be difficult to achieve a fine pattern.

[0139] Flexible circuit boards according to other embodiments will be described below with reference to Figures 13 to 23. Descriptions that are the same as or similar to the description of the flexible circuit boards according to the above-mentioned embodiments will be omitted.

[0140] 13 to 19, the flexible circuit board 1000 includes a substrate 100, a circuit pattern, and protective layers 310 and 320.

[0141] 16 and 17, metal patterns 250 and 260 are disposed on the first surface 1S and the second surface 2S, respectively. The metal patterns 250 and 260 are disposed adjacent to the first via V1. The metal patterns 250 and 260 are disposed between the first via V1 and the end E of the substrate 100. The metal patterns 250 and 260 are disposed between the first via V1 and the cut line CL.

[0142] 16, the metal pattern 260 is disposed on the second surface 2S. The metal pattern 260 is connected to the first via V1. Also, referring to FIG. 18, the metal pattern 250 is disposed on the first surface 1S. The metal pattern 250 is spaced apart from the first via V1.

[0143] The metal pattern 260 may be a test pad, which may be used to test the second circuit pattern 220 for short circuits.

[0144] The metal pattern 250 may be a dummy pattern. When the metal pattern 250 and the first via V1 are connected, a signal transmitted from the chip CH moves to the dummy pattern. Therefore, signal loss may occur. Therefore, the metal pattern 250 is spaced apart from the first via V1.

[0145] The metal pattern 250 is spaced apart from the first via V1 by a first distance d1.

[0146] The first distance d1 may be equal to or greater than the line width of the second wiring portion 221 and equal to or less than the width of the first via land VL1 in the first direction. If the first distance d1 is less than the line width of the second wiring portion 221, the metal pattern 250 and the first via V1 may come into contact with each other. This may allow electrical conduction between the first via V1 and the metal pattern 250. This may result in signal loss and power loss since a signal generated from the chip is transmitted to the metal pattern 250.

[0147] If the first distance d1 exceeds the width of the first via land VL1, the area in which the metal pattern 250 can be formed is narrowed. As a result, the area of ​​the metal pattern 250 may be reduced. The metal pattern 250 may be a dummy pattern spaced apart from the second circuit pattern 220. As a result, if the area of ​​the metal pattern 250 is reduced, the strength of the flexible circuit board may be reduced. As a result, the flexible circuit board may be warped in one direction.

[0148] In the flexible circuit board according to another embodiment, the second wiring part 221 is spaced apart from the metal pattern 250. This prevents the signal from traveling in the direction of the metal pattern when the signal transmitted from the chip travels to the display panel, thereby reducing signal loss and driving power of the flexible circuit board.

[0149] Furthermore, since the second wiring portion 221 and the metal pattern 250 are spaced apart, the reliability of the flexible circuit board is improved. The metal pattern 250 may extend to the cut line CL. As a result, the metal pattern 250 may be exposed to the outside. As a result, corrosion may occur in the metal pattern 250.

[0150] Since the second wiring part 221 is spaced apart from the metal pattern 250, corrosion of the metal pattern 250 can be prevented from spreading to the second wiring part 221. Therefore, corrosion of the second circuit pattern 220 can be prevented. Therefore, deterioration of the electrical characteristics of the flexible circuit board can be prevented, and reliability can be improved.

[0151] Furthermore, since the metal pattern is disposed between the second circuit pattern and the edge of the substrate, warping of the flexible circuit board is prevented. The metal pattern is disposed apart from the second circuit pattern and is not connected to the chip. Since the metal pattern is disposed between the second circuit pattern and the edge of the substrate, the strength of the flexible circuit board is improved. That is, the metal pattern may be a dummy pattern. Since the strength of the flexible circuit board is improved by the metal pattern, warping of the flexible circuit board is prevented.

[0152] 17, the second circuit pattern 220 on the first surface 1S is spaced apart from the cut line CL. The flexible circuit board is cut along the cut line CL. The second circuit pattern is also spaced apart from the edge of the substrate.

[0153] The minimum distance between the first via V1 and the cut line CL is defined as a second distance d2, which may be 1 to 4 times, 1.5 to 3.5 times, or 2 to 3 times the width of the first via land VL1 in the second direction.

[0154] If the second distance d2 is less than one time the width of the first via land V1, by-products generated when cutting the substrate along the cut line CL may be transferred to the second circuit pattern 220. As a result, the by-products may short-circuit adjacent first via portions V1, or the conductivity of the second circuit pattern may be reduced.

[0155] Also, if the second distance d2 is greater than four times the width of the first via land VL1, the bezel area of ​​the flexible circuit board increases, and therefore the size of the flexible circuit board increases.

[0156] 19, the second circuit pattern 220 on the first surface 1S may be surrounded by the first protective layer 310. In particular, the first via V1 may be surrounded by the first protective layer 310.

[0157] A first protective layer 310 is disposed between the metal pattern 250 and the first via V1. In particular, the metal pattern 250 and the first via V1 are spaced apart, and the first protective layer 310 is disposed on the spaced apart area.

[0158] Therefore, even if the size of the first distance d1 is reduced during the process, it is possible to prevent contact between the second circuit pattern 220 and the metal pattern 250. In addition, since the first protective layer 310 is disposed between the metal pattern 250 and the first via V1, it is possible to prevent corrosion of the metal pattern 250 from being transmitted to the second circuit pattern 220.

[0159] Furthermore, since the metal pattern 250 and the first via V1 are spaced apart, the process of forming the first protective layer 310 is facilitated. The first protective layer 310 may be formed of a liquid material. Therefore, the liquid material can move to the spaced apart area between the metal pattern 250 and the first via V1. This increases the movement path of the material forming the first protective layer. This reduces the process time for forming the first protective layer, and the thickness of the first protective layer becomes uniform.

[0160] 20, the line widths of the metal pattern 250 and the second wiring portion 221 may be different. For example, the line width W1 of the metal pattern 250 may be larger than the line width W2 of the second wiring portion 221. For example, the line width W1 of the metal pattern 250 may be 2 to 20 times, 3 to 15 times, or 5 to 10 times the line width W2 of the second wiring portion 221. Alternatively, the line width W1 of the metal pattern 250 may be 1 to 3 times, 1.5 to 2.5 times, or 1.7 to 2.3 times the width of the first via land VL1 in the first direction.

[0161] Therefore, the area of ​​the metal pattern disposed on the flexible circuit board is increased, which improves the strength of the flexible circuit board and prevents the flexible circuit board from warping.

[0162] In addition, the process time for forming the metal pattern 250 can be prevented from increasing excessively, thereby improving process efficiency.

[0163] 21, the metal pattern 250 includes a plurality of metal patterns. The plurality of metal patterns may have different line widths. For example, the metal pattern 250 may include a first metal pattern 251, a second metal pattern 252, and a third metal pattern 253. The line widths of the first metal pattern 251, the second metal pattern 252, and the third metal pattern 253 may be different.

[0164] For example, the line width W1a of the first metal pattern 251 may be larger than the line width W1b of the second metal pattern 252 and the line width W1c of the third metal pattern 253. Furthermore, the line width W1b of the second metal pattern 252 may be larger than the line width W1c of the third metal pattern 253.

[0165] Although FIG. 21 shows that the first metal pattern 251, the second metal pattern 252, and the third metal pattern 253 are regularly arranged, the embodiment is not limited thereto.

[0166] The metal patterns 250 are arranged with varying line widths at different positions. This improves the reliability of the flexible circuit board. In particular, the flexible circuit board may warp in one direction due to differences in the areas of the patterns arranged on the first and second surfaces. Therefore, the metal patterns are arranged with different widths at different positions, taking into account the differences in the areas of the patterns. This prevents the flexible circuit board from warping.

[0167] 22 and 23, the metal pattern 250 and the second wiring portion 221 may extend in different directions.

[0168] 22, the metal pattern 250 may extend in a first direction 1D. The second wiring portion 221 may extend in a second direction 2D. In particular, the metal pattern 250 may extend in a direction perpendicular to the direction in which the second wiring portion 221 extends.

[0169] 23, the metal pattern 250 may extend in a diagonal direction between the first direction 1D and the second direction 2D, and the second wiring portion 221 may extend in the second direction 2D.

[0170] The metal pattern 250 extends in various directions different from the direction in which the second wiring portion 221 extends. Therefore, even if the area of ​​the bezel region of the flexible circuit board is reduced, the metal pattern can be disposed over a sufficient area. In particular, if the number of terminal portions of the display panel is increased, the number of second circuit patterns also increases. Therefore, if the number of first vias increases, the area in which the metal pattern can be formed may become smaller. Therefore, in this embodiment, the dummy pattern is disposed to extend in various directions. As a result, even if the area of ​​the bezel region is reduced, the metal pattern can be disposed over a sufficient area.

[0171] The flexible circuit board according to the embodiment can be formed into a COF module by mounting a chip CH on the chip mounting area CHA and cutting along the cut line CL.

[0172] The COF module 2000 is connected to a display panel 4000 and a circuit board 3000, thereby transmitting signals between the display panel 4000 and the circuit board 3000.

[0173] 24 , one end of the COF module 2000 is connected to the display panel 4000. The other end of the COF module 2000 is connected to the circuit board 3000. For example, the display panel 4000 may be disposed on one side of the COF module 2000. Also, the circuit board 3000 may be disposed on the other side of the COF module 2000. However, embodiments are not limited thereto. The display panel 4000 and the circuit board 3000 may be disposed on the same side of the COF module 2000.

[0174] The COF module 2000 includes a flexible substrate, and therefore can have both a rigid form and a bending form between the display panel 4000 and the circuit board 3000. That is, the COF module 2000 can include a bending area BA.

[0175] The COF module 2000 can connect the display panel 4000 and the circuit board 3000 in a curved shape. This reduces the thickness of the electronic device, improving design flexibility. Furthermore, the COF module 2000 does not break wiring even in a curved shape. This improves the reliability of the electronic device including the COF module.

[0176] The COF module is flexible and can be used in a variety of electronic devices.

[0177] For example, referring to Fig. 25, the COF module may be applied to a flexible touch window, and thus a touch device including the COF module may be a flexible touch device, which can be bent or curved by a user's hand.

[0178] 26, the COF module can be applied to various wearable touch devices including curved displays, and therefore, electronic devices including the COF module can be slimmer or lighter.

[0179] Referring to FIG. 27, the COF module can be applied to various electronic devices having displays such as TVs, monitors, and notebooks.

[0180] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, the content related to such combinations and modifications should be interpreted as being included within the scope of the present invention.

[0181] Furthermore, while the above description has focused on the embodiments, these are merely illustrative and do not limit the present invention. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the present invention. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the present invention as defined by the appended claims.

Claims

1. a substrate including a first surface and a second surface opposite the first surface; a first circuit pattern disposed on the first surface; a second circuit pattern disposed on the first surface and the second surface; a third circuit pattern disposed on the first surface and the second surface; the second circuit pattern includes a first via and a second wiring portion; the third circuit pattern includes a second via and a third wiring portion; the first via and the second via include a via land and a via hole formed in the via land; At least one of the first via and the second via has a first distance between the via lands, a second distance between the via land and the second wiring portion or the third wiring portion adjacent to the via land, and a third distance between a side surface of the via land and the via hole, At least one of the first gap, the second gap, and the third gap is greater than the width of the wiring portion.

2. The flexible circuit board according to claim 1 , wherein the first interval is greater than 1 to 5 times the width of the wiring portion.

3. The flexible circuit board according to claim 1 , wherein the second interval is greater than one to three times the width of the wiring portion.

4. The flexible circuit board according to claim 1 , wherein the third interval is greater than 1 to 5 times the width of the wiring portion.

5. The flexible circuit board of claim 1 , wherein the first spacing and the second spacing are different.

6. The flexible circuit board according to claim 5, wherein the first gap is 1.1 to 5 times the second gap.

7. the first interval is 12 μm to 30 μm; The flexible circuit board according to claim 5, wherein the second gap is between 3 μm and 11 μm.

8. The flexible circuit board of claim 1 , wherein at least one corner of the via land includes a curved surface having a first radius of curvature.

9. A flexible circuit board according to any one of claims 1 to 8; A COF module including a chip disposed in the chip mounting area of ​​the flexible circuit board.

10. A COF module according to claim 9; a circuit board connected to the first circuit pattern; a display panel coupled to the second circuit pattern and the third circuit pattern.

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