Pixel circuit for light emitting device

Abstract

The pixel drive circuit includes a first transistor, a second transistor, and a first capacitor. The first transistor is configured to receive a data signal and drive the light-emitting element based on the data signal. The first transistor includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal that receives a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element. The first capacitor is disposed between the first gate terminal and the second gate terminal. The first transistor and the second transistor are different types of transistors.

Description

[Background technology]

[0001] The present disclosure relates generally to display technology, and more particularly to pixel circuits.

[0002] Some display devices may have the requirement to use tandem or triple OLEDs with high cross-voltage driving. In a commodity complementary metal-oxide semiconductor (CMOS) transistor process, the breakdown voltage of the transistors that drive the OLEDs using a threshold voltage (Vth) compensation architecture may be 6 to 8 volts. When these transistors are used in pixel driving circuits to drive tandem or triple OLEDs, the gate-drain voltage (VGD) or body-drain voltage (VBD) may exceed the breakdown voltage of the device.

[0003] Therefore, the display device may suffer from hot carrier injection (HCI) effects or current leakage, causing some detection or abnormal condition. Summary of the Invention

[0004] In one embodiment, a pixel driving circuit is disclosed. The pixel drive circuit includes a first transistor, a second transistor, and a first capacitor. The first transistor is configured to receive a data signal and drive a light-emitting element based on the data signal. The first transistor includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element. The first capacitor is disposed between the first gate terminal and the second bias source. The first transistor and the second transistor are different types of transistors.

[0005] In some implementations, the pixel drive circuit further includes a drive subcircuit and a data write subcircuit, the drive subcircuit coupled to the first gate terminal and the first source terminal for selectively providing a second bias signal from a third bias source to the first transistor, and the data write subcircuit coupled to the drive subcircuit for selectively providing the data signal to the first transistor.

[0006] In some implementations, the pixel driving circuit further includes a second capacitor disposed between the driving sub-circuit and the data writing sub-circuit.

[0007] In some implementations, the scanning period of each display frame includes a reset period and an emission period, and the driving subcircuit provides the second bias signal to the first transistor during the emission period to drive the light-emitting element.

[0008] In some implementations, the reset period includes an initialization period, a compensation period, and a data writing period, and the drive subcircuit provides a first initialization bias signal to the first capacitor during the initialization period.

[0009] In some implementations, the data writing sub-circuit provides a second initialization bias signal to the second capacitor during the initialization period and the compensation period.

[0010] In some implementations, the data write subcircuit provides the data signal to the first transistor during the data write period.

[0011] In some implementations, the drive subcircuit includes a first switch element disposed between the first source terminal and a first terminal of the second capacitor; a second switch element disposed between the first terminal of the second capacitor and the third bias source; and a third switch element disposed between the first terminal of the second capacitor and the first gate terminal.

[0012] In some implementations, the drive subcircuit includes a fourth switch element disposed between the third bias source and a first terminal of the second capacitor; and a fifth switch element disposed between the first terminal of the second capacitor and the first gate terminal.

[0013] In some implementations, the drive subcircuit includes a sixth switch element disposed between the first source terminal and the third bias source; a seventh switch element disposed between the first source terminal and a first terminal of the second capacitor; and an eighth switch element disposed between the first terminal of the second capacitor and a first initialization bias source.

[0014] In some implementations, the drive subcircuit includes a ninth switch element disposed between the first source terminal and the third bias source; a tenth switch element disposed between the first source terminal and a first terminal of the second capacitor; and an eleventh switch element disposed between the first terminal of the second capacitor and the first gate terminal.

[0015] In some implementations, the data write subcircuit has a twelfth switch element disposed between the second terminal of the second capacitor and a data signal source; and a thirteenth switch element disposed between the second terminal of the second capacitor and a second initialization bias source.

[0016] In some implementations, the data write sub-circuit includes a fourteenth switch element disposed between the second terminal of the second capacitor and a data signal source.

[0017] In some implementations, the data write sub-circuit and the second capacitor are shared by more than one drive sub-circuit.

[0018] In some implementations, the first bias source and the second bias source are provided by different voltage sources. In some implementations, the first bias source and the second bias source are provided by the same voltage source.

[0019] In another aspect, a light emitting device is disclosed, the light emitting device including a light emitting element and a drive circuit for driving the light emitting element. The drive circuit includes a first type transistor that receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal; a second type transistor that includes a second gate terminal that receives a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element; a first capacitor disposed between the first gate terminal and the second bias source; a drive subcircuit coupled to the first gate terminal and the first source terminal for providing the data signal and a second bias signal according to a third bias source; a data write subcircuit coupled to the drive subcircuit for providing the data signal to the drive subcircuit; and a second capacitor disposed between the drive subcircuit and the data write subcircuit.

[0020] In some implementations, the first type of transistor is a p-type transistor and the second type of transistor is an n-type transistor.

[0021] In some implementations, the drive subcircuit includes a first switch element disposed between the first source terminal and a first terminal of the second capacitor; a second switch element disposed between the first terminal of the second capacitor and the third bias source; and a third switch element disposed between the first terminal of the second capacitor and the first gate terminal.

[0022] In some implementations, the drive subcircuit includes a fourth switch element disposed between the third bias source and a first terminal of the second capacitor; and a fifth switch element disposed between the first terminal of the second capacitor and the first gate terminal.

[0023] In some implementations, the drive subcircuit includes a sixth switch element disposed between the first source terminal and the third bias source; a seventh switch element disposed between the first source terminal and a first terminal of the second capacitor; and an eighth switch element disposed between the first terminal of the second capacitor and a first initialization bias source.

[0024] In some implementations, the drive subcircuit includes a ninth switch element disposed between the first source terminal and the third bias source; a tenth switch element disposed between the first source terminal and a first terminal of the second capacitor; and an eleventh switch element disposed between the first terminal of the second capacitor and the first gate terminal.

[0025] In some implementations, the data write subcircuit has a twelfth switch element disposed between the second terminal of the second capacitor and a data signal source; and a thirteenth switch element disposed between the second terminal of the second capacitor and a second initialization bias source.

[0026] In some implementations, the data write sub-circuit includes a fourteenth switch element disposed between the second terminal of the second capacitor and a data signal source.

[0027] In some implementations, the drive circuit further includes a reset signal coupled to the second drain terminal.

[0028] In some implementations, the first bias source and the second bias source are provided by different voltage sources. In some implementations, the first bias source and the second bias source are provided by the same voltage source.

[0029] In a further aspect, a method for driving a light-emitting element using a pixel circuit is disclosed. The pixel circuit includes a first transistor, a second transistor disposed between the first transistor and the light-emitting element, a first capacitor disposed between a first gate terminal of the first transistor and a second gate terminal of the second transistor, and a second capacitor disposed between the first transistor and a data signal source. During an initialization period, a first end of the first capacitor is initialized to a first initialization bias, and a first end of the second capacitor is initialized to a second initialization bias. During a compensation period, the first end of the first capacitor is compensated to a compensation bias. During a data writing period, a data signal is provided to the first end of the second capacitor. During a light-emitting period, the light-emitting element is driven to emit light based on the data signal.

[0030] In some implementations, the pixel circuit may further include a reset bias source coupled to the second transistor and the light-emitting element, wherein a reset bias is provided to the pixel circuit by the reset bias source during the initialization period, the compensation period, and the data writing period.

[0031] In some implementations, the sum of the initialization period, the compensation period, the data writing period, and the light emitting period is a frame period.

[0032] In some implementations, the first initialization bias is provided to the first end of the first capacitor; a first bias is provided to the second end of the first capacitor; the second initialization bias is provided to the first end of the second capacitor; and the first end of the first capacitor and the second end of the second capacitor are coupled.

[0033] In some implementations, the first initialization bias at the first end of the first capacitor is discharged to the reset bias through the first transistor and the second transistor.

[0034] In some implementations, the voltage difference between the first end and the second end of the first capacitor is at least the sum of a first threshold voltage of the first transistor and a second threshold voltage of the second transistor.

[0035] In some implementations, the compensation bias is at least the sum of a first threshold voltage of the first transistor and a second threshold voltage of the second transistor. [Brief explanation of the drawings]

[0036] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure.

[0037] [Figure 1] 1 illustrates an apparatus including a display and control logic according to some aspects of the present disclosure.

[0038] [Figure 2]2 illustrates a block diagram of the display shown in FIG. 1 according to some aspects of the present disclosure.

[0039] [Figure 3] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0040] [Figure 4] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0041] [Figure 5] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0042] [Figure 6A] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure. [Figure 6B] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0043] [Figure 7] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0044] [Figure 8] 8 shows a timing diagram illustrating the operation of the pixel drive circuit in FIG. 7 according to some embodiments of the present disclosure.

[0045] [Figure 9] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0046] [Figure 10] 10 shows a timing diagram illustrating the operation of the pixel drive circuit in FIG. 9 according to some embodiments of the present disclosure.

[0047] [Figure 11] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0048] [Figure 12] 12 shows a timing diagram illustrating the operation of the pixel drive circuit in FIG. 11 according to some embodiments of the present disclosure.

[0049] [Figure 13] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0050] [Figure 14] 14 shows a timing diagram illustrating the operation of the pixel drive circuit in FIG. 13 according to some embodiments of the present disclosure.

[0051] [Figure 15] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0052] [Figure 16] 16 shows a timing diagram illustrating the operation of the pixel drive circuit in FIG. 15 according to some embodiments of the present disclosure.

[0053] [Figure 17] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0054] [Figure 18] 18 shows a timing diagram illustrating the operation of the pixel drive circuit in FIG. 17 according to some embodiments of the present disclosure.

[0055] [Figure 19] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0056] [Figure 20]20 shows a timing diagram illustrating the operation of the pixel drive circuit in FIG. 19 according to some embodiments of the present disclosure.

[0057] [Figure 21] 1 shows a circuit diagram of a pixel driving circuit for a light-emitting element according to some aspects of the present disclosure.

[0058] [Figure 22] 22 shows a timing diagram illustrating the operation of the pixel drive circuit in FIG. 21 according to some embodiments of the present disclosure.

[0059] [Figure 23] 7 illustrates an application of a pixel driving circuit 700 according to some aspects of the present disclosure.

[0060] [Figure 24] 9 illustrates an application of a pixel driving circuit 900 according to some aspects of the present disclosure.

[0061] [Figure 25] 11 illustrates an application of a pixel driving circuit 1100 according to some aspects of the present disclosure.

[0062] [Figure 26] 13 illustrates an application of a pixel driving circuit 1300 according to some aspects of the present disclosure.

[0063] [Figure 27] 13 illustrates an application of a pixel driving circuit 1300 according to some aspects of the present disclosure.

[0064] [Figure 28] 11 illustrates an application of a pixel driving circuit 1100 according to some aspects of the present disclosure.

[0065] [Figure 29] 1 shows a flowchart of a method for a pixel circuit to drive a light emitting element according to some aspects of the present disclosure.

[0066] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE INVENTION

[0067] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. It is contemplated that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It is further contemplated that the present disclosure may be used in a variety of other applications.

[0068] It should be noted that references herein to "one embodiment," "one embodiment," "exemplary embodiment," "some embodiments," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily all embodiments may include such a particular feature, structure, or characteristic. Moreover, such references do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is contemplated that such feature, structure, or characteristic may also be used in connection with other embodiments, whether or not explicitly described.

[0069] Generally, terminology can be understood, at least in part, from contextual usage. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on context. Similarly, terms such as "a," "an," or "the" can be understood to convey singular use or plural use, again depending at least in part on context. Additionally, the term "based on" may not necessarily be understood as intended to convey an exclusive set of elements, but rather may allow for the presence of additional elements not necessarily explicitly recited, again depending at least in part on the context.

[0070] As disclosed in detail below, pixel circuits for light emitting elements disclosed herein, such as organic light emitting elements (OLEDs) and micro LEDs, among other novel features, can improve various display specifications. It should be understood that the light emitting elements described herein are for illustrative purposes only, and that other types of light emitting elements may also be applicable.

[0071] 1 illustrates an apparatus 100 including a display 102 and control logic 104 according to some aspects of the present disclosure. The apparatus 100 may be any suitable device, such as a VR, AR, or MR device (e.g., a VR headset, etc.), a handheld device (e.g., a dumbbell or smartphone, a tablet, etc.), a wearable device (e.g., eyeglasses, a wristwatch, etc.), an automobile control station, a gaming console, a television set, a laptop computer, a desktop computer, a notebook computer, a media center, a set-top box, a global positioning system (GPS), an electronic billboard, an electronic sign, a printer, or any other suitable device. In some implementations, the display 102 is operably coupled to the control logic 104 and is part of the apparatus 100, such as, but not limited to, an HMD, a handheld device screen, a computer monitor, a television screen, a dashboard, an electronic billboard, or an electronic sign. The display 102 may be an OLED display, a microLED display, a liquid crystal display (LCD), an electronic ink display, an electroluminescent display (ELD), an LED or incandescent billboard display, or any other suitable type of display.

[0072] Control logic 104 may be any suitable hardware, software, firmware, or combination thereof configured to receive display data 106 (e.g., pixel data) and to generate control signals 108 for driving sub-pixels on display 102. Control signals 108 are used to control the writing of display data 106 to the sub-pixels and to direct the operation of display 102. For example, sub-pixel rendering (SPR) algorithms for various sub-pixel arrangements may be part of or implemented by control logic 104. The control logic 104 may be implemented as a standalone integrated circuit (IC) chip, such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The apparatus 100 may also include any other suitable components, such as, but not limited to, tracking devices 110 (e.g., inertial sensors, cameras, eye trackers, GPS receivers, or any other suitable devices for tracking eye movements, facial expressions, head movements, body movements, and hand gestures), input devices 112 (e.g., a mouse, keyboard, remote controller, handwriting input device, microphone, scanner, etc.), and speakers (not shown).

[0073] In some implementations, apparatus 100 may be a handheld or VR / AR / MR device, such as a smartphone, tablet, or VR headset. Apparatus 100 may also include a processor 114 and memory 116. Processor 114 may be, for example, a graphics processor (e.g., a graphics processing unit (GPU)), an application processor (AP), a general-purpose processor (e.g., an APU, accelerated processing unit; GPGPU, general-purpose computing on GPU), or any other suitable processor. Memory 116 may be, for example, a discrete frame buffer or integrated memory. Processor 114 is configured to generate display data 106 in display frames and may temporarily store display data 106 in memory 116 before transmitting it to control logic 104. Processor 114 may also generate other data, such as, but not limited to, control instructions 118 or test signals, and provide them to control logic 104 directly or through memory 116. The control logic 104 then receives the display data 106 from the memory 116 or directly from the processor 114 .

[0074] 2 shows a block diagram of the display 102 shown in FIG. 1 including drive circuitry, according to some embodiments of the present disclosure. In some implementations, the display 102 may include a display panel having an active area 200 including a plurality of subpixels. The display panel may also include on-panel drive circuitry, such as gate drive circuitry 202 and source drive circuitry 204. It should be understood that in some implementations, the gate drive circuitry 202 and source drive circuitry 204 may not be on-panel drive circuitry, i.e., may not be part of the display panel, but instead may be operably coupled to the display panel.

[0075] Each subpixel may be any of the constituent units of a pixel (i.e., a subdivision of a pixel). For example, a subpixel may be a monochrome display element that can be addressed individually. In some implementations where the display 102 is a light-emitting element display (e.g., an OLED display or a microLED display), each subpixel may include a light-emitting element (e.g., an OLED or microLED) and pixel circuitry for driving the light-emitting element. Multiple subpixels (and their light-emitting elements) may be arranged in an array having multiple rows and columns according to any suitable subpixel arrangement. Each light-emitting element may emit light at a predetermined brightness and in a predetermined color, such as, but not limited to, red, green, blue, yellow, cyan, magenta, or white. Each pixel circuit includes a thin-film transistor (TFT) and a capacitor and is configured to drive the corresponding subpixel by controlling light emission from the respective light-emitting element according to a control signal 108 from the control logic 104. The pixel circuit may be a 2T1C configuration (i.e., including a switching transistor, a drive transistor and a storage capacitor), or may include a compensation circuit with more transistors and / or capacitors for brightness uniformity, such as in a 7T1C, 5T1C, 5T2C or 6T1C configuration.

[0076] In some implementations, the gate drive circuit 202 is operably coupled to the active area 200 via a plurality of gate lines G1-Gm (also known as scan lines) and is configured to scan the plurality of sub-pixels. For example, the gate drive circuit 202 applies a plurality of scan signals, generated based on control signals 108 from the control logic 104, to the plurality of gate lines G1-Gm for scanning the plurality of sub-pixels in a gate scan order. During a scan period, the scan signals are applied to the gate electrodes of the switching transistors of each pixel circuit, turning the switching transistors on so that the data signals of the corresponding sub-pixels can be written by the source drive circuit 204. Although one gate drive circuit 202 is shown in FIG. 2, it should be understood that in some embodiments, a plurality of gate drive circuits may operate in conjunction with each other to scan the sub-pixels.

[0077] In some implementations, a source driver circuit 204 is operably coupled to the active area 200 via multiple source lines S1-Sn (also known as data lines) and configured to write display data 106 in a frame to multiple sub-pixels. For example, the source driver circuit 204 may simultaneously apply multiple data signals to the multiple source lines S1-Sn of these sub-pixels. That is, the source driver circuit 204 may include one or more shift registers, digital-to-analog converters (DACs), multiplexers (MUXs), and arithmetic circuits for controlling the timing of voltage application to the source electrodes of the switching transistors of each pixel circuit (i.e., during the scanning period in each frame) and the magnitude of the applied voltages according to the gradation of the display data 106. While one source driver circuit 204 is shown in FIG. 2, it should be understood that in some implementations, multiple source driver circuits may operate in conjunction with each other to apply data signals to the source lines of these sub-pixels.

[0078] Additionally, an emission drive circuit 206 may be included on the display panel. The emission drive circuit 206 may be operatively coupled to the active area 200 and configured to apply emission signals to emission lines E1-Ek to cause each subpixel to emit light for a particular period of time in each frame. While one emission drive circuit 206 is shown in FIG. 2, it should be understood that in some implementations, multiple emission drive circuits may operate in conjunction with one another.

[0079] FIG. 3 shows a circuit diagram of a pixel drive circuit 300 for a light-emitting element 302 according to some embodiments of the present disclosure. The light-emitting element 302 may be an OLED or micro-OLED driven by the pixel drive circuit 300. The pixel drive circuit 300 includes a p-type drive transistor 304 and a capacitor 306 (e.g., a storage capacitor). In some implementations, the pixel drive circuit 300 may further include a switch (e.g., a switching transistor or a discharge control switch) or other element. As shown in FIG. 3 , the maximum value of the gate-drain voltage (VGD) of the p-type drive transistor 304 may be (VDD−VSS), the maximum value of the body-drain voltage (VBD) of the p-type drive transistor 304 may be (VDD−VSS−VOLED_Min), and the minimum voltage at the anode of the light-emitting element 302 may be (VSS+VOLED_Min). In some implementations, the gate-drain voltage (VGD) of the p-type drive transistor 304 or the body-drain voltage (VBD) of the p-type drive transistor 304 may exceed the breakdown voltage of the p-type drive transistor 304.

[0080] FIG. 4 shows a circuit diagram of another pixel drive circuit 400 for a light-emitting element 402 according to some embodiments of the present disclosure. The light-emitting element 402 may be an OLED or micro-OLED driven by the pixel drive circuit 400. The pixel drive circuit 400 includes an n-type drive transistor 404 and a capacitor 406 (e.g., a storage capacitor). In some implementations, the pixel drive circuit 400 may further include a switch (e.g., a switching transistor or a discharge control switch) or other element. As shown in FIG. 4 , the maximum value of the drain-gate voltage (VDG) of the n-type drive transistor 404 may be (VDD-VSS), the maximum value of the drain-body voltage (VDB) of the n-type drive transistor 404 may be (VDD-VSS), and the minimum voltage at the anode of the light-emitting element 402 may be (VSS+VOLED_Min). In some implementations, the drain-gate voltage (VDG) of the n-type drive transistor 404 or the drain-body voltage (VDB) of the n-type drive transistor 404 may exceed the breakdown voltage of the n-type drive transistor 404.

[0081] 5 shows a circuit diagram of a pixel drive circuit 500 for a light-emitting element 502 according to some embodiments of the present disclosure. As shown in FIG. 5 , an n-type transistor 506 is connected to a p-type transistor 508 to drive the light-emitting element 502. In some implementations, the n-type transistor 506 and the p-type transistor 508 are collectively referred to as a pixel core 504. A capacitor 510 (C1) is coupled between the gate of the n-type transistor 506 and the gate of the p-type transistor 508, and a bias V3 is provided to the gate of the p-type transistor 508. In some implementations, a bias V4 may also be provided to the body of the n-type transistor 506, and a bias V5 may also be provided to the body of the p-type transistor 508. 5, the maximum value of the drain-gate voltage (VDG) of the n-type transistor 506 may be (VDD-V3) less than (VDD-VSS), and the maximum value of the drain-body voltage (VDB) of the n-type transistor 506 may be (VDD-V4) less than (VDD-VSS). In addition, as shown in FIG. 5, the maximum value of the gate-drain voltage (VGD) of the p-type transistor 508 may be (V3-VSS-VOLED_Min) less than (VDD-VSS), and the maximum value of the body-drain voltage (VBD) of the p-type transistor 508 may be (V5-VSS-VOLED_Min) less than (VDD-VSS-VOLED-Min). The minimum voltage at the anode of the light-emitting element 502 may be (VSS+VOLED_Min). In this circuit structure, when the light-emitting element 502 is driven using a high (VDD-VSS), the drain-gate voltage (VDG) of the n-type transistor 506, the gate-drain voltage (VGD) of the p-type transistor 508, the drain-body voltage (VDB) of the n-type transistor 506, or the body-drain voltage (VBD) of the p-type transistor 508 are operated within a safe bias range.

[0082] FIG. 6A shows a circuit diagram of a pixel drive circuit 600 for a light-emitting element 602 according to some embodiments of the present disclosure. As shown in FIG. 6A, the pixel drive circuit 600 includes a first transistor 606, a second transistor 608, and a first capacitor 610. In some implementations, the first transistor 606 and the second transistor 608 are different types of transistors. In some implementations, the first transistor 606 is an n-type transistor, and the second transistor 608 is a p-type transistor. In some implementations, the first transistor 606 and the second transistor 608 are collectively referred to as a pixel core 604. The first transistor 606 is configured to receive a data signal VDATA and drive the light-emitting element 602 based on the data signal. The first transistor 606 includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor 608 includes a second gate terminal receiving a bias signal from the bias source V3, a second source terminal coupled to the source terminal of the first transistor 606, and a second drain terminal coupled to the light-emitting element 602. A first capacitor 610 (C1) is disposed between the first gate terminal of the first transistor 606 and the second gate terminal of the second transistor 608.

[0083] 6A , the pixel drive circuit 600 further includes a drive subcircuit 620 and a data write subcircuit 630. The drive subcircuit 620 is coupled to the first gate terminal and the first drain terminal of the first transistor 606 to selectively provide a bias signal from a bias source VDD to the first transistor 606, the second transistor 608, and the light-emitting element 602. The data write subcircuit 630 is coupled to the drive subcircuit 620 to selectively provide a data signal to the first transistor 606 and the second transistor 608. A second capacitor 612 (C2) is disposed between the drive subcircuit 620 and the data write subcircuit 630.

[0084] It is understood that the drive subcircuit 620 may be an initialization / compensation / drive subcircuit according to different operation periods. For example, in some implementations, during the initialization period P1, the function of the drive subcircuit 620 may be an initialization circuit. As another example, in some implementations, during the compensation period P2, the function of the drive subcircuit 620 may be a compensation circuit. As a further example, in some implementations, during the light emission period P4, the function of the drive subcircuit 620 may be a light emission drive circuit. Detailed operations of the initialization period P1, the compensation period P2, and the light emission period P4 are discussed below.

[0085] In some implementations, when a drive circuit is used to drive a display panel, the source drive circuit may provide display data, such as a data signal VDATA, to multiple sub-pixels, such as light-emitting elements 602, via multiple source lines in a frame. In some implementations, the switching operation of the data signal VDATA may be controlled by providing switching signals S2-1, S2-2... to the data writing sub-circuit 630. Additionally, the drive sub-circuit 620 may be operatively coupled to the light-emitting elements 602 through the pixel core 604 to cause each sub-pixel (light-emitting element 602) to emit light for a specific period in each frame by providing switching signals EM, S1-1, S1-2... to the drive sub-circuit 620. In some implementations, multiple drive sub-circuits 620 may operate in conjunction with each other.

[0086] In some implementations, the scanning period of each display frame may include a reset period and an emission period, and during the emission period, the drive subcircuit 620 provides the bias signal VDD to the pixel core 604 to drive the light-emitting element 602. In some implementations, the reset period may include an initialization period, a compensation period, and a data writing period.

[0087] 6B shows another circuit diagram of a pixel drive circuit 600 for a light-emitting element 602 according to some embodiments of the present disclosure. The circuit diagram in FIG. 6B is similar to that in FIG. 6A, except that the first capacitor 610 and the gate terminal of the second transistor 608 are not coupled to the same voltage source. As shown in FIG. 6B, the gate terminal of the second transistor is connected to a bias source V3a, and an end of the first capacitor 610 is connected to a bias source V3b. In some implementations, the bias source V3a and the bias source V3b may have different voltage levels. In some implementations, the bias source V3a and the bias source V3b may have the same voltage level.

[0088] 7 shows a circuit diagram of a pixel drive circuit 700 for a light emitting element 702 according to some embodiments of the present disclosure. FIG. 8 shows a timing diagram illustrating the operation of the pixel drive circuit 700 in FIG. 7 according to some embodiments of the present disclosure. For the purpose of better explaining the present disclosure, the pixel drive circuit 700 in the timing diagrams of FIG. 7 and FIG. 8 will be discussed together.

[0089] As shown in FIG. 7 , the pixel drive circuit 700 may include a first transistor 706, a second transistor 708, a first capacitor 710, and a second capacitor 712. In some implementations, the first transistor 706 and the second transistor 708 are different types of transistors. In some implementations, the first transistor 706 is an n-type transistor and the second transistor 708 is a p-type transistor. In some implementations, the first transistor 706 and the second transistor 708 are collectively referred to as the pixel core 704. The first transistor 706 includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor 708 includes a second gate terminal receiving a bias signal from a bias source V3, a second source terminal coupled to the source terminal of the first transistor 706, and a second drain terminal coupled to the light-emitting element 702. A first capacitor 710 (C1) is disposed between the first gate terminal of the first transistor 706 and the second gate terminal of the second transistor 708.

[0090] 7. In addition, switch element S1 is disposed between the first drain terminal of the first transistor 706 and the first terminal of the second capacitor 712 (C2). Switch element S2 is disposed between the first terminal of the second capacitor 712 and the bias source VDD / V2. Switch element S3 is disposed between the first terminal of the second capacitor 712 and the first gate terminal of the first transistor 706. In some implementations, the drive subcircuit 620 in FIGS. 6A and 6B collectively includes switch element S1, switch element S2, and switch element S3 in FIG. 7. In some implementations, switch element S1, switch element S2, and switch element S3 may be realized using switching transistors or other suitable elements.

[0091] 7, switch element S12 is disposed between the second terminal of second capacitor 712 and the data signal source providing data signal VDATA, and switch element S13 is disposed between the second end of second capacitor 712 and bias source V1. In some implementations, data write sub-circuit 630 in FIGS. 6A and 6B may collectively include switch element S12 and switch element S13. In some implementations, switch element S12 and switch element S13 may be implemented using switching transistors or other suitable elements.

[0092] 8 , during the initialization period P1, a reset signal RS may connect a reset bias VR to the anode of the light-emitting element 702 to initiate the reset period, a control signal S1-1 may turn on a switch element S2 to connect a first end of the second capacitor 712 and a gate terminal of the first transistor 706, a control signal EM may turn on a switch element S2 to connect a bias source G and a first end of the second capacitor 712, and a control signal S2-1 may turn on a switch element S13 to connect a bias source V1 and a second end of the second capacitor 712. In some implementations, the bias source G may collectively provide a bias voltage V2 and a light-emitting voltage VDD for different periods. In some implementations, during the initialization period P1, a first end of the first capacitor 710 is initialized to a first initialization bias V2, and a first end of the second capacitor 712 is initialized to a second initialization bias V1.

[0093] In some implementations, during the initialization period P1, the gate terminal of the first transistor 706 may have an initial voltage. In some implementations, the initial voltage is a first initialization bias V2. In other words, (VG_N1 = V2 = initial voltage). In some implementations, during the initialization period P1, the voltage between the two ends of the first capacitor 710 may be (V2 - V3). In other words, (VCAP_C1 = V2 - V3). In some implementations, if the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source, the voltage between the two ends of the first capacitor 710 may be (V2 - V3b), as shown in FIG. 6B. In other words, (VCAP_C1 = V2 - V3b).

[0094] During the compensation period P2, the control signal EM may turn off the switch element S2, and the control signal S1-2 may turn on the switch element S1. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0095] In some implementations, during the compensation period P2, the voltage level at the gate terminal of the first transistor 706 may be equal to the sum of the threshold voltage of the first transistor 706, the threshold voltage of the second transistor 708, and the voltage V3. In other words, (VG_N1=VTH_N1+VTH_P1+V3). In some implementations, if the first capacitor 610 and the gate terminals of the second transistor 608 are not coupled to the same voltage source, then (VG_N1=VTH_N1+VTH_P1+V3a), as shown in FIG. 6B. In some implementations, during the compensation period P2, the voltage difference between the two ends of the first capacitor 710 may be the sum of the threshold voltage of the first transistor 706 and the threshold voltage of the second transistor 708. In other words, (VCAP_C1=VTH_N1+VTH_P1). In some implementations, when the first capacitor 610 and the gate terminal of the second transistor 608 are not coupled to the same voltage source, the voltage difference between the two ends of the first capacitor 710 is (VCAP_C1=VTH_N1+VTH_P1+(V3a-V3b)), as shown in FIG. 6B.

[0096] During the data writing period P3, the control signal S1-2 may turn off the switch element S1, the control signal S2-1 may turn off the switch element S13, and the control signal S2-2 may turn on the switch element S12. In some implementations, during the data writing period P3, the data signal VDATA is provided to the second end of the second capacitor 712.

[0097] In some implementations, during the write period P3, the voltage difference between the two ends of the first capacitor 710 may be the sum of the threshold voltage of the first transistor 706, the threshold voltage of the second transistor 708, and the partial voltage at the second end of the second capacitor 712 divided by the first capacitor 710 and the second capacitor 712. In other words, the voltage difference between the two ends of the first capacitor 710 is (VCAP_C1=VTH_N1+VTH_P1+ΔV_2 ndIn some implementations, if the first capacitor 610 and the gate terminal of the second transistor 608 are not coupled to the same voltage source, the voltage difference between the two ends of the first capacitor 710 is (VCAP_C1=VTH_N1+VTH_P1+(V3a-V3b)+ΔV_2 nd end_C2*C2 / (C1+C2)).

[0098] During the light-emitting period P4, the reset signal RS may disconnect the reset bias VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM may turn the switch element S2 on again to provide the light-emitting voltage VDD, the control signal S1-1 may turn the switch element S2 off, and the control signal S2-2 may turn the switch element S12 off. In some implementations, during the light-emitting period P4, the light-emitting voltage VDD may drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0099] In some implementations, a current I EM is (1 / 2*μn*Cox*W_N1 / L_N1*(VGS_N1VTH_N1) 2 ) or (1 / 2*μp*Cox*W_P1 / L_P1*(VSG_P1-VTH_P1]) 2 ), where W / L is the aspect ratio of the first transistor 606 or the second transistor 608, μ is the channel carrier mobility, and Cox is the capacitance of the channel insulating layer of the first transistor 606 or the second transistor 608. In some implementations, the gate-source voltage (VGS) of the first transistor 606 is given by VGS_N1=[α*ΔV_2 nd end_C2*C2 / (C1+C2)]+VTH_N1, and the gate-source voltage (VGS) of the second transistor 608 is VGS_P1=[β*ΔV_2 nd end_C2*C2 / (C1+C2)]+VTH_P1, where α+β=1.

[0100] In this circuit structure, when the light-emitting element 702 is driven using a high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0101] 9 shows a circuit diagram of another pixel drive circuit 900 for a light emitting element 702 according to some embodiments of the present disclosure. FIG. 10 shows a timing diagram illustrating the operation of the pixel drive circuit 900 in FIG. 9 according to some embodiments of the present disclosure. For the purpose of better explaining the present disclosure, the pixel drive circuit 900 in FIG. 9 and the timing diagram of FIG. 10 will be discussed together.

[0102] 9, the drive sub-circuit 620 in FIGS. 6A and 6B collectively includes switch element S1, switch element S2, and switch element S3 in FIG. 9 and is similar to the circuit structure in FIG. 7. The data write sub-circuit 630 in FIGS. 6A and 6B may include switch element S14 in FIG. 9. Switch element S14 is disposed between the second end of the second capacitor 712 and a bias source D. In some implementations, the bias source D may provide a bias voltage V1 and a data signal VDATA for different periods of time.

[0103] 10 , during the initialization period P1, a reset signal RS may connect a reset bias VR to the anode of the light-emitting element 702 to initiate the reset period, a control signal S1-1 may turn on a switch element S2 to connect a first end of the second capacitor 712 and a gate terminal of the first transistor 706, a control signal EM may turn on a switch element S2 to connect a bias source G and a first end of the second capacitor 712, and a control signal S2-1 may turn on a switch element S14 to connect a bias source V1 and a second end of the second capacitor 712. In some implementations, the bias source G may collectively provide a bias voltage V2 and a light-emitting voltage VDD for different periods. In some implementations, during the initialization period P1, a first end of the first capacitor 710 is initialized to a first initialization bias V2, and a first end of the second capacitor 712 is initialized to a second initialization bias V1.

[0104] During the compensation period P2, the control signal EM may turn off the switch element S2, and the control signal S1-2 may turn on the switch element S1. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0105] During the data writing period P3, the control signal S1-2 may turn off the switch element S1, the control signal S2-1 may keep the switch element S14 on, and the bias source D may be changed to provide the data signal VDATA instead of providing the bias voltage V1.

[0106] During the light-emitting period P4, the reset signal RS may disconnect the reset bias VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM may turn the switch element S2 back on to provide the light-emitting voltage VDD, the control signal S1-1 may turn the switch element S2 off, and the control signal S2-1 may turn the switch element S14 off. In some implementations, during the light-emitting period P4, the light-emitting voltage VDD may drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0107] In this circuit structure, when the light-emitting element 702 is driven using a high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0108] 11 shows a circuit diagram of another pixel drive circuit 1100 for a light emitting element 702 according to some embodiments of the present disclosure. FIG. 12 shows a timing diagram illustrating the operation of the pixel drive circuit 1100 in FIG. 11 according to some embodiments of the present disclosure. For the purpose of better explaining the present disclosure, the pixel drive circuit 1100 in the timing diagrams of FIG. 11 and FIG. 12 will be discussed together.

[0109] 11, switch element S4 is disposed between bias source G and the first end of second capacitor 712, and switch element S5 is disposed between the first end of second capacitor 712 and the gate of first transistor 706. In some implementations, drive subcircuit 620 in FIGS. 6A and 6B collectively includes switch element S4 and switch element S5 in FIG. 1. In some implementations, switch element S4 and switch element S5 may be realized using switching transistors or other suitable elements.

[0110] 11, switch element S12 is disposed between the second end of second capacitor 712 and the data signal source providing data signal VDATA, and switch element S13 is disposed between the second end of second capacitor 712 and bias source V1. In some implementations, data write subcircuit 630 in FIGS. 6A and 6B may collectively include switch element S12 and switch element S13. In some implementations, switch element S12 and switch element S13 may be realized using switching transistors or other suitable elements. In some implementations, the structure and operation of switch element S12 and switch element S13 in FIG. 11 may be similar to switch element S12 and switch element S13 in FIG. 7.

[0111] 12 , during the initialization period P1, a reset signal RS may connect a reset bias VR to the anode of the light-emitting element 702 to initiate the reset period, a control signal S1-1 may turn on a switch element S5 to connect a first end of the second capacitor 712 and a gate terminal of the first transistor 706, and a control signal EM may turn on a switch element S4 to connect a bias source G and a first end of the second capacitor 712. In some implementations, the bias source G may collectively provide a bias voltage V2 and a light-emitting voltage VDD for different periods. In some implementations, during the initialization period P1, a first end of the first capacitor 710 is initialized to a first initialization bias V2, and a second end of the second capacitor 712 is initialized to a second initialization bias V1.

[0112] During the compensation period P2, the control signal EM may turn off the switch element S4. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0113] During the data writing period P3, the control signal S2-1 may turn off the switch element S13, and the control signal S2-2 may turn on the switch element S12. In some implementations, during the data writing period P3, the data signal VDATA is provided to the second end of the second capacitor 712.

[0114] During the light-emitting period P4, the reset signal RS may disconnect the reset bias VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM may turn the switch element S4 back on to provide the light-emitting voltage VDD, the control signal S1-1 may turn off the switch element S5, and the control signal S2-2 may turn off the switch element S12. In some implementations, during the light-emitting period P4, the light-emitting voltage VDD may drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0115] In this circuit structure, when the light-emitting element 702 is driven using a high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0116] 13 shows a circuit diagram of another pixel drive circuit 1300 for a light emitting element 702 according to some embodiments of the present disclosure. FIG. 14 shows a timing diagram illustrating the operation of the pixel drive circuit 1300 in FIG. 13 according to some embodiments of the present disclosure. For the purpose of better explaining the present disclosure, the pixel drive circuit 1300 in FIG. 13 and the timing diagram of FIG. 14 will be discussed together.

[0117] 13, the drive sub-circuit 620 in Figures 6A and 6B collectively includes switch element S4 and switch element S5 in Figure 13, and is similar to the circuit structure in Figure 11. The data write sub-circuit 630 in Figures 6A and 6B may include switch element S14 in Figure 13, which is similar to switch element S14 in Figure 9.

[0118] 14 , during the initialization period P1, a reset signal RS may connect a reset bias VR to the anode of the light-emitting element 702 to initiate the reset period, a control signal S1-1 may turn on a switch element S5 to connect a first end of the second capacitor 712 and a gate terminal of the first transistor 706, and a control signal EM may turn on a switch element S4 to connect a bias source G and a first end of the second capacitor 712. In some implementations, the bias source G may collectively provide a bias voltage V2 and a light-emitting voltage VDD for different periods. In some implementations, during the initialization period P1, a first end of the first capacitor 710 is initialized to a first initialization bias V2, and a second end of the second capacitor 712 is initialized to a second initialization bias V1.

[0119] During the compensation period P2, the control signal EM may turn off the switch element S4. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0120] During the data writing period P3, the control signal S2-1 may hold the switch element S14 on, and the bias source D may be changed to provide the data signal VDATA instead of providing the bias voltage V1.

[0121] During the light-emitting period P4, the reset signal RS may disconnect the reset bias VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM may turn the switch element S4 back on to provide the light-emitting voltage VDD, the control signal S1-1 may turn off the switch element S5, and the control signal S2-1 may turn off the switch element S14. In some implementations, during the light-emitting period P4, the light-emitting voltage VDD may drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0122] In this circuit structure, when the light-emitting element 702 is driven using a high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0123] 15 shows a circuit diagram of another pixel drive circuit 1500 for a light emitting element 702 according to some embodiments of the present disclosure. FIG. 16 shows a timing diagram illustrating the operation of the pixel drive circuit 1500 in FIG. 15 according to some embodiments of the present disclosure. For the purpose of better explaining the present disclosure, the pixel drive circuit 1500 in the timing diagrams of FIG. 15 and FIG. 16 will be discussed together.

[0124] 15, switch element S6 is disposed between bias source VDD and the first drain terminal of first transistor 706, switch element S7 is disposed between the first drain terminal of first transistor 706 and the first end of second capacitor 712, and switch element S8 is disposed between the first end of second capacitor 712 and bias source V2. In some implementations, drive subcircuit 620 in FIGS. 6A and 6B collectively includes switch elements S6, S7, and S8 in FIG. 15. In some implementations, switch elements S6, S7, and S8 may be realized using switching transistors or other suitable elements.

[0125] 15, switch element S12 is disposed between the second end of second capacitor 712 and the data signal source providing data signal VDATA, and switch element S13 is disposed between the second end of second capacitor 712 and bias source V1. In some implementations, data write sub-circuit 630 in FIGS. 6A and 6B may collectively include switch element S12 and switch element S13. In some implementations, switch element S12 and switch element S13 may be implemented using switching transistors or other suitable elements.

[0126] 16 , during the initialization period P1, a reset signal RS may connect a reset bias VR to the anode of the light-emitting element 702 to start the reset period, and a control signal S1-1 may turn on a switch element S8 to connect a bias source V2 to a first end of the second capacitor 712 and a gate terminal of the first transistor 706. A control signal S2-1 may turn on a switch element S13 to connect the bias source V1 and a second end of the second capacitor 712. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to a first initialization bias V2, and the first end of the second capacitor 712 is initialized to a second initialization bias V1.

[0127] During the compensation period P2, a control signal S1-1 may turn off switch element S8, and a control signal S1-2 may turn on switch element S7. In some implementations, during the compensation period P2, a gate terminal of the first transistor 706, a first end of the first capacitor 710, and a first end of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some implementations, an initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0128] During the data writing period P3, the control signal S1-2 may turn off the switch element S7, the control signal S2-1 may turn off the switch element S13 to disconnect the bias source V1 and the second end of the second capacitor 712, and the control signal S2-2 may turn on the switch element S12. In some implementations, during the data writing period P3, the data signal VDATA is provided to the second end of the second capacitor 712.

[0129] During the light-emitting period P4, the reset signal RS may disconnect the reset bias VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM may turn on the switch element S6 to provide the light-emitting voltage VDD, and the control signal S2-2 may turn off the switch element S12. In some implementations, during the light-emitting period P4, the light-emitting voltage VDD may drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0130] In this circuit structure, when the light-emitting element 702 is driven using a high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0131] 17 shows a circuit diagram of another pixel drive circuit 1700 for a light emitting element 702 according to some embodiments of the present disclosure. FIG. 18 shows a timing diagram illustrating the operation of the pixel drive circuit 1700 in FIG. 17 according to some embodiments of the present disclosure. For the purpose of better explaining the present disclosure, the pixel drive circuit 1700 in the timing diagrams of FIG. 17 and FIG. 18 will be discussed together.

[0132] 17, the drive sub-circuit 620 in Figures 6A and 6B collectively includes switch element S6, switch element S7, and switch element S8 in Figure 17, and is similar to the circuit structure in Figure 15. The data write sub-circuit 630 in Figures 6A and 6B may include switch element S14 in Figure 17, which is similar to switch element S14 in Figure 9.

[0133] 18 , during the initialization period P1, a reset signal RS may connect a reset bias VR to the anode of the light-emitting element 702 to start the reset period, and a control signal S1-1 may turn on a switch element S8 to connect a bias source V2 to a first end of the second capacitor 712 and a gate terminal of the first transistor 706. A control signal S2-1 may turn on a switch element S14 to connect a bias source D and a second end of the second capacitor 712. In some implementations, during the initialization period P1, a first end of the first capacitor 710 is initialized to a first initialization bias V2, and a first end of the second capacitor 712 is initialized to a second initialization bias V1.

[0134] During the compensation period P2, a control signal S1-1 may turn off switch element S8, and a control signal S1-2 may turn on switch element S7. In some implementations, during the compensation period P2, a gate terminal of the first transistor 706, a first end of the first capacitor 710, and a first end of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some implementations, an initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0135] During the data write period P3, the control signal S1-2 may turn off the switch element S7, and the control signal S2-1 may keep the switch element S14 on. The bias source D is changed from providing the bias V1 to providing the data signal VDATA.

[0136] During the light-emitting period P4, the reset signal RS may disconnect the reset bias VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM may turn on the switch element S6 to provide the light-emitting voltage VDD, and the control signal S2-1 may turn off the switch element S14. In some implementations, during the light-emitting period P4, the light-emitting voltage VDD may drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0137] In this circuit structure, when the light-emitting element 702 is driven using a high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0138] 19 shows a circuit diagram of another pixel drive circuit 1900 for a light emitting element 702 according to some embodiments of the present disclosure. FIG. 20 shows a timing diagram illustrating the operation of the pixel drive circuit 1900 in FIG. 19 according to some embodiments of the present disclosure. For the purpose of better explaining the present disclosure, the pixel drive circuit 1900 in FIG. 19 and the timing diagram of FIG. 20 will be discussed together.

[0139] 19, switch element S9 is disposed between bias source G and the first drain terminal of first transistor 706, switch element S10 is disposed between the first drain terminal of first transistor 706 and a first end of second capacitor 712, and switch element S11 is disposed between the first end of second capacitor 712 and the gate terminal of first transistor 706. In some implementations, drive subcircuit 620 in FIGS. 6A and 6B collectively includes switch elements S9, S10, and S11 in FIG. 19. In some implementations, switch elements S9, S10, and S11 may be realized using switching transistors or other suitable elements.

[0140] 19, switch element S12 is disposed between the second end of second capacitor 712 and the data signal source providing data signal VDATA, and switch element S13 is disposed between the second end of second capacitor 712 and bias source V1. In some implementations, data write sub-circuit 630 in FIGS. 6A and 6B may collectively include switch element S12 and switch element S13. In some implementations, switch element S12 and switch element S13 may be realized using switching transistors or other suitable elements.

[0141] 20 , during the initialization period P1, a reset signal RS may connect a reset bias VR to the anode of the light-emitting element 702 to initiate the reset period, and a control signal S1-1 may turn on a switch element S11 to connect the gate terminal of the first transistor 706 to the first end of the second capacitor 712. A control signal EM may turn on a switch element S9 to provide a bias signal V2 to the drain terminal of the first transistor 706. A control signal S1-2 may turn on a switch element S10 to connect the first end of the second capacitor 712 and the drain terminal of the first transistor 706. A control signal S2-1 may turn on a switch element S13 to connect the bias source V1 and the second end of the second capacitor 712. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to a first initialization bias V2, and the first end of the second capacitor 712 is initialized to a second initialization bias V1.

[0142] During the compensation period P2, the control signal EM may turn off the switch element S9. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0143] During the data writing period P3, the control signal S1-2 may turn off the switch element S10, the control signal S2-1 may turn off the switch element S13 to disconnect the bias source V1 and the second end of the second capacitor 712, and the control signal S2-2 may turn on the switch element S12. In some implementations, during the data writing period P3, the data signal VDATA is provided to the second end of the second capacitor 712.

[0144] During the light-emitting period P4, the reset signal RS may disconnect the reset bias VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM may turn the switch element S9 back on to provide the light-emitting voltage VDD, and the control signal S2-2 may turn off the switch element S12. In some implementations, during the light-emitting period P4, the light-emitting voltage VDD may drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0145] In this circuit structure, when the light-emitting element 702 is driven using a high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0146] Figure 21 shows a circuit diagram of another pixel drive circuit 2100 for a light emitting element 702 according to some embodiments of the present disclosure. Figure 22 shows a timing diagram illustrating the operation of the pixel drive circuit 2100 in Figure 21 according to some embodiments of the present disclosure. For the purpose of better explaining the present disclosure, the pixel drive circuit 2100 in Figure 21 and the timing diagram of Figure 22 will be discussed together.

[0147] 21, the drive sub-circuit 620 in Figures 6A and 6B collectively includes switch element S9, switch element S10, and switch element S11 in Figure 21, and is similar to the circuit structure in Figure 19. The data write sub-circuit 630 in Figures 6A and 6B may include switch element S14 in Figure 21, which is similar to switch element S14 in Figure 9.

[0148] 22 , during the initialization period P1, a reset signal RS may connect a reset bias VR to the anode of the light-emitting element 702 to initiate the reset period, and a control signal S1-1 may turn on a switch element S11 to connect the gate terminal of the first transistor 706 to the first end of the second capacitor 712. A control signal EM may turn on a switch element S9 to provide a bias signal V2 to the drain terminal of the first transistor 706. A control signal S1-2 may turn on a switch element S10 to connect the first end of the second capacitor 712 and the drain terminal of the first transistor 706. A control signal S2-1 may turn on a switch element S14 to connect the bias source D and the second end of the second capacitor 712. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to a first initialization bias V2, and the first end of the second capacitor 712 is initialized to a second initialization bias V1.

[0149] During the compensation period P2, the control signal EM may turn off the switch element S9. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 are coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0150] During the data write period P3, the control signal S1-2 may turn off the switch element S10, the control signal S2-1 may keep the switch element S14 on, and the bias source D is changed from providing the bias V1 to providing the data signal VDATA.

[0151] During the light-emitting period P4, the reset signal RS may disconnect the reset bias VR from the anode of the light-emitting element 702 to start the light-emitting period, the control signal EM may turn the switch element S9 back on to provide the light-emitting voltage VDD, and the control signal S2-1 may turn off the switch element S14. In some implementations, during the light-emitting period P4, the light-emitting voltage VDD may drive the light-emitting element 702 to emit light based on the data signal VDATA.

[0152] In this circuit structure, when the light-emitting element 702 is driven using a high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0153] 23 to 26 show applications of pixel driving circuits 700, 900, 1100, and 1300 according to some embodiments of the present disclosure. As shown in FIG. 23 to 26, one data writing sub-circuit 630 may be coupled to multiple driving sub-circuits 620. In some implementations, as shown in FIG. 23 and FIG. 25, one set of second capacitor 712, switch element S12, and switch element S13 may be shared by multiple driving sub-circuits 620 to drive multiple light-emitting elements 702.

[0154] 24 and 26, one set of second capacitor 712 and switch element S14 may be shared by multiple drive sub-circuits 620 to drive multiple light-emitting elements 702. In addition, as shown in FIGS. 23 to 26, switch element S2 or switch element S4 coupled to bias source G may also be shared by multiple drive sub-circuits 620.

[0155] 27 and 28 show another application of the pixel driving circuit 1100 or 1300 according to some embodiments of the present disclosure. As shown in FIG. 27 and FIG. 28, one second capacitor 712 may be shared by multiple driving sub-circuits 620 and / or multiple data writing sub-circuits 630.

[0156] 29 shows a flowchart of a method 2900 for a pixel circuit to drive a light-emitting element according to some embodiments of the present disclosure. The pixel circuit may include a first transistor 706, a second transistor 708 disposed between the first transistor 706 and the light-emitting element 702. A first capacitor 710 is disposed between a first gate terminal of the first transistor 706 and a second gate terminal of the second transistor, and a second capacitor 712 is disposed between the first transistor 706 and a data signal source VDATA.

[0157] As shown in operation 2902 in Figure 29 , during an initialization period, a first end of the first capacitor 710 is initialized to a first initialization bias V2, and a first end of the second capacitor 712 is initialized to a second initialization bias V1. Then, as shown in operation 2904 in Figure 29 , during a compensation period, the first end of the first capacitor 710 is compensated to the compensation bias. As shown in operation 2906 in Figure 29 , during a data writing period, a data signal is provided to the first end of the second capacitor 712. As shown in operation 2908 in Figure 29 , during a light emission period, the pixel drive circuit drives the light emitting element 702 to emit light based on the data signal.

[0158] In some implementations, the pixel circuit may further include a reset bias source VR coupled to the second transistor 708 and the light emitting element 702. During the initialization period, the compensation period, and the data writing period, the reset bias VR is provided to the pixel circuit by the reset bias source.

[0159] In some implementations, the sum of the initialization period, the compensation period, the data writing period, and the light emitting period is a frame period. In some implementations, a first initialization bias V2 is provided to a first end of the first capacitor 710, and a first bias V3 is provided to a second end of the first capacitor 710. A second initialization bias V1 is provided to a first end of the second capacitor 712. The first end of the first capacitor 710 and the second end of the second capacitor 712 are coupled together.

[0160] In some implementations, the first initialization bias V2 at the first end of the first capacitor 710 is discharged to the reset bias through the first transistor 706 and the second transistor 708. The compensation bias is at least the sum of the first threshold voltage of the first transistor and the second threshold voltage of the second transistor.

[0161] The foregoing description of specific implementations may be readily modified and / or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0162] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. a first transistor configured to receive a data signal and drive a light-emitting element based on the data signal, the first transistor having a first gate terminal, a first source terminal, and a first drain terminal; a second transistor having a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light emitting element; and a first capacitor disposed between the first gate terminal and a second bias source; Equipped with the first transistor and the second transistor are different types of transistors; Pixel driving circuit.

2. a drive subcircuit coupled to the first gate terminal and the first drain terminal for selectively providing a second bias signal from a third bias source to the first transistor; and a data write subcircuit coupled to the drive subcircuit for selectively providing the data signal to the first transistor; The pixel drive circuit of claim 1 further comprising:

3. a second capacitor disposed between the drive subcircuit and the data write subcircuit; 3. The pixel drive circuit of claim 2, further comprising:

4. 4. The pixel driving circuit of claim 3, wherein a scanning period of each display frame includes a reset period and an emission period, and the driving sub-circuit provides the second bias signal to the first transistor during the emission period to drive the light-emitting element.

5. 5. The pixel drive circuit of claim 4, wherein the reset period includes an initialization period, a compensation period, and a data writing period, and the drive sub-circuit provides a first initialization bias signal to the first capacitor during the initialization period.

6. The pixel drive circuit of claim 5 , wherein the data writing sub-circuit provides a second initialization bias signal to the second capacitor during the initialization period and the compensation period.

7. The pixel drive circuit of claim 5 , wherein the data writing sub-circuit provides the data signal to the first transistor during the data writing period.

8. The drive subcircuit comprises: a first switch element disposed between the first drain terminal and a first terminal of the second capacitor; a second switch element disposed between the first terminal of the second capacitor and the third bias source; and a third switch element disposed between the first terminal and the first gate terminal of the second capacitor; having 4. A pixel driving circuit according to claim 3.

9. The drive subcircuit comprises: a fourth switch element disposed between the third bias source and the first terminal of the second capacitor; and a fifth switch element disposed between the first terminal and the first gate terminal of the second capacitor; having 4. A pixel driving circuit according to claim 3.

10. The drive subcircuit comprises: a sixth switch element disposed between the first source terminal and the third bias source; a seventh switch element disposed between the first source terminal and the first terminal of the second capacitor; and an eighth switch element disposed between the first terminal of the second capacitor and a first initialization bias source; having 4. A pixel driving circuit according to claim 3.

11. The drive subcircuit comprises: a ninth switch element disposed between the first source terminal and the third bias source; a tenth switch element disposed between the first source terminal and the first terminal of the second capacitor; and an eleventh switch element disposed between the first terminal and the first gate terminal of the second capacitor; having 4. A pixel driving circuit according to claim 3.

12. The data write subcircuit comprises: a twelfth switch element disposed between the second terminal of the second capacitor and a data signal source; and a thirteenth switch element disposed between the second terminal of the second capacitor and a second initialization bias source; having 4. A pixel driving circuit according to claim 3.

13. The data write subcircuit comprises: a fourteenth switch element disposed between the second terminal of the second capacitor and a data signal source; having 4. A pixel driving circuit according to claim 3.

14. The pixel drive circuit of claim 3 , wherein the data writing sub-circuit and the second capacitor are shared by more than one drive sub-circuit.

15. 15. A pixel drive circuit according to any preceding claim, wherein the first bias source and the second bias source are provided by different voltage sources.

16. 15. A pixel drive circuit according to any preceding claim, wherein the first bias source and the second bias source are provided by the same voltage source.

17. a light-emitting element; and a driving circuit for driving the light-emitting element; Equipped with The drive circuit a first type transistor for receiving a data signal and including a first gate terminal, a first source terminal, and a first drain terminal; a second type transistor including a second gate terminal receiving a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light emitting element; a first capacitor disposed between the first gate terminal and a second bias source; a drive subcircuit coupled to the first gate terminal and the first source terminal for providing the data signal and a third bias signal according to a third bias source; a data write subcircuit coupled to the drive subcircuit for providing the data signal to the drive subcircuit; and a second capacitor disposed between the drive subcircuit and the data write subcircuit; having Light-emitting device.

18. 18. The light emitting device of claim 17, wherein the first type of transistor is a p-type transistor and the second type of transistor is an n-type transistor.

19. The drive subcircuit comprises: a first switch element disposed between the first source terminal and a first terminal of the second capacitor; a second switch element disposed between the first terminal of the second capacitor and the third bias source; and a third switch element disposed between the first terminal and the first gate terminal of the second capacitor; having 18. The light emitting device of claim 17.

20. The drive subcircuit comprises: a fourth switch element disposed between the third bias source and the first terminal of the second capacitor; and a fifth switch element disposed between the first terminal and the first gate terminal of the second capacitor; 20. The light emitting device of claim 17, wherein:

21. The drive subcircuit comprises: a sixth switch element disposed between the first source terminal and the third bias source; a seventh switch element disposed between the first source terminal and the first terminal of the second capacitor; and an eighth switch element disposed between the first terminal of the second capacitor and a first initialization bias source; having 18. The light emitting device of claim 17.

22. The drive subcircuit comprises: a ninth switch element disposed between the first source terminal and the third bias source; a tenth switch element disposed between the first source terminal and the first terminal of the second capacitor; and an eleventh switch element disposed between the first terminal and the first gate terminal of the second capacitor; having 18. The light emitting device of claim 17.

23. The data write subcircuit comprises: a twelfth switch element disposed between the second terminal of the second capacitor and a data signal source; and a thirteenth switch element disposed between the second terminal of the second capacitor and a second initialization bias source; having 18. The light emitting device of claim 17.

24. The data write subcircuit comprises: a fourteenth switch element disposed between the second terminal of the second capacitor and a data signal source; having 18. The light emitting device of claim 17.

25. 20. The light emitting device of claim 17, further comprising a reset signal coupled to the second drain terminal.

26. 26. A light emitting device according to any one of claims 17 to 25, wherein the first bias source and the second bias source are provided by different voltage sources.

27. 26. A light emitting device according to any one of claims 17 to 25, wherein the first bias source and the second bias source are provided by the same voltage source.

28. 1. A method for driving a light-emitting element with a pixel circuit, the pixel circuit including: a first transistor; a second transistor disposed between the first transistor and the light-emitting element; a first capacitor disposed between a first gate terminal of the first transistor and a second gate terminal of the second transistor; and a second capacitor disposed between the first transistor and a data signal source, the method comprising: initializing a first end of the first capacitor to a first initialization bias and a first end of the second capacitor to a second initialization bias during an initialization period; compensating the first end of the first capacitor to a compensation bias during a compensation period; providing a data signal to the first end of the second capacitor during a data write period; and driving the light emitting element to emit light based on the data signal during a light emitting period; A method comprising:

29. the pixel circuit further comprising a reset bias source coupled to the second transistor and the light emitting element, the method comprising: providing a reset bias to the pixel circuit by the reset bias source during the initialization period, the compensation period, and the data writing period; 30. The method of claim 28, further comprising:

30. The method of claim 28 , wherein the sum of the initialization period, the compensation period, the data writing period, and the light emitting period is a frame period.

31. initializing the first end of the first capacitor to the first initialization bias and the first end of the second capacitor to the second initialization bias includes: providing the first initialization bias to the first end of the first capacitor; providing a first bias to a second end of the first capacitor; providing the second initialization bias to the first end of the second capacitor; and coupling the first end of the first capacitor and the second end of the second capacitor together; having 30. The method of claim 29.

32. The step of compensating the first end of the first capacitor to the compensation bias comprises: discharging the first initialization bias at the first end of the first capacitor to the reset bias through the first transistor and the second transistor; having 32. The method of claim 31 .

33. 33. The method of claim 32, wherein a voltage difference between the first end and the second end of the first capacitor is based on the sum of a first threshold voltage of the first transistor and a second threshold voltage of the second transistor.

34. 34. The method of claim 32 or 33, wherein the compensation bias is based on the sum of a first threshold voltage of the first transistor and a second threshold voltage of the second transistor.

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