High-Frequency Impedance Matching Networks Using a Flexible Tuning Algorithm

Abstract

Embodiments provided herein generally include apparatus and methods for generating plasma in a plasma processing chamber, controlled by a flexible tuning algorithm. Flexible communication between equipment in a plasma processing system enables the sharing of process information and equipment settings for evaluation and refinement of the tuning algorithms used. This improves productivity for batch processing of multiple semiconductor wafers during a manufacturing process, as tuning algorithms can be changed on the fly during processing of multiple semiconductor wafers. Tuning algorithms can be recorded, reused, and / or modified to control future plasma processes.

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION Embodiments of the present disclosure generally relate to a system including a radio frequency (RF) power source and an impedance matching network adapted to generate a plasma in a substrate processing chamber. [Background technology]

[0002] In a plasma processing chamber, an RF power source provides RF power to an electrode in the plasma processing chamber through an impedance matching network coupled between the RF power source and an electrode in the plasma processing chamber to generate plasma within the plasma processing chamber. The RF impedance of the plasma is a complex and highly variable function of numerous process parameters and conditions. The impedance matching network maximizes power transfer from the RF power source to the plasma in the reactor chamber. This is achieved when the output impedance of the impedance matching network is equal to the complex conjugate of the input impedance of the plasma in the reactor chamber. The impedance matching network transforms the impedance of the plasma in the reactor chamber to the characteristic operating output impedance of the RF power source, e.g., 50 ohms, for optimal RF power transfer from the reactor chamber.

[0003] An RF impedance matching network is an electrical module disposed between an RF power source and a plasma reactor to optimize RF power transfer efficiency. To optimize RF power transfer, it is important that the RF impedance matching network be accurately tuned to a desired complex impedance at a desired frequency. This is important for providing reliable, efficient, and predictable plasma processing results on semiconductor substrates. To ensure operational efficiency and accuracy, the RF impedance matching network relies on the accuracy of real-time plasma processing conditions, such as plasma chamber impedance, and associated RF sensors, such as RF voltage sensors, RF current sensors, and RF power sensors, used to determine the RF power delivered to the plasma chamber during semiconductor manufacturing process operation. However, during execution of a semiconductor manufacturing process on a substrate, the load impedance changes as one or more process variables change during different phases of the plasma processing recipe. Generally, most conventional impedance matching networks utilize a single tuning algorithm that adjusts variable matching components within the matching network to match the load impedance. However, it has been found that most tuning algorithms cannot adequately respond to all phases of the plasma processing recipe executed on the substrate, leading to undesirable and inconsistent plasma processing results on the substrate.

[0004] Therefore, there is a need for a system that solves the problems outlined above. Summary of the Invention

[0005] An embodiment of the present disclosure includes a system for controlling plasma generation in a plasma processing chamber. The system includes an impedance matching network having a first node adapted to couple to a radio frequency (RF) power generator, a second node adapted to couple to an electrode in the plasma processing chamber, and an adjustable tuning element for transforming at least one of a plurality of impedances at the second node to an output impedance of the RF power generator at the first node. The system further includes a tool controller in communication with the match controller and including instructions stored in a memory and executed by a processor of the tool controller to cause a sequence of process recipe steps to be performed in the plasma processing chamber, the sequence of process recipe steps including a first process recipe step, the first process recipe step, when executed by the processor, to adjust at least one process variable to a first setting and to execute a first tuning algorithm of a plurality of tuning algorithms by the match controller, wherein execution of the first tuning algorithm sets at least one of the adjustable tuning elements to the first impedance setting. The sequence of process recipe steps further includes a second process recipe step that, when executed by the processor, causes the at least one process variable to be adjusted to a second setting and causes a second tuning algorithm of the plurality of tuning algorithms to be executed by the matching controller, wherein execution of the second tuning algorithm sets at least one of the adjustable tuning elements to a second impedance setting, wherein selection of the second tuning algorithm is based on a determination that the at least one process variable is adjusted from the first setting to the second setting.

[0006] An embodiment of the present disclosure includes a method for processing a substrate in a plasma processing chamber by performing a first process recipe step of a plasma processing recipe, wherein performing the first process recipe step includes executing a first tuning algorithm through the use of a matching controller, wherein performing the first tuning algorithm adjusts at least one adjustable tuning element of an impedance matching network to at least a first impedance setting, the impedance matching network including a first node adapted for coupling to a radio frequency (RF) power generator, a second node adapted for coupling to an electrode in the plasma processing chamber, and at least one adjustable tuning element. While the first tuning algorithm is being performed by the matching controller, providing RF power through the use of the impedance matching network to an electrode disposed in the plasma processing chamber, thereby forming or maintaining a plasma with a first load impedance of a gas disposed in the plasma processing chamber. Performing a second process recipe step of the plasma processing recipe includes executing a second tuning algorithm through the use of the matching controller to set the at least one adjustable tuning element to at least a second impedance setting. Then, continuing to supply RF power to an electrode disposed within the plasma processing chamber through use of the impedance matching network, and further adjusting at least one plasma processing variable to change the first load impedance to a second load impedance while continuing to supply RF power while a second tuning algorithm is executed by the matching controller based on the adjusted at least one plasma processing variable.

[0007] An embodiment of the present disclosure includes an impedance matching network adapted for coupling between an RF power generator and a plasma processing chamber. The impedance matching network includes a first node adapted for coupling to the RF power generator, a second node adapted for coupling to an electrode in the plasma processing chamber, and an adjustable tuning element for transforming at least one of a plurality of impedances at the second node to an output impedance of the RF power generator at the first node. The impedance matching network further includes a matching controller coupled to the adjustable tuning element, the matching controller controlling setting the impedance transformation using at least one of the adjustable tuning elements by using at least one of a plurality of tuning algorithms stored in a memory.

[0008] As the above-cited features of the present disclosure may be better understood in detail, a more particular description of the present disclosure, briefly summarized herein, may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, which may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0009] [Figure 1A] 1 is a schematic block diagram of a semiconductor wafer plasma processing system in accordance with one or more embodiments of the present disclosure. [Figure 1B] 1B is a schematic diagram of a plasma processing chamber and associated plasma generating equipment forming at least a portion of the plasma processing system shown in FIG. 1A in accordance with one or more embodiments of the present disclosure. [Figure 2] FIG. 1 is a schematic block diagram of an RF power generation device in accordance with one or more embodiments of the present disclosure. [Figure 3] FIG. 1 is a schematic block diagram of an RF impedance measurement module in accordance with one or more embodiments of the present disclosure. [Figure 4] 1A-C are schematic diagrams of RF tuning circuits according to one or more embodiments of the present disclosure. [Figure 5] FIG. 1 is a schematic block diagram of a matching controller in accordance with one or more embodiments of the present disclosure. [Figure 6] FIG. 1 illustrates a graphical plot of DC wafer voltage and reflected RF power versus time for a chamber plasma process recipe performed on a substrate in a plasma processing chamber in accordance with one or more embodiments of the present disclosure. [Figure 7] 1 is a flow diagram of a tuning recipe that is coordinated with a plasma processing step during plasma processing of a semiconductor wafer in accordance with one or more embodiments of the present disclosure. [Figure 8] FIG. 10 is a flow diagram of a process that may be performed by a tool controller to oversee the execution of a tuning algorithm in accordance with one or more embodiments of the present disclosure. [Figure 9] 1 is a flow diagram for selecting a tuning algorithm based on plasma chamber conditions in accordance with one or more embodiments of the present disclosure. [Figure 10] FIG. 10 is a flow diagram that enables a tool controller to determine which of stored matching algorithms should be executed during different semiconductor manufacturing process applications in different plasma processing chambers, in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] To facilitate understanding, where possible, like reference numerals have been used to designate like elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0011] Embodiments of the present disclosure generally relate to apparatus and methods for providing an RF impedance matching network with flexible tuning algorithms that can be loaded in real time for use in different portions of a process recipe that may be used during the manufacture of semiconductor devices or other useful products. More specifically, embodiments provided herein generally include apparatus and methods for providing and using flexible RF impedance matching network tuning algorithms for controlling the delivery of RF power to a complex load formed within a plasma processing chamber during different phases of a plasma processing recipe used to process substrates within the plasma processing chamber. These RF impedance matching network tuning algorithms can be used during different portions of a process recipe executed in the plasma processing chamber when the load impedance changes due to variations in one or more plasma processing parameters. The RF impedance matching network tuning algorithms are configured to take into account measured parameter variations, such as RF voltage, current, and frequency, and make adjustments to tuning elements of the RF impedance matching network and / or RF power from an RF power generator. Furthermore, predictive adjustments can be made to slower response tuning elements of the RF impedance matching network to provide smoother and more efficient application of required RF power (voltage) to a complex load formed within the plasma processing chamber. Modifications to other process algorithms based on historical learning may also benefit and improve the overall operation of the plasma process performed in the plasma chamber.

[0012] The tuning algorithms utilized by the matching network may be stored in fast and / or slower module memories depending on their application and requirements. The fast module memory may be associated with the matching controller but may have a smaller memory capacity, while the slower memory may be associated with the tool controller, which has a larger memory capacity. Because the matching controller has extremely low time latency associated with the matching tuning elements it controls, this may be the most effective location for the tuning algorithms due to the often-fast fluctuations in load impedance experienced during most plasma processing recipes. However, it is contemplated, and within the scope of the present disclosure, that the tuning algorithms stored in the matching controller memory may be easily and rapidly changed (replaced) and / or updated using replacement tuning element control algorithms stored in the slower tool controller memory. In some embodiments, the tool controller is configured to make decisions regarding which tuning algorithms to implement by the matching controller during different phases of a chamber plasma processing recipe based on stored historical data, settings within the chamber plasma processing recipe executed by the tool controller, detected changes in one or more plasma processing variables during execution of the chamber plasma processing recipe, or other useful tuning algorithm selection techniques.

[0013] As used herein, the term “algorithm” includes a set of instructions configured, when executed by a processor, to perform the method or activity described herein. In one example, a tuning algorithm is configured to tune the impedance of a variable impedance-generating element, such as an electrically driven variable capacitor, to a desired position where a tuning target is achieved, such as minimum reflected power or better power coupling. As used herein, the term “recipe” is a set of rules or instructions that precisely defines a sequence of steps and operations for performing one or more defined functions in a plasma chamber. The recipe may select one or more tuning algorithms during one or more of the defined sequences of steps or operations. In one example, based on process conditions, substrate, and chemistry, a preferred algorithm may be selected and defined in the recipe that, when executed during a manufacturing process, achieves, for example, reproducible and optimized reflected power back to an RF generator. Multiple predefined and / or “learned” tuning algorithms may be stored in either or both the fast module memory and the slower module memory. The tuning recipe may pick / select an appropriate tuning algorithm stored in either or both memories and transfer the selected tuning algorithm from the slower memory to the faster memory as needed. It will be noted that the tool controller also includes one or more "process recipes" that include a sequence of wafer processing steps, each including process variable settings, that, when executed during a process performed in the process chamber, produce reproducible substrate (e.g., semiconductor wafer) processing results. Because the storage capacity of faster memories may be limited, algorithms that are no longer needed for a process may be replaced with subsequent algorithms that are needed to complete the manufacturing process, thus maximizing processing flexibility and minimizing memory storage capacity requirements. The terms "fast" memory and "slow" memory are intended to describe the controller's ability to transfer and / or implement algorithms during processing.In one example, a controller including fast memory may be configured to implement an algorithm capable of making adjustments on a nanosecond (ns) timescale, and a controller including slower memory may be configured to implement an algorithm capable of making adjustments on a microsecond (μs) timescale.

[0014] Embodiments of the present disclosure relate to a plasma processing system including independent, autonomous circuit functions with application-specific sensor interface, data processing, and computation and control circuit modules. Independent communication between circuit module functions uses a fast, secure communication protocol for communication between the circuit modules, tool controller, and supervisory system. Communication may be provided using an industrial-quality software protocol, such as, but not limited to, Ethernet for Control Automation Technology (EtherCAT) or (ECAT). EtherCAT communication enables fast and easy circuit and system updates and maintenance in the field, as well as efficient in-process testing and qualification of manufacturing systems. Sensor and controller circuit testing, qualification, and firmware / software updates may be performed remotely using Failover EtherCAT (FoE), which may reduce maintenance, calibration, and logistics costs. Each EtherCat communication interface has a unique address and is adapted to communicate sensor and control data to other EtherCat communication interfaces, thereby making all process information available to all circuit functions in the system.

[0015] An RF matching network with a flexible tuning algorithm can be uploaded to the matching controller on the fly before or during processing of a semiconductor wafer in a plasma chamber. The tool controller, which oversees the tuning execution of the tuning recipe, can update the tuning algorithm of the tuning recipe on the fly based on previous process executions or steps. The tuning algorithm can be uploaded to the matching controller and / or the tool controller using File over EtherCAT (FoE) or other data transfer protocols. The tuning algorithm of the tuning recipe can be uploaded from a user interface, such as a personal computer (e.g., a laptop PC), using, for example, but not limited to, USB, RS-232, RS-422, or other serial communication protocols. Different tuning algorithms can be stored in the matching controller memory, the tool controller memory, and / or the user personal computer (PC) memory. Based on recipe conditions and process requirements, different tuning algorithms can be used for different recipes, process steps, wafer types, etc.

[0016] RF impedance and RF power sensor information from independent RF impedance and power circuit modules can be shared throughout the plasma processing system for diagnostic purposes, algorithm pre-training, and / or improvements in process speed, quality, and / or efficiency. Circuit modules can provide sensor information that can be reusable for impedance matching unit design scalability. Sensor circuits can be adapted for use with other impedance matching units and / or operate at other RF frequencies and load impedances. Each sensor circuit module can have a unique communication address and be accessible, with its data available for process data logging in all other plasma processing system circuit modules, controllers, and manufacturing supervisory systems.

[0017] In some embodiments, plasma process sensor data can be used and recorded for learning purposes, and then the sensors can be disconnected and the recorded learning process data can be used in place of the sensor data. Process control algorithm settings, such as impedance matching element setting positions and RF power process levels, can be stored in the tool controller and subsequently used by the tool controller for multiple different tuning recipes. Thus, a well-established and consistent manufacturing process can be run without the need for sensor monitoring of the manufacturing process. This is particularly advantageous when multiple chamber plasma processes occur during a day of manufacturing semiconductor devices. The same tuning recipe does not need to be applied to all plasma processing systems simultaneously, but can be modified using different process control algorithms depending on the intended semiconductor manufacturing process required. Different plasma processing tuning recipes can be distributed among manufacturing plasma chamber systems depending on the manufacturing requirements for different semiconductor products.

[0018] Processing information, such as RF sensor values ​​and tuning element positions, can be evaluated during a semiconductor manufacturing process. The processing information can be recorded (stored in memory) for subsequent evaluation and possible refinement for future manufacturing process runs. For example, plasma chamber conditions can change over time, and different or modified RF matching tuning algorithms can be implemented using a total runtime to reduce the variations. Similar configured plasma processing chambers can have slight differences that can result in undesirable excess RF reflected power, resulting in process result variations that can be corrected by adjustments made to the tuning algorithm. Different adapted tuning algorithms can also be used to reduce chamber-to-chamber variations. Different tuning algorithms can be selected for different process steps when creating a chamber plasma processing recipe. Other examples may be: 1) using a predetermined impedance matching setting (tuning element position) as a starting matching point to compensate for known changes in load impedance during execution of a chamber plasma processing recipe; 2) predicting future impedance matching settings while taking into account the rate (time) at which the tuning element position may change to the desired matching setting; and 3) making predictive tuning element position changes (impedance matching points) to compensate for known changes in load impedance to attenuate and / or reduce initial high reflected power that may result from the load impedance change.

[0019] Referring now to the drawings, details of an exemplary embodiment are shown generally, in which like elements within the drawings are represented by like numbers, and similar elements are represented by like numbers with different lower case suffixes.

[0020] 1A, a schematic block diagram of a semiconductor wafer plasma processing system is shown in accordance with certain exemplary embodiments of the present disclosure. The plasma processing system, generally designated by the numeral 100, may generally include a plasma chamber 102 for processing substrates therein, an RF power generator 106, an RF impedance matching network 104, a tool controller 108, and a user interface 110 having a communication interface 128. The plasma processing system 100 may further include an RF power measurement circuit module 120, an RF filter 122, the RF impedance matching network 104 including an RF tuning circuit 112 and a matching controller 114, another RF filter 122a, an RF impedance measurement circuit module 124, and a DC voltage pulse generator 140.

[0021] 1B shows a schematic block diagram of a plasma processing chamber 102 and associated plasma-generating equipment in accordance with one or more embodiments of the present disclosure. The plasma processing chamber 102 includes an impedance matching unit 104, an RF power generator 106, a DC pulse generator 177, an RF electrode 172, and a workpiece pedestal 174. The RF electrode 172 is coupled to the impedance matching unit 104, which receives RF power from the RF power generator 106. In one example, the RF electrode 172 may be a showerhead used to form a capacitively coupled plasma in the plasma processing chamber 102 or a multi-turn coil used to form an inductively coupled plasma in the plasma processing chamber 102. The impedance matching unit 104, the RF power generator 106, and the DC pulse generator 177 are monitored and controlled via their associated respective EtherCat communication lines. Information from and control of these elements may be processed in a tool controller 108, which communicates with each of these elements via the aforementioned respective EtherCat communication lines. For example, the RF voltage detected by the RF voltage sensor 178 may be utilized by both the impedance match unit 104 and the tool controller 108. The output of the DC pulse generator 177 is coupled to a recessed electrode 180 in the workpiece pedestal 174. The recessed electrode 180 may be an electrostatic chucking electrode disposed in an electrostatic chuck within the workpiece pedestal 174. An RF filter 176 is coupled between the DC pulse generator 177 and the recessed electrode 180 and is used to substantially block RF energy from entering the DC pulse generator 177. The DC pulse generator 177 may be adapted to supply asymmetric DC pulses to the recessed electrode 180 for control of a plasma sheath formed above the surface of the substrate. In some embodiments, the plasma processing chamber 102 is configured for a plasma-assisted etching process, such as a reactive ion etch (RIE) plasma process.The plasma processing chamber 102 may also be used in other plasma-assisted processes, such as plasma-enhanced deposition processes (e.g., plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processes, plasma-based ion implantation processes, or plasma doping (PLAD) processes.

[0022] The RF impedance matching network 104, the RF power generator 106, the RF power measurement circuit module 120, the RF impedance measurement circuit module 124, the DC voltage pulse generator 140, the tool controller 108, and the user interface 110 may communicate with each other to control and monitor the delivery of RF power to the plasma chamber 102 during semiconductor substrate processing using a protocol, such as, but not limited to, Ethernet for Control and Automation Technology (EtherCAT) or (ECAT). Other industrial communication protocols may also be effectively used and are contemplated herein. For purposes of discussion herein, the primary means (protocol) of communication used for control and monitoring may be EtherCat. EtherCAT is a high-performance, low-cost, easy-to-use industrial Ethernet technology with a flexible topology. More information about EtherCat can be found at the EtherCat Technology website https: / / www.ethercat.org, which is incorporated herein by reference for all purposes. EtherCat uses Ethernet packet-based communication, but is much faster and more robust than typical Ethernet systems and other similar communication protocols. It is particularly applicable to industrial manufacturing processes that require a high degree of security and reliability while maintaining high data and control throughput in real time. Because EtherCat is a serial communications protocol with inherent latency delays, a directly coupled "TTL" signal can be utilized to trigger microsecond sampling and blanking processes during DC pulse generation by the DC voltage pulse generator 140.

[0023] The impedance matching network 104 may include an RF tuning circuit 112, a matching controller 114 for controlling the RF tuning circuit 112, a memory 116 coupled to the matching controller 114, a safety and operational interlock 118, an RF power measurement circuit module 120 having an input coupled to the output of the RF power generator 106, an RF filter 122 coupled between the RF power measurement circuit module 120 and the input of the RF tuning circuit 112, another RF filter 122a coupled to the output of the RF tuning circuit 112, an RF impedance measurement circuit module 124, and a temperature sensor 126. The matching controller 114 may include a communication interface adapted for a communication protocol, such as, but not limited to, EtherCat communication. A synchronization or trigger (TTL) signal 150 may be provided to the circuit module as shown and may be adapted (programmable) to function as either a passive (receive) signal node or an active (transmit) signal node on a single TTL “party line.” The TTL signals 150 are hardwired logic circuits with virtually no communication latency delay and can be used to control RF power blanking, sensor value sampling, DC pulse timing, and other important timing relationships that occur in the nanosecond or even picosecond range. All of the above circuit modules are accessible between each other for monitoring and control through EtherCat communication and the TTL signals 150.

[0024] The user interface 110, e.g., a computer (laptop), may communicate with the tool controller 108 (EtherCat master) using a USB to EtherCat adapter 128, or may be coupled to the tool controller 108 using RS-232, Wi-Fi, or other communication protocols not shown. This communication link may give the user interface 110 access to all sensor information and control of the plasma processing system 100, for example, but not limited to, via EtherCat communications coupled to each subsystem of the plasma processing system 100. RF power from the RF power generator 106 may be coupled to the RF power measurement circuit module 120 via a high-voltage coaxial cable 130, e.g., an LMR-600, and RF power from the impedance matching unit 104 may be coupled to the plasma chamber 102 RF coil (not shown) via a coaxial cable 130a.

[0025] 1B , the DC voltage pulse generator 140 may comprise a pulsed high-voltage DC power supply in communication with an EtherCat communication interface. The DC voltage pulse generator 140 is generally configured to provide a voltage waveform, including asymmetric DC voltage pulses (e.g., non-sinusoidal pulses), to an electrode (e.g., electrode 180) disposed within the plasma processing chamber 102. The DC voltage pulses may include multiple voltage pulse characteristics, such as a voltage pulse repetition rate, a voltage pulse on-time during a voltage pulse period, and a peak positive or negative voltage applied to the electrode during the on-time of each voltage pulse. In some embodiments, the DC voltage pulses may be generated from about minus (−) 5000 volts to about plus (+) 5000 volts at a pulse repetition rate of about 100 kHz to about 500 kHz, with a pulse on-time of about 5 percent to about 90 percent of the pulse period, provided by the high-voltage DC power supply. In one example, the DC voltage pulses include a negative (-) 5000 volts peak applied voltage applied at a pulse repetition rate of about 400 kHz and a pulse on-time of about 85 percent of the pulse period (e.g., 2.5 μs). During plasma processing, a voltage waveform including asymmetric DC voltage pulses is typically applied while RF power provided by an RF power source is used to generate a plasma in the processing region of the plasma processing chamber 102.

[0026] DC pulse supply characteristics for the DC voltage pulse generator circuit module 140 may be stored in the memory of the DC voltage pulse generator 140 and accessed therefrom as needed. The supply and characteristics of the DC voltage pulses (i.e., the DC pulse waveform) provided by the DC voltage pulse generator circuit module 140 may also be controlled by signals provided from the tool controller 108 and / or through the use of TTL level signals provided from one or more of the system components. Control of the DC voltage pulse generator may be performed by the tool controller 108 and / or the user interface 110 via an EtherCat communication line 822 to an Ethernet communication interface. A synchronization or trigger (TTL) signal 150 may be provided to the DC voltage pulse generator circuit module 140. The TTL signal 150 may control the DC voltage pulse generation profile according to a DC voltage pulse generator algorithm, which may be stored in the memory of the DC voltage pulse generator circuit module 140.

[0027] High Frequency Impedance and Power Determination Radio frequency (RF) impedance is determined by the RF voltage V(t), RF current I(t), the phase angle θ of the RF waveform, and the frequency. RF voltage and current sensors measure the RF voltage V(t) and RF current I(t), from which the phase angle θ is determined. The frequency is measured by a frequency detector. The phase angle is the lead or lag time between the RF voltage V(t) and RF current I(t) waveforms at a given harmonic frequency, although the fundamental frequency is often considered and expressed in degrees θ. RF power P(t) is the product of voltage and current, or P(t) = V(t) * I(t), and the RMS (root mean square) value of each after the sensor detection is P = V * I * cos θ, where θ is the phase between the voltage and current waveforms. is the angle. Using Ohm's law, Z(t) = V(t) / I(t), or Z can be expressed as Z = R + jX, where R = Z cos θ and jX = Z sin θ. jX = jωL-j / ωC, where ω = 2πf, f is in frequency, C is in farads, and L is in henrys. R is the resistance in ohms, and jX is the reactance in ohms, where +jX is the inductive reactance and -jX is the capacitive reactance. When analyzing in the frequency domain, power is independent of frequency, and impedance is frequency dependent.

[0028] Referring to FIG. 2 , a schematic block diagram of an RF power generator circuit module 106 is shown, according to one embodiment of the present disclosure. The RF power generator circuit module 106 may include a frequency generator 202, an RF power amplifier 204, a temperature sensor 210, a microcontroller 212 having a memory 214, and an EtherCat communication interface 218. The microcontroller 212 is adapted to set the frequency of the frequency generator 202 and the RF power output of the RF power amplifier 204. The RF power generator circuit module 106 may be adapted to provide RF power at frequencies from about 100 kHz to about 200 MHz. The RF power output from the RF power generator circuit module 106 may be from about 100 to about 40,000 watts (W). The RF power may also be pulsed on and off at a pulse rate from about 1 Hz to about 100 kHz with an on / off duty cycle from about 1 percent to about 99 percent.

[0029] Referring to FIG. 3 , a schematic block diagram of an RF impedance measurement circuit module according to one embodiment of the present disclosure is shown. The RF impedance measurement circuit module may include at least one of the RF impedance measurement circuit modules 120 and 124, and may include an RF current sensor 302, an RF voltage sensor 304, an RF frequency detector 306, an RF phase detector 308, a temperature sensor 310, a microcontroller 312 with memory 314 and digital signal processing (DSP) / fast Fourier transform (FFT) 316 capabilities, and an EtherCat communication interface 318. In some embodiments, a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC) may be used for faster speed and better performance. The EtherCat communication interface 318 may be adapted for EtherCat-P, which may provide DC power for the electronics of the RF impedance measurement circuit modules 120 and 124. A synchronization or trigger (TTL) signal 150 may be provided to the microcontroller 312 as an alert to take RF current, RF voltage, RF phase, and frequency samples at each trigger pulse from the TTL signal 150. The microcontroller 312 may then store these samples in memory 314 for later use, calculations, and / or communication through the Ethernet communication interface 318. The TTL signal 150 may also be used as a "blanking signal" to prevent sensor readings during the DC pulse from the pulse voltage generator 140.

[0030] The RF current sensor 302 senses the RF current I(t), and the RF voltage sensor 304 senses the RF voltage V(t). The RF current I(t) and voltage V(t) may be received by analog inputs of the microcontroller 312 and then converted to their digital representations. The phase angle θ (the time difference between I(t) and V(t)) may be determined by the phase detector 308, or may be determined after I(t) and V(t) are converted to digital representations. In either case, the phase angle θ may be converted to digital form by the microcontroller 312. The frequency detector 306 provides frequency information to the microcontroller 312 in digital form, for example, from a time-based digital counter. Knowing the RF current, voltage, phase, and frequency, the impedance and RF power entering the load (plasma processing chamber) may be calculated using the DSP / FFT 316 functionality of the microcontroller 312, as described above. The memory 314 may be adapted to store calculated real-time impedance and power, and may be used to store calibration coefficients for the RF current and voltage sensors, and frequency and phase detectors, and the sensor, detector, impedance, and power information may be presented in digital form from the microcontroller 312 to an EtherCat communication interface 318 for use (information and control) by the plasma processing system 100 and other subsystems of the plasma processing system 100.

[0031] Impedance Matching Unit Control and Tuning 4A, 4B, and 4C each include a schematic diagram of an RF tuning circuit 112 according to one or more embodiments of the present disclosure. FIGS. 4A and 4B show three variable capacitors V C1 , V C2 , and V C3 , and FIG. 4C shows two variable capacitors V C1 and V C3 , e.g., electromotive vacuum variable capacitors, in combination with inductor L C1 (and L C2 ), for the RF tuning circuit 112. Variable capacitors V C1 , V C2 , and V C3 may have a capacitance range, but are not limited to, from about 3 pF to about 5000 pF. L C1 is an inductor and may have an inductance range, but is not limited to, from about 0.01 μH to about 1000 μH. V C3 may be used to adjust a target frequency from about 100 kHz to about 250 MHz, and V C1 and V C2 may be used to tune to a target impedance. In some embodiments, particularly complex loads for lower frequencies, the RF circuit schematic configuration shown in FIG. 4B may be implemented. An additional inductor L2 can be added to tune the RF tuning circuit 112 to a desired value. The inductor L2 can be in the range of, but is not limited to, approximately 0.01 μH to approximately 1000 μH. A low-pass Pi matching circuit is shown in FIGS. 4A and 4B. In some embodiments, the RF tuning circuit 112 can be an L-type circuit using only two electrically driven vacuum variable capacitors, e.g., VC1 and VC3, as shown in FIG. 4C.

[0032] The capacitance and / or inductance values ​​of the variable elements, e.g., VC1, VC2, VC3, may be controlled and monitored by the position control and monitoring circuit 402 for each variable element (as shown). Additional capacitors and / or inductors may also be switched into the matching circuit (not shown) if necessary. The motor position actuator of the position control and monitoring circuit 402 may also include a position sensor that indicates the mechanical position of the adjustable element, e.g., the amount of shaft rotation of a variable vacuum capacitor or a synchronous stepper motor position count after the minimum and maximum rotational positions have been determined (detecting maximum and minimum clockwise and counterclockwise shaft rotations). The position values ​​may be correlated in a capacitance (or inductance)-position value table so that capacitance and / or inductance values ​​can be monitored and set to desired positions based on the required capacitance / inductance values. The tuning element position values ​​may be used to monitor and preset tuning element positions according to the teachings of the present disclosure.

[0033] Referring to FIG. 5, a schematic block diagram of the matching controller 114 is shown in accordance with one embodiment of the present disclosure. The matching controller 114 may monitor and control the variable tuning elements (e.g., variable capacitors V, V, and V) of the RF tuning circuit 112. The matching controller 114 may include a microcontroller 512, memory (volatile and / or non-volatile) 514, a stepper motor driver and position sensor 402 (FIGS. 4A-4C), and an EtherCat communication interface 518. The microcontroller 512 may include a processor configured to execute instructions in a tuning algorithm to adjust and control at least one of the capacitance and inductance values ​​of the variable elements (e.g., V, V, and V) in the RF tuning circuit 112. Via EtherCat communication, the microcontroller 612 may receive plasma chamber impedance information from the RF impedance measurement circuit module 124 and / or the RF power measurement circuit module 120. This impedance information then controls the positions of variable tuning elements (e.g., variable capacitors VC1, VC2, and VC3) of RF tuning circuit 112 to complete impedance matching between RF power generator 106 and plasma chamber 102. EtherCat communication interface 518 can provide downloaded matching tuning algorithms for storage in memory 514. TTL signal 150 can initiate or inhibit matching tuning events depending on the matching tuning algorithm in operation. Tuning latency issues caused by slow mechanical movement of variable tuning elements can be compensated for by preset and predictive adjustments to minimize adjustment latency of tuning element controls in impedance matching networks during semiconductor manufacturing processes, for example, but not limited to.

[0034] Plasma treatment example In an effort to control a process performed in the plasma processing chamber 102, a chamber plasma processing recipe is typically generated from inputs provided by a user, such as a process engineer. The chamber plasma processing recipe is controlled by a process recipe algorithm stored in memory and executed using a processor in the tool controller 108. The chamber plasma processing recipe includes a sequence of processing steps, each used to define and control one or more substrate processing variables during each processing step, such that, when combined with one another, a desired process result is achieved on the substrate. The chamber plasma processing recipe includes multiple processing steps, generally referred to herein as process recipe substeps, or substeps. Typically, substrate processing variables include, but are not limited to, chamber pressure, gas flow rates, gas flow composition, PV waveform bias voltage, PV waveform pulse frequency, PV waveform pulse on-time, RF power level, RF pulse frequency, substrate temperature, or other useful processing parameters. As the various processing steps of the chamber plasma processing recipe are performed, the tool controller 108 issues or causes to be issued commands to various hardware and electrical components within the plasma processing chamber 102 that are used to execute aspects of the chamber plasma processing recipe to achieve the desired process result on the substrate. Commands provided by the tool controller 108 may be provided through the use of various EtherCat communication interfaces and TTL signal lines that enable communication between various hardware and electrical components within the plasma processing chamber 102 .

[0035] As part of the process of controlling various process parameters defined in the chamber plasma processing recipe, the tool controller 108 is also configured to cause the matching controller 114 to implement tuning algorithms that control the performance of the RF matching 104 during processing. As described above, these tuning algorithms can be used during different portions of the chamber plasma processing recipe executed in the plasma processing chamber when the load impedance changes due to variations in one or more plasma processing parameters. The tuning algorithms are configured to take into account measured parameter variations, such as RF voltage, current, and frequency, and make adjustments to tuning elements of the RF impedance matching network and / or RF power from the RF power generator. The tuning algorithms can be formed based on historical learning, user-created settings, or attributes of the current process variables within the process recipe step, so that the overall operation of the plasma process executed in the plasma chamber can be improved. In some embodiments, different RF tuning algorithms can be implemented based on the RF source, DC voltage pulse source, and matching synchronization settings when using synchronization or trigger (TTL) signals. Different RF power algorithms can be provided using synchronization or trigger (TTL) signals generated from the RF power generator circuit module 106, from the DC voltage pulse generator circuit module 140, or from an external trigger signal. RF power algorithms for controlling the RF power generator circuit module 106 can be stored in memory 214 and accessed therefrom as needed. These RF power algorithms can be communicated from the memory of the tool controller 108 and / or user interface 110 via EtherCat communication line 222 to the Ethernet communication interface 218 and stored in the memory 214 of the microcontroller 212. Synchronization or trigger (TTL) signals 150 can be provided to the frequency generator 202 and the microcontroller 212. The trigger of the TTL signal 150 can be programmed with the RF power algorithm as part of a process recipe, which can be stored in memory 214.

[0036] 6 is a graphical plot of DC wafer voltage and reflected RF power versus time for a chamber plasma process recipe executed on a substrate in plasma processing chamber 102 in accordance with the teachings of the present disclosure. In this example, the chamber plasma process recipe includes substeps S1-S5, each of which includes instructions used by tool controller 108 to adjust one or more plasma processing parameters during plasma processing to achieve a desired process result on the substrate. 12 6, the sub-step start times are from times T0 to T10. 12 where T0 is the start of the chamber plasma processing recipe, and the substep duration can be found by taking the difference between the start times. For example, the duration of substep S6 is the difference between time T6 and time T5. As described above, execution of a chamber plasma processing recipe is generally performed through the use of a process chamber algorithm executing on the tool controller 108. Coded instructions found in the process chamber algorithm are used to cause the tool controller 108 and / or the matching controller 114 to select and use one or more tuning algorithms during each of one or more of the substeps of the chamber plasma processing recipe. The one or more tuning algorithms can be stored in the tool controller 108 memory and / or the matching controller 114 memory and retrieved therefrom for implementation during one or more of the substeps. A process recipe executed in the plasma processing chamber 102 may use different tuning algorithms in different phases (e.g., substeps) of the process recipe executed by the tool controller 108.

[0037] 7 illustrates a method 700 that includes multiple different tuning recipes that are selected based on information stored within one or more of the process recipe substeps of a chamber plasma processing recipe, such as the chamber plasma process recipe illustrated in FIG. 6. The succession of different tuning recipes is performed during plasma processing of a semiconductor wafer by substeps S1-S5. 12 7, etc. During each of steps 702-706, a process control algorithm executing within the tool controller 108 is used to define which tuning algorithm should be implemented by the matching controller. The implemented tuning algorithm generates control commands that are provided to the position control and monitoring circuitry 402 so that capacitance and / or inductance values ​​of variable elements (e.g., VC1, VC2, VC3) within the RF tuning circuit 112 of the matching network 104 are adjusted to compensate for the varying impedance of the composite load due to changes in process parameters within the plasma processing chamber. The tuning algorithm settings, e.g., impedance matching element setting positions, may be stored in the tool controller or matching controller and subsequently used during different phases within one or more of steps 702-706 of a plasma processing recipe, such as that shown in FIG.

[0038] In step 702, a first tuning algorithm is used for the plasma ignition portion of the process recipe step. For illustrative purposes, in step 702, the chamber plasma processing recipe selects a first tuning algorithm stored in memory to be used by RF matching during the delivery of RF power to the load during the first substep S1. In one example, the first substep S1 of the chamber plasma processing recipe ignites a plasma in the processing region of the plasma processing chamber. During substep S1, the tuning algorithm implemented by the matching controller 114 adjusts the positions of variable tuning elements, such as the three variable capacitors VC1, VC2, and VC3 shown in FIG. 4A, to match the impedance of the plasma chamber RF load. In one example, the first tuning algorithm is adjusted by the chamber plasma processing recipe, which includes the initial delivery of RF power to gases disposed in the processing region of the plasma processing chamber 102.

[0039] In step 704 of method 700, the chamber plasma processing recipe is stored in memory and used to select a second tuning algorithm to be used by RF matching during the delivery of RF power to the load during one or more plasma processing steps, such as second substep S2. During substep S2, the tuning algorithm executed by matching controller 114 readjusts the positions of variable tuning elements, such as three variable capacitors VC1, VC2, and VC3, to match changes in the impedance of the load. In one example, the changes in impedance load are caused, at least in part, by the delivery of multiple DC voltage pulses of a voltage waveform provided by DC voltage pulse generator 140 during at least second substep S2. In some cases, the second tuning algorithm is used throughout the remaining substeps of the chamber plasma processing recipe (i.e., substeps S2-S3). 12) are utilized for all of the sub-steps. However, in other embodiments, step 704 may be repeated multiple times, with a different tuning algorithm for each sub-step, to provide the desired control over the delivery of RF power to the load in each of the sub-steps.

[0040] In step 706, a third tuning algorithm is utilized to enable a cleaning process recipe to be performed on the plasma processing chamber components during a post-processing step when no substrate is present in the processing chamber 102. During the post-processing step, the tuning algorithm executed by the matching controller 114 readjusts the positions of variable tuning elements, such as three variable capacitors VC1, VC2, and VC3, to match changes in the impedance of the load. In one example, the tuning algorithm is adjusted by the chamber plasma processing recipe, or an alternative chamber plasma processing recipe, and includes adjusting the gas composition and / or RF power provided to the processing region of the plasma processing chamber 102.

[0041] Referring to FIG. 6 , during execution of substeps within a chamber plasma process recipe, one or more events, such as events E1-E3, may occur as one or more plasma processing parameters are adjusted during the substeps. During substep S1, high reflected power is experienced during a first event E1 as plasma is generated in the plasma processing chamber between times T0 and T1. Therefore, a first tuning algorithm is used during the first event E1 to adjust a variable tuning element to a first setting to reduce the amount of reflected power experienced during this time period. The tuning algorithm and its selected variable tuning element settings may be derived from previous testing or previous processing of substrates using the same chamber plasma process recipe. In some embodiments, control of the adjustment of the setpoint of the variable tuning element is controlled by the tuning algorithm to adjust for real-time fluctuations in the plasma generated in the plasma processing chamber. In some cases, the rate at which the algorithm makes adjustments to the variable tuning element, or the amount of damping response applied to the adjustment, is set within each tuning algorithm applied by the matching controller 114 during the substep, for example, to account for the characteristics of the events experienced during the substep. In one example, due to the magnitude or different rates of change in the amount of reflected power experienced during the sub-steps, i.e., the first event E1 and the third event E3, the speed at which the tuning algorithm reacts to changes in the detected amount of reflected power during the first event E1 is greater than the speed at which the tuning algorithm reacts to changes in the detected amount of reflected power during the third event E3. In some embodiments, the process of setting the impedance of the variable tuning elements (e.g., one or more of capacitors VC1, VC2, and VC3) performed during execution of the tuning algorithm includes adjusting the set point of at least one of the variable tuning elements and / or the rate at which the set point is adjusted.

[0042] Referring to FIG. 8 , a method 800 may be performed by the tool controller 108 to oversee the execution of a tuning algorithm according to one embodiment of the present disclosure. In the tool controller 108, a learning-based algorithm may be utilized to oversee and update the matching tuning performance of the tuning algorithm, updating the tuning algorithm on-the-fly based on the operation and results of a previous process recipe or step. In step 802, the tool controller accesses historical data stored in memory from a previous process step completed. The historical data may include information regarding the reflected power and tuning speed of the RF matching variable impedance component, which are used as a baseline or as the last tuning parameters performed by the matching controller 114. In step 804, weighting or correction parameters are empirically developed or provided by a user to optimize the tuning gain and / or tuning matrix based on the previous process step or run. In step 806, a new tuning algorithm is generated and stored in the memory of the tool controller 108 or matching controller 114, and may then be implemented by the matching controller during the process recipe during the next process run or next process step.

[0043] Referring to FIG. 9 , a method 900 is illustrated for selecting a tuning algorithm based on plasma chamber conditions, according to certain exemplary embodiments of the present disclosure. In step 902, RF matching is controlled by a first algorithm when the total process chamber run time is less than a first time. In step 904, RF matching is controlled by a second algorithm when the total run time is greater than the first run time but less than a second time. In step 906, RF matching is controlled by a third algorithm when the total run time is greater than the second time. In one embodiment, the first, second, and third algorithms are configured to adjust for drift in one or more of the plasma processing variables over time. In one example, the capacitance of at least one of three variable capacitors VC1, VC2, and VC3 of the RF tuning circuit 112 is continuously increased or decreased by adjusting the variable capacitor settings provided by each of the first, second, and third algorithms.

[0044] 10 illustrates a method 1000 for enabling a tool controller to determine which of stored matching algorithms should be executed during different substrate manufacturing process applications in different plasma processing chambers, according to one embodiment of the present disclosure. In step 1002, a first RF matching algorithm is programmed into and used by the matching controller when used with a first plasma chamber. In step 1004, a second RF matching algorithm is programmed into and used by the matching controller when used with a second plasma chamber. The first and second plasma chambers may be running different process applications requiring different tuning algorithms.

[0045] While this disclosure has been described in terms of one or more embodiments, it should be appreciated that many equivalents, alternatives, variations, and modifications, aside from those expressly stated, are possible and are within the scope of the present disclosure.

Claims

1. 1. A system for controlling plasma generation in a plasma processing chamber, comprising: An impedance matching network comprising: a first node adapted to couple to a radio frequency (RF) power generator; a second node adapted to couple to an electrode in the plasma processing chamber; an adjustable tuning element for transforming at least one of a plurality of impedances at the second node to an output impedance of the RF power generator at the first node; an impedance matching network including a matching controller coupled to the adjustable tuning elements of the impedance matching network, the matching controller controlling the setting of at least one of the adjustable tuning elements of the impedance matching network by using at least one of a plurality of tuning algorithms stored in a matching controller memory; a tool controller in communication with the matching controller and including instructions that, when stored in a tool controller memory and executed by a processor of the tool controller, cause a sequence of process recipe steps to be performed in the plasma processing chamber; and wherein the sequence of process recipe steps comprises: a first process recipe step that, when executed by the processor, causes at least one process variable to be adjusted to a first setting and causes a first tuning algorithm of the plurality of tuning algorithms to be executed by the matching controller, wherein the execution of the first tuning algorithm sets the at least one of the adjustable tuning elements to a first impedance setting; a second process recipe step that, when executed by the processor, causes the at least one process variable to be adjusted to a second setting and causes the matching controller to execute a second tuning algorithm of the plurality of tuning algorithms, wherein the execution of the second tuning algorithm sets the at least one of the adjustable tuning elements to a second impedance setting; Including, the system.

2. The system of claim 1 , wherein the selection of the second tuning algorithm is based on a determination that the at least one process variable is adjusted from the first setting to the second setting.

3. The system of claim 1 , wherein the plurality of tuning algorithms are stored in the tool controller memory, and one of the plurality of tuning algorithms is stored in the matching controller memory.

4. 4. The system of claim 3, wherein at least one of the plurality of tuning algorithms stored in the tool controller memory is transmitted to the matching controller memory while at least one of the process recipe steps is being performed.

5. 4. The system of claim 3, wherein at least one of the plurality of tuning algorithms stored in the matching controller memory is updated with a modified tuning algorithm while at least one of the process recipe steps is being performed.

6. The system of claim 5 , wherein the modified tuning algorithm is transmitted from the tool controller memory to the matching controller memory.

7. The system of claim 1 , wherein the matching controller memory is faster than the tool controller memory.

8. 10. The system of claim 1, wherein the at least one process variable comprises a change in a characteristic of a DC voltage pulse applied to an electrode in the plasma processing chamber by a DC voltage pulse generator.

9. The system of claim 8 , wherein the change in the characteristic of the DC voltage pulse applied to the electrode comprises an initiation of delivery of the DC voltage pulse.

10. 2. The system of claim 1, wherein the process of setting the first impedance setting performed during the execution of the first tuning algorithm includes adjusting a set point of at least one of the adjustable tuning elements and a rate at which the set point is adjusted.

11. 1. A method for processing a substrate in a plasma processing chamber, comprising: performing a first process recipe step of a plasma processing recipe, and executing a first tuning algorithm by use of a matching controller, wherein executing the first tuning algorithm includes adjusting at least one adjustable tuning element of an impedance matching network to at least a first impedance setting, the impedance matching network comprising: a first node adapted to couple to a radio frequency (RF) power generator; a second node adapted to couple to an electrode in the plasma processing chamber; the at least one adjustable tuning element; executing the first tuning algorithm, supplying RF power to an electrode disposed within the plasma processing chamber using the impedance matching network, the supplying of RF power occurring while the first tuning algorithm is being executed by the matching controller, causing a gas disposed within the plasma processing chamber to form or sustain a plasma having a first load impedance; performing a first process recipe step, the first process recipe step comprising: performing a second process recipe step of the plasma processing recipe, executing a second tuning algorithm using the matching controller, the second tuning algorithm including setting the at least one adjustable tuning element to at least a second impedance setting; continuing to supply RF power to the electrode disposed within the plasma processing chamber using the impedance matching network; adjusting at least one plasma process variable to change the first load impedance to a second load impedance, wherein the continued supply of RF power occurs while the second tuning algorithm is being executed by the matching controller, and wherein the second tuning algorithm is executed based on the adjusted at least one plasma process variable; and performing a second process recipe step comprising:

12. 12. The method of claim 11, wherein the supplying of RF power while the first tuning algorithm is being performed causes the gas disposed within the plasma processing chamber to form the plasma.

13. 13. The method of claim 12, wherein executing the second tuning algorithm comprises exchanging the first tuning algorithm with the second tuning algorithm in a matching controller memory.

14. 14. The method of claim 13, further comprising uploading, during a post-process step, a third tuning algorithm for controlling the at least one of the adjustable tuning elements of the impedance matching network for performing a cleaning recipe process step.

15. 14. The method of claim 13, wherein exchanging the first tuning algorithm for the second tuning algorithm in the matching controller memory comprises accessing historical matching tuning process data for tuning algorithms stored in a tool controller memory.

16. The method of claim 15 , wherein the historical tuning algorithm process data includes RF reflected power and adjustable tuning element adjustment speed.

17. 17. The method of claim 16, further comprising optimizing tuning element adjustment rates using weighting parameters stored in the tool controller memory and based on the historical process data.

18. 17. The method of claim 16, wherein the second tuning algorithm is formed by generating a new tuning algorithm based on the historical tuning algorithm process data and storing the new tuning algorithm in the matching controller memory for use in a next process run or step.

19. 1. An impedance matching network adapted for coupling between an RF power generator and a plasma processing chamber, comprising: a first node adapted to couple to the RF power generator; a second node adapted to couple to an electrode in the plasma processing chamber; an adjustable tuning element for transforming at least one of a plurality of impedances at the second node to an output impedance of the RF power generator at the first node; a matching controller coupled to the adjustable tuning elements, the matching controller controlling setting the impedance transformation using at least one of the adjustable tuning elements by using at least one of a plurality of tuning algorithms stored in a matching controller memory; an impedance matching network, including:

20. a tool controller having a memory for storing the plurality of tuning algorithms; a communication device between the tool controller and the matching controller for communicating tuning algorithms between the tool controller and the matching controller memory; 20. The impedance matching network of claim 19, further comprising:

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