Semiconductor structure having a backside metallization layer

Abstract

A semiconductor structure including a first metallization layer having a first plurality of metal-containing lines and a second metallization layer positioned above the first metallization layer, the second metallization layer including a second plurality of metal-containing lines, a first group of the second plurality of metal-containing lines disposed within the first metallization layer, and the first group of the second plurality of metal-containing lines separated from the first metallization layer by a dielectric barrier layer.

Description

[Background technology]

[0001] Generally, a semiconductor device may include multiple circuits forming an integrated circuit fabricated on a substrate. A complex network of signal paths may be routed to connect circuit elements distributed on the surface of the substrate. Efficient routing of these signals may involve the formation of multilevel or multilayer schemes (e.g., single or dual damascene wiring structures) in the back-end-of-line (BEOL) phase of fabrication. Within the interconnect structure, conductive vias may extend perpendicular to the substrate and conductive lines may extend parallel to the substrate. Summary of the Invention

[0002] Exemplary embodiments of the present application include a method for use in semiconductor manufacturing. In one exemplary embodiment, a semiconductor structure includes a first metallization layer having a first plurality of metal-containing lines and a second metallization layer positioned above the first metallization layer. The second metallization layer includes a second plurality of metal-containing lines. A first group of the second plurality of metal-containing lines is disposed within the first metallization layer. The first group of the second plurality of metal-containing lines is separated from the first metallization layer by a dielectric barrier layer.

[0003] Advantageously, the semiconductor structure of this exemplary embodiment allows for the formation of power (Vdd) and ground (GND or Vss) rails on the backside metallization level for the backside power supply network without via connections. This, in turn, can improve chip performance by increasing decoupling capacitance while reducing power supply noise. Additionally, forming the backside metallization level without via patterning requires fewer steps, allowing for more efficient fabrication of the resulting semiconductor structure.

[0004] In one or more additional exemplary embodiments combinable with the preceding paragraph, the first metallization layer is a first backside metallization layer and the second metallization layer is a second backside metallization layer.

[0005] In one or more additional exemplary embodiments combinable with the preceding paragraph, the second plurality of metal-containing lines are oriented perpendicular to the first plurality of metal-containing lines.

[0006] In one or more additional exemplary embodiments combinable with the preceding paragraph, the second plurality of metal-containing wires further comprises a second group of the second plurality of metal-containing wires, wherein at least one of the metal-containing wires of the second group is disposed above at least one of the first plurality of metal-containing wires.

[0007] In one or more additional exemplary embodiments combinable with the preceding paragraph, the first group of the second plurality of metal-containing lines includes a ground Vss rail.

[0008] In one or more additional exemplary embodiments combinable with the preceding paragraph, the second group of the second plurality of metal-containing lines includes a power supply Vdd rail.

[0009] In one or more additional exemplary embodiments that may be combined with the preceding paragraph, the dielectric barrier layer comprises a high-k dielectric material.

[0010] In one or more additional exemplary embodiments that may be combined with the preceding paragraph, the first metallization layer and the second metallization layer are part of a backside power network.

[0011] In one or more additional exemplary embodiments combinable with the preceding paragraph, the second plurality of metal-containing wires further comprises a second group of the second plurality of metal-containing wires in direct contact with a first group of the first plurality of metal-containing wires.

[0012] According to another exemplary embodiment, a semiconductor structure includes a first metallization layer having a first plurality of metal-containing lines in a first orientation and a second metallization layer positioned above the first metallization layer. The second metallization layer has a second plurality of metal-containing lines in a second orientation. The second plurality of metal-containing lines includes a first group of the second plurality of metal-containing lines and a second group of the second plurality of metal-containing lines. The first group of the second plurality of metal-containing lines is disposed within the first metallization layer and separated from the first metallization layer by a dielectric barrier layer. At least one of the metal-containing lines of the second group of the second plurality of metal-containing lines is directly connected to at least one of the first plurality of metal-containing lines.

[0013] Advantageously, the semiconductor structure of this exemplary embodiment allows for the formation of power (Vdd) and ground (GND or Vss) rails on the backside metallization level for the backside power supply network without via connections. This, in turn, can improve chip performance by increasing decoupling capacitance while reducing power supply noise. Additionally, forming the backside metallization level without via patterning requires fewer steps, allowing for more efficient fabrication of the resulting semiconductor structure.

[0014] In one or more additional exemplary embodiments combinable with the preceding paragraph, the first metallization layer is a first backside metallization layer and the second metallization layer is a second backside metallization layer.

[0015] In one or more additional exemplary embodiments combinable with the preceding paragraph, the second plurality of metal-containing lines are oriented perpendicular to the first plurality of metal-containing lines.

[0016] In one or more additional exemplary embodiments combinable with the preceding paragraph, the first group of the second plurality of metal-containing lines includes a ground Vss rail.

[0017] In one or more additional exemplary embodiments combinable with the preceding paragraph, the second group of the second plurality of metal-containing lines includes a power supply Vdd rail.

[0018] In one or more additional exemplary embodiments that may be combined with the preceding paragraph, the dielectric barrier layer comprises a high-k dielectric material.

[0019] In one or more additional exemplary embodiments that may be combined with the preceding paragraph, the first metallization layer and the second metallization layer are part of a backside power network.

[0020] In one or more additional exemplary embodiments combinable with the preceding paragraph, the first plurality of metal-containing lines includes a first group including ground Vss rails and a second group including power Vdd rails.

[0021] Another exemplary embodiment comprises an integrated circuit including one or more semiconductor structures, at least one of which is a semiconductor structure according to one or more of the exemplary embodiments described above.

[0022] Advantageously, the integrated circuit of this exemplary embodiment allows for the formation of power (Vdd) and ground (GND or Vss) rails on the backside metallization level for the backside power supply network without via connections. This, in turn, can improve chip performance by increasing decoupling capacitance while reducing power supply noise. Additionally, forming the backside metallization level without via patterning requires fewer steps, allowing for more efficient fabrication of the resulting semiconductor structure.

[0023] These and other exemplary embodiments are described in or will be apparent from the following detailed description of exemplary embodiments, which should be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0024] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings.

[0025] [Figure 1A] 1 illustrates a top view of a semiconductor structure according to an example embodiment.

[0026] [Figure 1B] 1B illustrates a cross-sectional view of a semiconductor structure along axis XX of FIG. 1A at a first intermediate fabrication stage, according to an example embodiment.

[0027] [Figure 2] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at a second intermediate fabrication stage, according to an example embodiment.

[0028] [Figure 3] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at a third intermediate fabrication stage, according to an example embodiment.

[0029] [Figure 4] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at a fourth intermediate fabrication stage, according to an example embodiment.

[0030] [Figure 5] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at a fifth intermediate fabrication stage, according to an example embodiment.

[0031] [Figure 6] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at a sixth intermediate fabrication stage, according to an example embodiment.

[0032] [Figure 7] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at a seventh intermediate fabrication stage, according to an exemplary embodiment.

[0033] [Figure 8] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at an eighth intermediate fabrication stage, according to an exemplary embodiment.

[0034] [Figure 9] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at a ninth intermediate fabrication stage, according to an example embodiment.

[0035] [Figure 10] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at a tenth intermediate fabrication stage, according to an exemplary embodiment.

[0036] [Figure 11] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at an eleventh intermediate fabrication stage, according to an exemplary embodiment.

[0037] [Figure 12] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at a twelfth intermediate fabrication stage, according to an exemplary embodiment.

[0038] [Figure 13] 1B illustrates a cross-sectional view of the semiconductor structure along axis XX of FIG. 1A at a thirteenth intermediate fabrication stage, according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0039] This disclosure relates generally to semiconductor devices, and more particularly to metallization levels and methods for fabricating same for increasing decoupling capacitance between power (Vdd) and ground (GND or Vss) rails for backside power delivery networks (BSPDN). However, it should be understood that embodiments of the present invention are not limited to the exemplary methods, apparatus, systems, and devices, but instead may be more broadly applicable to other suitable methods, apparatus, systems, and devices.

[0040] A semiconductor device may include multiple metallization levels ("levels"), each level including conductive lines ("lines") formed in an interlayer dielectric (ILD). Although the term metallization is used herein, metallization levels may be formed to include any suitable conductive material according to embodiments described herein. Upper lines may be connected to lower lines by vias. Levels are identified herein by an X designation, where X is a positive integer from 1 to N. Levels are identified as 1 to N, from the level closest to the substrate to the level farthest from the substrate, where 1 is the first or lowest level and N is the last or highest level. Lines in an X level may be connected to M X The X level via is represented as V (X-1) There is no via or via bar for V0. The upper level line is M X If it is expressed as M, the line at the next level (X-1) Similarly, the lower level line can be expressed as M X If the line is expressed as M, the line immediately above it is M. (X+1)For the first level (X=1), the line is M1 and there is no "V0" via because the connection from M1 to the device below it is typically through a separately formed contact in the contact layer ("CA"). For the second level (X=2), the line is M2 and the via is V1, and for the third level (X=3), the line is M3 and the via or via bar is V3.

[0041] It should be understood that the various layers, structures, and / or regions shown in the accompanying figures are schematic representations that are not necessarily drawn to scale. Also, for ease of illustration, one or more layers, structures, and regions of the type commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This is not to imply that any not-explicitly shown layers, structures, and regions are omitted from the actual semiconductor structure.

[0042] Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it should be emphasized that the descriptions provided herein are not intended to be inclusive of all of the processing steps that may be used to form functional semiconductor integrated circuit devices. Rather, for the sake of brevity, this specification intentionally does not describe specific processing steps commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps.

[0043] Furthermore, the same or similar reference numbers are used throughout the figures to indicate the same or similar features, elements, layers, regions, or structures, and thus a detailed description of the same or similar features, elements, layers, regions, or structures will not be repeated from figure to figure. Also, the scale of one layer, structure, and / or region shown in the figures relative to another layer, structure, and / or region is not necessarily intended to represent the actual scale.

[0044] It should be understood that the terms "about" or "substantially" as used herein with respect to thickness, width, percentage, range, etc., are intended to indicate close or approximation, rather than exactness. For example, the terms "about" or "substantially" as used herein suggest that there may be a small tolerance, such as 1% or less, of the stated amount.

[0045] References herein to "one embodiment" or "an embodiment" of the present principles, and other variations thereof, mean that the particular features, structures, characteristics, etc. described in connection with that embodiment are included in at least one embodiment of the present principles. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" and any other variations thereof in various places throughout this specification are not necessarily all referring to the same embodiment. The term "positioned on" means that a first element, such as a first structure, is on a second element, such as a second structure, and there may be an intervening element, such as an interface structure, e.g., an interface layer, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conducting, insulating, or semiconducting layer at the interface between the two elements.

[0046] Although terms such as "first," "second," etc. may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed below could be referred to as a second element without departing from the scope of the present concepts.

[0047] As used herein, "height" refers to the vertical size of an element (e.g., a layer, a groove, a hole, an opening, etc.) in a cross-sectional view, measured from the bottom to the top of the element and / or measured relative to the surface in which the element is located. Conversely, "depth" refers to the vertical size of an element (e.g., a layer, a groove, a hole, an opening, etc.) in a cross-sectional view, measured from the top to the bottom of the element. Where indicated, terms such as "thick," "thickness," "thin," or derivatives thereof may be used in place of "height."

[0048] As used herein, "width" or "length" refers to the size of an element (e.g., a layer, groove, hole, opening, etc.) in the drawings, as measured from the side of the element to the opposite surface. Where indicated, terms such as "thick," "thickness," "thin," or derivatives thereof may be used in place of "width" or "length."

[0049] In conventional semiconductor technology, there are front-end (FEOL), back-end (BEOL), and the section connecting the two, middle-of-line (MOL) interconnects. Interconnects in BEOL include both signal wiring and power distribution networks. Because signal wiring requires minimal parasitic capacitance, it is desirable to minimize capacitance by separating metal lines on different levels and connecting them where necessary with vias.

[0050] Recently, the industry has been moving to backside power distribution networks, so this technology includes four components: FEOL, MOL, BEOL, and backside interconnect. When backside interconnect is used for power delivery, there is no need to minimize parasitic capacitance (because it is a requirement for signal routing). Therefore, exemplary embodiments disclosed herein teach methods and structures for eliminating vias between metal lines on different levels, bringing these metal lines closer together and increasing parasitic capacitance.

[0051] Referring now to the drawings, in which like numerals represent like elements, FIGS. 1A-13 illustrate various processes for fabricating skip via connections between backside metallization levels. Note that the same reference numeral (100) is used to designate the semiconductor structure throughout the various intermediate fabrication stages illustrated in FIGS. 1A-13. Note also that the semiconductor structures described herein may be considered semiconductor devices and / or integrated circuits, or portions thereof. For clarity, some fabrication steps leading to the production of a semiconductor structure as illustrated in FIGS. 1A-13 have been omitted. In other words, one or more well-known processing steps not shown but well-known to those skilled in the art are not included in the figures. This is not intended to be construed as limiting any particular embodiment, or example, or the scope of the claims.

[0052] 1A is a top view illustrating where power (Vdd) and ground (GND or Vss) rails will be formed in a second and third backside metallization layer M2, M3 for a backside power distribution network (BSPDN) (see, e.g., FIGS. 12 and 13). FIG. 1A further illustrates that the second metallization layer M2 includes a first plurality of metal-containing lines in a first orientation, and that the third metallization layer M3 positioned above the second metallization layer M2 includes a second plurality of metal-containing lines in a second orientation. In an exemplary embodiment, the second plurality of metal-containing lines are oriented perpendicular to the first plurality of metal-containing lines.

[0053] FIG. 1B illustrates a cross-sectional view of the semiconductor structure 100 along the XX axis of FIG. 1A at a first intermediate fabrication stage. The semiconductor structure 100 includes a substrate layer 102. The substrate layer 102 may be formed of any suitable semiconductor material, including, but not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and various silicon-containing materials, including multilayers thereof. While silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like, may be employed as additional layers. In one exemplary embodiment, the substrate layer 102 is silicon.

[0054] An etch stop layer 104 is formed on the substrate layer 102. The etch stop layer 104 may comprise a buried oxide (BOX) layer or another suitable material, such as silicon germanium (SiGe), or a III-V semiconductor epitaxial layer. The height of the etch stop layer 104 may be in the range of 10 to 30 nanometers (nm).

[0055] The device layer 106 includes various device components of the semiconductor structure 100, such as, for example, complementary metal oxide semiconductor (CMOS) circuitry, active transistors such as bipolar junction transistor (BJT) transistors, and passive elements such as resistors, capacitors, diodes, etc. The device layer 106 may also include a wiring scheme (e.g., middle-of-line interconnects for wiring devices to the backside interconnect, and source / drain sacrificial placeholders to later enable backside contact formation for wiring devices to backside interconnects) located on both sides of the device layer.

[0056] The lower front-side BEOL layers 108 include various BEOL interconnect structures including, for example, insulating layers (dielectrics), metal levels, and / or via levels. In an exemplary embodiment, the lower front-side BEOL layers 108 may be used only for signal routing without a power distribution network.

[0057] The upper front side BEOL layers 110 include various BEOL interconnect structures including, for example, insulating layers (dielectrics), metal levels, via levels, and bonding sites. In an exemplary embodiment, the upper front side BEOL layers 110 may include only signal wiring. In an exemplary embodiment, the upper front side BEOL layers 110 may include both signal wiring and power wires.

[0058] Bonded to the upper front side BEOL layers 110 is a carrier wafer 112. The carrier wafer 112 may be formed of a similar material as the substrate layer 102 and may be formed on the upper front side BEOL layers 110 using a wafer bonding process such as dielectric-to-dielectric bonding.

[0059] 2 shows semiconductor structure 100 at a second intermediate fabrication stage, in which carrier wafer 112 is used to "flip" semiconductor structure 100 so that the backside (i.e., rear surface) of substrate layer 102 faces up for backside processing as shown.

[0060] 3 illustrates the semiconductor structure 100 at a third intermediate fabrication stage, in which portions of the substrate layer 102 may be removed from the backside using, for example, a combination of wafer grinding, chemical mechanical planarization (CMP), dry etching, and wet etching processes to selectively remove the substrate layer 102 down to the etch stop layer 104.

[0061] 4 illustrates the semiconductor structure 100 at a fourth intermediate fabrication stage, in which the etch stop layer 104 is selectively removed, for example, using a wet etch to selectively remove the etch stop layer 104 down to the substrate layer 102.

[0062] 5 illustrates semiconductor structure 100 at a fifth intermediate fabrication stage, in which remaining portions of substrate layer 102 are removed to expose device layer 106. The remaining portions of substrate layer 102 may be removed using a selective etching process, such as a wet etch.

[0063] 6 illustrates the semiconductor structure 100 at a sixth intermediate fabrication stage, in which a backside interlayer dielectric (ILD) layer 114 is formed over the device layer 106 and includes a backside middle-of-line contact 116 and a first backside metallization layer M1 having metal-containing lines 118. The backside ILD layer 114 may be formed of any suitable insulating material, such as SiO, SiOC, SiON, etc. In an exemplary embodiment, the backside ILD layer 114 is first formed over the device layer 106 using any conventional deposition technique, such as physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or plating, followed by a planarization process such as CMP or any other suitable planarization process.

[0064] The backside mid-of-line contacts 116 are formed in the backside ILD layer 114 in any conventional manner. For example, the backside mid-of-line contacts 116 may be formed by patterning the backside ILD layer 114 and forming vias using conventional lithography and etching processes. Next, contact metal is formed, including a silicide liner such as Ti, Ni, NiPt, etc., an adhesion metal liner such as TiN, and a high conductance metal (e.g., tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo)), or any other suitable conductive material. In various embodiments, the high conductance metal can be deposited by PVD, ALD, CVD, and / or plating. The high conductance metal can be planarized using a planarization process such as, for example, CMP. Other planarization processes can include grinding and polishing.

[0065] The first backside metallization layer M1 is formed in the backside ILD layer 114 in any conventional manner. For example, the first backside metallization layer M1 may be formed by depositing an additional backside ILD layer 114 on the top surface of the semiconductor structure 100, patterning the additional backside ILD layer 114, and forming vias using conventional lithography and etching processes. The etching process may be an anisotropic etch, such as reactive ion etch (RIE). The etching process may also be a selective etch process. The metal-containing wires 118 are then formed from any suitable conductive metal, including, for example, copper (Cu), aluminum (Al), chromium (Cr), cobalt (Co), hafnium (Hf), iridium (Ir), molybdenum (Mo), niobium (Nb), osmium (Os), rhenium (Re), rhodium (Rh), ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V), zirconium (Zr), and alloys thereof. In one embodiment, the conductive metal layer is one or more of Al, Ru, Ta, Ti, or W. In one embodiment, the conductive metal is Ru.

[0066] 7 shows the semiconductor structure 100 at a seventh intermediate fabrication stage. At this stage, a first backside via layer V1 and a second backside metallization layer M2 are formed on the first backside metallization layer M1. The first backside via layer V1 may be formed by depositing an additional backside ILD layer 114 on top of the first backside metallization layer M1, patterning the additional backside ILD layer 114, and forming vias using conventional lithography and etching processes. The etching process may be an anisotropic etch, such as RIE. The etching process may also be a selective etch process. A suitable conductive metal is then deposited in the via to form a metal via 120 in the first backside via layer V1.

[0067] The second backside metallization layer 122 (also referred to as the second backside metallization layer M2) can be formed by depositing any suitable conductive metal on the first backside via layer V1 using any conventional deposition technique, such as PVD, ALD, CVD, and / or plating, followed by a planarization process, such as CMP or any other suitable planarization process. Suitable conductive metals for the second backside metallization layer M2 can be any of those discussed above. Next, conventional lithography and etching processes are performed to pattern the second backside metallization layer M2.

[0068] 8 illustrates the semiconductor structure 100 at an eighth intermediate fabrication stage. At this stage, an opening 126 is formed in the backside ILD layer 124. For example, the backside ILD layer 124 is deposited on the second backside metallization layer M2 using any conventional deposition technique, such as PVD, ALD, CVD, and / or plating, followed by a planarization process, such as CMP or any other suitable planarization process. The backside ILD layer 124 may be made of the same or similar material as the backside ILD layer 114 discussed above. The backside ILD layer 124 may then be patterned, and a selective etching process, such as RIE, may be performed to form the opening 126.

[0069] 9 illustrates the semiconductor structure 100 at a ninth intermediate fabrication stage. At this stage, a dielectric barrier layer 128 is formed on the backside ILD layer 124 and the exterior surface of the opening 126. The dielectric barrier layer 128 may be formed using any conventional deposition technique, such as PVD, ALD, CVD, and / or plating. Suitable materials for the dielectric barrier layer 128 include, for example, any suitable high-k dielectric material. Suitable high-k dielectric materials include any dielectric material having a dielectric constant greater than 7.0. In one exemplary embodiment, suitable high-k dielectric materials include, for example, oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. In one exemplary embodiment, suitable high-k dielectric materials include metal oxides such as, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0070] 10 illustrates the semiconductor structure 100 at a tenth intermediate fabrication stage, in which a mask layer 130 (e.g., an organic planarization layer (OPL) or spin-on-carbon (SOC)) is formed in selected openings 126. For example, in one illustrative embodiment, spin-on coating or any other suitable deposition process is used to deposit the mask layer 130 in the selected openings 126. The mask layer 130 may then be patterned, and a selective etching process, such as RIE, may be performed to selectively remove the mask layer 130, leaving openings 126a and 126b, which define the areas where the second and third backside metallization layers M2, M3 are to be connected.

[0071] 11 shows semiconductor structure 100 at an eleventh intermediate fabrication stage, in which exposed portions of dielectric barrier layer 128 are removed using any selective etching process, such as RIE.

[0072] 12 illustrates the semiconductor structure 100 at a twelfth intermediate fabrication stage. At this stage, a third backside metallization layer M3 is formed, including a power (Vdd) rail 132 for providing a supply voltage to the structure and a ground (GND or Vss) rail 134 for forming a power chain. For example, in an exemplary embodiment, the mask layer 130 is first removed, e.g., by an ash etch process, and then a suitable conductive metal is deposited in each opening. The conductive metal may be deposited in a similar manner and made of similar materials as discussed above. Any overfill of the conductive metal may be removed by a planarization process, such as CMP.

[0073] 13 illustrates the semiconductor structure 100 at a thirteenth intermediate fabrication stage. At this stage, power signals can be routed through a backside power network 136 to provide power to several semiconductor devices. In an exemplary embodiment, the backside power network 136 has a smaller metal level (approximately 5 or so) than the BEOL (greater than 10). The backside power network 136 is formed over the structure, including a power (Vdd) rail 132 and a ground (GND or Vss) rail 134, based on the creation of a wiring scheme located on both sides of the device layer (front-end structure).

[0074] A variety of applications, hardware, and / or electronic systems may employ semiconductor devices and methods for forming the same according to the above-described techniques. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., mobile phones and smartphones), solid-state media storage devices, functional circuit configurations, and the like. Systems and hardware incorporating semiconductor devices are contemplated embodiments of the present invention. Given the teachings provided herein, those skilled in the art will be able to envision other implementations and applications of embodiments of the present invention.

[0075] In some embodiments, the above techniques are used in connection with semiconductor devices that may require or otherwise utilize, for example, CMOS, MOSFETs, and / or FinFETs. By way of non-limiting example, the semiconductor devices may include, but are not limited to, CMOS, MOSFET, and FinFET devices and / or semiconductor devices that use CMOS, MOSFET, and / or FinFET technologies.

[0076] The various structures described above may be implemented into integrated circuits. The resulting integrated circuit chips may be distributed by manufacturers in raw wafer form (i.e., as a single, unpackaged wafer containing multiple chips), as bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (e.g., a plastic carrier with leads secured to a motherboard or other upper carrier) or a multi-chip package (e.g., a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard or (b) a final product. The final product may be any product containing integrated circuit chips, ranging from toys and other low-cost applications to sophisticated computer products with displays, keyboards, or other input devices, and central processing units.

[0077] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a first metallization layer having a first plurality of metal-containing lines; and a second metallization layer positioned above the first metallization layer, the second metallization layer having a second plurality of metal-containing lines; Equipped with a first group of the second plurality of metal-containing lines disposed within the first metallization layer; the first group of the second plurality of metal-containing lines being separated from the first metallization layer by a dielectric barrier layer; Semiconductor structure.

2. 2. The semiconductor structure of claim 1, wherein the first metallization layer is a first backside metallization layer and the second metallization layer is a second backside metallization layer.

3. 10. The semiconductor structure of claim 1, wherein the second plurality of metal-containing lines are oriented perpendicular to the first plurality of metal-containing lines.

4. 10. The semiconductor structure of claim 1, wherein the second plurality of metal-containing lines further comprises a second group of the second plurality of metal-containing lines, at least one of the metal-containing lines of the second group being disposed above at least one of the first plurality of metal-containing lines.

5. 10. The semiconductor structure of claim 1, wherein the first group of the second plurality of metal-containing lines comprises a ground Vss rail.

6. 6. The semiconductor structure of claim 5, wherein the second plurality of metal-containing lines further comprises a second group comprising a power supply Vdd rail.

7. The semiconductor structure of claim 1 , wherein the dielectric barrier layer comprises a high-k dielectric material.

8. 10. The semiconductor structure of claim 1, wherein the first metallization layer and the second metallization layer are part of a backside power network.

9. 2. The semiconductor structure of claim 1, wherein the second plurality of metal-containing lines further comprises a second group of the plurality of metal-containing lines in direct contact with a first group of the first plurality of metal-containing lines.

10. a first metallization layer having a first plurality of metal-containing lines in a first orientation; and a second metallization layer positioned above the first metallization layer and having a second plurality of metal-containing lines in a second orientation; Equipped with the second plurality of metal-containing lines includes a first group of the second plurality of metal-containing lines and a second group of the second plurality of metal-containing lines; the first group of the second plurality of metal-containing lines is disposed within the first metallization layer and separated from the first metallization layer by a dielectric barrier layer; at least one of the metal-containing wires of the second group of the second plurality of metal-containing wires is directly connected to at least one of the first plurality of metal-containing wires; Semiconductor structure.

11. 11. The semiconductor structure of claim 10, wherein the first metallization layer is a first backside metallization layer and the second metallization layer is a second backside metallization layer.

12. 11. The semiconductor structure of claim 10, wherein the second plurality of metal-containing lines are oriented perpendicular to the first plurality of metal-containing lines.

13. 11. The semiconductor structure of claim 10, wherein the first group of the second plurality of metal-containing lines comprises a ground Vss rail.

14. 14. The semiconductor structure of claim 13, wherein the second group of the second plurality of metal-containing lines comprises a power supply Vdd rail.

15. The semiconductor structure of claim 10 , wherein the dielectric barrier layer comprises a high-k dielectric material.

16. 11. The semiconductor structure of claim 10, wherein the first metallization layer and the second metallization layer are part of a backside power network.

17. 11. The semiconductor structure of claim 10, wherein the first plurality of metal-containing lines includes a first group including ground Vss rails and a second group including power supply Vdd rails.

18. 1. An integrated circuit comprising one or more semiconductor structures, at least one of the one or more semiconductor structures comprising: a first metallization layer including a first plurality of metal-containing lines; and a second metallization layer positioned above the first metallization layer, the second metallization layer including a second plurality of metal-containing lines; and a first group of the second plurality of metal-containing lines disposed within the first metallization layer; the first group of the second plurality of metal-containing lines being separated from the first metallization layer by a dielectric barrier layer; Integrated circuit.

19. 20. The integrated circuit of claim 18, wherein the first metallization layer is a first backside metallization layer, the second metallization layer is a second backside metallization layer; and the second plurality of metal-containing lines are oriented perpendicular to the first plurality of metal-containing lines.

20. 20. The integrated circuit of claim 18, wherein the first metallization layer and the second metallization layer are part of a backside power network.

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