Voltage waveform generator for ion energy control in plasma processing.

Abstract

A voltage waveform generator (1107) for a plasma-assisted processing apparatus includes an output node (510), a switch node (511) electrically coupled to the output node, and a multilevel voltage source converter (1101) coupled to the switch node and configured to apply a sequence of monotonically decreasing voltage levels at the switch node, each of the voltage levels applied for a respective predetermined period such that a slope defined by the voltage levels and the respective predetermined periods corresponds to a negative voltage slope of a portion of the adapted voltage waveform at the output node. The adapted voltage waveform controls ion energy on an exposed surface of a substrate being processed by ions generated by the plasma. The multilevel voltage source converter includes a T-type converter (1111) in series with at least one H-bridge cell (1112).

Description

[Technical Field]

[0001] The present invention relates to a voltage waveform generator for controlling ion energy in plasma-assisted processing and an associated method for doing so. [Background technology]

[0002] Plasma etching and deposition are two important processes in semiconductor manufacturing. As the minimum design dimensions of integrated circuits continue to shrink, the precision of plasma processing becomes increasingly important, especially in atomic-scale processes including atomic layer etching (ALE) and atomic layer deposition (ALD). One of the increasing requirements is to obtain a unimodal, narrow plasma ion energy distribution (IED), which is beneficial for process selectivity.

[0003] In plasma-assisted processing, plasma ions are accelerated and bombarded onto the substrate surface. A narrow IED requires a quasi-constant potential on the substrate surface. In both multi-frequency capacitively coupled plasma and inductively coupled plasma, ion energy can be controlled by biasing the substrate surface using a specific voltage waveform. For conductive substrates, a dc voltage can be applied to maintain a constant potential on the substrate surface. For insulating substrates, radio frequency waveforms are the most typical bias waveforms, which usually result in a broad, bimodal ion energy distribution. Recently, tailored waveforms have been found to be effective for precisely controlling ion energy to produce a focused, unimodal IED in a wide range of applications.

[0004] The adapted waveform consists of a possibly linearly decreasing voltage ramp and a positive voltage pulse. The voltage ramp is used to compensate for the charging effect of ions impinging on the insulating substrate. The insulating substrate can be considered equivalent to a capacitance. The equivalent current induced by the impinging ions charges the capacitance of the substrate. By linearly decreasing the potential on the backside of the substrate (i.e., the side opposite the exposed surface), the potential on the substrate surface can be kept constant. As the voltage across the substrate increases during the process, voltage pulses are applied periodically to attract electrons and discharge the capacitance, preventing overvoltage.

[0005] The adapted waveform can be produced by both linear amplifiers and switched mode power converters (SMPCs). The repetition rate of the adapted waveform can range from a few kHz to several MHz. Linear amplifiers usually have a much higher bandwidth than SMPCs. Using an impedance matching network, linear amplifiers can generate the required adapted voltage waveform at high repetition rates. For SMPCs, both voltage source converters and hybrid converters including voltage and current sources have been proposed. The bandwidth of voltage source converters is usually not sufficient to accurately produce the required voltage ramp at high repetition rates.

[0006] WO 2022 / 013017 A1 discloses such a hybrid converter. A multilevel voltage source converter is configured to generate the required voltage pulses of controllable magnitude. During the rise and fall of the required pulses, different voltage levels can be applied with the help of a small pulse inductance to suppress resonance and generate a smooth waveform. A negative voltage ramp is generated by a current source converter formed by an inductor in series with a half-bridge voltage source converter. The half-bridge voltage source converter is switched to maintain voltage balance across the inductors in a steady state.

[0007] This type of hybrid converter generally works well for adapted voltage waveforms that are not excessively large. Indeed, to achieve a narrow IED, the output current of the current-source converter must be as constant as possible, which requires very small inductor current ripple. This can be achieved by a small inductor voltage ripple or by using a very large inductance. First, as the adapted voltage waveform becomes larger, the difference between the voltage levels of the half-bridge voltage-source converter must be increased to balance the inductor voltages. However, this increases the voltage ripple across the inductor and, consequently, the inductor current ripple. Second, a larger inductance usually results in a larger parasitic capacitance and therefore a lower self-resonant frequency. This limits the repetition frequency of the adapted waveform that can be generated. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] International Application Publication No. 2022 / 013017A1 [Non-patent literature]

[0009] [Non-Patent Document 1] DOI: 10.23919 / IPEC-Himeji2022-ECCE53331.2022.9806909, Yu Qihao et al., "Accurate Ion Energy Control in Plasma Processing by Switched-Mode Power Converter", 2022 International Power Electronics Conference Summary of the Invention [Problem to be solved by the invention]

[0010] There is therefore a need to be able to generate larger and / or higher repetition rate adapted voltage waveforms while maintaining high accuracy, particularly with respect to the negative voltage slope that defines the IED. [Means for solving the problem]

[0011] According to a first aspect of the present invention, there is therefore provided a voltage waveform generator, as set forth in the accompanying claims. The voltage waveform generator according to the present disclosure is configured for use with a plasma-assisted processing apparatus. The voltage waveform generator may be a power converter, comprising an output node, a switch node electrically coupled to the output node, and a multilevel voltage source converter coupled to the switch node. An output of the multilevel voltage source converter is available at the switch node. In particular, the multilevel voltage source converter is configured to apply a plurality of different voltage levels, which may be constant or variable, at the switch node.

[0012] The voltage waveform generator is configured to generate an adapted voltage waveform at the output node, the adapted voltage waveform being suitable for controlling ion energy on an exposed surface of a substrate being processed by ions generated in the plasma. The adapted voltage waveform may comprise a first portion having a negative voltage slope (i.e., a monotonically decreasing voltage level) and further comprise a second portion consisting of positive voltage pulses. The first and second portions may alternate, and the adapted voltage waveform may be periodic. The first portion is configured to maintain a constant potential on the exposed surface of the substrate while ions bombard the surface.

[0013] According to one aspect, a multilevel voltage source converter is configured to apply a sequence of monotonically decreasing voltage levels at a switch node, each of the voltage levels being applied for a respective predetermined period of time, which may be constant or variable. Specifically, the slope (or gradient) defined by the monotonically decreasing voltage levels and the respective predetermined period of time corresponds to the negative voltage slope (or gradient) of a first portion of an adapted voltage waveform. As a result, the first portion of the adapted voltage waveform can be accurately obtained at an output node.

[0014] Thus, according to the present disclosure, a voltage waveform generator for controlling ion energy impinging on a substrate to be processed in a plasma-assisted processing apparatus is configured to obtain the negative voltage slope of the adapted voltage waveform through a multilevel voltage source converter configured to generate a sequence of monotonically decreasing (stepped) voltage levels that sufficiently approximates the negative voltage slope. Specifically, the slope of the stepped sequence, which refers to the ratio of a voltage level to the duration for which that voltage level is applied, corresponds to or defines the negative voltage slope or gradient. By doing so, a current source converter, as utilized in prior art voltage waveform generators, can be advantageously eliminated; the voltage waveform generator according to the present disclosure advantageously does not include a current source converter configured to generate the negative voltage slope by sinking current. Such current source converters typically include large inductors for stabilizing the current, eliminating these bulky and expensive components. Furthermore, utilizing a multilevel voltage source converter to define and generate the portion of the adapted voltage waveform having the negative voltage slope without utilizing a current source allows the repetition frequency and / or voltage of the adapted voltage waveform to be increased while still maintaining the desired accuracy.

[0015] The negative voltage slope may be constant or variable, and the slope of the step sequence may also be constant or variable. Thus, by controlling the step sequence and / or its predetermined period, it is possible to easily adapt the tailored voltage waveform flexibly according to the processing demands. Advantageously, the negative voltage slope is constant, and the slope is constant throughout the sequence of monotonically decreasing voltage levels. Advantageously, the multilevel voltage source converter is configured to output a plurality of different voltage levels that are integer multiples of the voltage step, such that the difference between successive voltage levels in the sequence of monotonically decreasing voltage levels is constant and equal to the voltage step. Advantageously, each predetermined period is the same throughout the sequence.

[0016] Advantageously, the multilevel voltage source converter is configured to have at least three different voltage levels. Advantageously, the multilevel voltage source converter is a switched-mode power converter configured to have redundant switching states to obtain the at least three voltage levels. One advantage is that a non-isolated DC / DC converter can be used instead of a more expensive isolated DC / DC converter. Furthermore, common-mode interference that would be added by an isolated DC / DC converter can be avoided. In addition, multiple DC link capacitors corresponding to at least some of the at least three voltage levels can be utilized.

[0017] A further advantage is that both the positive voltage pulse and the negative voltage ramp portion of the adapted voltage waveform can now be generated through the same kind of multilevel voltage source converter, which can reduce the complexity and cost of the voltage waveform generator.

[0018] According to one embodiment, a multilevel voltage source converter includes a T-type converter in series with at least one H-bridge cell. One advantage of such a multilevel voltage source converter is that it can achieve a larger number of (intermediate) voltage levels than the number of submodules (i.e., the number of T-type converters and H-bridge cells). As a result, a more accurate stepped voltage waveform can be achieved with fewer hardware components. In addition, through these larger number of intermediate voltage levels, smaller voltage steps can be applied, allowing the voltage at the load to converge to the target value more quickly due to LC resonance.

[0019] The T-converter may comprise at least one, preferably two non-isolated DC voltage sources configured to have the same or preferably different voltage levels, in particular voltage levels that are not integer multiples of each other, which allows the multilevel voltage source converter to advantageously generate voltage pulse portions of the adapted voltage waveform in addition to the negative voltage ramp portion and / or to balance the DC link capacitors of at least one H-bridge cell, if such DC link capacitors are provided.

[0020] The multilevel voltage source converter advantageously comprises a plurality of H-bridge cells cascaded in series between the T-converter and the output, each H-bridge cell comprising a DC-link voltage source, and any one or all of the DC-link voltage sources of the H-bridge cells may comprise or consist of a DC-link capacitor, a non-isolated DC voltage source, or an isolated DC voltage source, with the DC-link capacitor having the advantage of simpler hardware design but requiring greater control effort due to the need for voltage balancing.

[0021] Advantageously, the voltage waveform generator is further configured to process the sequence of monotonically decreasing voltage levels applied at the switch node and to apply the processed sequence of voltage levels at the output node, the processed sequence of voltage levels corresponding to at least a portion of the adapted voltage waveform, in particular the decreasing voltage slope portion of the adapted voltage waveform. The voltage processing operation between the switch node and the output node may comprise or consist of one or a combination of filtering, voltage clamping, offsetting, and attenuation. To this end, the voltage waveform generator advantageously comprises one or more of a filter inductor, a blocking capacitor, and an attenuation element such as a resistor connected in series between the switch node and the output node.

[0022] Advantageously, the voltage waveform generator comprises a clamp node connected between the switch node and the output node. A voltage clamp circuit is advantageously connected to the clamp node. The voltage clamp circuit is configured to fix a maximum and / or minimum voltage at the clamp node. This makes it possible to limit the voltage applied at the output node to a maximum and / or minimum level. Advantageously, the voltage clamp circuit comprises a blocking diode connected directly to the voltage level of the multilevel voltage source converter. This allows a voltage source to be shared between the clamp circuit and the multilevel voltage source converter, reducing circuit complexity and cost.

[0023] According to a second aspect of the present disclosure, there is provided an apparatus for plasma-assisted processing of substrates, particularly insulating substrates. Specifically, the apparatus is configured to process the substrate using ions generated by a plasma. Such an apparatus includes a voltage waveform generator according to the present disclosure for controlling ion energy at an exposed surface of the substrate.

[0024] According to a third aspect of the present disclosure, there is provided a method for generating an adapted waveform, as set forth in the appended claims. The method according to the present disclosure comprises applying a sequence of monotonically decreasing voltage levels to a switch node, each voltage level being applied for a respective predetermined time period, such that the voltage level and the respective predetermined time period define a slope corresponding to the negative voltage slope of a first portion of the adapted waveform. To obtain the first portion of the adapted voltage waveform, the switch node is electrically coupled to an output node. To this end, the sequence of voltage levels can be appropriately processed between the switch node and the output node. This advantageously results in an adapted waveform whose magnitude, ramp rate, and frequency are precisely controllable. The adapted voltage waveform can be adjusted to obtain a desired ion energy. The voltage waveform generator according to the first aspect or the device according to the second aspect can be configured to perform the method according to the third aspect, for example by implementing it in a controller.

[0025] According to a fourth aspect of the present disclosure, there is provided a method for processing a substrate, particularly an insulating substrate, through ions generated by a plasma, as set forth in the appended claims. Such a method is referred to as plasma-assisted processing of a substrate. The method comprises generating an adapted voltage waveform according to the third aspect of the present disclosure and applying the adapted voltage waveform to a processing stage on which the substrate is disposed. A first portion of the adapted voltage waveform is applied while ions are bombarded with an exposed surface of the substrate, thereby maintaining a constant potential on the exposed surface and thereby achieving a narrow IED. The ions are generated through a plasma excited and sustained by an external power source, optionally through a matching network. An apparatus according to the second aspect may be configured to perform the method according to the fourth aspect, for example by implementing it in a controller.

[0026] Aspects of the present invention will now be described in more detail with reference to the accompanying drawings, in which like reference numerals refer to like features. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a block diagram of an exemplary apparatus for plasma-assisted processing. [Figure 2] FIG. 1 is a diagram showing an equivalent electrical circuit model of a plasma reactor system. [Figure 3] The base voltage ut, the substrate surface potential ush1, and the voltage across the substrate capacitance

number

[0028] An apparatus 100 for plasma processing of insulating substrates, such as semiconductor substrates, is shown in FIG. 1. Gas is injected into a reactor 110. The reactor walls are grounded to a protective earth (PE) 121. A plasma is ignited in the reactor 110 using an external power supply 101, which is coupled to the gas by a matching network 105 coupled to a coil 108 located outside the reactor 110. The power supply is connected to the matching network 105 using two connecting leads 102, 103, which are connected to the coil 108 by two connectors 106 and 107. The power supply 101 can be any suitable power source, including radio frequency (RF), microwave frequency (MF), and pulsed DC power sources. While the plasma source shown in FIG. 1 is inductively coupled, it can be any other variant, such as a capacitively coupled plasma source and a helicon-type plasma source.

[0029] Apparatus 100 can be used for plasma etching or plasma deposition. Accordingly, an insulating substrate material 109 is placed on a pedestal 111 inside a reactor 110. The pressure inside the reactor is kept low (i.e., below atmospheric pressure, such as a partial vacuum) by a (vacuum) pump, as shown in FIG.

[0030] A power converter 114 is connected to the pedestal 111 through an electrical connection 113. As described in this disclosure, the power converter 114 is configured to output an adapted voltage waveform intended to control an IED. Accordingly, in this disclosure, the terms "power converter" and "voltage waveform generator" are used interchangeably. It will be understood that the voltage waveform generator may include additional circuitry and measurement units to enable controlling the output of the power converter 114 as described in more detail below.

[0031] A voltage measurement unit 116 may be connected to the power converter 114 and measures the output voltage of the power converter 114. The voltage measurement unit 116 is coupled to the controller 115 through a (data) connection 117 for transmitting the measured results to the controller 115.

[0032] A current measurement unit 119 may be provided to measure the output current of the power converter 114, for example through an electrical connection 113 and / or an interface 112 connected to the base 111. The current measurement unit 119 is coupled to the controller 115 through a (data) connection 120 for transmitting the measured results to the controller 115.

[0033] The controller 115 is configured to implement a voltage waveform control algorithm and control the power converter 114 to output an adapted voltage waveform that is applied to the pedestal 111. The controller 115 can further provide any one of over-voltage, over-current, over-temperature, and short-circuit protection to the power converter 114. To this end, the controller 115 is configured to send a control signal 118 to the power converter 114 to adjust the output waveform to obtain a desired IED. The result is an ion energy control system that is capable of providing real-time control of the output waveform, specifically including voltage and current feedback.

[0034] A basic equivalent electrical model of the plasma reactor system of Figure 1 is shown in Figure 2. The nonlinear resistance R p represents the bulk plasma 201 in the reactor. Under some circumstances, the bulk plasma can alternatively be modeled as a constant voltage source. A sheath 202 formed between the bulk plasma and the substrate surface is driven by a current source I i1 , capacitance C sh1 , and diode D1. i1 represents the equivalent current generated by the impinging ions in the sheath. C sh1represents the equivalent sheath capacitance. D1 indicates the direction of the sheath voltage. Similarly, there is another sheath 203 formed between the bulk plasma 201 and the exposed part of the work table. In some applications, this sheath 203 is ignored for simplicity, as its effect is not dominant. In many cases, the substrate 204 is dielectric, which means that it has a capacitance C sub It is modeled by C t is a lumped capacitance, which represents the parasitic capacitance 205 formed between the pedestal and the reactor wall and between the substrate and the reactor wall. s represents the total leakage inductance in the loop 206. The output of the power converter (voltage waveform generator) 207 is connected to the platform.

[0035] In plasma etching and deposition processes, assuming that plasma ions carry only one net charge, plasma ions have an initial ion energy eu p into the substrate sheath 202 at , where e is the elementary charge and u p is the plasma potential as shown in Figure 2. Positive ions are accelerated in the substrate sheath 202. As a result, ions reaching the exposed surface of the substrate E ion =-eu sh1 Therefore, controlling the ion energy is important to control the substrate surface potential u sh1 This can be achieved by controlling

[0036] For highly selective etching and deposition processes, the ion energy distribution should fall within a specific narrow energy interval, which is achieved by a quasi-constant substrate surface potential u sh1 The ion current I i1 is continuously C sub This is the u sh1 From the equivalent electrical circuit model in Figure 2,

[0037]

number

[0038] In the steady state, the plasma potential u p can be considered to be constant, so that a constant u sh1 teeth

[0039]

number

[0040] In other words, for a given u sh1 To maintain this, the ionic current charging effect is applied to the back of the substrate, i.e., the potential u t -I i1 C sub -1 In this condition, the output current i out teeth

[0041]

number

[0042] This should be a negative DC value. Therefore, we can either use a linearly decreasing voltage source converter, or a current source converter that actively sinks DC current, for a constant u sh1 There are two equivalent ways to maintain

[0043] Furthermore, C sub Since C is continuously charging during the charging phase, it is necessary to discharge it periodically to avoid overvoltage on the board. sub A positive voltage pulse can be applied to rapidly discharge the capacitances of the capacitors and possibly other capacitances. After these capacitances are fully discharged, a negative u sh1 The negative voltage can again be applied to form V. The value of the initial negative voltage applied at the output of the power converter 207 can be changed to V s Then, the initial voltage on the substrate surface is

[0044]

number

[0045] Figure 3 shows the u obtained in this way. t , u sh1 , and

[0046]

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[0047] The typical waveform of u applied to the processing table is shown. t The waveform of is called the adapted voltage waveform. It consists of a pulse phase T pulse and the gradient stage T slope The pulse phase T pulse is the (positive) voltage level V d voltage rise to a (negative) voltage level V s The pulse stage involves a voltage drop to V d The tilt stage T slope is the voltage level V s The voltage drop portion of the pulse stage corresponds to the negative voltage ramp starting from the ramp stage T slope The voltage waveform u has a different, usually steeper, slope compared to the negative voltage slope of t is the output voltage waveform u at the output node of the power converter 207. out is generated by

[0048] According to the present disclosure, the voltage ramps in the graph of Figure 3 are obtained by a multilevel voltage source converter, eliminating the need to utilize current sources. Because current sources are no longer required (and are not included in the voltage waveform generator), it becomes much easier to scale the waveform to higher voltages and operate at higher repetition rates.

[0049] Referring to Figure 4, the concept of approximating an adapted voltage waveform using a multi-level voltage waveform according to the present disclosure is illustrated. Voltage waveform 401 represents the output voltage waveform of a multi-level power converter. When compared to the required adapted voltage waveform 402, T slope A series of periodically decreasing (step or staircase shaped) voltage levels 404 are generated to approximate a (linear) voltage ramp between .

[0050] In some examples, the decreasing voltage level 404 is V step Each voltage level has the same voltage difference of T step Waveform 404 can be viewed as the superposition of two separate waveforms: a negative continuous, possibly linear voltage ramp 405 and a sawtooth waveform 403. Assuming waveform 402 is the desired adapted waveform, the ramp or slope portion 405 of the adapted waveform is:

[0051]

number

[0052] Based on the previous analysis,

[0053]

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[0054] The value of is required to closely compensate for the ionic current charging effect on the substrate capacitance.

[0055]

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[0056] On the other hand, waveform 403 can be seen as a steady-state sawtooth voltage pulsation, which produces high frequency errors. According to the equivalent electrical circuit model shown in Figure 2, this output voltage pulsation is

[0057]

number

[0058] This should produce a voltage variation on the substrate surface given by: sh1 is eΔu sh1 As a result, given the quantitative requirement for the ion energy distribution width, the maximum allowable V step can be calculated, which is

[0059]

number

[0060] is determined by.

[0061] It should be noted that while FIG. 4 shows a waveform with five consecutive voltage steps, there may be either more or fewer voltage steps depending on the converter topology and operating conditions.

[0062] In other examples, V step and / or T step may be different between different steps. This may allow for improved control of the voltage ramp, may allow for the generation of other types of (negative) voltage ramp waveforms, such as non-linear ramps, and / or may relax the requirements for the multilevel voltage source converter. In such cases,

[0063]

number

[0064] The instantaneous value of

[0065]

number

[0066] can be made to match the instantaneous value of

[0067] 5A, a multilevel converter for generating a required multilevel voltage waveform 404 comprises a multilevel voltage source converter unit 501 coupled to a switch node 511. The multilevel converter unit 501 generates a switch node voltage u at the switch node 511. sn The switch node 511 is configured to generate a blocking capacitor C b and / or a switched damping circuit 504. out and the output current i out The output of the voltage waveform generator, including: is applied at output node 510. Output node 510 may be connected to the work table 111 (FIG. 1). Since the plasma reactor load is grounded to PE (FIG. 1), multilevel converter unit 501 should also be grounded to PE 503.

[0068] 5B-5D, the multilevel converter unit 501 can be realized with various converter topologies, such as a cascaded H-bridge converter 505, a neutral-point clamped converter (NPC) 506, and a flying capacitor converter (FCC) 507, all of which are scalable and can be scaled to more voltage levels. It will be understood that possible implementations of the multilevel converter unit are not limited to these topologies. Other multilevel topologies, such as a modular multilevel converter (MMC), or a combination of different multilevel topologies, can be used to realize the multilevel converter unit 501.

[0069] In FIGS. 5B-5D, the power switches are modeled by ideal switches in parallel with diodes. In practice, various types of power semiconductors may be used, including, but not limited to, silicon-based and silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs) with anti-parallel diodes, and gallium nitride (GaN) transistors. These switches are advantageously controllable, and their operation is controlled through the control unit 115 (FIG. 1). In addition, the voltage sources 508, 509 of the cascaded H-bridge 505 and neutral-point-clamped converter 506, respectively, may be replaced by flying capacitors 5070 as shown in FIG. 5D. Voltage balancing to maintain constant capacitor voltages may be performed by utilizing redundant switching states, possibly in combination with measurement feedback from the voltage measurement unit 116 and the current measurement unit 119 (FIG. 1). In some examples, the voltage levels of the voltage sources or capacitor voltages may be different; for example, an asymmetric multilevel converter may be utilized as the multilevel converter unit 501. An asymmetric multi-level converter may refer to a converter having multiple voltage levels defined by sub-modules or cells (e.g., cascaded H-bridge cells or flying capacitor circuits) with different voltages. Specifically, an asymmetric cascaded H-bridge converter unit refers to a cascaded H-bridge converter including cascaded H-bridge modules with different DC link voltages.

[0070] In the steady state, the blocking capacitor C b Over a period of time, the self-biased blocking voltage V b is formed, and C b The average current through C is zero. b If the value of is large enough, C b The voltage ripple across the blocking capacitor C can be neglected and the blocking voltage can be considered as a DC value. bOne advantage of the C is that it not only maintains a balanced net output charge and provides a well-defined output current, but also makes it possible to achieve bipolar output voltages using only a unipolar (positive) DC power supply. b Without this, a negative voltage source would be required to maintain a negative bias on the output voltage waveform. Additionally, the blocking voltage can be controlled by adapting one or more parameters of the adapted waveform, including but not limited to, frequency, pulse length, and discharge voltage. This further increases the degree of control over the adapted waveform, improving flexibility in controlling ion energy.

[0071] The switched damping circuit 504 includes a damping resistor R d A (semiconductor) power switch S in parallel with a damping element, such as d Equipped with. S d When turned on (conducting), the damping resistor R d is shorted. S d When turned off (open), the damping resistor R d is connected to the output, which may limit transient currents or damp any resonances, but introduces losses. There is leakage inductance and resistance in the loop, which also helps limit transient currents, so this component is not needed if transient currents are not an issue. In practice, there may be non-idealities that cause small LC resonances in the adapted voltage waveform. Under these circumstances, the damping resistor R d makes it possible to practically eliminate this small LC resonance. In combination with further measures such as additional intermediate voltage and trajectory control, which aim to reduce the LC resonance that does occur as much as possible without introducing losses, the power losses caused by the switched damping circuit can be reduced considerably.

[0072] Referring to FIG. 6A, a multi-level converter 501 controls the switch node voltage u sn The waveform 601 can be configured to generate a voltage waveform 601 as a voltage step (drop) V stepand time step (depth) T step The waveform 601 further comprises a voltage pulse V dsn , which may be generated by the multi-level converter 501 or by another suitable converter included in the voltage waveform generator 207. The stepped waveform 603 may be V dsn A smaller starting voltage level V ssn Advantageously, the stepped waveform 603 starts at a voltage level V defined by the required energy of the impinging ions when they reach the substrate surface to be processed. ssn Start with, or in other words, V ssn is advantageously a desired substrate surface potential u that takes into account all possible bias voltages acting between the switch node 511 and the output node 510. sh1 (FIG. 2). The stepped waveform 603 is defined by a voltage pulse V dsn It may start immediately after

[0073] Referring to FIG. 6B, a voltage waveform 601 is shown for the output node voltage u out The waveforms 601 and 602 are converted into a voltage waveform 602 as b The self-biased voltage V formed across b By U sn and u out are identical except for the bias between b Since is a positive value (Fig. 5A), this means that u out =u sn -V b Therefore, the ion energy is increased by the V applied at the beginning of the negative voltage ramp (step) waveform 604. s =V ssn -V b is determined by the value of V s preferably corresponds to the first voltage level of the stepped waveform 604. The slope (gradient) of the stepped voltage waveforms 603, 604 is step and T step is determined by

[0074] 7, an alternative embodiment of a voltage waveform generator 707 comprises a multilevel converter unit 701, which may be identical to the multilevel converter unit 501 of FIG. 5. To further reduce the ripple of the output voltage during the ramp phase for a narrower IED, an output filter inductor 704 may be added between the switch node 511 and the output node 510. Advantageously, the filter inductor L f 704 is added in series to the multilevel converter unit 701. f Since the capacitive plasma load and the load form an LC resonant circuit, large resonances may be introduced into the output waveform at the rising and falling edges of the voltage pulse, resulting in overvoltage and overcurrent.

[0075] Advantageously, clamp circuit 705 is connected to a clamp node 712 between switch node 511 and output node 501. Advantageously, clamp node 712 is connected to a filter inductor L f 704 and blocking capacitor C b The clamp circuit 705 is arranged between the cn The maximum value of V max Limit to u cn The minimum value of V min Each of the upper clamp leg 715 and the lower clamp leg 725 may be configured to limit the voltage source V max and V min Clamp diode D c1 and D c2 V max and V min It will be understood that D can be either an additional voltage source or the voltage source of the multilevel converter unit 701. Using the neutral-point clamped converter 506 of FIG. 5C as an example of the multilevel converter unit 701, D c1 can be connected to the highest voltage of the NPC unit 506, and D c2 can be connected to ground.

[0076] 8A-8C show typical waveforms generated by voltage waveform generator 704 with filter inductor 704. A stepped voltage waveform 801 applied at switch node 511 is smoothed by filter inductor 704 to obtain a waveform 802 with a smooth voltage ramp at downstream clamp node 512. The presence of the filter inductor reduces the out The rising and falling edges of the voltage pulse 803 of u become slower. out is filtered and the waveform can be smoother. out The slope of V step and T step By correctly selecting the value of the filter inductance, the voltage pulsation can be further reduced and the IED can be made narrower.

[0077] A method for determining the filter inductance value may be based on an equivalent circuit analysis as shown in FIG. b The value of C should be much larger than the other capacitances in the load. b The voltage at u can be considered to be constant. cn In addition, the leakage inductance in the loop is usually much smaller than the filter inductance, so it can be ignored for simplicity. Therefore, in the equivalent circuit shown in Figure 9A, the original circuit shown in Figure 7 is sn -V b is connected to the filter inductor and then to the plasma reactor pedestal. Furthermore, this voltage waveform can be viewed as a superposition of two waveforms, such as waveforms 402 and 403 shown in FIG. 4. These two waveforms can be analyzed separately as shown in FIGS. 9B and 9C. The voltage ramp in FIG. 9B shows that the sawtooth voltage waveform in FIG. 9C induces IED-spreading voltage fluctuations at the substrate surface potential u. sh1 During this time, the ionic current I i1 should be compensated.

[0078] Inductance L f To determine the voltage and current waveforms of the filter inductor during the ramp phase should be derived as plotted in Figure 10. step The sawtooth voltage waveform in

[0079]

number

[0080] The average inductor current can be described by:

[0081]

number

[0082] The inductor current in one switching period is determined by

[0083]

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[0084] To narrow the IED, a DC inductor current is required during the ramp phase. The inductor current pulsation caused by the sawtooth voltage waveform is due to the sheath capacitance C sh1 This can lead to charge differences across the substrate, which creates voltage fluctuations on the surface of the substrate and propagates the IED. sh1 Maximum charge difference ΔQ through max is represented by times A and B in FIG.

[0085]

number

[0086] This occurs when

[0087]

number

[0088] IEDW is equal to

[0089]

number

[0090] where IEDW is in eV. Therefore, given the load parameters and required IEDW, the minimum filter inductance is

[0091]

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[0092] Furthermore, the slope rate can be calculated by

[0093]

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[0094] Since it is determined by f,min is a fixed T step If you use

[0095]

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[0096] can be determined by

[0097] 11, a voltage waveform generator 1107 can combine features of the voltage waveform generator 207 of FIG. 5 and the voltage waveform generator 707 of FIG. 7. The multilevel converter unit 1101 can be identical to the multilevel converter unit 501 and is connected between the PE 1103 and a switch node 511. A switched damping circuit 1106, which can be identical to the switched damping circuit 504 of the voltage waveform generator 207, can be arranged between the switch node 511 and the output node 510 in series with the filter inductor 1104 and the blocking capacitor 1102. The clamp circuit 1105 can be identical to the clamp circuit 705. Advantageously, the clamp node 512 is arranged between the filter inductor 1104 and the blocking capacitor 1102.

[0098] 12, in an alternative voltage waveform generator 1207, a switched damping circuit 1206 (identical to switched damping circuit 1106) is placed between a filter inductor 1204 and a blocking capacitor 1202, and optionally between a clamp node formed by a clamp circuit 1205 and the blocking capacitor 1202. The multilevel converter unit 1201 may be identical to the multilevel converter unit 1101, connected between the PE 1203 and the switch node 511.

[0099] 13, an exemplary topology of the voltage waveform generator 1107 comprises a multilevel converter unit 1101 comprising a T-converter 1111 and a series of cascaded H-bridge cells 1112. The T-converter 1111 comprises a low voltage node 1113, a midpoint voltage node 1114, and a high voltage node 1115, which form the input nodes of the T-converter 1111. The voltage levels V dsn and k1V stepTwo DC voltage sources 1108, 1109, each providing a low voltage node 1113, are connected in series between nodes 1113 and 1115. Specifically, the negative voltage terminal of DC voltage source 1109 is coupled to low voltage node 1113, and the positive voltage terminal of DC voltage source 1109 is coupled to mid-voltage node 1114. Mid-voltage node 1114 is coupled to the negative voltage terminal of DC voltage source 1108, and the positive voltage terminal of DC voltage source 1108 is coupled to high voltage node 1115. Mid-voltage node 1114 may be connected to PE 1103. Switch S, which is advantageously a bidirectional current (two-quadrant) switch, 11 and S 12 respectively connect each of the high voltage node 1115 and the low voltage node 1113 to the output node 1116 of the T-converter 1111. The midpoint voltage node 1114 is connected to the output node 1116 of the T-converter 1111 by a switch S 13 -S 14 , which is advantageously a four-quadrant switch. The output node 1116 of the T-converter 1111 is advantageously connected to (a first terminal 1117 of) a series of cascaded H-bridge cells 1112. Advantageously, the second terminal of the last H-bridge cell of the series of cascaded H-bridge cells 1112 defines the switch node 511. The advantage of using a T-converter on the back side is that a non-isolated DC-DC converter can be used as the DC voltage source, thus resulting in fewer electromagnetic interference (EMI) issues compared to when using a floating voltage source. V dsn The value of V step It will be appreciated that the voltage pulses may not be multiples of . As a result, the required voltage pulses can be generated more flexibly.

[0100] A total number of cascaded H-bridge cells 1112 equal to n-1 (n=2, 3, ...) may be cascaded between converter 1111 (output node 1116) and switch node 511. Advantageously, each of cascaded H-bridge cells 1112 has two switch arms, S i1 -S i4 and S i2 -S i3A capacitor 1118 is provided in the DC link connecting the midpoints of the cascaded H-bridge cells (i=2,...,n). The DC link voltage of each cascaded H-bridge cell is kV. step , k3V step , …, k n V step and k2, k3, …, k n are all positive integers, possibly different values ​​to obtain asymmetric converters. The maximum and minimum switch node voltages u sn are V dsn +(k2+k3+…+k n )V step and -(k1+k2+k3+...+k n )V step k2, k3, …, k n Depending on the combination of values ​​of , some H-bridge cells may have redundant switching states when they result in the same voltage value. In this case, the redundant switching states may be used to keep the voltage of the DC link capacitor 1118 balanced. Alternatively, an isolated DC-DC voltage source may be used instead of the DC link capacitor 1118 for one or more (or all) of the H-bridge cells without redundant switching states. One advantage of the asymmetric configuration of the multilevel converter unit 1101 is that it allows for a much larger number of different voltage levels than the number of modules (the number of T-converters 1111 and H-bridge cells 1112).

[0101] For example, k1=k2=k3=…=k n , the cascaded H-bridge cells scale linearly. As a result, each H-bridge cell has redundant states and voltage balancing is possible. Symmetrically, k1=3k2=3 2 k3=…=3 n-1 k n If , i.e., the cascaded H-bridge cells are scaled in a ternary configuration, there are no redundant switching states and all cascaded H-bridge cells should use isolated DC-DC converters.

[0102] Power Switch S 11 , S 12 , …, S n4 can be modeled by an ideal switch in parallel with a diode. In practice, various types of semiconductors can be utilized, including but not limited to Si-based and SiC MOSFETs, IGBTs with anti-parallel diodes, and GaN transistors. In addition, the switch S of the switched damping circuit 1106 d1 and S d2 form a four-quadrant switch, which can pass bidirectional current when turned on and block bidirectional voltage when turned off. A switched damping circuit 1106 can be used to suppress the LC resonance.

[0103] Advantageously, the multi-level converter unit 1101 can be utilized to generate voltage pulses in addition to step-wise ramp voltages. This is especially true for voltage pulses (T pulse The voltage level between step Alternatively, the magnitude of the pulse (both rising and falling edges) should be flexibly determined, and this value can be expressed as a multilevel voltage (V step The voltage waveform generator may include different converters for the voltage pulse and the voltage ramp, especially when the voltage may not be an integer multiple of V. This allows a wider range of voltage values ​​to be generated, but this is not always necessary. dsn is V step , it can be advantageously selected to generate voltage pulses of flexible values, as it need not be a multiple of .

[0104] The combination of a T-converter and a cascaded H-bridge cell allows for intermediate voltage levels not only during the voltage ramp, but also during the voltage pulse period and between the voltage pulse and the negative voltage ramp. Advantageously, this allows the load capacitor voltage to gently resonate to the target value by LC resonance. For example, the flat time (T pulse ), the multilevel converter unit is connected to Vdsn At the beginning of the negative voltage ramp, the multilevel converter unit outputs 3V step If V is to be output, V dsn and 3V step One or more intermediate voltage levels between, e.g., V dsn -V step , V dsn -2V step , or V dsn -3V step As a result, the voltage of the load capacitor can be smoothly reduced by LC resonance, and ideally, this process can be lossless. The selection of the intermediate voltage levels and their corresponding time lengths can be determined by a method called trajectory control, as known in the art (see, for example, DOI: 10.23919 / IPEC-Himeji2022-ECCE53331.2022.9806909, Yu Qihao et al., "Accurate Ion Energy Control in Plasma Processing by Switched-Mode Power Converter," 2022 International Power Electronics Conference).

[0105] Referring to FIG. 14, a specific example of a voltage waveform generator 1107 may comprise two cascaded H-bridge cells 1112 scaled in a binary configuration where k1=2k2=4k3.

[0106] In a particular implementation of the clamp circuit 1105, the upper clamp leg is fixed to the (highest) voltage level of the multilevel converter unit 1101. Specifically, u cn The maximum value of D c1 Through V dsn This advantageously eliminates the need for an extra voltage source V compared to the clamp circuit of FIG. max In addition, V dsn Exceeds sn voltage level can be omitted, so V dsn +V step , Vdsn +2V step , and V dsn +3V step is not used, which enhances the voltage balancing capability of this converter.

[0107] Assume that the states of the submodules 1111, 1112 of the multilevel converter unit 1101 are represented by 1, 0, and -1 when the positive voltage, 0 voltage, and negative voltage of the submodules are connected to the outputs, respectively. For example, the vector [1,0,0] represents the positive V of the first submodule (T-converter 1111) while the two H-bridge cells 1112 are bypassed. dsn Therefore, [1,0,0] represents u sn =V dsn Similarly, as shown in Table 1, u sn All possible voltage levels of , as well as the corresponding state vectors, can be found. It can be seen that there are enough redundant switching states for both H-bridge cells. Therefore, those redundant states can be used to balance both flying capacitors.

[0108] [Table 1]

[0109] Figure 15 shows an example of how the voltage waveform generator 1107 of Figure 14 can operate to obtain a tailored voltage waveform. The switching frequency of each cell is inversely proportional to its DC link voltage. At the end of the previous ramp phase, denoted T0, V dsn Ga u sn Connected to Filter Inductor Current

[0110]

number

[0111] and u cn and uout The voltage on the load capacitors begins to rise. Meanwhile, all the load capacitors begin to discharge.

[0112] At T1,

[0113]

number

[0114] rises to a relatively large value, and u cn is V dsn and V between T1 and T2 dsn During the steady state of the system, the DC blocking voltage V b appears across the blocking capacitor. Therefore, the output voltage u out hau out =V dsn -V b is fixed at V b The value of V can be adjusted by controlling the time length between T1 and T2. dsn When is fixed, u out is V b Between T1 and T2, all load capacitors should be fully discharged and ready for the new ramp stage. When all load capacitors are fully discharged, the output current i out will have a small DC value.

[0115] At T2, the new voltage value is u sn This is applied to V dsn -V step , V dsn -2V step , or V dsn -3V step The filter inductor has a negative voltage applied to it,

[0116]

number

[0117] begins to decrease.

[0118]

number

[0119] is i out is larger, so u cn is still V dsn At T3,

[0120]

number

[0121] but

[0122]

number

[0123] When it decreases to cn is no longer V dsn LC resonance occurs. cn and u out Both begin to decline.

[0124] In T4, u cn and u out reaches the desired starting voltage value of the ramping step. Then, to obtain the stepwise voltage that decreases periodically, T4 to T 15 3V between step , 2V step , …, -7V step By continuously applying , an output ramp can be generated. Based on Table 1, the correct switching state can be selected for voltage balancing purposes. The voltage ramp is

[0125]

number

[0126] Therefore, to obtain different slopes of the stepped voltage waveform, V step and T step Any of the above may be changed.

[0127] T4~T 15 In order to suppress the LC resonance that may occur during d1 and S d2 A switched damping circuit can be connected in the loop by turning off (opening)

[0128] Aspects of the present disclosure are described in the following alphanumeric clauses: A1. A voltage waveform generator (207, 707, 1107, 1207) for a plasma-assisted processing apparatus, the voltage waveform generator comprising: an output node (510); a switch node (511) electrically coupled to the output node; and a multilevel voltage source converter (501, 1101) coupled to the switch node; the voltage waveform generator is configured to generate an adapted voltage waveform (402) at the output node, the adapted voltage waveform comprising a first portion (405) having a negative voltage slope; The multilevel voltage source converter is configured to apply a sequence of monotonically decreasing voltage levels at the switch nodes, and the voltage levels and their respective predetermined periods (T step ) corresponds to a negative voltage slope, thereby obtaining a first portion of an adapted voltage waveform at the output node. A2. The voltage waveform generator of clause A1, wherein the negative voltage slope is constant and the slope is constant over the sequence of monotonically decreasing voltage levels. A3. A multilevel voltage source converter is a converter in which the difference between successive voltage levels in a sequence of monotonically decreasing voltage levels is constant and the voltage steps (V step ) the voltage waveform generator of clause A1 or A2, configured to output a plurality of different voltage levels that are integer multiples of the voltage step. A4. Each specified period (T step ) is the same throughout the sequence of voltage levels. A5. The voltage waveform generator of any one of clauses A1 to A4, wherein the multi-level voltage source converter is configured to output at least three different voltage levels. A6. The voltage waveform generator of clause A5, wherein the multi-level voltage source converter is a switched mode power converter configured to have redundant switching states to obtain at least three voltage levels. A7. The voltage waveform generator of clause A6, wherein the multilevel voltage source converter comprises at least one non-isolated DC / DC converter and a plurality of DC link capacitors corresponding to at least some of the at least three voltage levels. A8. The voltage waveform generator of any one of clauses A1 to A7, wherein the multilevel voltage source converter comprises a T-converter (1111) in series with at least one H-bridge cell (1112). A9. The voltage waveform generator of clause A8, further comprising a first DC voltage source (1108) and a second DC voltage source (1109) connected in series, wherein the negative terminal of the second DC voltage source (1109) is connected to the first node, the positive terminal of the second DC voltage source is connected to the midpoint node, the negative terminal of the first DC voltage source (1108) is connected to the midpoint node, and the positive terminal of the first DC voltage source is connected to the second node, and a T-type converter is connected to the first node, the second node, and the midpoint node, preferably configured such that the midpoint node is connected to permanent earth (1103). A10. A second DC voltage source (1109) provides a first voltage level (kV step ), and at least one H-bridge cell (1112) is configured to output a respective second voltage level (k2V step ), wherein the ratio of the first voltage level to the second voltage level is a fraction of a positive integer. A11. The voltage waveform generator of any one of clauses A1-A10, further comprising a filter inductor (1104) coupled between the switch node and the output node. A12. The voltage waveform generator of any one of clauses A1 to A11, further comprising: a clamp node (511) between the switch node and the output node; and a voltage clamp circuit (1105) coupled to the clamp node and configured to fix a maximum voltage and / or a minimum voltage at the clamp node. A13. The voltage waveform generator of any one of clauses A1-A12, further comprising a blocking capacitor (1102) coupled to the output node and configured to apply a voltage offset. A14. The voltage waveform generator of any one of clauses A1-A13, further comprising a switched damping circuit coupled to the output node and configured to limit transient current. A15. The voltage waveform generator of any one of clauses A1-A14, wherein the adapted voltage waveform further comprises a second portion consisting of a positive voltage pulse, and wherein the multilevel voltage source converter is further configured to generate the positive voltage pulse. A16. The voltage waveform generator of clause A15 in conjunction with clause A9 or clause A10, wherein the multilevel voltage source converter is configured to generate a positive voltage pulse by connecting the first DC voltage source (1108) to the switch node (511). A17. The voltage waveform generator of any one of clauses A1 to A16, comprising a control unit (115), the control unit configured to control operation of the multi-level voltage source converter to generate a sequence of voltage levels, preferably the control unit comprising a current measurement unit (119) and / or a voltage measurement unit (116) configured to sense respective currents and / or voltages at the output nodes (510). A18. Apparatus for plasma-assisted processing of insulating substrates, comprising: a plasma generator; a processing stage configured to support an insulating substrate; and a voltage waveform generator according to any one of clauses A1 to A17; The apparatus has an output node connected to a processing table. B1. A method of generating a tailored voltage waveform for plasma-assisted processing of a substrate, the tailored voltage waveform comprising a first portion having a negative voltage slope, the first portion comprising: applying a sequence of monotonically decreasing voltage levels to the switch node, the voltage levels and their respective predetermined periods (T step each voltage level is applied for a respective predetermined period such that ≡ ... electrically coupling the switch node to the output node to obtain a first portion of the adapted voltage waveform; A method characterized in that it is obtained by B2. The method of clause B1, wherein the negative voltage slope is constant in the first portion, and the slope is constant over the sequence of monotonically decreasing voltage levels. B3. A sequence of monotonically decreasing voltage levels is generated with a constant voltage step (V step ) a method according to clause B1 or B2. B4. The method of any one of clauses B1 to B3, wherein each predetermined period is the same throughout the sequence of voltage levels. B5. The method of any one of clauses B1 to B4, comprising processing a sequence of monotonically decreasing voltage levels between the switch node and the output node through one or more of a filtering inductor, a voltage clamp, signal damping, and a voltage bias. B6. A method for plasma-assisted processing of insulating substrates, comprising: placing an insulating substrate on a processing table; generating an adapted voltage waveform according to the method of any one of clauses B1 to B5; generating a plasma to produce ions; applying a tailored voltage waveform to the work stage to control the energy of the ions at the exposed surface of the insulating substrate; The method wherein the first portion is applied while ions are bombarding the exposed surface. B7. The method of clause B6, wherein the sequence of monotonically decreasing voltage levels begins at a first voltage level defined by a predetermined ion energy at the exposed surface. B8. The method of clause B6 or B7, wherein the tilt is selected to maintain a constant potential at the exposed surface while ions bombard the exposed surface. B9. The method of any one of clauses B6 to B8, wherein the adapted voltage waveform further comprises a second portion consisting of a positive voltage pulse. B10. The method of clause B9, wherein the adapted voltage waveform comprises a plurality of sequences of positive voltage pulses and descending voltage ramps. [Explanation of symbols]

[0129] 100 devices 101 Power supply 102 connecting lead wire 103 Connecting lead wire 105 Matching Network 106 Connector 107 Connector 108 coil 109 Insulating substrate materials 110 Reactor 111 units 112 Interface 114 Power Converter 115 Controller 116 Voltage Measuring Unit 117 Connections 118 Control Signal 119 Current Measuring Unit 120 connections 121 Protective Earth 201 Bulk Plasma 202 Sheath 203 Sheath 204 Substrate 205 Parasitic capacitance 206 Leakage Inductance 207 Power Converter 401 Voltage waveform 402 Adapted voltage waveform 403 Sawtooth Waveform 404 Voltage Level 405 negative continuous and possibly linear voltage ramp, first part 501 Multilevel Converter Unit 502 Voltage Bias Component 503 PE 504 Switched Damping Circuit 505 Cascaded H-Bridge Converter 506 Neutral Point Clamped Converter 507 Flying Capacitor Converter 508 Voltage Source 509 Voltage Source 510 Output Nodes 511 Switch Node 601 Voltage waveform 602 Voltage waveform 603 Stepped voltage waveform 604 Stepped voltage waveform 701 Multilevel Converter Unit 702 Blocking Capacitor 704 Output filter inductor 705 Clamp Circuit 707 Voltage Waveform Generator 715 Upper clamp leg 725 Lower Clamp Leg 801 Stepped voltage waveform 802 Voltage waveform 803 Voltage Pulse 1101 Multilevel Converter Unit 1102 Blocking Capacitor 1103 PE 1104 Filter inductor 1105 Clamp Circuit 1106 Switched damping circuit 1107 Voltage Waveform Generator 1108 DC voltage source 1109 DC voltage source 1111 T-type converter 1112 Cascaded H-Bridge Cells 1113 Low Voltage Node 1114 Midpoint voltage node 1115 High Voltage Node 1116 Output Node 1117 First terminal 1118 Capacitor 1201 Multilevel Converter Unit 1202 Blocking Capacitor 1203 PE 1204 filter inductor 1205 clamp circuit 1206 Switched Damping Circuit 1207 Voltage Waveform Generator 5070 Flying Capacitor

Claims

1. A voltage waveform generator (207, 707, 1107, 1207) for a plasma-assisted processing apparatus, the voltage waveform generator comprising: an output node (510); a switch node (511) electrically coupled to the output node; and a multilevel voltage source converter (501, 1101) coupled to the switch node; the voltage waveform generator is configured to generate an adapted voltage waveform (402) at the output node, the adapted voltage waveform comprising a first portion (405) having a negative voltage slope; The multilevel voltage source converter is configured to apply a sequence of monotonically decreasing voltage levels at the switch nodes, the voltage levels and their respective predetermined periods (T step ) corresponds to the negative voltage slope, thereby obtaining the first portion of the adapted voltage waveform at the output node; A voltage waveform generator, characterized in that the multilevel voltage source converter comprises at least one H-bridge cell (1112) and a series T-converter (1111).

2. 2. The voltage waveform generator of claim 1, wherein the negative voltage slope is constant, and the slope is constant over the sequence of monotonically decreasing voltage levels.

3. The multilevel voltage source converter is configured such that the difference between successive voltage levels of the sequence of monotonically decreasing voltage levels is constant and the voltage step (V step 3. The voltage waveform generator of claim 1, configured to output a plurality of different voltage levels that are integer multiples of the voltage step, such that the voltage step is equal to

4. Each of the predetermined periods (T step 4. The voltage waveform generator of claim 1, wherein the first and second inputs are the same throughout the sequence.

5. 5. The voltage waveform generator of claim 1, wherein at least one of the at least one H-bridge cells comprises a DC link capacitor (1118).

6. 6. The voltage waveform generator of claim 1, wherein the at least one H-bridge cell comprises a plurality of H-bridge cells cascaded between the T-converter and the switch node.

7. 7. The voltage waveform generator of claim 6, wherein the plurality of H-bridge cells are configured to have redundant switching states that result in the same voltage value.

8. 8. A voltage waveform generator according to any one of claims 1 to 7, wherein the T-converter comprises at least one non-isolated DC / DC converter, preferably a pair of non-isolated DC / DC converters.

9. 9. The voltage waveform generator of claim 1, further comprising a first DC voltage source (1108) and a second DC voltage source (1109) connected in series, the negative terminal of the second DC voltage source (1109) being connected to a first node, the positive terminal of the second DC voltage source being connected to a midpoint node, the negative terminal of the first DC voltage source (1108) being connected to the midpoint node, and the positive terminal of the first DC voltage source being connected to a second node, and the T-type converter (1111) being connected to the first node, the second node, and the midpoint node, preferably configured such that the midpoint node is connected to a permanent earth (1103).

10. The second DC voltage source (1109) provides a first voltage level (k 1 V step ), wherein the at least one H-bridge cell (1112) is configured to output a respective second voltage level (k 2 V step 10. The voltage waveform generator of claim 9, configured to output a voltage waveform generator having a first voltage level and a second voltage level, the ratio of which is a fraction of a positive integer.

11. 11. The voltage waveform generator of claim 1, further comprising a filter inductor (1104) coupled between the switch node and the output node.

12. 12. The voltage waveform generator of claim 1, further comprising: a clamp node (511) between the switch node and the output node; and a voltage clamp circuit (1105, 1205) coupled to the clamp node and configured to fix a maximum voltage and / or a minimum voltage at the clamp node.

13. 13. The voltage waveform generator of claim 1, further comprising a blocking capacitor (1102) coupled to the output node and configured to apply a voltage offset.

14. 14. The voltage waveform generator of claim 1, further comprising a switched damping circuit (1106) coupled to the output node.

15. The switched damping circuit (1106) includes a lossy element (R d ) and a power switch (S d 15. The voltage waveform generator of claim 14, comprising:

16. The adapted voltage waveform further comprises a second portion consisting of a positive voltage pulse, the positive voltage pulse having a positive voltage level (V d ) followed by the initial voltage level (V s 16. The voltage waveform generator of claim 1, wherein the negative voltage ramp of the first portion (405) starts from the initial voltage level.

17. 17. The voltage waveform generator of claim 16, wherein the multilevel voltage source converter is further configured to generate the positive voltage pulse.

18. 18. The voltage waveform generator of claim 17, wherein the multilevel voltage source converter is configured to generate the positive voltage pulse by connecting the first DC voltage source (1108) to the switch node (511).

19. 19. The voltage waveform generator of claim 1, comprising a control unit (115), configured to control operation of the multilevel voltage source converter to generate the sequence, preferably comprising a current measurement unit (119) and / or a voltage measurement unit (116) configured to sense respective currents and / or voltages at the output nodes (510).

20. 1. An apparatus for plasma-assisted processing of insulating substrates, comprising: a plasma generator; a processing table configured to support the insulating substrate; a voltage waveform generator according to any one of claims 1 to 19; Equipped with The apparatus, wherein the output node is connected to the work table.

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