Position-based prefetching in processor-based devices

Abstract

A method for performing position-based prefetching in a processor-based device is disclosed, in which the processor-based device includes a position-based prefetcher circuit associated with a first cache memory device having a faster access time and smaller capacity than a second cache memory device. The position-based prefetcher circuit identifies an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request and determines a set and way of the second cache memory device that stores data corresponding to the second memory address. The position-based prefetcher circuit then stores the first memory address as a trigger memory address and a set indicator and a way indicator of the set and way, respectively, of the second cache memory device as a target identifier in a prefetcher array entry of a prefetcher array.

Description

[Technical Field]

[0001] Field of Disclosure The disclosed technology relates to prefetching and storing data for multi-level cache memories or structures, and more particularly to storing prefetched data more efficiently. [Background technology]

[0002] background Memory access latency in a processor-based device refers to the interval between the time the processor initiates a memory access request for data (i.e., by executing a memory load instruction) and the time the processor actually receives the requested data. If the time interval is large enough that the processor is forced to stall further execution of instructions while waiting for the memory access request to be fulfilled, memory access latency can adversely affect processor performance. One technique for minimizing the effects of memory access latency is the use of cache memory, also simply referred to as a "cache." A cache is a memory device that has a smaller capacity than system memory but is more quickly accessible by the processor due to the type of memory used and / or the cache's physical location relative to the processor. A cache can be used to reduce memory access latency by storing copies of data retrieved from frequently accessed memory locations in system memory or from another higher-level cache (i.e., a cache further from the processor).

[0003] Modern processor-based devices use a memory hierarchy that includes a system memory along with multiple levels of cache memories located between the system memory and the processor. Levels of cache memories closer to the processor (i.e., lower-level caches) have faster access times and smaller storage capacities, while levels of cache memories further from the processor have slower access times and larger storage capacities. When a memory access request is received from the processor, the first-level cache (i.e., the smallest, fastest cache located closest to the processor) is queried to see if the requested data is stored in the first-level cache. If the requested data is not stored, the memory access request is forwarded to the next higher cache level in the memory hierarchy (presumably system memory), which may result in increased memory access latency.

[0004] To mitigate this scenario, processor-based devices may use prefetchers that fetch data from a higher-level cache (or from system memory) and attempt to place the data in a lower-level cache memory before the data is actually requested by the processor. To accomplish this, conventional prefetchers track memory access patterns and identify correlations between current memory access requests and previous memory access requests or processor activity. Once the prefetcher correlates a previously accessed memory address (i.e., a "trigger") with the currently accessed memory address (i.e., a "target"), subsequent occurrences of a memory access request to the trigger address cause the prefetcher to retrieve the data stored at the target memory address. Traditionally, prefetchers track triggers and targets using corresponding full or partial cache line addresses, resulting in increased precision at the expense of significant storage space. Summary of the Invention

[0005] overview Exemplary embodiments disclosed herein include performing position-based prefetching in a processor-based device. In this regard, in one exemplary embodiment, the processor-based device provides a position-based prefetcher circuit. As used herein, "position-based" refers to a position-based prefetcher circuit configured to store the location of data corresponding to a target memory address in a next-higher level cache, instead of storing all or a portion of the target memory address itself. Accordingly, the position-based prefetcher circuit includes a prefetcher array that stores a plurality of prefetcher array entries. Each prefetcher array entry stores a target identifier including a trigger memory address and a set indicator and a way indicator that respectively represent a set and a way of the next-higher level cache that stores the data corresponding to the trigger memory address. The position-based prefetcher circuit is associated with a first cache memory device (i.e., the next-higher level cache) having a faster access time and smaller capacity than a second cache memory device (i.e., the next-higher level cache).

[0006] During typical operation, a prefetcher array is populated in a location-based prefetcher circuit by first identifying an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request. The location-based prefetcher circuit then determines a set and way of a second cache memory device that stores data (e.g., a cache line) corresponding to the second memory address. In some embodiments, when providing prefetch data, the set and way may be determined by the location-based prefetcher circuit based on location information provided by the second cache memory device. The location-based prefetcher circuit then stores the first memory address as a trigger memory address of a prefetcher array entry, and further stores the set indicator and way indicator of the set and way, respectively, of the second cache memory device as target identifiers of the prefetcher array entry. In some embodiments, the set indicator of each target identifier may include a number of bits N (where N is the binary logarithm of the number of sets in the second cache memory device), while the way indicator of each target identifier may include a number of bits W (where W is the binary logarithm of the number of ways in the second cache memory device).

[0007] Because each prefetcher array entry stores a set indicator and a way indicator instead of a target memory address, fewer data bits are required. This allows a position-based prefetcher to have a larger capacity than a conventional prefetcher while occupying the same area and consuming the same amount of power, or to have the same capacity as a conventional prefetcher while occupying a smaller area and consuming less power. Furthermore, embodiments of the position-based prefetcher circuit disclosed herein can achieve greater energy efficiency, and the techniques described herein can be applied to any multi-level cache or data structure. Some embodiments of the position-based prefetcher circuit may provide additional data structures to further improve performance. For example, in some embodiments, the position-based prefetcher circuit may provide a memory reference history list that stores multiple memory addresses corresponding to observed memory access requests. The memory reference history list may be placed in the position-based prefetcher circuit when observing a memory access request, and the position-based prefetcher circuit may later use the memory reference history list to identify an association between a trigger memory address and a target memory address.

[0008] Furthermore, in some embodiments, the position-based prefetcher circuit may perform the prefetch by first observing a subsequent memory access request for the first memory address and then determining that the first memory address corresponds to a trigger memory address of the prefetcher array entry. The position-based prefetcher circuit prefetches data by using the set indicator and way indicator of the target identifier of the prefetcher array entry to retrieve data stored in a set and way of the second cache memory device identified by the set indicator and way indicator, respectively. In some embodiments, the retrieved data may be stored in a prefetcher buffer entry of a prefetcher buffer of the position-based prefetcher circuit. In such embodiments, when the position-based prefetcher circuit observes a subsequent memory access request for the second memory address, the position-based prefetcher circuit may promote the prefetcher buffer entry that stores the retrieved data from the prefetcher buffer to the first cache memory device.

[0009] In some embodiments, each prefetcher array entry in the prefetcher array may further include a confidence value associated with a target memory address corresponding to the prefetcher array entry, which is increased or decreased if the position-based prefetcher circuit observes a positive or negative confidence event, respectively. If the confidence value for the prefetcher array entry falls below a confidence threshold, in such embodiments, the position-based prefetcher circuit may remove the prefetcher array entry. Some embodiments of the position-based prefetcher circuit may include a prefetcher filter that tracks target locations of recent prefetches (e.g., a set indicator and a way indicator for each recent prefetch). Before retrieving data from the second cache memory device, the position-based prefetcher circuit checks the prefetcher filter to see if it stores a target location corresponding to the target memory address, and performs the data retrieval only if a target location corresponding to the target memory address is not found in the prefetcher filter.

[0010] According to some embodiments, the position-based prefetcher circuitry further provides a throttling counter that is incremented or decremented when the position-based prefetcher circuitry observes an event that indicates negative or positive cache performance, respectively. If the throttling counter exceeds a throttling threshold, in such embodiments, the position-based prefetcher circuitry may throttle prefetching (e.g., by pausing prefetching operations of the position-based prefetcher circuitry for a specified time interval).

[0011] In another exemplary embodiment, a processor-based device is provided. The processor-based device includes a first cache memory device and a second cache memory device, the first cache memory device having a faster access time and smaller capacity than the second cache memory device. The processor-based device further includes a position-based prefetcher circuit associated with the first cache memory device, the position-based prefetcher circuit including a prefetcher array including a plurality of prefetcher array entries. The plurality of prefetcher array entries include a corresponding plurality of trigger memory addresses and a corresponding plurality of target identifiers, each target identifier including a set indicator and a way indicator. The position-based prefetcher circuit is configured to identify an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request. The position-based prefetcher circuit is further configured to determine a set and a way of the second cache memory device that stores data corresponding to the second memory address. The position-based prefetcher circuit is further configured to store in a prefetcher array entry among the plurality of prefetcher array entries the first memory address as a trigger memory address prefetcher array entry and a set indicator and a way indicator of the set and way, respectively, of the second cache memory device as a target identifier of the prefetcher array entry.

[0012] In another exemplary embodiment, a method for performing position-based prefetching is provided. The method includes identifying, by a position-based prefetcher circuit associated with a first cache memory device of a processor-based device, an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request. The method further includes determining, by the position-based prefetcher circuit, a set and a way of a second cache memory device that stores data corresponding to the second memory address, wherein the first cache memory device has a faster access time and a smaller capacity than the second cache memory device. The method further includes storing, by the position-based prefetcher circuit, the first memory address as a trigger memory address of the prefetcher array entry and a set indicator and a way indicator of the set and way, respectively, of the second cache memory device as a target identifier of the prefetcher array entry in a prefetcher array entry among a plurality of prefetcher array entries of a prefetcher array of the position-based prefetcher circuit associated with the first memory address as a trigger memory address of the prefetcher array entry and a set indicator and a way indicator of the set and way, respectively, of the second cache memory device as a target identifier of the prefetcher array entry.

[0013] In another exemplary embodiment, a non-transitory computer-readable medium having computer-executable instructions stored thereon is provided. The computer-executable instructions, when executed by a processor, cause the processor to perform a position-based prefetch on a first cache memory device by identifying an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request. The computer-executable instructions further cause the processor to determine a set and a way of a second cache memory device that stores data corresponding to the second memory address, the first cache memory device having a faster access time and a smaller capacity than the second cache memory device. The computer-executable instructions further cause the processor to store the first memory address as a trigger memory address of the prefetcher array entry and a set indicator and a way indicator of the set and the way of the second cache memory device as a target identifier of the prefetcher array entry in a prefetcher array entry among a plurality of prefetcher array entries of a prefetcher array of the position-based prefetcher circuit.

[0014] Those skilled in the art will appreciate the scope of the present disclosure and realize additional embodiments of the present disclosure after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.

[0015] BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a block diagram illustrating an example processor-based device including a position-based prefetcher circuit configured to perform position-based prefetching. [Figure 2]2 provides a flowchart illustrating an example operation of the processor-based device of FIG. 1 performing position-based prefetching, according to some embodiments. [Figure 3A] 10 provides a flowchart illustrating a further exemplary operation of the processor-based device of FIG. 1 retrieving data from a cache using position data stored in a prefetcher array of the position-based prefetcher circuit of FIG. 1 , according to some embodiments. [Figure 3B] 10 provides a flowchart illustrating a further exemplary operation of the processor-based device of FIG. 1 retrieving data from a cache using position data stored in a prefetcher array of the position-based prefetcher circuit of FIG. 1 , according to some embodiments. [Figure 4] A flowchart illustrating an example operation of the processor-based device of FIG. 1 to detect positive and negative confidence events and adjust the confidence values ​​of prefetcher array entries of the prefetcher array of the position-based prefetcher circuit of FIG. 1 is provided, according to some embodiments. [Figure 5] 1 provides a flowchart illustrating an example operation of the processor-based device of FIG. 1 for detecting positive and negative cache performance events and adjusting throttling counters of the position-based prefetcher circuit of FIG. 1 according to some embodiments. [Figure 6] 2 is a block diagram of an example processor-based device (e.g., the processor-based device of FIG. 1) configured to perform position-based prefetching, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0017] Detailed Description Exemplary embodiments disclosed herein include performing position-based prefetching in a processor-based device. In this regard, in one exemplary embodiment, the processor-based device provides a position-based prefetcher circuit. As used herein, "position-based" refers to a position-based prefetcher circuit configured to store the location of data corresponding to a target memory address in a next-higher level cache, instead of storing all or a portion of the target memory address itself. Accordingly, the position-based prefetcher circuit includes a prefetcher array that stores a plurality of prefetcher array entries. Each prefetcher array entry stores a target identifier including a trigger memory address and a set indicator and a way indicator that respectively represent a set and a way of the next-higher level cache that stores the data corresponding to the trigger memory address. The position-based prefetcher circuit is associated with a first cache memory device (i.e., the next-higher level cache) having a faster access time and smaller capacity than a second cache memory device (i.e., the next-higher level cache).

[0018] During typical operation, a prefetcher array is populated in a location-based prefetcher circuit by first identifying an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request. The location-based prefetcher circuit then determines a set and way of a second cache memory device that stores data (e.g., a cache line) corresponding to the second memory address. In some embodiments, when providing prefetch data, the set and way may be determined by the location-based prefetcher circuit based on location information provided by the second cache memory device. The location-based prefetcher circuit then stores the first memory address as a trigger memory address of a prefetcher array entry, and further stores the set indicator and way indicator of the set and way, respectively, of the second cache memory device as target identifiers of the prefetcher array entry. In some embodiments, the set indicator of each target identifier may include a number of bits N (where N is the binary logarithm of the number of sets in the second cache memory device), while the way indicator of each target identifier may include a number of bits W (where W is the binary logarithm of the number of ways in the second cache memory device).

[0019] Because each prefetcher array entry stores a set indicator and a way indicator instead of a target memory address, fewer data bits are required. This allows a position-based prefetcher to have a larger capacity than a conventional prefetcher while occupying the same area and consuming the same amount of power, or to have the same capacity as a conventional prefetcher while occupying a smaller area and consuming less power. Furthermore, embodiments of the position-based prefetcher circuit disclosed herein can achieve greater energy efficiency, and the techniques described herein can be applied to any multi-level cache or data structure. Some embodiments of the position-based prefetcher circuit may provide additional data structures to further improve performance. For example, in some embodiments, the position-based prefetcher circuit may provide a memory reference history list that stores multiple memory addresses corresponding to observed memory access requests. The memory reference history list may be placed in the position-based prefetcher circuit when observing a memory access request, and the position-based prefetcher circuit may later use the memory reference history list to identify an association between a trigger memory address and a target memory address.

[0020] Furthermore, in some embodiments, the position-based prefetcher circuit may perform the prefetch by first observing a subsequent memory access request for the first memory address and then determining that the first memory address corresponds to a trigger memory address of the prefetcher array entry. The position-based prefetcher circuit prefetches data by using the set indicator and way indicator of the target identifier of the prefetcher array entry to retrieve data stored in a set and way of the second cache memory device identified by the set indicator and way indicator, respectively. In some embodiments, the retrieved data may be stored in a prefetcher buffer entry of a prefetcher buffer of the position-based prefetcher circuit. In such embodiments, when the position-based prefetcher circuit observes a subsequent memory access request for the second memory address, the position-based prefetcher circuit may promote the prefetcher buffer entry that stores the retrieved data from the prefetcher buffer to the first cache memory device.

[0021] In some embodiments, each prefetcher array entry in the prefetcher array may further include a confidence value associated with a target memory address corresponding to the prefetcher array entry, which is increased or decreased if the position-based prefetcher circuit observes a positive or negative confidence event, respectively. If the confidence value for the prefetcher array entry falls below a confidence threshold, in such embodiments, the position-based prefetcher circuit may remove the prefetcher array entry. Some embodiments of the position-based prefetcher circuit may include a prefetcher filter that tracks target locations of recent prefetches (e.g., a set indicator and a way indicator for each recent prefetch). Before retrieving data from the second cache memory device, the position-based prefetcher circuit checks the prefetcher filter to see if it stores a target location corresponding to the target memory address, and performs the data retrieval only if a target location corresponding to the target memory address is not found in the prefetcher filter.

[0022] According to some embodiments, the position-based prefetcher circuitry further provides a throttling counter that is incremented or decremented when the position-based prefetcher circuitry observes an event that indicates negative or positive cache performance, respectively. If the throttling counter exceeds a throttling threshold, in such embodiments, the position-based prefetcher circuitry may throttle prefetching (e.g., by pausing prefetching operations of the position-based prefetcher circuitry for a specified time interval).

[0023] In this regard, FIG. 1 illustrates an exemplary processor-based device 100 that provides a processor 102 that performs position-based prefetching. In some aspects, processor 102 may include a central processing unit (CPU) having one or more processor cores, and in some exemplary aspects, may be one of multiple similarly configured processors (not shown) of processor-based device 100. Processor 102 is communicatively coupled to an interconnect bus 104, which in some embodiments may include additional components not shown in FIG. 1 for clarity (e.g., bus controller circuitry and / or arbitration circuitry, as non-limiting examples). Processor 102 is further communicatively coupled via interconnect bus 104 to a memory controller 106, which controls access to and manages the flow of data into and out of system memory 108. System memory 108 provides addressable memory used for data storage by processor-based device 100, and as such may include, as a non-limiting example, synchronous dynamic random access memory (SDRAM).

[0024] 1 includes a memory hierarchy that includes cache memory device 110 and cache memory device 112. In the example of FIG. 1, cache memory device 110 comprises a first level cache that has a faster access speed and smaller capacity than cache memory device 112, which represents the next higher level cache. Cache memory device 110 and cache memory device 112 may each be used to cache local copies of frequently accessed data within processor 102 for faster access (e.g., by a memory access stage of an execution pipeline (not shown) of processor 102).

[0025] Cache memory device 110 and cache memory device 112 each provide a plurality of cache lines (not shown) that store frequently accessed data retrieved from system memory 108. As can be seen in FIG. 1 , cache memory device 112 is organized into a plurality of sets 114(0)-114(S), each including a plurality of ways 116(0)-116(W), 116'(0)-116'(W), in which cache lines can be stored. Thus, in an embodiment in which cache memory device 112 has a capacity of 32 kilobytes (32K) and stores cache lines having a size of 64 bytes, cache memory device 112 may be organized into 64 sets of eight ways each. Although not shown in FIG. 1 , it is understood that cache memory device 110 may be organized into sets and ways in a manner similar to that shown for cache memory device 112.

[0026] The processor-based device 100 of FIG. 1 and its components may include, among other elements, any one or combination of known digital logic elements, semiconductor circuits, processing cores, and / or memory structures. The embodiments described herein are not limited to any particular arrangement of elements, and the disclosed techniques may be readily extended to various configurations and layouts on a semiconductor socket or package. It is understood that some embodiments of the processor-based device 100 may include more or fewer elements than those illustrated in FIG. 1 . For example, the processor 102 may further include one or more functional units, instruction caches, unified caches, memory controllers, interconnect buses, and / or additional memory devices, caches, and / or controller circuits, which are omitted from FIG. 1 for clarity.

[0027] As described above, when a memory access request is received, the cache memory device 110 is first queried to determine whether the requested data should be stored in the cache memory device 110. If the requested data is not stored, the memory access request is forwarded to the cache memory device 112 (and possibly the system memory 108), which may result in increased memory access latency. Conventional processors may mitigate this scenario by using a prefetcher that attempts to fetch data from the cache memory device 112 and place the data in the cache memory device 110 before the data is actually requested by the processor 102. Such a prefetcher tracks memory access patterns and identifies correlations between trigger memory addresses and target memory addresses, which are stored using corresponding full or partial cache line addresses for the target memory addresses. While this approach provides increased precision, conventional prefetchers require significant storage space for the target memory addresses.

[0028] In this regard, processor-based device 100 of FIG. 1 provides position-based prefetcher circuit 118 configured to perform position-based prefetching. Position-based prefetcher circuit 118 is considered “position-based” insofar as it is configured to store the location of data corresponding to a target memory address in a next-higher level cache (e.g., cache memory device 112) instead of storing all or part of the target memory address itself. Thus, position-based prefetcher circuit 118 includes prefetcher array 120, which includes a plurality of prefetcher array entries 122(0) through 122(P) (labeled “PREF ARRAY ENTRY” in FIG. 1 ). As can be seen in FIG. 1 , prefetcher array entry 122(0) stores a trigger memory address 124(0) (labeled “TRIGGER MEM ADDR” in FIG. 1 ) that is used to reference prefetcher array entry 122(0) along with a target identifier 126(0) (labeled “TARGET” in FIG. 1 ). Target identifier 126(0) includes a set indicator 128(0) (labeled "SET" in FIG. 1 ) and a way indicator 130(0) (labeled "WAY" in FIG. 1 ) that represent one of sets 114(0)-114(S) and one of ways 116(0)-116(W), 116'(0)-116'(W), respectively, of cache memory device 112 that stores data corresponding to the target memory address. Although not shown in FIG. 1 for clarity, each prefetcher array entry 122(0)-122(P) includes a trigger memory address and a target identifier that correspond to trigger memory address 124(0) and target identifier 126(0) of prefetcher array entry 122(0).Additionally, although FIG. 1 illustrates position-based prefetcher circuitry 118 as being associated with cache memory device 110 and configured to prefetch data from cache memory device 112, some embodiments may include position-based prefetcher circuitry (not shown) that operates in a similar manner for other levels of the memory hierarchy shown in FIG. 1.

[0029] By using position-based prefetching, position-based prefetcher circuit 118 can reduce the storage costs associated with conventional prefetchers while providing comparable performance. For example, a conventional prefetcher operating in a system using 46-bit virtual memory addresses and a 64-byte cache line size and prefetching cache lines from an 8-way, 32-kilobyte cache memory device requires 40 bits to store the target memory address (i.e., 46 (virtual memory address size in bits) - 6 (binary logarithm of cache line size)). However, by storing the location of data associated with the target memory in the cache memory device, in the same scenario, position-based prefetcher circuit 118 requires only a total of 9 bits: set indicator 128(0) requires 6 bits (i.e., the binary logarithm of 64, the number of sets in the cache memory device), while way indicator 130(0) requires 3 bits (i.e., the binary logarithm of 8, the number of ways in the cache memory device).

[0030] During typical operation, the prefetcher array 120 in the location-based prefetcher circuit 118 of FIG. 1 is populated by first identifying an association between a first memory address 132(0) (labeled “MEM ADDR” in FIG. 1) of a first memory access request 134(0) (labeled “MEM ACC REQ” in FIG. 1) and a second memory address 132(1) (labeled “MEM ADDR” in FIG. 1) of a subsequent second memory access request 134(1) (labeled “MEM ACC REQ” in FIG. 1). In some embodiments, this association is identified by the location-based prefetcher circuit 118 using a memory reference history list 136 (labeled “MEMORY REF HISTORY LIST” in FIG. 1) that stores multiple memory addresses (not shown) corresponding to recently observed memory access requests (e.g., memory access requests 134(0) and 134(1)). Position-based prefetcher circuit 118 may place a memory address in memory reference history list 136 upon observing a corresponding memory access request, and may then use memory reference history list 136 to identify an association between a trigger memory address (e.g., memory address 132(0) in FIG. 1 ) and a target memory address (e.g., memory address 132(1) in FIG. 1 ). For example, memory reference history list 136 may be configured to store a specified number of most recently requested memory addresses, and may identify the trigger memory address and the corresponding target memory address in memory reference history list 136 as memory addresses separated by a given correlation distance.

[0031] Next, position-based prefetcher circuit 118 determines a set (e.g., set 114(0)) and a way (e.g., way 116(0)) of cache memory device 112 that stores data corresponding to memory address 132(1). In some embodiments, position-based prefetcher circuit 110 may determine set 114(0) and way 116(0) based on location information provided by cache memory device 112 (e.g., when providing prefetch data to position-based prefetcher circuit 118). Position-based prefetcher circuit 118 stores memory address 132(0) as a trigger memory address 124(0) of a prefetcher array entry (e.g., prefetcher array entry 122(0)), and further stores set indicator 128(0) and way indicator 130(0) of set 114(0) and way 116(0), respectively, of cache memory device 112 as target identifiers for prefetcher array entry 122(0). As described above, in some embodiments, the set indicator 128(0) of the target identifier 126(0) may include a number of bits N (where N is the binary logarithm of the number S of sets 114(0) through 114(S) of the cache memory device 112), while the way indicator 130(0) of the target identifier 126(0) may include a number of bits W (where W is the binary logarithm of the number W of ways 116(0) through 116(W), 116'(0) through 116'(W) of the cache memory device 112).

[0032] 1 illustrates trigger memory address 124(0) associated with a single target identifier 126(0), in some embodiments, trigger memory address 124(0) can be associated with multiple target identifiers. Such embodiments with multiple target identifiers associated with a single trigger memory address can handle more complex control access patterns.

[0033] In some embodiments, position-based prefetcher circuit 118 performs prefetching by first observing a subsequent memory access request for memory address 132(0) (e.g., a subsequent occurrence of memory access request 134(0)). Position-based prefetcher circuit 118 then determines that memory address 132(0) corresponds to trigger memory address 124(0) of prefetcher array entry 122(0). Position-based prefetcher circuit 118 then uses set indicator 128(0) and way indicator 130(0) of target identifier 126(0) of prefetcher array entry 122(0) to prefetch data by retrieving data stored in set 114(0) and way 116(0) of cache memory device 112 identified by set indicator 128(0) and way indicator 130(0), respectively.

[0034] In some embodiments, the retrieved data may be stored directly in cache memory device 110. However, to avoid polluting cache memory device 110 with prefetched data, in some embodiments, position-based prefetcher circuit 118 may provide a prefetcher buffer 138 that stores the prefetched data and the corresponding target memory address to be prefetched in the prefetcher buffer in one of multiple prefetcher buffer entries 140(0)-140(B) (labeled "BUF" in FIG. 1 ). In some embodiments, prefetcher buffer entries 140(0)-140(B) may store additional metadata (not shown) for the corresponding prefetched data (e.g., a pointer to a corresponding prefetcher array entry 122(0)-122(P) in prefetcher array 120). In such an embodiment, target memory address 132(1) and the retrieved data are stored in a prefetcher buffer entry (e.g., prefetcher buffer entry 140(0)). If position-based prefetcher circuit 118 later observes a subsequent memory access request to target memory address 132(1) that results in a hit to prefetcher buffer 138 (e.g., a subsequent occurrence of memory access request 134(1)), position-based prefetcher circuit 118 may promote prefetcher buffer entry 140(0), which stores data retrieved from prefetcher buffer 138, to cache memory device 110. In some embodiments, when prefetcher buffer 138 is full, position-based prefetcher circuit 118 may use an aging mechanism that operates in a first-in, first-out (FIFO) manner to replace older prefetched data that has not been promoted with new prefetched data.According to some embodiments, prefetcher array entries 122(0)-122(P) of prefetcher array 120 may further include a confidence value (e.g., confidence value 142(0) (labeled "CONF VALUE" in FIG. 1 )) for prefetcher array entry 122(0) to provide feedback regarding confidence in the corresponding target identifier 126(0) stored in prefetcher array 120. In such embodiments, position-based prefetcher circuit 118 may increase or decrease confidence value 142(0) if position-based prefetcher circuit 118 observes a positive confidence event or a negative confidence event, respectively. A positive confidence event may include, by way of non-limiting example, promoting the corresponding prefetcher buffer entry (e.g., prefetcher buffer entry 140(0)) to cache memory device 110. A negative confidence event may include, by way of non-limiting example, the removal of prefetcher buffer entry 140(0) from prefetcher buffer 138 without promotion to cache memory device 110, or a memory access request hitting both cache memory device 110 and prefetcher buffer 138. To link a positive confidence event or a negative confidence event to a prefetcher array entry 122(0)-122(P), position-based prefetcher circuit 118 may use metadata (e.g., a pointer associating prefetcher buffer entry 140(0)-140(B) with the corresponding prefetcher array entry 122(0)-122(P)) stored in prefetcher buffer entry 140(0)-140(B) of prefetcher buffer 138. In such an embodiment, position-based prefetcher circuit 118 is further configured to determine whether confidence value 142(0) for prefetcher array entry 122(0) is below confidence threshold 144. If the confidence value 142(0) is below the confidence threshold 144, the position-based prefetcher circuit 118 removes the prefetcher array entry 122(0) from the prefetcher array 120.

[0035] To avoid unnecessary generation of prefetches, in some embodiments, position-based prefetcher circuit 118 may include a prefetcher filter 146 that tracks target locations 148(0)-148(F) (labeled "LOC" in FIG. 1 ) of recent prefetches (i.e., the set and way indicators for each prefetch). In such an embodiment, position-based prefetcher circuit 118 places the target locations in prefetcher filter 146 whenever it performs a prefetch. Later, before prefetching data from cache memory device 112, position-based prefetcher circuit 118 first determines whether the target location (e.g., the target location corresponding to memory address 132(1)) is stored in cache memory device 112. Position-based prefetcher circuit 118 is configured to perform the data retrieval only if the target location corresponding to memory address 132(1) is not found in prefetcher filter 146.

[0036] Some embodiments of the position-based prefetcher circuit 118 may provide a throttling mechanism that tracks its respective performance and inhibits prefetching (e.g., by pausing prefetching operations for a specified time) if performance degrades. Accordingly, in such embodiments, the position-based prefetcher circuit 118 provides a throttling counter 150 that is decremented or incremented when the position-based prefetcher circuit 118 observes a positive or negative cache performance event, respectively. A positive cache performance event may include, by way of non-limiting example, a promotion from the prefetcher buffer 138 to the cache memory device 110, or a memory access request miss to both the cache memory device 110 and the prefetcher buffer 138. A negative cache performance event may include, by way of non-limiting example, a eviction from the prefetcher buffer 138 without promotion, a memory access request hit in both the cache memory device 110 and the prefetcher buffer 138, or a memory access request hit in the prefetcher filter 146. In such an embodiment, the position-based prefetcher circuit 118 is further configured to determine whether the throttling counter 150 exceeds a throttling threshold 152. If the throttling counter 150 exceeds the throttling threshold 152, the position-based prefetcher circuit 118 may inhibit prefetching. To illustrate an example operation of the processor-based device 100 of FIG. 1 performing position-based prefetching according to some embodiments, FIG. 2 provides a flowchart illustrating example operations 200. For clarity, reference will be made to elements of FIG. 1 when describing FIG. 2. It is understood that some of the example operations 200 illustrated in FIG. 2 may be performed in an order other than that illustrated herein or may be omitted.In some embodiments, the example operations 200 may begin with a position-based prefetcher circuit (e.g., position-based prefetcher circuit 118 of FIG. 1 ) associated with a first cache memory device (e.g., cache memory device 110 of processor-based device 100 of FIG. 1 ) of a processor-based device observing a plurality of memory access requests (e.g., memory access requests 134(0)-134(1) of FIG. 1 ) (block 202). Next, in such embodiments, the position-based prefetcher circuit 118 stores a corresponding memory address for each memory access request of the plurality of memory access requests 134(0)-134(1) in a memory reference history list (e.g., memory reference history list 136 of FIG. 1 ) (block 204).

[0037] The location-based prefetcher circuit 118 identifies an association between the first memory address of the first memory access request and the second memory address of the subsequent second memory access request (e.g., memory address 132(0) of memory access request 134(0) and memory address 132(1) of memory access request 134(1), respectively, in FIG. 1 (block 206). In some embodiments, the operation of block 206 of identifying an association between the first memory address 132(0) of the first memory access request 134(0) and the second memory address 132(1) of the subsequent second memory access request 134(1) is based on the memory reference history list 136 (block 208).

[0038] Next, the position-based prefetcher circuit 118 determines a set and way (e.g., set 114(0) and way 116(0), respectively, in FIG. 1 ) of a second cache memory device (e.g., cache memory device 112 in FIG. 1 ) that stores data corresponding to the second memory address 132(1), where the first cache memory device 110 has a faster access time and smaller capacity than the second cache memory device 112 (block 210). Next, the position-based prefetcher circuit 118 stores the first memory address 132(0) as the trigger memory address (e.g., trigger memory address 124(0) in FIG. 1 ) of the prefetcher array entry 122(0) and the set indicator and way indicator (e.g., set indicator 128(0) and way indicator 130(0) in FIG. 1 ) of the set 114(0) and way 116(0), respectively, of the second cache memory device 112 as the target identifier (e.g., target identifier 126(0) in FIG. 1 ) of the prefetcher array entry 122(0) in a prefetcher array entry among the multiple prefetcher array entries of the prefetcher array (e.g., prefetcher array entry 122(0) among prefetcher array entries 122(0)-122(P) of the prefetcher array 120 in FIG. 1 ) (block 212).

[0039] 3A and 3B provide a flowchart illustrating a further exemplary operation 300 of the processor-based device 100 of FIG. 1 for retrieving data from a cache memory device using location data stored in the prefetcher array 120 of the location-based prefetcher circuit 118 of FIG. 1 , according to some embodiments. For clarity, reference will be made to elements of FIG. 1 when describing FIGS. 3A and 3B. It is understood that portions of the exemplary operation 300 illustrated in FIGS. 3A and 3B may be performed in an order other than that illustrated herein or may be omitted. In FIG. 3A, the exemplary operation 300 begins with the location-based prefetcher circuit 118 observing a third memory access request for a first memory address 132(0) (e.g., a subsequent occurrence of memory access request 134(0) of FIG. 1) (block 302). The location-based prefetcher circuit 118 determines that the first memory address 132(0) corresponds to the trigger memory address 124(0) of the prefetcher array entry 122(0) (block 304). In an embodiment of position-based prefetcher circuit 118 providing a prefetcher filter (e.g., prefetcher filter 146 of FIG. 1), position-based prefetcher circuit 118 determines whether a target location corresponding to second memory address 132(1) is found among a plurality of target locations of the prefetcher filter (e.g., a plurality of target locations 148(0)-148(F) of prefetcher filter 146 of FIG. 1), and whether the plurality of target locations correspond to a plurality of recent prefetches (block 306). If the plurality of target locations correspond to a plurality of recent prefetches, a prefetch has recently been performed on data at second memory address 132(1), and therefore, another prefetch is not required. Accordingly, processing continues in a conventional manner (block 308).

[0040] If, in decision block 306, position-based prefetcher circuit 118 determines that a target location corresponding to second memory address 132(1) is not found among the plurality of target locations 148(0)-148(F) of prefetcher filter 146, position-based prefetcher circuit 118 retrieves set indicator 128(0) and way indicator 130(0) of target identifier 126(0) of prefetcher array entry 122(0) (i.e., the prefetcher array entry that stores first memory address 132(0) as trigger memory address 124(0)) (block 310). Next, the position-based prefetcher circuit 118 retrieves from the second cache memory device 112 data corresponding to the second memory address 132(1) stored in the set 114(0) and way 116(0) of the second cache memory device 112, as identified by the set indicator 128(0) and way indicator 130(0), respectively (block 312). In some embodiments, the example operation 300 continues to block 314 or block 318 of FIG. 3B.

[0041] Referring now to FIG. 3B , in some embodiments, position-based prefetcher circuit 118 stores second memory address 132(1) and the data corresponding to second memory address 132(1) in first cache memory device 110 (block 314). Processing then continues in a conventional manner (block 316). In some embodiments, instead of storing second memory address 132(1) and the corresponding data in first cache memory device 110, position-based prefetcher circuit 118 may store second memory address 132(1) and the data corresponding to second memory address 132(1) in a prefetcher buffer entry among a plurality of prefetcher buffer entries in a prefetcher buffer (e.g., prefetcher buffer entry 140(0) among a plurality of prefetcher buffer entries 140(0)-140(B) of prefetcher buffer 138 of FIG. 1 ) (block 318). Next, in such an embodiment, position-based prefetcher circuit 118 may later observe a fourth memory access request (e.g., a subsequent occurrence of memory access request 134(1) in FIG. 1 ) for second memory address 132(1) (block 320). Position-based prefetcher circuit 118 determines whether to store second memory address 132(1) in prefetcher buffer entry 140(0) of multiple prefetcher buffer entries 140(0)-140(B) of prefetcher buffer 138 (block 322). If second memory address 132(1) is not to be stored in prefetcher buffer entry 140(0), processing continues in a conventional manner (block 316). However, if the position-based prefetcher circuit 118 determines that the second memory address 132(1) should be stored in prefetcher buffer entry 140(0), then the position-based prefetcher circuit 118 promotes prefetcher buffer entry 140(0) from the prefetcher buffer 138 to the first cache memory device 110 (block 324). Then, at block 316, processing continues in a conventional manner.To illustrate an example operation of the processor-based device 100 of FIG. 1 for detecting positive and negative confidence events and adjusting confidence values ​​accordingly, according to some embodiments, FIG. 4 provides a flowchart illustrating an example operation 400. For clarity, reference will be made to elements of FIG. 1 when describing FIG. 4. In FIG. 4, the example operation 400 begins with the position-based prefetcher circuit 118 detecting a positive confidence event or a negative confidence event (block 402). As described above, a positive confidence event may include promoting one of the prefetcher buffer entries 140(0)-140(B) from the prefetcher buffer 138 to the cache memory device 110, while a negative confidence event may include one of removing one of the prefetcher buffer entries 140(0)-140(B) from the prefetcher buffer 138 without promotion, or a memory access request hitting both the cache memory device 110 and the prefetcher buffer 138.

[0042] If the position-based prefetcher circuit 118 detects a positive confidence event, the position-based prefetcher circuit 118 increases the confidence value for the corresponding prefetcher array entry (e.g., confidence value 142(0) for prefetcher array entry 122(0) in FIG. 1 ) (block 404). Processing then continues in a conventional manner (block 406). If the position-based prefetcher circuit 118 detects a negative confidence event, the position-based prefetcher circuit 118 decreases the confidence value 142(0) for prefetcher array entry 122(0) (block 408). The position-based prefetcher circuit 118 then determines whether the confidence value 142(0) for prefetcher array entry 122(0) is less than a confidence threshold (e.g., confidence threshold 144 in FIG. 1 ) (block 410). If the confidence value 142(0) for prefetcher array entry 122(0) is not less than the confidence threshold, processing continues in a conventional manner (block 406). However, if the position-based prefetcher circuit 118 determines in decision block 410 that the confidence value 142(0) for prefetcher array entry 122(0) is less than the confidence threshold 144, then the position-based prefetcher circuit 118 removes prefetcher array entry 122(0) (block 412). Processing then continues in the conventional manner (block 406).

[0043] FIG. 5 provides a flowchart illustrating an example operation 500 of the processor-based device 100 of FIG. 1 for detecting positive and negative cache performance events and adjusting the throttling counters of the position-based prefetcher circuit 118 of FIG. 1 accordingly, according to some embodiments. For clarity, reference will be made to elements of FIG. 1 when describing FIG. 5. The example operation 500 begins with the position-based prefetcher circuit 118 detecting a positive cache performance event or a negative cache performance event (block 502). According to some embodiments, a positive cache performance event may include one of a promotion from the prefetcher buffer 138 to the cache memory device 110, or a memory access request miss to both the cache memory device 110 and the prefetcher buffer 138. A negative cache performance event may include one of a eviction without promotion from the prefetcher buffer 138, a memory access request hit in both the cache memory device 110 and the prefetcher buffer 138, or a memory access request hit in the prefetcher filter 146.

[0044] If the position-based prefetcher circuit 118 detects a positive cache performance event, the position-based prefetcher circuit 118 decrements a throttling counter (e.g., throttling counter 150 of FIG. 1 ) (block 504). Processing then continues in a conventional manner (block 506). If the position-based prefetcher circuit 118 detects a negative cache performance event, the position-based prefetcher circuit 118 increments the throttling counter 150 (block 508). The position-based prefetcher circuit 118 then determines whether the throttling counter 150 exceeds a throttling threshold (e.g., throttling threshold 152 of FIG. 1 ) (block 510). If the throttling counter 150 does not exceed the throttling threshold, processing continues in a conventional manner (block 506). However, if the position-based prefetcher circuit 118 determines at decision block 510 that the throttling counter 150 exceeds the throttling threshold 152, then the position-based prefetcher circuit 118 inhibits prefetching by the position-based prefetcher circuit 118 (block 512). Processing then continues in the conventional manner (block 506).

[0045] FIG. 6 is a block diagram of an exemplary processor-based device 600 (e.g., processor-based device 100 of FIG. 1 ) that uses fetch character data to issue an immediate value for a program counter (PC)-relative load instruction. Processor-based device 600 may be a circuit or circuits included in an electronic board card, e.g., a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a handheld device, or any other device, and may represent, for example, a server or a user computer. In this example, processor-based device 600 includes processor 602. Processor 602 represents one or more general-purpose processing circuits (e.g., a microprocessor, a central processing unit, etc.) and may correspond to processor 102 of FIG. 1 . Processor 602 is configured to execute processing logic with instructions that perform the operations and steps described herein. In this example, processor 602 includes an instruction cache 604 for temporary fast-access memory storage of instructions, and instruction processing circuitry 610. Instructions fetched or prefetched from memory (e.g., system memory 608) across system bus 606 are stored in instruction cache 604. Instruction processing circuitry 610 is configured to process instructions fetched into instruction cache 604 and to process the instructions for execution.

[0046] The processor 602 and the system memory 608 are coupled to a system bus 606, which can interconnect peripheral devices included in the processor-based device 600. As is well known, the processor 602 communicates with these other devices by exchanging address, control, and data information over the system bus 606. For example, the processor 602 can communicate bus transaction requests to a memory controller 612 in the system memory 608, an example of a peripheral device. Although not illustrated in FIG. 6, multiple system buses 606 can be provided, with each system bus comprising a different fabric. In this example, the memory controller 612 is configured to provide memory access requests to a memory array 614 in the system memory 608. The memory array 614 comprises an array of storage bit cells that store data. The system memory 608 can be, by way of non-limiting example, a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM)), and a static memory (e.g., flash memory, static random access memory (SRAM)), etc.

[0047] Other devices may be connected to the system bus 606. As illustrated in FIG. 6, these devices may include, by way of example, a system memory 608, one or more input devices 616, one or more output devices 618, a modem 624, and one or more display controllers 620. The input devices 616 may include any type of input device, including, but not limited to, input keys, switches, audio processors, etc. The output devices 618 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The modem 624 may be any device configured to enable the exchange of data over a network 626. The network 626 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a Bluetooth™ network, and the Internet. The modem 624 may be configured to support any type of desired communication protocol. Additionally, the processor 602 may be configured to access a display controller 620 over the system bus 606 to control information sent to one or more displays 622. The displays 622 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0048] 6 may include a set of instructions 628 that are executed by processor 602 for any desired application in accordance with the instructions. The instructions 628 may be stored in system memory 608, processor 602, and / or instruction cache 604, as examples of non-transitory computer-readable medium 630. Furthermore, the instructions 628 may reside completely or at least partially within system memory 608 and / or processor 602 during execution. Furthermore, the instructions 628 may be transmitted or received over network 626, such that network 626 includes computer-readable medium 630.

[0049] While the computer-readable medium 630 is shown in an exemplary embodiment to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions 628. Furthermore, the term "computer-readable medium" should be taken to include any medium that can store, encode, or retain a set of instructions for execution by a processing device, causing the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. Accordingly, the term "computer-readable medium" should be taken to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0050] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or embodied in machine-executable instructions usable to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software processes.

[0051] Embodiments disclosed herein may be provided as a computer program product or software process including a machine-readable medium (or computer-readable medium) having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0052] Unless otherwise specified, as is apparent from the above, throughout the specification, descriptions using, for example, the terms "processing," "computing," "determining," "displaying," etc., will be understood to refer to the operations and processing of a computer system or similar electronic computing device that manipulates and transforms data and memory represented as physical (electronic) quantities in the registers of the computer system into other data that is similarly represented as physical quantities in the memory or registers of the computer system or other such information storage, transmission, or display device.

[0053] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will emerge from the description above. Further, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​can be used to implement the teachings of the embodiments as described herein.

[0054] Furthermore, those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The components of the systems described herein may be used in, by way of example, any circuit, hardware component, integrated circuit (IC), or IC chip. The memories disclosed herein may be any type and size of memory and may be configured to store any type of desired information. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented will depend on the particular application, design choices, and / or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as a departure from the scope of the present embodiments.

[0055] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed by a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a controller may be a processor. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. Further, a processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0056] The embodiments disclosed herein may be embodied in hardware and with instructions stored in hardware, which may reside, for example, in RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0057] It should also be noted that the operational steps described in any of the exemplary embodiments described herein are described for purposes of example and explanation. The described operations may be performed in many different orders other than the illustrated order. Furthermore, an operation described as a single operational step may actually be performed in many different steps. Furthermore, one or more operational steps described in an exemplary embodiment may be combined. Furthermore, those skilled in the art will appreciate that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above specification may be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields or particles, or any combination thereof.

[0058] Unless otherwise expressly specified, it is in no way intended that any method described herein be construed as requiring that the method steps be performed in a particular order. Thus, unless a method claim actually recites the order in which the method steps should be followed, or unless the claim or specification specifically states otherwise that the steps should be limited to a particular order, no particular order is intended to be inferred.

[0059] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, subcombinations and variations of the disclosed embodiments that incorporate the spirit and essence of the present invention may occur to those skilled in the art, the present invention should be construed as including all within the scope of the appended claims and equivalents of the claims.

Claims

1. a first cache memory device and a second cache memory device, the first cache memory device having a faster access time and a smaller capacity than the second cache memory device; a position-based prefetcher circuit associated with the first cache memory device, the position-based prefetcher circuit including a prefetcher array including a plurality of prefetcher array entries; the plurality of prefetcher array entries including a corresponding plurality of trigger memory addresses and a corresponding plurality of target identifiers; Each target identifier of the plurality of target identifiers includes a set indicator and a way indicator. Position-based prefetcher circuit and Including, The position-based prefetcher circuitry comprises: Identifying an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request; determining a set and way of the second cache memory device that stores data corresponding to the second memory address; storing the first memory address as a trigger memory address prefetcher array entry, and a set indicator and a way indicator of the set and the way of the second cache memory device as the target identifier of the prefetcher array entry in a prefetcher array entry among the plurality of prefetcher array entries; It is configured as follows: Processor-based devices.

2. the set indicator comprises a number N of bits, where N is the binary logarithm of the number of sets in the second cache memory device; the way indicator comprises a number of bits W, where W is the binary logarithm of the number of ways of the second cache memory device; The processor-based device of claim 1 .

3. the position-based prefetcher circuit further includes a memory reference history list; The position-based prefetcher circuitry comprises: Observe multiple memory access requests, storing a corresponding memory address for each of the plurality of memory access requests in the memory reference history list; It is further structured as follows:

2. The processor-based device of claim 1, wherein the position-based prefetcher circuitry is configured to identify the association between the first memory address of the first memory access request and the second memory address of the subsequent second memory access request based on the memory reference history list.

4. The position-based prefetcher circuitry comprises: observing a third memory access request to the first memory address; determining that the first memory address corresponds to the trigger memory address of the prefetcher array entry; extracting the set indicator and the way indicator of the target identifier of the prefetcher array entry; Retrieving from the second cache memory device the data corresponding to the second memory address stored in the set and the way of the second cache memory device identified by the set indicator and the way indicator, respectively. The processor-based device of claim 1 further configured to:

5. the position-based prefetcher circuitry further includes a prefetcher buffer including a plurality of prefetcher buffer entries; 5. The processor-based device of claim 4, wherein the position-based prefetcher circuitry is further configured to store the second memory address and the data corresponding to the second memory address in a prefetcher buffer entry among the plurality of prefetcher buffer entries of the prefetcher buffer.

6. The position-based prefetcher circuitry comprises: observing a fourth memory access request to the second memory address; determining that the second memory address is stored in the prefetcher buffer entry among the plurality of prefetcher buffer entries of the prefetcher buffer; In response to determining that the second memory address is found in a prefetcher buffer entry among the plurality of prefetcher buffer entries in the prefetcher buffer, promote the prefetcher buffer entry from the prefetcher buffer to the first cache memory device. The processor-based device of claim 5 further configured to:

7. the plurality of prefetcher array entries further including a corresponding plurality of confidence values; The position-based prefetcher circuitry comprises: decreasing a confidence value for the prefetcher array entry in response to detecting a negative confidence event, the negative confidence event comprising: removing the prefetcher buffer entry from the prefetcher buffer without promoting it to the first cache memory device; and A memory access request hits both the first cache memory device and the prefetcher buffer. including one of increasing a confidence value for the prefetcher buffer entry in response to detecting a positive confidence event, the positive confidence event including promoting the prefetcher buffer entry to the first cache memory device; The processor-based device of claim 5 further configured to:

8. The position-based prefetcher circuitry comprises: determining that the confidence value for the prefetcher array entry is less than a confidence threshold; In response to determining that the confidence value for the prefetcher array entry is less than the confidence threshold, remove the prefetcher array entry.

8. The processor-based device of claim 7, further configured to:

9. the position-based prefetcher circuit further includes a prefetcher filter including a plurality of target locations corresponding to a plurality of recent prefetches; the location-based prefetcher circuitry is further configured to determine, before retrieving the data corresponding to the second memory address, that a target location corresponding to the second memory address is not found among the plurality of target locations of the prefetcher filter; 6. The processor-based device of claim 5, wherein the location-based prefetcher circuitry is configured to retrieve the data corresponding to the second memory address in response to determining that the target location corresponding to the second memory address is not found among the plurality of memory addresses of the prefetcher filter.

10. the position-based prefetcher circuit further includes a throttling counter; The position-based prefetcher circuitry comprises: decrementing the throttling counter in response to detecting a positive cache performance event, the positive cache performance event being promoting from the prefetcher buffer to the first cache memory device; and a memory access request miss in both the first cache memory device and the prefetcher buffer; including one of Incrementing the throttling counter in response to detecting a negative cache performance event, the negative cache performance event being removing from the prefetcher buffer without promoting; a hit of the memory access request in both the first cache memory device and the prefetcher buffer; and A memory access request hits the prefetcher filter including one of the following:

10. The processor-based device of claim 9, further configured to:

11. The position-based prefetcher circuitry comprises: determining that the throttling counter exceeds a throttling threshold; inhibiting prefetching by the position-based prefetcher circuit in response to determining that the throttling counter exceeds the throttling threshold.

11. The processor-based device of claim 10, further configured to:

12. 1. A method for position-based prefetching, comprising: identifying, by a position-based prefetcher circuit associated with a first cache memory device of the processor-based device, an association between a first memory address of a first memory access request and a second memory address of a subsequent second memory access request; determining, by the position-based prefetcher circuitry, a set and way of a second cache memory device that stores data corresponding to the second memory address, the first cache memory device having a faster access time and a smaller capacity than the second cache memory device; storing, by the position-based prefetcher circuit, a prefetcher array entry among a plurality of prefetcher array entries in a prefetcher array of the position-based prefetcher circuit associated with the first memory address as a trigger memory address of a prefetcher array entry and the set indicator and the way indicator of the set and the way, respectively, of the second cache memory device as a target identifier of the prefetcher array entry; A method comprising:

13. observing a third memory access request to the first memory address by the position-based prefetcher circuit; determining by the position-based prefetcher circuitry that the first memory address corresponds to the trigger memory address of the prefetcher array entry; retrieving, by the position-based prefetcher circuitry, the set indicator and the way indicator of the target identifier of the prefetcher array entry; retrieving, from the second cache memory device by the position-based prefetcher circuit, the data corresponding to the second memory address stored in the set and the way of the second cache memory device identified by the set indicator and the way indicator, respectively; The method of claim 12 further comprising:

14. 14. The method of claim 13, further comprising storing, by the position-based prefetcher circuitry, the second memory address and the data corresponding to the second memory address in a prefetcher buffer entry among a plurality of prefetcher buffer entries of a prefetcher buffer.

15. observing a fourth memory access request to the second memory address by the position-based prefetcher circuit; determining by the position-based prefetcher circuitry that the second memory address is stored in the prefetcher buffer entry among the plurality of prefetcher buffer entries of the prefetcher buffer; promoting, by the position-based prefetcher circuitry, the prefetcher buffer entry from the prefetcher buffer to the first cache memory device in response to determining that the second memory address is found in the prefetcher buffer entry among the plurality of prefetcher buffer entries of the prefetcher buffer; The method of claim 14 further comprising:

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