Semiconductor device and manufacturing method thereof

Abstract

An embodiment of the present invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, an epitaxial structure located on one side of the substrate, and a plurality of gates located on one side of the epitaxial structure away from the substrate. The gates extend along a first direction. The plurality of gates are arranged along a second direction. The first direction and the second direction intersect and are both parallel to a plane in which the substrate is located. The plurality of gates include a first gate and a second gate. Along the second direction, the first gate is located on one side of the second gate closer to an edge of the semiconductor device. The maximum temperature of the first gate is T1, and the maximum temperature of the second gate is T2, where (T2 - T1) / T1≦20%. The above technical solution can uniformly distribute the temperature of the semiconductor device, reduce attenuation of the device's high-frequency performance, and improve output power.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to the field of semiconductors, and more particularly to semiconductor devices and methods for fabricating the same. [Background technology]

[0002] Gallium nitride (GaN) semiconductor devices have significant advantages, including a wide bandgap, high electron mobility, high breakdown field strength, and high heat resistance. Compared to first-generation silicon semiconductors and second-generation gallium arsenide semiconductors, GaN is more suitable for the manufacture of high-temperature, high-voltage, high-frequency, and high-power electronic devices, and is expected to have a wide range of applications, including in the RF / microwave and power electronics fields. GaN is already being actively researched in the current semiconductor industry.

[0003] Currently, 5G communications are placing increasing demands on the bandwidth and operating frequency of semiconductor chips. Gallium nitride high electron mobility transistors are high electron mobility devices formed by two-dimensional electron gas in an AlGaN / GaN heterojunction. Due to their excellent suitability for high frequency, high voltage, and high power applications, they are attracting considerable attention in the 5G communications field.

[0004] In gallium nitride high-frequency power amplifiers, improving the device's power and high-frequency performance has always been a goal pursued by gallium nitride high-frequency chips. However, various factors affect the device's output power, high-frequency performance, and reliability in the design and use of semiconductor devices. For example, uneven temperature distribution within the device increases the amount of heat generated by the device, reducing reliability and further affecting the device's output power and reliability. Therefore, achieving uniform temperature distribution within the semiconductor device is a critical technology in the semiconductor device design process. Summary of the Invention [Problem to be solved by the invention]

[0005] In view of this, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, which can distribute the temperature of the semiconductor device uniformly, reduce attenuation of the high frequency performance of the device, and improve output power. [Means for solving the problem]

[0006] In a first aspect, an embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, an epitaxial structure located on one side of the substrate, and a plurality of gates located on one side of the epitaxial structure away from the substrate. The gates extend along a first direction. The plurality of gates are arranged along a second direction. The first direction and the second direction intersect and are both parallel to a plane in which the substrate is located. The plurality of gates include a first gate and a second gate. Along the second direction, the first gate is located on one side of the second gate closer to an edge of the semiconductor device. The maximum temperature of the first gate is T1, and the maximum temperature of the second gate is T2, where (T2-T1) / T1≦20%.

[0007] Optionally, the semiconductor device further includes a plurality of sources located on one side of the epitaxial structure away from the substrate, the sources extending along the first direction, and the plurality of sources arranged along the second direction.

[0008] The plurality of sources include a first source and a second source. Along the second direction, the first source is disposed adjacent to the first gate, the second source is disposed adjacent to the second gate, and the first source is located on one side of the second source closer to an edge of the semiconductor device. The semiconductor device further includes through holes penetrating the substrate and the epitaxial structure. The through holes include a first type through hole and a second type through hole. Along the thickness direction of the semiconductor device, the first source overlaps the first type through hole, and the second source overlaps the second type through hole. The first type through holes have a larger total opening area than the second type through holes.

[0009] Optionally, the first type of through-holes includes at least one first through-hole, and the second type of through-holes includes at least one second through-hole, and the first through-hole has a larger opening area than the second through-hole.

[0010] Alternatively, the first through hole is located on one side of the other through hole closer to an edge of the semiconductor device along the second direction, and the second through hole is located on one side of the other through hole closer to a center of the semiconductor device along the second direction, and the opening areas of the through holes gradually decrease along a direction from the first through hole to the second through hole.

[0011] Alternatively, the first through hole is located on one side of the other through hole that is closer to an edge of the semiconductor device along the second direction, and the second through hole is located on one side of the other through hole that is closer to a center of the semiconductor device along the second direction. The opening area of ​​the first through hole is S1, the opening area of ​​the second through hole is S2, and S2 <S1≦4*S2である。

[0012] Optionally, the first type of through holes includes at least two first through holes, the second type of through holes includes at least one second through hole, and the first through holes are more numerous than the second through holes.

[0013] Alternatively, the first through holes may be located on one side of the other through holes closer to an edge of the semiconductor device along the second direction, and the second through holes may be located on one side of the other through holes closer to a center of the semiconductor device along the second direction, and the number of the through holes may gradually decrease along a direction from the first through holes to the second through holes.

[0014] Alternatively, the first through holes are located on one side of the other through holes closer to an edge of the semiconductor device along the second direction, and the second through holes are located on one side of the other through holes closer to a center of the semiconductor device along the second direction. The number of the first through holes among the first type through holes is n1, and the number of the second through holes among the second type through holes is n2, where (n1-n2)≦5.

[0015] Optionally, the semiconductor device further includes a plurality of sources located on one side of the epitaxial structure away from the substrate. The sources extend along the first direction. The plurality of sources are arranged along the second direction. The plurality of sources include a first source and a second source. Along the second direction, the first source is located adjacent to the first gate, the second source is located adjacent to the second gate, and the first source is located on one side of the second source closer to the edge of the semiconductor device. The semiconductor device further includes through holes penetrating the substrate and the epitaxial structure. The through holes include a first type through hole and a second type through hole. Along the thickness direction of the semiconductor device, the first source overlaps the first type through hole, and the second source overlaps the second type through hole. Along the first direction, the center of the first type through hole is located on one side closer to the center of the semiconductor device than the center of the second type through hole.

[0016] Optionally, there is a gate spacing along the second direction between two adjacent gates. The plurality of gate spacings include a first gate spacing close to an edge of the semiconductor device along the second direction and a second gate spacing away from the edge of the semiconductor device relative to the first gate spacing. The first gate spacing is narrower than the second gate spacing along the second direction.

[0017] Optionally, the second gate spacing is located on one side of any other gate spacing closer to the center of the semiconductor device, and the gate spacing gradually increases along a side from the first gate spacing toward the second gate spacing.

[0018] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor device. The method includes providing a substrate, forming an epitaxial structure on one side of the substrate, and forming a plurality of gates on one side of the epitaxial structure away from the substrate. The gates extend along a first direction. The plurality of gates are arranged along a second direction. The first direction and the second direction intersect with each other and are parallel to a plane in which the substrate is located. The plurality of gates include a first gate and a second gate. Along the second direction, the first gate is located on one side of the second gate closer to an edge of the semiconductor device. The maximum temperature of the first gate is T1, the maximum temperature of the second gate is T2, and (T2-T1) / T1≦20%.

[0019] In the semiconductor device according to the embodiment of the present invention, a plurality of gates are disposed on one side of the epitaxial structure away from the substrate, and a first gate of the plurality of gates is located on one side of the semiconductor device closer to the edge of the second gate, and the maximum temperature T1 of the first gate and the maximum temperature T2 of the second gate satisfy (T2-T1) / T1≦20%, thereby ensuring a small temperature difference between the gates and distributing the temperature of the semiconductor device uniformly, reducing the attenuation of the high frequency performance of the device and improving the output power. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a structural schematic diagram of a semiconductor device according to an embodiment of the present invention; [Figure 2] 2 is a schematic cross-sectional view of the semiconductor device taken along the line AA' in FIG. 1. [Figure 3] 2 is a schematic cross-sectional view of the semiconductor device taken along the line BB' in FIG. 1. [Figure 4] 10A and 10B are structural schematic diagrams of another semiconductor device according to an embodiment of the present invention; [Figure 5] 10A and 10B are structural schematic diagrams of another semiconductor device according to an embodiment of the present invention. [Figure 6]10A and 10B are structural schematic diagrams of another semiconductor device according to an embodiment of the present invention. [Figure 7] 10A and 10B are structural schematic diagrams of another semiconductor device according to an embodiment of the present invention. [Figure 8] 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be described in more detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are merely for the purpose of understanding the present invention and are not intended to limit the present invention. For the sake of convenience, the drawings show only a portion related to the present invention, and not all of the structures.

[0022] FIG. 1 is a structural schematic diagram of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device includes a substrate 110, an epitaxial structure 120 located on one side of the substrate 110, and a plurality of gates 130 located on one side of the epitaxial structure 120 away from the substrate 110. The gates 130 extend along a first direction (the X direction shown in FIG. 1). The plurality of gates 130 are arranged along a second direction (the Y direction shown in FIG. 1). The first direction X and the second direction Y intersect and are both parallel to the plane in which the substrate 110 is located. The plurality of gates 130 include a first gate 1301 and a second gate 1302. Along the second direction Y, the first gate 1301 is located on one side of the second gate 1302 near the edge of the semiconductor device. The maximum temperature of the first gate 1301 is T1, the maximum temperature of the second gate 1302 is T2, and (T2-T1) / T1≦20%.

[0023] 1, the substrate 110 may be made of one or more of the following materials: silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, diamond, or other materials suitable for growing gallium nitride. The epitaxial structure 120 is located on one side of the substrate 110 and may be made of one or more of III-V compound semiconductor materials, such as gallium arsenide, aluminum gallium arsenide, gallium nitride, aluminum gallium nitride, or indium gallium nitride.

[0024] Furthermore, among the multiple gates 130 located on one side of the epitaxial structure 120 away from the substrate 110, a first gate 1301 is located on one side of the second gate 1302 near the edge of the semiconductor device. During operation of the semiconductor device, each gate 130 located in the active region self-heats, i.e., each gate generates heat. Furthermore, the heat generated in each gate 130 diffuses to adjacent gates 130, i.e., mutual heating also occurs between two adjacent gates 130. That is, during normal operation of the semiconductor device, each gate 130 generates self-heating and mutual heating, and the temperature of each gate 130 is the sum of the temperatures generated by self-heating and mutual heating. Although the temperature difference between the gates 130 due to self-heating is small, the temperature of the first gate 1301 due to mutual heating is low because the first gate 1301 is located on one side near the edge of the semiconductor device along the second direction Y and there are fewer gates 130 adjacent to the first gate 1301.

[0025] Specifically, when the maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate satisfy (T2-T1) / T1≦20%, the temperature difference between the maximum temperature T1 of the first gate 1301 located on one side near the edge of the semiconductor device and the maximum temperature T2 of the second gate 1302 can be reduced, thereby distributing the temperature of the semiconductor device evenly, reducing the heat loss of the device and improving the output power of the semiconductor device.

[0026] In the semiconductor device according to the embodiment of the present invention, multiple gates are disposed on one side of the epitaxial structure away from the substrate, and a first gate of the multiple gates is located on one side of the semiconductor device closer to the edge of the second gate, and the maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate satisfy (T2-T1) / T1≦20%, thereby ensuring a small temperature difference between the gates. This allows for uniform temperature distribution of the semiconductor device, reducing attenuation in high frequency performance and improving output power.

[0027] Alternatively, with continued reference to FIG. 1, the maximum temperatures of any two adjacent gates 130 are similar.

[0028] Specifically, the maximum temperatures of any two adjacent gates 130 are similar to ensure uniform temperature distribution in the semiconductor device and sufficient reduction in attenuation of high frequency performance.

[0029] 2 is a schematic cross-sectional view of the semiconductor device taken along line A-A' in FIG. 1. Referring to FIGS. 1 and 2, the semiconductor device further includes a plurality of sources 140 located on one side of the epitaxial structure 120 away from the substrate 110. The sources 140 extend along a first direction X. The plurality of sources 140 are arranged along a second direction Y. The plurality of sources 140 include a first source 1401 and a second source 1402. Along the second direction Y, the first source 1401 is disposed adjacent to the first gate 1301, and the second source 1402 is disposed adjacent to the second gate 1302, with the first source 1401 located on one side of the second source 1402 near the edge of the semiconductor. The semiconductor device further includes a through-hole 150 penetrating the substrate 110 and the epitaxial structure 120. The through holes 150 include a first type through hole 1501 and a second type through hole 1502. Along the thickness direction of the semiconductor device (the Z direction shown in FIG. 2), the first source 1401 overlaps with the first type through hole 1501, and the second source 1402 overlaps with the second type through hole 1502. The first type through hole 1501 has a larger total opening area than the second type through hole.

[0030] Specifically, the source 140 is connected to the back surface of the semiconductor device by a through-hole 150. For example, the through-hole 150 may penetrate the substrate 110 and the epitaxial structure 120, i.e., may be connected to the source 140 by a source signal input electrode D located on one side of the substrate 110 away from the epitaxial structure 120. That is, the source 140 is electrically connected to the source signal input electrode D by the through-hole 150. For example, when the substrate 110 and the epitaxial structure 120 are formed in sequence, the source signal input electrode D can be electrically connected to the source 140 by drilling holes and filling the holes in the substrate 110 and each layer of the epitaxial structure 120 with a metal connection material.

[0031] Note that the through-hole 150 penetrates the substrate 110 and the epitaxial structure 120, i.e., the through-hole 150 has a lower thermal conductivity than the substrate 110, and therefore the temperature of the through-hole 150 becomes higher. Furthermore, the larger the area of ​​the through-hole 150, the lower the thermal conductivity and the higher the temperature.

[0032] Furthermore, the through holes 150 include first-type through holes 1501 and second-type through holes 1502. The first-type through holes 1501 have a larger total opening area than the second-type through holes 1502. That is, the product of the number of first-type through holes 1501 and the area of ​​one first-type through hole 1501 is larger than the product of the number of second-type through holes 1502 and the area of ​​one second-type through hole 1502. This balances the temperatures between the first gate 1301 and the second gate 1302, i.e., the temperature at the first-type through hole 1501 is higher than the temperature at the second-type through hole 1502, offsetting the small mutual heat generation effect of the first gate 1301. This ensures a small temperature difference between the first gate 1301 and the second gate 1302, resulting in a uniform temperature distribution of the semiconductor device.

[0033] Optionally, Fig. 3 is a schematic cross-sectional structure diagram of the semiconductor device taken along the cross-sectional line B-B' in Fig. 1. Referring to Figs. 1 to 3, the first type through hole 1501 includes at least one first through hole 15011, and the second type through hole 1502 includes at least one second through hole 15022. The opening area of ​​the first through hole 15011 is larger than the opening area 15022 of the second through hole 15022.

[0034] Specifically, the opening area of ​​the first through hole 15011 is larger than the opening area of ​​the second through hole 15022. That is, because the opening area of ​​the first through hole 15011 is larger than that of the second through hole 15022, the total opening area of ​​the first type through hole 1501 consisting of at least one first through hole 15011 is large, ensuring low heat dissipation and high temperature of the first type through hole 1501. This offsets the small mutual heat generation effect of the first gate 1301, uniformly distributing the temperature of the semiconductor device, reducing attenuation in the high frequency performance of the device and improving output power.

[0035] 4 is a structural schematic diagram of another semiconductor device according to an embodiment of the present invention. As shown in Fig. 4, along the second direction Y, the first through hole 15011 is located on one side closer to the edge of the semiconductor device than any of the other through holes 150, and the second through hole 15022 is located on one side closer to the center of the semiconductor device than any of the other through holes 150. The opening area of ​​the through hole 150 gradually decreases in the direction from the first through hole 15011 to the second through hole 15022.

[0036] For example, the fact that the first through hole 15011 may be located on one side closer to the edge of the semiconductor device can be understood as the first through holes being close to the edge of the semiconductor device and being located on both sides of the semiconductor device along the second direction Y. The fact that the second through hole 15022 is located on one side closer to the center of the semiconductor device than any of the other through holes 150 can be understood as the second through hole 15022 covering the center of the semiconductor device or the distance between the second through hole 15022 and the center of the semiconductor device being shorter than the distance between any of the other through holes 150 and the center of the semiconductor device.

[0037] Specifically, the opening area of the through-hole 150 gradually decreases along the direction from the first through-hole 15011 to the second through-hole 15022, that is, it gradually decreases from both sides in the second direction Y towards the center of the semiconductor device along the second direction Y. That is, since the opening area of the first through-hole 15011 is larger than that of the second through-hole 15022, less heat dissipation of the first through-hole 15011 can be ensured, the mutual heat generation effect of the first gate 1301 can be offset, and the temperature difference between the first gate 1301 and the second gate 1302 can be ensured to be small. Thereby, the temperature of the semiconductor device can be uniformly distributed, the attenuation of the high-frequency performance of the device can be reduced, and the output power can be improved.

[0038] Selectively, continuing to refer to FIG. 1, along the second direction Y, the first through-hole 15011 is located on the side closer to the edge of the semiconductor device than any of the other through-holes 150, and the second through-hole 15022 is located on the side closer to the center of the semiconductor device than any of the other through-holes 150. The opening area of the first through-hole 15011 is S1, the opening area of the second through-hole 15022 is S2, and S2 < S1 ≤ 4 * S2.

[0039] Specifically, by satisfying S2 < S1 ≤ 4 * S2 for the opening area S1 of the first through-hole 15011 and the opening area S2 of the second through-hole 15022, not only the heat dissipation of the first through-hole 15011 is reduced, but it can also be avoided that the opening area of the first through-hole 15011 is too large and affects the normal heat dissipation of the semiconductor device, and it can also be ensured that the formation of the through-hole meets the process requirements.

[0040] Selectively, FIG. 5 is a structural schematic diagram of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 5, the first type of through-hole 1501 includes at least two first through-holes 15011, and the second type of through-hole 1502 includes at least one second through-hole 15022. The number of the first through-holes 15011 is larger than that of the second through-holes 15022.

[0041] Specifically, the number of first through holes 15011 is greater than the number of second through holes 15022. By increasing the number of first through holes 15011, the temperature difference between the first gate 1301 and the second gate 1302 can be balanced, ensuring that the higher temperature in the first through holes 15011 offsets the small mutual heat generation effect of the first gate 1301. This allows for a more uniform temperature distribution in the semiconductor device, reducing attenuation in the high frequency performance of the device and improving output power.

[0042] 6 is a structural schematic diagram of another semiconductor device according to an embodiment of the present invention. As shown in Fig. 6, along the second direction Y, the first through hole 15011 is located on one side closer to the edge of the semiconductor device than any of the other through holes 150, and the second through hole 15022 is located on one side closer to the center of the semiconductor device than any of the other through holes 150. The number of through holes 150 gradually decreases along the direction from the first through hole 15011 to the second through hole 15022.

[0043] Specifically, the number of through holes 150 gradually decreases from the first through holes 15011 to the second through holes 15022, and increasing the number of first through holes 15011 ensures that the temperature in the first through holes 15011 is higher, offsetting the small mutual heat generation effect of the first gate 1301. This not only ensures that the temperature of the semiconductor device is uniformly distributed, reduces heat loss from the device, but also simplifies the process of forming the through holes.

[0044] 5, along the second direction Y, the first through holes 15011 are located on one side closer to the edge of the semiconductor device than any of the other through holes 150, and the second through holes 15022 are located on one side closer to the center of the semiconductor device than any of the other through holes 150. The number of first through holes 15011 among the first type through holes 1501 is n1, and the number of second through holes 15022 among the second type through holes 1502 is n2, where n1-n2≦5.

[0045] Specifically, by satisfying the relationship (n1-n2)≦5 between the number n1 of first through holes 15011 and the number n2 of second through holes 15022, the number of first through holes 15011 can be increased relative to the number of second through holes 15022. In other words, the temperature difference between the first gate 1301 and the second gate 1302 can be balanced. Furthermore, heat dissipation throughout the semiconductor device can be ensured, and it is possible to avoid the problem of having too many through holes affecting the heat dissipation of the entire semiconductor device, thereby ensuring normal operation of the semiconductor device. Furthermore, it is possible to simplify the process of forming the through holes, and it is possible to avoid the problem of having too many through holes increasing the difficulty of the semiconductor device process.

[0046] Optionally, with continued reference to FIG. 1 , the semiconductor device further includes a plurality of sources 140 located on one side of the epitaxial structure 120 away from the substrate 110. The sources 140 extend along a first direction X. The plurality of sources 140 are arranged along a second direction Y. The plurality of sources 140 include a first source 1401 and a second source 1402. Along the second direction Y, the first source 1401 is disposed adjacent to the first gate 1301, and the second source 1402 is disposed adjacent to the second gate 1302, with the first source 1401 located on one side of the second source 1402 closer to the edge of the semiconductor device. The semiconductor device further includes through-holes 150 penetrating the substrate 110 and the epitaxial structure 120. The through-holes 150 include a first type through-hole 1501 and a second type through-hole 1502. Along the thickness direction Z of the semiconductor device, the first source 1401 overlaps with the first type through hole 1501, and the second source 1402 overlaps with the second type through hole 1502. Along the first direction X, the center of the first type through hole 1501 is located on one side of the center of the second type through hole 1502, closer to the center of the semiconductor device.

[0047] During operation of the semiconductor device, a large amount of heat is generated toward the center of the semiconductor device in the first direction X, resulting in a high temperature. Specifically, by positioning the center of the first type through hole 1501 along the first direction X on one side of the center of the second type through hole 1502, which is closer to the center of the semiconductor device, a high temperature can be ensured in the first through hole 15011. This offsets the small mutual heat generation effect of the first gate 1301, balances the temperature difference between the first gate 1301 and the second gate 1302, and reduces attenuation of high-frequency performance.

[0048] Optionally, continuing to refer to FIG. 1, there is a gate spacing between two adjacent gates 130 along the second direction Y. The plurality of gate spacings includes a first gate spacing d1 near an edge of the semiconductor device along the second direction Y, and a second gate spacing d2 located on one side of the first gate spacing d1 away from the edge of the semiconductor device. Along the second direction Y, the first gate spacing d1 is narrower than the second gate spacing d2.

[0049] Note that the larger the gate spacing between two adjacent gates 130, the less the thermal interaction. Specifically, the first gate spacing d1 in the second direction Y is narrower than the second gate spacing d2. That is, the narrower the first gate spacing d1 is near the edge of the semiconductor device, the greater the thermal interaction. To balance the thermal interaction difference between the first gate 1301 and the second gate 1302, the first gate spacing d1 is narrower than the second gate spacing d2 in the second direction Y, thereby reducing the temperature difference between the first gate 1301 and the second gate 1302. This allows for a more uniform temperature distribution in the semiconductor device, reducing attenuation in the device's high-frequency performance, and improving output power.

[0050] Optionally, FIG. 7 is a structural schematic diagram of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 7, the second gate spacing d2 is located on one side closer to the center of the semiconductor device than any other gate spacing. The gate spacing gradually increases from the first gate spacing d1 toward the second gate spacing d2.

[0051] Specifically, continuing to refer to FIG. 7, the gate pitch between the first gate 1301 and the adjacent second gate 1302 is d1, the gate pitches between two adjacent second gates 1302 are d21 and d2 respectively, and d1 < d21 < d2. That is, the gate pitch gradually increases along the side toward the second gate pitch d2 from the first gate pitch d1, and the maximum gate pitch is at the center position of the semiconductor device, which is beneficial for reducing the mutual heating effect of the second gates 1302. Further, by gradually decreasing the gate pitch in the direction away from the center position of the semiconductor device from this center position, the difference in thermal interaction between the first gate 1301 and the second gate 1302 can be balanced, and the temperature at the center of the semiconductor device can be reduced. Thereby, the temperature of the semiconductor device can be evenly distributed, and the thermal loss of the device can be reduced.

[0052] The embodiment of the present invention improves the output power of the semiconductor device by adjusting the structural design of the semiconductor device. The semiconductor device may include, but is not limited to, a high-power gallium nitride high electron mobility transistor (HEMT) that operates under a high voltage and high current environment, a silicon-on-insulator (SOI) transistor, a gallium arsenide (GaAs)-based transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-semiconductor field-effect transistor (MISFET), a double heterojunction field-effect transistor (DHFET), a junction field-effect transistor (JFET), a metal-semiconductor field-effect transistor (MESFET), a metal-semiconductor heterojunction field-effect transistor (MISHFET), or other field-effect transistors.

[0053] According to the same inventive concept, an embodiment of the present invention further provides a method for manufacturing a semiconductor device. As shown in Figure 5, the method for manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps:

[0054] S101: Provide a substrate.

[0055] For example, the substrate material may be Si, SiC, or sapphire, or other materials suitable for gallium nitride growth. The substrate may be fabricated by atmospheric pressure chemical vapor deposition, subatmospheric pressure chemical vapor deposition, metal organic chemical vapor deposition, reduced pressure chemical vapor deposition, high density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical chemical vapor deposition, rapid thermal chemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.

[0056] S102: Form an epitaxial structure on one side of the substrate.

[0057] For example, the epitaxial structure may be formed of one or more of Group III nitrides and Group V nitrides, such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, and indium aluminum gallium nitride. Furthermore, two-dimensional electron gas may be formed in the epitaxial structure. Growth methods for the epitaxial structure include, but are not limited to, metalorganic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, and liquid phase epitaxy. Specifically, two-dimensional electron gas is formed in the epitaxial structure.

[0058] Optionally, the epitaxial structure may include a nucleation layer, a buffer layer, a channel layer, and a barrier layer.

[0059] For example, the material of the nucleation layer may be aluminum nitride. The nucleation layer is located between the substrate and the buffer layer and serves as an adhesive for the next semiconductor material layer to be grown. The buffer layer is located on one side of the substrate. The material of the buffer layer may be gallium nitride. The buffer layer may also contain iron atoms, which contribute to the high resistivity of the buffer layer, ensuring the prevention of vertical leakage and improving the pinch-off performance of the semiconductor device.

[0060] For example, the channel layer may be made of a group III nitride, such as Al x Ga 1-x The n-th element may be N (0≦x<1), where the energy of the conduction band edge at the interface between the channel layer and the barrier layer is less than that of the barrier layer. For example, x=0 indicates that the channel layer is GaN. The channel layer may be made of other III-nitrides, such as InGaN or AlInGaN. The channel layer may be undoped or unintentionally doped. The channel layer may be a multilayer structure, such as a superlattice, a combination of GaN or AlGaN.

[0061] For example, a barrier layer may be formed on one side of the channel layer away from the substrate, forming a heterojunction structure between the barrier layer and the channel layer. The barrier layer may be AlN, AlInN, AlGaN, or AlInGaN. The barrier layer has a sufficient thickness and a sufficiently high Al content to dope the interface between the channel layer and the barrier layer and form a significant carrier concentration. For example, the barrier layer may be 20 nm thick and have a dopant concentration of 25% Al.

[0062] For example, the channel layer may include GaN and the barrier layer may include AlGaN. That is, the material of the barrier layer may have a higher bandgap than the material of the channel layer, and the channel layer may have a higher electron affinity than the barrier layer. The bandgap difference between the barrier layer and the channel layer, and the piezoelectric effect at the interface between the barrier layer and the channel layer, result in the formation of a two-dimensional electron gas in the channel layer and the barrier layer.

[0063] The epitaxial structure may further include a cap layer located on the surface of the barrier layer away from the substrate. The cap layer can reduce surface states, reduce surface leakage in a subsequent semiconductor device, and suppress current collapse, thereby improving the performance and reliability of the epitaxial structure and the semiconductor device.

[0064] S103: Form a plurality of gates on one side of the epitaxial structure away from the substrate. The gates extend along a first direction. The plurality of gates are arranged along a second direction. The first direction and the second direction intersect with each other and are both parallel to a plane in which the substrate is located. The plurality of gates include a first gate and a second gate. Along the second direction, the first gate is located on one side of the second gate closer to an edge of the semiconductor device. The maximum temperature of the first gate is T1, and the maximum temperature of the second gate is T2, where (T2-T1) / T1≦20%.

[0065] Specifically, referring to FIG. 1 , a plurality of gates 130 are formed on one side of an epitaxial structure 120, away from a substrate 110. A first gate 1301 of the plurality of gates 130 is located on one side of the second gate 1302, closer to the edge of the semiconductor device. Furthermore, during operation of the semiconductor device, each gate 130 located in the active region self-heats, i.e., each gate generates heat. The heat generated in each gate 130 diffuses to adjacent gates 130, resulting in mutual heating between two adjacent gates 130. Mutual heating also occurs between two adjacent gates 130. That is, during normal operation of the semiconductor device, each gate 130 self-heats and mutual heating also occurs, and the temperature of each gate 130 is the sum of the temperatures generated by self-heating and mutual heating. Although the temperature difference between each gate 130 caused by self-heating is small, the first gate 1301 is located on one side near the edge of the semiconductor device along the second direction Y, and the number of gates 130 adjacent to the first gate 1301 is small, so the temperature of the first gate 1301 caused by mutual heat generation is reduced.

[0066] 1, when the maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate satisfy (T2-T1) / T1≦20%, the temperature difference between the maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate 1302 located on one side near the edge of the semiconductor device can be reduced, thereby distributing the temperature of the semiconductor device evenly, reducing heat loss from the device and improving the output power of the semiconductor device.

[0067] In a method for manufacturing a semiconductor device according to an embodiment of the present invention, a plurality of gates are formed on one side of an epitaxial structure away from a substrate, and a first gate of the plurality of gates is located on one side of the semiconductor device closer to an edge of the semiconductor device than a second gate, and the maximum temperature T1 of the first gate 1301 and the maximum temperature T2 of the second gate satisfy (T2-T1) / T1≦20%, thereby ensuring a small temperature difference between the gates. This allows for uniform temperature distribution of the semiconductor device, reducing attenuation in high frequency performance and improving output power.

[0068] It should be noted that the above is merely a preferred embodiment of the present invention and the technical principles employed therein. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that those skilled in the art can make various obvious changes, adjustments, mutual combinations, and substitutions without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and can include many other equivalent embodiments without departing from the concept of the present invention, and the scope of protection of the present invention is determined by the appended claims.

Claims

1. A semiconductor device, A substrate; an epitaxial structure located on one side of the substrate; a plurality of gates located on one side of the epitaxial structure away from the substrate; The gate extends along a first direction; The plurality of gates are arranged along a second direction, the first direction and the second direction intersect with each other and are both parallel to a plane in which the substrate is located; the plurality of gates include a first gate and a second gate; along the second direction, the first gate is located on one side of the second gate that is closer to an edge of the semiconductor device; A semiconductor device characterized in that the highest temperature of the first gate is T1, the highest temperature of the second gate is T2, and (T2-T1) / T1≦20%.

2. further comprising a plurality of sources located on one side of the epitaxial structure away from the substrate; the source extends along the first direction; The plurality of sources are arranged along the second direction, the plurality of sources includes a first source and a second source; Along the second direction, the first source is disposed adjacent to the first gate, the second source is disposed adjacent to the second gate, and the first source is located on one side of the second source that is close to an edge of the semiconductor device; further comprising a through hole passing through the substrate and the epitaxial structure; the through holes include a first type of through hole and a second type of through hole; the first source overlaps with the first type through hole and the second source overlaps with the second type through hole along a thickness direction of the semiconductor device; 2. The semiconductor device according to claim 1, wherein the first type through holes have a total opening area larger than that of the second type through holes.

3. the first type of through holes includes at least one first through hole; the second type of through holes includes at least one second through hole; 3. The semiconductor device according to claim 2, wherein the first through hole has an opening area larger than that of the second through hole.

4. the first through hole is located on one side of the other through hole that is closer to an edge of the semiconductor device along the second direction, and the second through hole is located on one side of the other through hole that is closer to a center of the semiconductor device along the second direction; 4. The semiconductor device according to claim 3, wherein an opening area of ​​the through hole gradually decreases in a direction from the first through hole to the second through hole.

5. the first through hole is located on one side of the other through hole that is closer to an edge of the semiconductor device along the second direction, and the second through hole is located on one side of the other through hole that is closer to a center of the semiconductor device along the second direction; 4. The semiconductor device according to claim 3, wherein the opening area of ​​the first through hole is S1, the opening area of ​​the second through hole is S2, and S2<S1≦4*S2.

6. the first type of through holes includes at least two first through holes; the second type of through holes includes at least one second through hole; 3. The semiconductor device according to claim 2, wherein the number of the first through holes is greater than the number of the second through holes.

7. the first through hole is located on one side of the other through hole that is closer to an edge of the semiconductor device along the second direction, and the second through hole is located on one side of the other through hole that is closer to a center of the semiconductor device along the second direction; 7. The semiconductor device according to claim 6, wherein the number of the through holes gradually decreases along a direction from the first through holes to the second through holes.

8. the first through hole is located on one side of the other through hole that is closer to an edge of the semiconductor device along the second direction, and the second through hole is located on one side of the other through hole that is closer to a center of the semiconductor device along the second direction; 7. The semiconductor device according to claim 6, wherein the number of the first through holes among the first type through holes is n1, the number of the second through holes among the second type through holes is n2, and (n1-n2)≦5.

9. further comprising a plurality of sources located on one side of the epitaxial structure away from the substrate; the source extends along the first direction; The plurality of sources are arranged along the second direction, the plurality of sources includes a first source and a second source; Along the second direction, the first source is disposed adjacent to the first gate, the second source is disposed adjacent to the second gate, and the first source is located on one side of the second source that is close to an edge of the semiconductor device; further comprising a through hole passing through the substrate and the epitaxial structure; the through holes include a first type of through hole and a second type of through hole; the first source overlaps with the first type through hole and the second source overlaps with the second type through hole along a thickness direction of the semiconductor device; 2. The semiconductor device according to claim 1, wherein the center of the first type through hole is located on one side of the center of the second type through hole closer to the center of the semiconductor device along the first direction.

10. a gate spacing is provided between two adjacent gates along the second direction; the plurality of gate intervals include a first gate interval close to an edge of the semiconductor device along the second direction, and a second gate interval located on one side of the first gate interval away from the edge of the semiconductor device, 2. The semiconductor device according to claim 1, wherein the first gate spacing is narrower than the second gate spacing along the second direction.

11. the second gate spacing is located on one side of any other gate spacing closer to the center of the semiconductor device; 11. The semiconductor device according to claim 10, wherein the gate spacing gradually increases along a side from the first gate spacing to the second gate spacing.

12. A method for manufacturing a semiconductor device according to any one of claims 1 to 11, comprising: Providing a substrate; forming an epitaxial structure on one side of the substrate; forming a plurality of gates on a side of the epitaxial structure away from the substrate; The gate extends along a first direction; The plurality of gates are arranged along a second direction, the first direction and the second direction intersect with each other and are both parallel to a plane on which the substrate is located; the plurality of gates include a first gate and a second gate; the first gate is located on one side of the second gate that is closer to an edge of the semiconductor device along the second direction; A method for manufacturing a semiconductor device, wherein the highest temperature of the first gate is T1, the highest temperature of the second gate is T2, and (T2-T1) / T1≦20%.

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