Embedded ReRAM with backside contact

Abstract

A semiconductor structure is provided that includes a one-transistor, one-capacitor (1T1R) element, the semiconductor structure including an embedded resistive random access memory (ReRAM) having a width greater than one gate pitch present on a front or back surface of the structure, a front contact structure electrically connected to a source region of a transistor in the 1T1R element, and a back contact structure electrically connected to a drain region of a transistor in the 1T1R element.

Description

[Technical Field]

[0001] This application relates to semiconductor technology, and more particularly to semiconductor structures that include embedded resistive random access memory (ReRAM) with backside contacts to reduce the formation voltage of the ReRAM. [Background technology]

[0002] Non-volatile memory (NVM) or non-volatile storage is a type of computer memory that can retain stored information even after power is removed. In contrast, volatile memory requires a certain amount of power to retain data. NVM, such as ReRAM (or sometimes simply RRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM), has attracted renewed attention for its potential applications in neuromorphic computing with in-memory processing capabilities that significantly reduce power consumption and eliminate the data bus time between the central processing unit (CPU) and memory of traditional complementary metal oxide semiconductor (CMOS)-based neuromorphic computing. ReRAM is considered a promising technology for realizing electronic synaptic elements, or memristors, for neuromorphic computing and high-density, high-speed NVM applications. In neuromorphic computing applications, resistive memory elements such as ReRAM elements may be used as connections (i.e., synapses) between pre-neurons and post-neurons, representing connection weights in the form of element resistances. Summary of the Invention

[0003] A semiconductor structure is provided that includes a one-transistor, one-capacitor (1T1R) element, the semiconductor structure including an embedded ReRAM present on the front or back side of the structure, a front contact structure electrically connected to a source region of the transistor in the 1T1R element, and a back contact structure electrically connected to a drain region of the transistor in the 1T1R element. By arranging these two contact structures on opposite sides of the structure, a low-voltage switching ReRAM can be achieved without increasing the size or formation voltage of the ReRAM itself. The ReRAM can have a width greater than one gate pitch. Throughout this application, the term "gate pitch" refers to the distance from one point on a gate structure to a precise point on the nearest neighboring gate structure.

[0004] In one embodiment of the present application (i.e., a front-side ReRAM embodiment), the semiconductor structure includes a transistor located in the memory element region and having a gate structure, a source region located on a first side of the gate structure, and a drain region located on a second side of the gate structure, where the second side of the gate structure is opposite the first side of the gate structure. The structure further includes a ReRAM located in the memory element region and positioned above the transistor, a front-side contact structure electrically connecting the ReRAM to the source region of the transistor, and a back-side contact structure electrically connecting the drain region of the transistor to a back-end-of-the-line (BEOL) structure. In this front-side ReRAM embodiment, the ReRAM switching area is effectively increased without increasing the gate pitch.

[0005] In this front-side ReRAM embodiment, the transistor may be a nanosheet transistor including a plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets, with the transistor's gate structure wrapped around a central portion of each of the vertically stacked and spaced-apart semiconductor channel material nanosheets. In such an embodiment, the structure may further include a bottom dielectric isolation layer and a backside interlayer dielectric material layer positioned below the nanosheet transistor, where a backside contact structure passes through both the backside interlayer dielectric material layer and the bottom dielectric isolation layer and is in direct physical contact with the drain region of the transistor.

[0006] In this front side ReRAM embodiment, the structure may further include a source / drain contact structure positioned between the front side contact structure and a source region of the transistor, where the front side contact structure is in direct physical contact with a first surface of the source / drain contact structure and a second surface of the source / drain contact structure opposite the first surface is in direct physical contact with the source region of the transistor.

[0007] In this front side ReRAM embodiment, the structure further includes a front side BEOL structure positioned above the ReRAM, where the front side BEOL structure is electrically connected to the top electrode of the ReRAM by a front side BEOL-to-ReRAM metal via. In such an embodiment, the front side BEOL-to-ReRAM metal via passes through a dielectric material layer overlying the ReRAM.

[0008] In this front side ReRAM embodiment, the structure may further include a carrier wafer positioned on the surface of the front side BEOL structure.

[0009] In this front side ReRAM embodiment, the ReRAM is embedded in a front side interlayer dielectric material layer.

[0010] In this front side ReRAM embodiment, the structure may further include a logic element area positioned adjacent to the memory element region, where the logic element area has another transistor including another gate structure, another source region positioned on a first side of the another gate structure, and another drain region positioned on a second side of the another gate structure, the second side of the another gate structure opposite the first side of the another gate structure. In such an embodiment, the structure may further include another front side contact structure electrically connecting the another source region of the another transistor to the front side BEOL structure and another back side contact structure electrically connecting the another drain region of the another transistor to the back side BEOL structure.

[0011] In another embodiment of the present application (i.e., a backside ReRAM embodiment), a semiconductor structure includes a transistor located in a memory element region and having a gate structure, a source region located on a first side of the gate structure, and a drain region located on a second side of the gate structure, where the second side of the gate structure is opposite to the first side of the gate structure. The structure of this backside ReRAM embodiment further includes a ReRAM located in the memory element region and positioned below the transistor, a front side contact structure electrically connecting the source region of the transistor to a front side BEOL structure, and a back side contact structure electrically connecting the drain region of the transistor to the ReRAM. In this backside ReRAM embodiment, the ReRAM switching area is effectively increased without increasing the gate pitch.

[0012] In this backside ReRAM embodiment, the transistor is a nanosheet transistor including a plurality of vertically stacked and spaced apart semiconductor channel material nanosheets, and the transistor gate structure wraps around a central portion of each semiconductor channel material nanosheet of the vertically stacked and spaced apart semiconductor channel material nanosheets. In such an embodiment, the structure further includes a bottom dielectric isolation layer and a backside interlayer dielectric material layer positioned below the nanosheet transistor, where a backside contact structure passes through both the backside interlayer dielectric material layer and the bottom dielectric isolation layer and is in direct physical contact with the drain region of the transistor.

[0013] In this backside ReRAM embodiment, the structure can further include a source / drain contact structure positioned between the front side contact structure and the source region of the transistor, where the front side contact structure is in direct physical contact with a first surface of the source / drain contact structure and a second surface of the source / drain contact structure opposite the first surface is in direct physical contact with the source region of the transistor.

[0014] In this backside ReRAM embodiment, the structure may further include a front side metal via positioned between the front side contact structure and the front side BEOL structure, where the front side metal via has a first surface in direct contact with the front side BEOL structure and a second surface opposite the first surface in direct contact with the front side contact structure.

[0015] In this backside ReRAM embodiment, the structure can further include a backside BEOL structure positioned below the ReRAM, where the backside BEOL structure is electrically connected to the bottom electrode of the ReRAM by a metal via from the backside BEOL to the ReRAM.

[0016] In this backside ReRAM embodiment, the structure may further include a carrier wafer positioned on the surface of the frontside BEOL structure.

[0017] In this backside ReRAM embodiment, the ReRAM is embedded in a backside interlayer dielectric material layer.

[0018] In this backside ReRAM embodiment, the structure may further include a logic element area positioned adjacent to the memory element region, where the logic element area has another transistor including another gate structure, another source region positioned on a first side of the another gate structure, and another drain region positioned on a second side of the another gate structure, the second side of the another gate structure opposite the first side of the another gate structure. In such an embodiment, the structure may further include another front side contact structure electrically connecting the another source region of the another transistor to the front side BEOL structure and another back side contact structure electrically connecting the another drain region of the another transistor to the backside BEOL structure. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1A is a cross-sectional view of exemplary structures present in a memory device region of a semiconductor substrate, including a transistor, a ReRAM, a front-side contact structure, a front-side BEOL structure, and a carrier wafer, all of which are present on the front side of the semiconductor substrate. FIG. 1B is a cross-sectional view of exemplary structures present in a logic device region of a semiconductor substrate, the logic device region being positioned adjacent to the memory device region shown in FIG. 1A, and exemplary structures in the logic device region including a transistor, a front-side contact structure, a front-side BEOL structure, and a carrier wafer, all of which are present on the front side of the semiconductor substrate.

[0020] [Figure 2]2A is a cross-sectional view of the exemplary structure shown in FIG. 1A after the semiconductor substrate has been removed to allow backside processing in both the memory element region and the logic element region, and FIG. 2B is a cross-sectional view of the exemplary structure shown in FIG. 1B after the semiconductor substrate has been removed to allow backside processing in both the memory element region and the logic element region.

[0021] [Figure 3] 3A is a cross-sectional view of the exemplary structure shown in FIG. 2A after forming a backside interlayer dielectric material layer in both the memory element region and the logic element region, and FIG. 3B is a cross-sectional view of the exemplary structure shown in FIG. 2B after forming a backside interlayer dielectric material layer in both the memory element region and the logic element region.

[0022] [Figure 4] 4A is a cross-sectional view of the exemplary structure shown in FIG. 3A after forming backside contact structures in both the memory element region and the logic element region, and FIG. 4B is a cross-sectional view of the exemplary structure shown in FIG. 3B after forming backside contact structures in both the memory element region and the logic element region.

[0023] [Figure 5] 5A is a cross-sectional view of the exemplary structure shown in FIG. 4A after forming a backside BEOL structure, and FIG. 5B is a cross-sectional view of the exemplary structure shown in FIG. 4B after forming a backside BEOL structure.

[0024] [Figure 6] FIG. 6A is a cross-sectional view of another exemplary structure present in a memory device region of a semiconductor substrate, the exemplary structure including a transistor, a front side contact structure, a front side BEOL structure, and a carrier wafer, all of which are present on the front side of the semiconductor substrate. FIG. 6B is a cross-sectional view of another exemplary structure present in a logic device region of a semiconductor substrate, the logic device region being positioned adjacent to the memory device region shown in FIG. 6A, and another exemplary structure within the logic device region including a transistor, a front side contact structure, a front side BEOL structure, and a carrier wafer, all of which are present on the front side of the semiconductor substrate.

[0025] [Figure 7] 7A is a cross-sectional view of the exemplary structure shown in FIG. 6A after the semiconductor substrate has been removed to allow backside processing in both the memory element region and the logic element region, and FIG. 7B is a cross-sectional view of the exemplary structure shown in FIG. 6B after the semiconductor substrate has been removed to allow backside processing in both the memory element region and the logic element region.

[0026] [Figure 8] 8A is a cross-sectional view of the exemplary structure shown in FIG. 7A after forming a first backside interlayer dielectric material layer in both the memory element region and the logic element region, and FIG. 8B is a cross-sectional view of the exemplary structure shown in FIG. 7B after forming a first backside interlayer dielectric material layer in both the memory element region and the logic element region.

[0027] [Figure 9] 9A is a cross-sectional view of the exemplary structure shown in FIG. 8A after forming backside contact structures in both the memory element region and the logic element region, and FIG. 9B is a cross-sectional view of the exemplary structure shown in FIG. 8B after forming backside contact structures in both the memory element region and the logic element region.

[0028] [Figure 10] 10A is a cross-sectional view of the exemplary structure shown in FIG. 9A after further back surface processing including forming a ReRAM in the memory element region and forming a back surface BEOL structure, and FIG. 10B is a cross-sectional view of the exemplary structure shown in FIG. 9B after further back surface processing including forming a ReRAM in the memory element region and forming a back surface BEOL structure. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present application will now be described in more detail by reference to the following discussion and drawings accompanying this application, which are provided for illustrative purposes only and, as such, are not drawn to scale, and it should also be noted that like and corresponding elements are referred to by like reference numerals.

[0030] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, those skilled in the art will understand that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0031] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it is understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it is understood that the element can be directly below or directly underneath the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0032] Conventional filamentary switching ReRAM devices require a formation step to cause soft breakdown. On the one hand, shrinking the switching area increases the formation voltage, requiring additional external components and resulting in power consumption. On the other hand, increasing the ReRAM switching area and decreasing the formation voltage incurs an area penalty. The present application solves the above problem by providing a 1T1R device, in which the ReRAM (which functions as a memory element in the 1T1R structure) is present on either the front or back side of the device, with source and drain contacts located on opposite sides of the device. Specifically, in the present application, a front contact is present on the front side of the device electrically connected to the source region of the transistor, and a back contact structure is present on the back side of the device electrically connected to the drain region of the transistor. Here, the front side of the device is the region that includes and is located above the transistor, while the back side of the device is the region that is located below the transistor. Therefore, the ReRAM switching area is not limited by the drain contact (as in conventional 1T1R devices). In the present application, the size of the ReRAM can be larger than one gate pitch. This aspect of the present application allows for a reduction in the formation voltage without increasing the size of the 1T1R element.

[0033] 1A-10B, there is typically a memory device region 100 and a logic device region 102. The logic device region 102 is positioned adjacent to the memory device region 100. In the present application, the transistors present in the memory device region 100 and the logic device region 102 are positioned on the same semiconductor substrate 10. The memory device region 100 includes a 1T1R device including a transistor T1 and a ReRAM. The ReRAM may be positioned on the front or back side of the semiconductor substrate 10. Similarly, the logic device region 102 includes a transistor T2. In the memory device region 100 and the logic device region 102, front side contacts are made to the source regions of the transistors present in each device region, and back side contacts are made to the drain regions of the transistors in each device region. This provides a low-voltage switching ReRAM in the memory device region 100 without the need to increase the size of the ReRAM.

[0034] In this application, the term "transistor" refers to a three-terminal device including a gate electrode, a source region, and a drain region, and the gate electrode is a component of the gate structure. In this application, both the transistors in the memory element region 100 and the logic element region are referred to as nanosheet transistors. The term "nanosheet transistor" refers to a type of transistor in which the transistor's channel is a plurality of vertically stacked and spaced apart nanosheets of semiconductor channel material. In a nanosheet transistor, the gate structure wraps around each of the plurality of vertically stacked and spaced apart nanosheets of semiconductor channel material. Nanosheet transistors are advantageous in this application because such transistors typically include a bottom dielectric isolation layer that allows backside processing without adversely affecting the transistor's channel. In some embodiments, a transistor formed on a semiconductor-on-insulator substrate can be used instead of a nanosheet transistor because the semiconductor-on-insulator substrate includes a buried insulating layer.

[0035] 1A , an exemplary structure present in a memory device region 100 of a semiconductor substrate 10 is shown. The exemplary structure includes a transistor T1, ReRAMs 34 / 35 / 36, a front surface contact structure 32, a front surface BEOL structure 44, and a carrier wafer 46, all of which are present on the front surface of the semiconductor substrate 10. The transistor T1 present in the memory device region 100 includes a plurality of vertically stacked and spaced apart semiconductor channel material nanosheets 16, a gate structure 22 wrapped around a central portion of each semiconductor channel material nanosheet 16, a source region 26 located on one side of the gate structure 22, and a drain region 27 located on the opposite side of the gate structure 22. The exemplary structure also shows dummy gate regions on the left and right sides of the transistor T1. Each dummy gate region also includes at least a gate structure 22 wrapped around each end of a semiconductor channel material nanosheet 16, and the dummy transistor lacks at least one of the source region or the drain region. Also present in the memory device region 100 are a shallow trench isolation structure 12, inner spacers 18, gate spacers 20, gate caps 24, front surface source / drain contact structures 28, a first front surface interlayer dielectric material layer 30, a dielectric material layer 38, a second front surface interlayer dielectric material layer 40, and a front surface BEOL-to-ReRAM metal via 42. In the present application, the shallow trench isolation structure 12 is formed in the semiconductor substrate 10 and can surround unetched portions of the semiconductor substrate 10. The structure further includes a bottom dielectric isolation layer 14 present between the transistor T1 and the semiconductor substrate 10.

[0036] 1A, the ReRAM 34 / 35 / 36 is a front-side ReRAM positioned above the transistor T1 present in the memory element region 100. As further shown in FIG. 1A, the front-side contact structure 32 electrically connects the ReRAM 34 / 35 / 36 to the source region 26 of the transistor T1, and in the memory element region 100, one of the front-side source / drain contact structures 28 is positioned between the front-side contact structure 32 and the source region 26 of the transistor T1. In the present application, the front-side contact structure 32 has a first surface that is in physical contact with the front-side source / drain contact structure 28 and a second surface that is opposite the first surface and is in physical contact with the first electrode 34 of the ReRAM 34 / 35 / 36. A front-side BEOL-to-ReRAM metal via 42 electrically connects the second electrode 36 of the ReRAM 34 / 35 / 36 to a front-side BEOL structure 44, and a carrier wafer 46 is positioned on top of the front-side BEOL structure 44. A dielectric material layer 38 exists along the top and sidewall surfaces of the ReRAM 34 / 35 / 36, and this dielectric material layer also exists between the first front-side interlayer dielectric material layer 30 and the second front-side interlayer dielectric material layer 40. In this embodiment of the present application, as shown in FIG. 1A , the first front-side interlayer dielectric material layer 30 incorporates the transistor T1 and the dummy transistor, the front-side source / drain contact structure 28, the front-side contact structure 32, and the bottom dielectric isolation layer 14, and the second front-side interlayer dielectric material layer 40 incorporates at least the ReRAM 34 / 35 / 36 and the front-side BEOL-to-ReRAM metal via 42.

[0037] 1B, an exemplary structure present in a logic device region 102 of a semiconductor substrate 10 is shown. Note that the logic device region 102 and the memory device region 100 reside on the same substrate, i.e., the semiconductor substrate 10. The logic device region 102 is positioned adjacent to the memory device region 100 shown in FIG. 1A, and exemplary structures within the logic device region 102 include a transistor T2, a front-side contact structure 32, a front-side BEOL structure 44, and a carrier wafer 46, all of which reside on the front side of the semiconductor substrate 10. The transistor T2 present in the logic device region 102 includes a plurality of vertically stacked and spaced-apart semiconductor channel material nanosheets 16, a gate structure 22 wrapped around a central portion of each semiconductor channel material nanosheet 16, a source region 26 located on one side of the gate structure 22, and a drain region 27 located on the opposite side of the gate structure 22. The exemplary structure also shows dummy gate regions on the left and right sides of the transistor T2. Each dummy gate region also includes at least a gate structure 22 wrapped around each end of the semiconductor channel material nanosheet 16, and the dummy transistor lacks at least one of a source or drain region. Also present in the logic element region 102 are shallow trench isolation structures 12, inner spacers 18, gate spacers 20, gate caps 24, front surface source / drain contact structures 28, a first front surface interlayer dielectric material layer 30, a dielectric material layer 38, a second front surface interlayer dielectric material layer 40, and a front surface metal via 43. The structure shown in FIG. 1B further includes a bottom dielectric isolation layer 14 present between transistor T2 and the semiconductor substrate 10.

[0038] 1B , front surface contact structure 32 electrically connects front surface BEOL structure 44 to source region 26 of transistor T2, and in logic element region 102, one of front surface source / drain contact structures 28 is positioned between front surface contact structure 32 and source region 26 of transistor T2. In the present application, front surface contact structure 32 has a first surface that is in physical contact with front surface source / drain contact structure 28 and a second surface that is in physical contact with metal via 43 opposite the first surface and positioned between front surface BEOL structure 44 and front surface contact structure 32. In logic element region 102, dielectric material layer 38 is present between first front surface interlayer dielectric material layer 30 and second front surface interlayer dielectric material layer 40. In this embodiment of the present application, as shown in FIG. 1B, the first front surface inter-layer dielectric material layer 30 incorporates transistor T2 and dummy transistors, front surface source / drain contact structures 28, front surface contact structures 32, and bottom dielectric isolation layer 14, and the second front surface inter-layer dielectric material layer 40 incorporates at least metal vias 43.

[0039] The semiconductor substrate 10, present in both the memory device region 100 and the logic device region 102, is composed of at least one semiconductor material having semiconducting properties. Examples of semiconductor materials that may be used to provide the semiconductor substrate 12 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), a III / V compound semiconductor, or a II / VI compound semiconductor.

[0040] The shallow trench isolation structures 12 present in both the memory device region 100 and the logic device region 102 can include a trench dielectric material and an optional trench liner. If present, the trench liner is formed along the sidewalls and bottom wall of the trench dielectric material. The trench dielectric material can be composed of any trench dielectric material, such as, for example, silicon oxide, while the trench liner can be composed of any trench liner material, such as, for example, silicon nitride.

[0041] The bottom dielectric isolation layer 14 present in both the memory device region 100 and the logic device region 102 is composed of a spacer dielectric material including, but not limited to, SiN, SiBCN, SiOCN, SiON, or SiOC. Typically, although not always, the spacer dielectric material providing the bottom dielectric isolation layer 14 is compositionally the same as the spacer dielectric material providing the gate spacers 20.

[0042] Each semiconductor channel material nanosheet 16 is composed of one of the semiconductor materials described above for the semiconductor substrate 10. In one example, each semiconductor channel material nanosheet 16 is composed of Si or SiGe. In some embodiments, each semiconductor channel material nanosheet 16 may be composed of a semiconductor material capable of providing high channel mobility for an nFET device. In other embodiments, each semiconductor channel material nanosheet 16 may be composed of a semiconductor material capable of providing high channel mobility for a pFET device. Each semiconductor channel material nanosheet 16 typically has a width of 6 nm to 100 nm and a vertical height of 4 nm to 15 nm.

[0043] Each inner spacer 18 is positioned below each semiconductor channel material nanosheet 16. Each inner spacer 18 is made of a spacer dielectric material, including, but not limited to, SiN, SiBCN, SiOCN, SiON, or SiOC.

[0044] Each gate spacer 20 along the sidewall of the gate structure 22 may also be composed of a spacer dielectric material. The spacer dielectric material providing the gate spacers 20 may be compositionally the same as or different from the dielectric spacer material providing the inner spacers 18.

[0045] Gate structure 22 includes a gate dielectric material and a gate electrode, both of which are not shown separately but are intended to be within the region defined by gate structure 22. As known to those skilled in the art, the gate dielectric material directly contacts the physically exposed surface of each semiconductor channel material structure, and the gate electrode is formed on top of the gate dielectric material. The gate dielectric material of gate structure 22 has a dielectric constant of 4.0 or greater. All dielectric constants stated herein are measured in a vacuum unless otherwise indicated. Illustrative examples of gate dielectric materials include, but are not limited to, silicon dioxide, hafnium dioxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium dioxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium silicon oxynitride (ZrSiO). x N y ), tantalum oxide (TaO x ), titanium oxide (TiO), barium strontium titanium oxide (BaOSrTi), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YbO), aluminum oxide (AlO), lead scandium tantalum oxide (Pb(Sc,Ta)O), and / or lead zinc niobate (Pb(Zn,Nb)O). The gate dielectric material can further include dopants such as La, Al, and / or Mg.

[0046] The gate electrode of gate structure 22 can include a work function metal (WFM) and optionally a conductive metal. The WFM can be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM can be selected to provide an n-type threshold voltage shift. "N-type threshold voltage shift," as used herein, refers to a shift of the effective work function of a work function metal-containing material toward the conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV. Examples of such materials that can provide an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM can be selected to provide a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. "Threshold voltage," as used herein, is the lowest achievable gate voltage that turns on a semiconductor device, such as a transistor, by making the channel of the device conductive. The term "p-type threshold voltage shift," as used herein, refers to a shift in the effective work function of a WFM-containing material toward the valence band of silicon in a silicon-containing material. Examples of such materials that can result in a p-type threshold voltage shift include, but are not limited to, titanium nitride, and tantalum carbide, hafnium carbide, and combinations thereof. Optional conductive metals can include, but are not limited to, Al, W, or Co.

[0047] Each gate cap 24 present in the memory device region 100 and the logic device region 102 may be composed of a dielectric hard mask material such as, for example, silicon nitride and / or silicon oxynitride. The gate cap 24 resides on the top surface of the gate structure 22 and is laterally surrounded by upper portions of the gate spacers 20, which in turn are laterally surrounded by lower portions of the gate spacers 20. At this point in the application, the top surface of the gate cap 24 is flush with the top surfaces of the gate spacers 20.

[0048] The source and drain regions 26 and 27 present in the memory element region 100 and the logic element region 102 comprise a semiconductor material and a dopant. The dopant may be either an n-type dopant or a p-type dopant, both of which are defined below. The semiconductor material providing the source and drain regions 26 and 27 includes one of the semiconductor materials described above for providing the semiconductor substrate 10. The semiconductor material providing the source and drain regions 26 and 27 may be compositionally the same or different from the semiconductor material providing each semiconductor channel material nanosheet 16. The term "n-type" refers to the addition of an impurity that provides free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that results in a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. The concentration of n-type or p-type dopants in the source region 26 and the drain region 27 is 1×10 18 atoms / cm 3 ~1×10 21 atoms / cm 3 However, the dopant concentration can be in the range of 1×10 21 atoms / cm 3 Higher or 1 x 10 18 atoms / cm 3 It is also expected that the number will be less than 100.

[0049] The first interlayer dielectric material layer 30 present in the memory device region 100 and the logic device region 102 may be composed of dielectric materials including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" as used throughout this application refers to a dielectric material having a dielectric constant less than 4.0. The first interlayer dielectric material layer 30 typically includes a plurality of the aforementioned dielectric materials.

[0050] Each front-side source / drain contact structure 28 present in the memory device region 100 and the logic device region 102 is positioned on the surface of the source region 26 and the surface of the drain region 27. Each front-side source / drain contact structure 28 is composed of at least a contact conductor material. The contact conductor material may include, for example, a silicide liner such as Ni, Pt, or NiPt, or an adhesion metal liner such as TiN and a conductive metal (e.g., W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, etc.) or an alloy thereof. Each front-side source / drain contact structure 28 may also include one or more contact liners (not shown). In one or more embodiments, the contact liners (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof such as Ti / TiN and Ti / WC. In one or more embodiments in which a contact liner is present, the contact liner (not shown) may include a silicide liner, such as Ti, Ni, NiPt, etc., and a diffusion barrier material, as defined above.

[0051] The front surface contact structures 32 present in the memory device region 100 and the logic device region 102 are comprised of at least a contact conductor material, as described above for the front surface source / drain contact structures 28. The front surface contact structures 32 may also include a diffusion barrier material, as defined above, present along the sidewalls and bottom wall of the front surface contact structures 32. In the memory device region 100, the front surface contact structures 32 and the front surface source / drain contact structures 28 electrically connect the front surface ReRAM 34 / 35 / 36 to the source region 26 of transistor T1.

[0052] The front-side ReRAM 34 / 35 / 36 includes a first electrode 34, a filament-forming layer 35 (which may also be referred to herein as a dielectric switching layer), and a second electrode 36. The first electrode 34 may be composed of a conductive material such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Cu, Co, CoWP, CoN, W, WN, or any combination thereof. The first electrode 34 may have a thickness of 2 nm to 80 nm, although other thicknesses are also contemplated and may be used herein as the thickness of the first electrode 34. The filament-forming layer 35 is composed of a dielectric material such as a dielectric metal oxide having a dielectric constant of 4.0 or greater. The filament-forming layer 35 is electrically insulating at this point in the present application; in actual use, a conductive filament may be formed in the filament-forming layer 35. Examples of dielectric metal oxides that may be employed as the filament-forming layer 35 include, but are not limited to, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, or combinations thereof. In some embodiments, hydrogen may be present in the dielectric material providing the filament-forming layer 35. The filament-forming layer 35 may have a thickness of 1 nm to 50 nm, although it is contemplated that other thicknesses may be used for the filament-forming layer 35. The second electrode 36 may comprise one of the conductive materials described above for the first electrode 34. In some embodiments, the conductive material providing the second electrode 36 is compositionally identical to the conductive material providing the first electrode 34. In one example, the conductive material providing both the first electrode 34 and the second electrode 36 is comprised of TiN. In other embodiments, the conductive material providing the second electrode 36 is compositionally different from the conductive material providing the first electrode 34. In one example, the conductive material providing the first electrode 34 is comprised of TaN, and the conductive material providing the second electrode 36 is comprised of TiN. The width of the ReRAM can be larger than one gate pitch.

[0053] The dielectric material layer 38 positioned on the top surface and sidewalls of the ReRAMs 34 / 35 / 36 and on the first front surface interlayer dielectric material layer 30 may be composed of a dielectric hard mask material such as silicon nitride and / or silicon oxynitride. The dielectric material layer 38 present in the memory element region may be referred to as a dielectric encapsulation material layer. The dielectric material layer 38 may have a thickness of 5 nm to 50 nm, although other thicknesses are also contemplated and may be used herein as the thickness of the dielectric material layer 38. The dielectric material layer 38 may be a conformal dielectric material layer. "Conformal" means that the vertical thickness of the material layer along horizontal planes is substantially the same (i.e., within ±10%) as the lateral thickness along vertical planes.

[0054] The second front inter-layer dielectric material layer 40 is composed of a dielectric material such as those described above for the first front inter-layer dielectric material layer 30. The dielectric material providing the second front inter-layer dielectric material layer 40 may be compositionally the same as or compositionally different from the dielectric material providing the first front inter-layer dielectric material layer 30.

[0055] The front side BEOL-to-ReRAM metal vias 42 present in the memory device region 100 are comprised of at least a contact conductor material, as described above for the front side source / drain contact structures 28. The front side BEOL-to-ReRAM metal vias 42 may also include a diffusion barrier material, as defined above, present along the sidewalls and bottom wall of the front side BEOL-to-ReRAM metal vias 42. In the memory device region 100, the front side BEOL-to-ReRAM metal vias 42 electrically connect the second (i.e., top) electrodes 36 of the front side ReRAMs 34 / 35 / 36 to the front side BEOL structures 44. As shown, the front side BEOL-to-ReRAM metal vias 42 pass through a dielectric material layer 38 present on the top surface of the ReRAMs 34 / 35 / 36.

[0056] In logic device region 102, there are front surface metal vias 43 that electrically connect front surface BEOL structures 44 to front surface contact structures 32. Front surface metal vias 43 are comprised of at least a contact conductor material, as described above for front surface source / drain contact structures 28. Front surface metal vias 43 may also include a diffusion barrier material, as defined above, present along the sidewalls and bottom wall of front surface metal vias 43.

[0057] The front side BEOL structures 44 present in the memory device region 100 and the logic device region 102 may include one or more interconnect dielectric material layers (including one of the dielectric materials described above for the first front side interlayer dielectric material layer 30) that include one or more wiring regions (the wiring regions may include any conductive metal (e.g., Cu) or metal alloy (e.g., Cu-Al) incorporated therein). The carrier wafer 46 may include one of the semiconductor materials described above for the semiconductor substrate 10.

[0058] The exemplary structure shown in FIGS. 1A-1B may be formed using a combination of front-end-of-the-line (FEOL) processing, middle-of-the-line (MOL) processing, and front-side BEOL processing, each of which processing steps are well known to those skilled in the art. FEOL processing can include conventional nanosheet device formation processes, also well known to those skilled in the art. MOL processing and BEOL processing can also include metallization processes, also well known to those skilled in the art. Metallization can include forming openings in at least one material layer and then filling the openings with at least a conductive material. Filling can include deposition of a conductive material followed by a planarization process, such as chemical mechanical polishing (CMP). BEOL processing can also include ReRAM device processing steps, also well known to those skilled in the art. Details of FEOL processing, MOL processing, and BEOL processing are not provided herein to avoid obscuring the present method.

[0059] 2A-2B, the exemplary structure shown in FIGS. 1A-1B is illustrated after removing the semiconductor substrate 10 to allow for backside processing in both the memory device region 100 and the logic device region 102, respectively. Prior to removing the semiconductor substrate 10, the wafer is typically flipped 180 degrees to physically expose the backside of the semiconductor substrate 10; however, for simplicity, the wafer flip is not shown in the drawings. Backside processing occurs on the side of the wafer opposite the transistors. Flipping the structure can be performed manually or using mechanical means, such as a robotic arm. Removal of the semiconductor substrate 10 can be performed using a material removal process (e.g., chemical wet etching) that is selective in removing the semiconductor material that provides the semiconductor substrate 10. Depending on the composition of the semiconductor substrate 10, this material removal process can include a single step, or multiple steps can be used. It should be noted that the material removal process that removes the semiconductor substrate 10 in both the memory device region 100 and the logic device region 102 creates gaps 48 between the shallow trench isolation structures 12, thereby physically exposing the bottom dielectric isolation layer 14.

[0060] 3A-3B, the exemplary structure shown in FIGS. 2A-2B is illustrated after forming a backside interlayer dielectric material layer 50 in both the memory device region 100 and the logic device region 102, respectively. The backside interlayer dielectric material layer 50 is formed in each gap 48 formed by removing the semiconductor substrate 10 from the structure. The backside interlayer dielectric material layer 50 has a surface that directly contacts the bottom dielectric isolation layer 14 and another surface that is coplanar with the physically exposed horizontal surface of the shallow trench isolation structure 12 opposite the surface that contacts the bottom dielectric isolation layer 14. The backside interlayer dielectric material layer 50 comprises a dielectric material such as those described above for the first frontside interlayer dielectric material layer 30. The backside interlayer dielectric material layer 50 may be formed by deposition followed by planarization. Deposition of the backside interlayer dielectric material layer 50 may include chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or spin-on coating. Planarization can include CMP and / or grinding.

[0061] 4A-4B, the exemplary structures shown in FIGS. 3A-3B are illustrated after the formation of backside contact structures 52 in both the memory device region 100 and the logic device region 102, respectively. Each backside contact structure 52 is in direct physical contact with the drain region 27 of a respective transistor, i.e., T1 or T2, present in a particular device region. Each backside contact structure 52 passes through the backside interlayer dielectric material layer 50 and the bottom dielectric isolation layer 14. Each backside contact structure 52 is comprised of at least a contact conductor material, as described above for the frontside source / drain contact structures 28. Each backside contact structure 52 may also include a diffusion barrier material, as defined above, present along the sidewalls and bottom wall of each backside contact structure 52. Each backside contact structure 52 may be formed by a metallization process, as defined above.

[0062] 5A-5B, the exemplary structures shown in FIGS. 4A-4B are illustrated after forming backside BEOL structures 54 in each of the memory device region 100 and the logic device region 102, respectively. The backside BEOL structures 54 include materials such as those described above for the frontside BEOL structure 44. The backside BEOL structures 54 may be formed utilizing any interconnect device process, including, for example, a damascene process. As shown, the backside contact structure 52 in the memory device region 100 electrically connects the drain region 27 of transistor T1 to the backside BEOL structure 54, and the backside contact structure 52 in the logic device region 102 electrically connects the drain region 27 of transistor T2 to the backside BEOL structure 54.

[0063] In particular, FIG. 5A illustrates a semiconductor structure including a transistor T1 located in a memory device region 100 according to an embodiment of the present application. The transistor T1 includes a gate structure 22, a source region 26 located on a first side of the gate structure 22, and a drain region 27 located on a second side of the gate structure 22, the second side of the gate structure 22 being opposite the first side of the gate structure 22. The structure further includes a front side ReRAM 34 / 35 / 36 located in the memory device region 100 and positioned above the transistor T1. There is also a front side contact structure 32 electrically connecting the front side ReRAM 34 / 35 / 36 to the source region 26 of the transistor T1. There is also a back side contact structure 52 electrically connecting the drain region 27 of the transistor T1 to a back side BEOL structure 54. With the structure illustrated in FIG. 5A, the switching area of ​​the front side ReRAM 34 / 35 / 36 is effectively increased without increasing the gate pitch. Thus, in embedded memory applications, there are wiring advantages to structures present in logic element region 102 (see FIG. 5B).

[0064] Referring now to Figure 6A, another exemplary structure present in memory device region 100 of semiconductor substrate 10 is shown, this exemplary structure including transistor T1 as defined above, front surface contact structure 32, front surface BEOL structure 44, and carrier wafer 46, all present on the front surface of semiconductor substrate 10 and all constructed of materials as described above for the exemplary structure shown in Figures 1A-1B. Transistor T1 shown in Figure 6A is a nanosheet transistor including bottom dielectric isolation layer 14, semiconductor channel material nanosheet 16, inner spacer 18, gate spacer 20, gate structure 22, gate cap 24, source region 26, and drain region 27, all of which are defined above in connection with the exemplary structure shown in Figures 1A-1B. The exemplary structure shown in Figure 6A further includes source / drain contact structure 28, first front surface interlayer dielectric material layer 30, and second front surface interlayer dielectric material layer 40, each of which are described above in connection with the structure shown in Figures 1A-1B. In this embodiment, in memory device region 100, front surface metal vias 43 are present in the second front surface inter-layer dielectric material layer that electrically connect front surface BEOL structures 44 to front surface contact structures 32 present in first front surface inter-layer dielectric material layer 30. Note that there are no front surface ReRAMs 34 / 35 / 36 or dielectric material layer 38 present on the front surface of the exemplary structure shown in Figure 6A. The front surface metal vias 43 present in memory device region 100 include materials such as those described above for the front surface metal vias 43 present in the exemplary structure shown in Figure 1B.

[0065] 6B, another exemplary structure is shown in logic device region 102 of semiconductor substrate 100, where logic device region 102 is positioned adjacent to memory device region 100 shown in FIG. 6A. The another exemplary structure shown in FIG. 6B includes elements as shown in FIG. 1B above. Note that there is no dielectric material layer 38 on the front surface of logic device region 102 separating first front inter-layer dielectric material layer 30 from second front inter-layer dielectric material layer 40.

[0066] The exemplary structures shown in Figures 6A-6B may be formed using a combination of FEOL processing, MOL processing, and front-side BEOL processing, each of which processing steps are well known to those skilled in the art. FEOL processing can include conventional nanosheet device processing, which is also well known to those skilled in the art. MOL processing and BEOL processing can include metallization processes (as defined above), which are also well known to those skilled in the art. Details of FEOL processing, MOL processing, and BEOL processing are not provided herein so as not to obscure the present methods.

[0067] 7A-7B, the exemplary structures shown in FIGS. 6A-6B are illustrated after removing the semiconductor substrate 10 to allow for backside processing in both the memory device region 100 and the logic device region 102, respectively. Prior to removing the semiconductor substrate 10, the wafer is typically flipped 180 degrees to physically expose the backside of the semiconductor substrate 10; however, for simplicity, the wafer flip is not shown in the drawings. Backside processing occurs on the side of the wafer opposite the transistors. Flipping the structure can be performed manually or using mechanical means, such as a robotic arm. Removal of the semiconductor substrate 10 can be performed using a material removal process (e.g., chemical wet etching) that is selective in removing the semiconductor material that provides the semiconductor substrate 10. Depending on the composition of the semiconductor substrate 10, this material removal process may include a single step, or multiple steps may be used. It should be noted that the material removal process that removes the semiconductor substrate 10 in both the memory device region 100 and the logic device region 102 creates gaps 48 between the shallow trench isolation structures 12, thereby physically exposing the bottom dielectric isolation layer 14.

[0068] 8A-8B, the exemplary structure shown in FIGS. 7A-7B is illustrated after forming a first backside interlayer dielectric material layer 50 in both the memory device region 100 and the logic device region 102, respectively. The backside interlayer dielectric material layer 50 is formed in each gap 48 formed by removing the semiconductor substrate 10 from the structure. The backside interlayer dielectric material layer 50 has a surface that directly contacts the bottom dielectric isolation layer 14 and another surface that is coplanar with the physically exposed horizontal surface of the shallow trench isolation structure 12 opposite the surface that contacts the bottom dielectric isolation layer 14. The backside interlayer dielectric material layer 50 comprises a dielectric material such as those described above for the first frontside interlayer dielectric material layer 30. The backside interlayer dielectric material layer 50 may be formed by deposition followed by planarization as defined above to provide the backside interlayer dielectric material layer 50 shown in FIGS. 3A-3B.

[0069] 9A-9B, the exemplary structures shown in FIGS. 8A-8B are illustrated after forming backside contact structures 52 in both the memory device region 100 and the logic device region 102, respectively. Each backside contact structure 52 is in direct physical contact with the drain region of a respective transistor, i.e., T1 or T2, present in a particular device region. Each backside contact structure 52 passes through the backside interlayer dielectric material layer 50 and the bottom dielectric isolation layer 14. Each backside contact structure 52 is comprised of at least a contact conductor material, as described above for the frontside source / drain contact structures 28. Each backside contact structure 52 may also include a diffusion barrier material, as defined above, present along the sidewalls and bottom wall of each backside contact structure 52. Each backside contact structure 52 may be formed by a metallization process, as defined above.

[0070] 10A-10B, the exemplary structure shown in FIGS. 9A-9B is shown after further backside processing, including forming ReRAMs 56 / 57 / 58 in the memory element region 100 and forming a backside BEOL structure 54, respectively. The ReRAMs 56 / 57 / 58 are backside ReRAMs including a first electrode 56, a filament-forming layer 57, and a second electrode 58. The first electrode 56 includes a conductive material such as that described above for the first electrode 34 of the frontside ReRAM, the filament-forming layer 57 includes a dielectric material such as that described above for the filament-forming layer 35 of the frontside ReRAM, and the second electrode 58 includes a conductive material such as that described above for the second electrode 36 of the frontside ReRAM. This backside ReRAM 56 / 57 / 58 may be formed by the deposition of various material layers followed by lithographic patterning of these various deposited material layers, and these processing steps may be used to form the frontside ReRAM shown in FIG. 1A. As shown in FIG. 10A, the backside ReRAM 56 / 57 / 58 has a surface that is in direct physical contact with a backside contact structure 52 formed in contact with the drain region 27 of the transistor T1 present in the memory element region 100.

[0071] After forming the backside ReRAM 56 / 57 / 58, a dielectric material layer 59 is formed. The dielectric material layer 59 includes a dielectric material such as those described above for the dielectric material layer 38. The dielectric material layer 59 encapsulates the backside ReRAM 56 / 57 / 58, i.e., it resides on the physically exposed surfaces of the backside ReRAM 56 / 57 / 58.

[0072] A second backside dielectric material layer 60 is then formed over the dielectric material layer 59. The second backside dielectric material layer 60 incorporates the backside ReRAM 56 / 57 / 58. The second backside dielectric material layer 60 comprises a dielectric material such as those described above for the first frontside interlayer dielectric material layer 30, and the second backside dielectric material layer 60 may be formed by a deposition process such as, for example, CVD, PECVD, or spin-on coating.

[0073] Then, a backside BEOL-to-ReRAM metal via 62 is formed in the memory device region 100, and a backside metal via 63 is formed in the logic device region 102. The backside BEOL-to-ReRAM metal via 62 and the backside metal via 63 are composed of at least a contact conductor material as described above for the frontside source / drain contact structures 28. These via structures may also include a diffusion barrier material, as defined above, present along the sidewalls and bottom wall of each of the via structures. The backside BEOL-to-ReRAM metal via 62 and the backside metal via 63 may be formed in a metallization process as defined above. As shown, the backside BEOL-to-ReRAM metal via 62 passes through a dielectric material layer 59 and contacts the second electrode 58 of the backside ReRAM 56 / 57 / 58.

[0074] The backside BEOL structure 54 includes materials such as those described above for the frontside BEOL structure 44. The backside BEOL structure 54 may be formed utilizing any interconnect device process, including, for example, a damascene process. As shown, a backside contact structure 52 in the memory device region 100 electrically connects the drain region 27 of transistor T1 to the backside ReRAM 56 / 57 / 58, a backside BEOL-to-ReRAM metal via 62 electrically connects the backside ReRAM 56 / 57 / 58 to the backside BEOL structure 54, and a backside contact structure 52 and a backside metal via 63 in the logic device region 102 electrically connects the drain region 27 of transistor T2 to the backside BEOL structure 54.

[0075] 10A illustrates a semiconductor structure including a transistor T1 located in a memory device region 100 according to another embodiment. The transistor T1 includes a gate structure 22, a source region 26 located on a first side of the gate structure 22, and a drain region 27 located on a second side of the gate structure 22, the second side of the gate structure 22 being opposite the first side of the gate structure 22. The structure of this embodiment further includes a ReRAM 56 / 57 / 58 located in the memory device region 100 and positioned below the transistor T1. The structure further includes a front contact structure 32 electrically connecting the source region 26 of the transistor T1 to the front BEOL structure 44 and a backside contact structure 52 electrically connecting the drain region 27 of the transistor T1 to the ReRAM 56 / 57 / 58. The backside ReRAM 56 / 57 / 58 is electrically connected to the backside BEOL structure 54 by a backside BEOL-to-ReRAM metal via 62. In the structure shown in FIG. 10A, the backside ReRAM 56 / 57 / 58 switching area is effectively increased without increasing the gate pitch. In other words, the lateral width of the ReRAM can be larger than one gate pitch. Thus, in embedded memory applications, there is a wiring advantage for the structures present in the logic element region 102 (see FIG. 10B). In this embodiment of the present application, there is no need to shift the gate contact (not shown) as in the embodiment shown in FIG. 5A.

[0076] While the present application has been particularly shown and described with respect to preferred embodiments thereof, those skilled in the art will recognize that the foregoing and other changes in form and detail may be made without departing from the scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. a transistor located in the memory element region and having a gate structure, a source region located on a first side of the gate structure, and a drain region located on a second side of the gate structure, the second side of the gate structure being opposite the first side of the gate structure; a resistive random access memory (ReRAM) located in the memory element region and positioned above the transistor; a front contact structure electrically connecting the ReRAM to the source region of the transistor; and a backside contact structure electrically connecting the drain region of the transistor to a backside interconnect (BEOL) structure; 1. A semiconductor structure comprising:

2. 10. The semiconductor structure of claim 1, wherein said transistor is a nanosheet transistor comprising a plurality of vertically stacked and spaced apart semiconductor channel material nanosheets, and wherein said gate structure of said transistor wraps around a central portion of each semiconductor channel material nanosheet of said plurality of vertically stacked and spaced apart semiconductor channel material nanosheets.

3. 3. The semiconductor structure of claim 2, further comprising a bottom dielectric isolation layer and a backside interlayer dielectric material layer positioned beneath said nanosheet transistor, said backside contact structure passing through both said backside interlayer dielectric material layer and said bottom dielectric isolation layer and in direct physical contact with said drain region of said transistor.

4. 10. The semiconductor structure of claim 1, further comprising a source / drain contact structure positioned between said front side contact structure and said source region of said transistor, said front side contact structure being in direct physical contact with a first surface of said source / drain contact structure and a second surface of said source / drain contact structure opposite said first surface being in direct physical contact with said source region of said transistor.

5. 10. The semiconductor structure of claim 1, further comprising a front side BEOL structure positioned above said ReRAM, said front side BEOL structure electrically connected to a top electrode of said ReRAM by a metal via from said front side BEOL to said ReRAM.

6. 6. The semiconductor structure of claim 5 wherein said metal via from said front side BEOL to said ReRAM passes through a layer of dielectric material overlying said ReRAM.

7. 6. The semiconductor structure of claim 5 further comprising a carrier wafer positioned on a surface of said front side BEOL structure.

8. 10. The semiconductor structure of claim 1 wherein said ReRAM is embedded in a front surface interlevel dielectric material layer.

9. 10. The semiconductor structure of claim 1, further comprising: a logic element area positioned adjacent to said memory element region, said logic element area having another transistor including another gate structure, another source region positioned on a first side of said another gate structure, and another drain region positioned on a second side of said another gate structure, said second side of said another gate structure opposite said first side of said another gate structure.

10. 10. The semiconductor structure of claim 9, further comprising: another front side contact structure electrically connecting said another source region of said another transistor to a front side BEOL structure; and another back side contact structure electrically connecting said another drain region of said another transistor to a back side BEOL structure.

11. a transistor located in the memory element region and having a gate structure, a source region located on a first side of the gate structure, and a drain region located on a second side of the gate structure, the second side of the gate structure being opposite the first side of the gate structure; a resistive random access memory (ReRAM) located in the memory element region and positioned below the transistor; a front contact structure electrically connecting the source region of the transistor to a back-end-of-line (BEOL) structure; and a backside contact structure electrically connecting the drain region of the transistor to the ReRAM; 1. A semiconductor structure comprising:

12. 12. The semiconductor structure of claim 11 , wherein said transistor is a nanosheet transistor comprising a plurality of vertically stacked and spaced apart semiconductor channel material nanosheets, and wherein said gate structure of said transistor wraps around a central portion of each semiconductor channel material nanosheet of said plurality of vertically stacked and spaced apart semiconductor channel material nanosheets.

13. 13. The semiconductor structure of claim 12, further comprising a bottom dielectric isolation layer and a backside interlayer dielectric material layer positioned beneath said nanosheet transistor, said backside contact structure passing through both said backside interlayer dielectric material layer and said bottom dielectric isolation layer and in direct physical contact with said drain region of said transistor.

14. 12. The semiconductor structure of claim 11, further comprising a source / drain contact structure positioned between said front side contact structure and said source region of said transistor, said front side contact structure being in direct physical contact with a first surface of said source / drain contact structure and a second surface of said source / drain contact structure opposite said first surface being in direct physical contact with said source region of said transistor.

15. 12. The semiconductor structure of claim 11, further comprising a front side metal via positioned between said front side contact structure and said front side BEOL structure, said front side metal via having a first surface in direct contact with said front side BEOL structure and a second surface opposite said first surface in direct contact with said front side contact structure.

16. 12. The semiconductor structure of claim 11, further comprising a backside BEOL structure positioned below said ReRAM, said backside BEOL structure electrically connected to a bottom electrode of said ReRAM by a metal via from the backside BEOL to the ReRAM.

17. 12. The semiconductor structure of claim 11 further comprising a carrier wafer positioned on a surface of said front side BEOL structure.

18. 12. The semiconductor structure of claim 11 wherein said ReRAM is embedded in a backside interlayer dielectric material layer.

19. 12. The semiconductor structure of claim 11 , further comprising: a logic element area positioned adjacent to said memory element region, said logic element area having another transistor including another gate structure, another source region positioned on a first side of said another gate structure, and another drain region positioned on a second side of said another gate structure, said second side of said another gate structure opposite said first side of said another gate structure.

20. 20. The semiconductor structure of claim 19, further comprising: another front side contact structure electrically connecting said another source region of said another transistor to a front side BEOL structure; and another back side contact structure electrically connecting said another drain region of said another transistor to a back side BEOL structure.

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