Systems and methods for bonding semiconductor devices

Abstract

A method for manufacturing a semiconductor package, the method includes: providing a first semiconductor die including a plurality of metallization layers, completely overlying a topmost one of the metallization layers with a barrier layer, completely overlying, in order, a stop layer and a laser lift-off layer on the barrier layer, attaching a first side of the first semiconductor die to a first wafer via at least the laser lift-off layer, attaching a second side of the first semiconductor die to a second wafer, removing the first wafer from the first semiconductor die based on the laser lift-off layer, forming a plurality of connectors on the first side of the first semiconductor die to electrically couple to the topmost metallization layer, and bonding the first semiconductor die to a third wafer including the second semiconductor die.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Non-Provisional Patent Application No. 18 / 072,096, filed November 30, 2022, which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to semiconductor devices and methods for bonding multiple semiconductor devices. [Background technology]

[0003] The semiconductor industry has grown rapidly due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density has been achieved by iteratively reducing the size of the minimum feature, allowing more components to be integrated into a given area. As the demand for smaller size, higher speed and bandwidth, as well as reduced power consumption and latency, has increased in recent years, there has been an increasing need for smaller and more creative packaging techniques for semiconductor dies. Summary of the Invention [Means for solving the problem]

[0004] At least one aspect of the present disclosure is directed to a method for manufacturing a semiconductor package, the method including: providing a first semiconductor die including a plurality of metallization layers, completely overlying a topmost one of the metallization layers with a barrier layer, completely overlying the barrier layer with a stop layer and a laser lift-off layer, attaching a first side of the first semiconductor die to a first wafer via at least the laser lift-off layer, attaching a second side of the first semiconductor die to a second wafer, removing the first wafer from the first semiconductor die via the laser lift-off layer, forming a plurality of connectors on the first side of the first semiconductor die to electrically couple to the topmost metallization layer, and bonding the first semiconductor die to a third wafer including the second semiconductor die.

[0005] In some embodiments, the second semiconductor die includes a plurality of second metallization layers and a plurality of second connectors, and bonding the first semiconductor die to the third wafer includes connecting at least one connector of the plurality of connectors to a corresponding one second connector of the plurality of second connectors.

[0006] In some embodiments, the method further includes forming a plurality of vias through the barrier layer and contacting the top metallization layer prior to forming the plurality of connectors, each of the plurality of vias contacting a corresponding one of the plurality of connectors.

[0007] In some embodiments, removing the first wafer includes applying a laser from the first side of the first semiconductor die to cause thermochemical dissociation of the laser lift-off layer, and the method further includes polishing away any remaining portions of the laser lift-off layer until the stop layer is exposed.

[0008] In some embodiments, attaching the second side of the first semiconductor die to the second wafer includes forming a first bonding layer on the second side of the first semiconductor die, planarizing the first bonding layer using a laser, forming a second bonding layer on the second wafer, and bonding the first bonding layer to the second bonding layer, wherein forming the first bonding layer, planarizing the first bonding layer, and bonding the first bonding layer to the second bonding layer are each performed at an elevated temperature.

[0009] In some embodiments, the step of forming the plurality of connectors on the first surface of the first semiconductor die is performed at a temperature of about 250° C. or less.

[0010] At least another aspect of the present disclosure is directed to a method of manufacturing a semiconductor package, the method including: bonding a plurality of semiconductor dies on their respective first sides to a first wafer, bonding the plurality of semiconductor dies on their respective second sides to a second wafer, separating the first wafer from the plurality of semiconductor dies, forming a plurality of first connectors in electrical contact with the plurality of semiconductor dies disposed on the second wafer, and bonding the plurality of semiconductor dies to the third wafer by connecting the plurality of first connectors to a plurality of second connectors disposed on a third wafer, respectively.

[0011] In some embodiments, forming the plurality of first connectors is performed after any of bonding the plurality of semiconductor dies to a first wafer, bonding the plurality of semiconductor dies to a second wafer, or separating the first wafer from the plurality of semiconductor dies, and each of bonding the plurality of semiconductor dies to a first wafer, bonding the plurality of semiconductor dies to a second wafer, and separating the first wafer from the plurality of semiconductor dies is performed at an elevated temperature.

[0012] In some embodiments, separating the first wafer from the plurality of semiconductor dies includes applying a laser through the first wafer onto the first faces of the semiconductor dies.

[0013] In some embodiments, prior to forming the plurality of first connectors, each of the semiconductor dies includes a plurality of metallization layers, a barrier layer completely overlying a top layer of the plurality of metallization layers, a dielectric layer overlying the barrier layer, a stop layer overlying the dielectric layer, and a laser lift-off layer overlying the stop layer. Following separating the first wafer from the plurality of semiconductor dies, the method further includes polishing a first surface of the semiconductor die until the stop layer of at least one of the semiconductor dies is exposed, and forming a plurality of vias through the barrier layer and the dielectric layer. Each of the plurality of first connectors is electrically coupled to the top metallization layer through the plurality of vias.

[0014] In some embodiments, the step of bonding the plurality of semiconductor dies to the third wafer is performed by a hybrid bonding technique.

[0015] Yet another aspect of the present disclosure is directed to a method for manufacturing a semiconductor package, the method including: providing a plurality of semiconductor dies, each of the plurality of semiconductor dies including, on a first surface thereof, a plurality of metallization layers, a dielectric layer completely overlying a topmost one of the metallization layers, a stop layer overlying the dielectric layer, and a laser lift-off layer overlying the stop layer; bonding the plurality of semiconductor dies to a first wafer using their respective first surfaces; bonding the plurality of semiconductor dies to a second wafer using their respective second surfaces; separating the first wafer from the plurality of semiconductor dies by inducing thermochemical dissociation of the laser lift-off layer of each of the plurality of semiconductor dies; forming a plurality of vias through the dielectric layer, each of the vias contacting the topmost metallization layer; forming a plurality of first connectors, each of the vias contacting the plurality of first connectors; and bonding the plurality of semiconductor dies to a third wafer by connecting the plurality of first connectors to a plurality of second connectors disposed on a third wafer, respectively.

[0016] In some embodiments, each of the steps of bonding the plurality of semiconductor dies to the first wafer, bonding the plurality of semiconductor dies to the second wafer, and separating the first wafer from the plurality of semiconductor dies is performed at an elevated temperature.

[0017] In some embodiments, each of the steps of forming the plurality of vias and forming the plurality of first connectors is performed at a temperature of about 250° C. or less.

[0018] These and other aspects and implementations are described in detail below. The foregoing information and the following detailed description, including illustrative examples of various aspects and implementations, provide an overview or framework for understanding the nature and characteristics of the claimed aspects and implementations. The drawings provide illustrations and a further understanding of the various aspects and implementations and are incorporated into and constitute a part of this specification. It will be readily understood that multiple aspects can be combined and that features described in the context of one aspect of the invention can be combined with other aspects. Multiple aspects can be implemented in any convenient manner. As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0019] Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying drawings, which are schematic and are not intended to be to scale. Unless indicated as representing background art, the drawings depict aspects of the present disclosure. For clarity, not every component is necessarily labeled in every drawing. [Brief explanation of the drawings]

[0020] [Figure 1] 1 illustrates a flowchart of an exemplary method for fabricating a semiconductor package, according to some embodiments. [Figure 2-11] 2A-2C illustrate respective cross-sectional views of a semiconductor package produced by the method of FIG. 1 at various stages of fabrication, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0021] Reference will now be made to the exemplary embodiments illustrated in the drawings, and specific language will be used to describe the embodiments herein. It will be understood, however, that no limitation on the scope of the claims or the present disclosure is intended. Variations and further modifications to the features of the invention illustrated herein, and further applications of the principles of the subject matter illustrated herein, which may occur to one skilled in the art in possession of this disclosure, are intended to be within the scope of the subject matter disclosed herein. Other embodiments may be used and / or other changes may be made without departing from the spirit or scope of the disclosure. The exemplary embodiments described in the detailed description are not intended to limit the subject matter presented.

[0022] As semiconductor technology continues to advance, stacked semiconductor devices, such as 3D integrated circuits (3DICs), have emerged as an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, and processor circuits are fabricated on different semiconductor wafers. To further reduce the form factor of a semiconductor device, two or more semiconductor wafers can be placed on top of each other.

[0023] Two semiconductor wafers or dies can be bonded together by a suitable bonding technique. Commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reactive bonding, hybrid bonding, etc. Electrical connections can be provided between stacked semiconductor wafers / dies (or stacked semiconductor devices). Stacked semiconductor devices can offer increased density in a smaller form factor, enabling increased performance and reduced power consumption.

[0024] Of particular interest are hybrid bonding techniques that do not require a specific high-temperature annealing process. In hybrid bonding techniques, a permanent bond is formed using a dielectric bond (e.g., SiOx ) with one or more buried metal (e.g., Cu) bonds. Hybrid bonding extends fusion bonding with buried metal pads at the bonding interface, enabling the connection of different semiconductor wafer / die faces. However, in existing technologies, the buried metal pads of a semiconductor device are typically formed immediately after the top metallization layer of the semiconductor device is formed, i.e., before the semiconductor device is processed for bonding to another semiconductor device. One or more of such process steps (e.g., fusion bonding to a carrier / sacrificial substrate, laser planarization, laser lift-off, etc.) typically require high-temperature annealing processes that can damage the metal pads. Therefore, existing technologies for bonding different semiconductor devices have not been completely satisfactory in some aspects.

[0025] The present disclosure provides various embodiments of methods for bonding semiconductor devices (e.g., die-to-wafer, wafer-to-wafer, die-to-die) that may advantageously avoid the above-identified problems. In one aspect of the present disclosure, instead of forming metal pads immediately after the top metallization layer of the semiconductor devices to be bonded, the methods disclosed herein may include not forming the metal pads (and corresponding via structures connecting them to the top metallization layer) until the semiconductor devices have progressed through steps requiring a high-temperature annealing process. For example, a semiconductor device may first be bonded to a first carrier / sacrificial wafer through multiple layers that fully overlie the top metallization layer, bonded to a second carrier / sacrificial wafer through a bonding layer, and then delaminated from the first carrier / sacrificial wafer. Each of these steps may involve a high-temperature annealing process. By placing the step of forming the metal pads after these high-temperature annealing processes, the metal pads may advantageously not be subject to damage induced by the high-temperature annealing process. Thus, the disclosed methods may solve technical problems faced by existing technologies.

[0026] 1 illustrates a flowchart of an exemplary method 100 for forming a semiconductor package having at least one reconstituted wafer having multiple semiconductor dies bonded to another wafer by multiple low-temperature hybrid bonds. Note that method 100 is merely an example and is not intended to limit the present disclosure. Thus, it should be understood that additional operations may be provided before, during, and after method 100 of FIG. 1, and that some other operations may only be briefly described herein.

[0027] In various embodiments, the operations of method 100 may be associated with cross-sectional views of an exemplary semiconductor package 200 at various stages of fabrication, as shown in Figures 2-11, respectively, which are described in further detail below. It should be understood that the semiconductor package 200 shown in Figures 2-11 may include a number of other devices, such as inductors, fuses, capacitors, coils, etc., while remaining within the scope of the present disclosure.

[0028] Generally, method 100 begins with operation 102, which includes providing a plurality of first semiconductor dies, each including a plurality of metallization layers formed on a first surface. In various embodiments, the topmost one of the metallization layers of each of the first semiconductor dies may be completely overlaid with at least a barrier layer, a stop layer, and a laser lift-off (LLO) layer. Method 100 then proceeds to operation 104, which includes attaching the first semiconductor dies on their first surfaces to a first (sacrificial) wafer. Method 100 then proceeds to operation 106, which includes thinning the first semiconductor dies from their respective second surfaces (e.g., backsides). Method 100 then proceeds to operation 108, which includes overlaying the first semiconductor dies with an encapsulation layer. Method 100 then proceeds to operation 110, which includes planarizing the encapsulation layer. Method 100 then proceeds to operation 112, which includes attaching the first semiconductor dies on their second surfaces to a second (support) wafer. Method 100 proceeds to operation 114, which involves removing the first wafer based on the LLO layer. Method 100 proceeds to operation 116, which involves forming a metal connector on a first side of each of the first semiconductor dies. Method 100 proceeds to operation 118, which involves bonding the first semiconductor die to a third (semiconductor) wafer that includes a plurality of second semiconductor dies. In various embodiments of the present disclosure, any operation after operation 116 (e.g., operation 118) can be performed without an annealing process or at a substantially low temperature, for example, at or below about 250°C.

[0029] Corresponding to operation 102 of FIG. 1, FIG. 2 is a cross-sectional view of an exemplary first semiconductor die 250 to be included in a semiconductor package 200 at one of various stages of fabrication, according to various embodiments.

[0030] As shown, a first semiconductor die 250 includes a substrate 252, multiple metallization layers 254 on the substrate 252, a barrier layer 256 on a top one of the metallization layers, an interlayer dielectric (ILD) or intermetal dielectric (IMD) material 258 on the barrier layer 256, a stop layer 260 on the ILD material 258, and a laser lift-off (LLO) layer 262 on the stop layer 260. Each of the metallization layers 254 disposed on a first surface of the substrate 252 includes multiple interconnect structures, such as, for example, metal lines 270 and vias 272. The bottom most metallization layer 254 may be referred to as M0, with subsequent metallization layers being referred to as M1, M2, etc., respectively, and the top most metallization layer being referred to as Mx. In various embodiments of the present disclosure, the barrier layer 256 (and subsequent layers 258-262) may completely overlap the top metallization layer Mx.

[0031] The substrate 252 may be a semiconductor substrate, such as a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 252 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 252 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0032] Substrate 252 includes a plurality of device features / structures 253 (e.g., transistors, diodes, resistors, etc., not shown for simplicity) formed along the surface of substrate 252. A plurality of metallization layers 254 may be formed over the surface of substrate 252, each of which includes a plurality of interconnect structures (e.g., metal lines 270 and vias 272). These interconnect structures throughout metallization layers 254 are configured to electrically connect the device structures to one another to form an integrated circuit that may function as a logic device, a memory device, an input / output device, etc. The interconnect structures (e.g., formed of a conductive material such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers or combinations thereof) may be embedded in one or more ILD or IMD materials (e.g., low-k dielectric materials such as phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-on glass, spin-on polymer, silicon carbon materials, compounds thereof, composites thereof, combinations thereof, etc.).

[0033] Further, a barrier layer 256 is formed on the top metallization layer Mx, followed by an ILD / IMD material 258, a stop layer 260, and an LLO layer 262. The barrier layer 256 may include, by way of example, cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, titanium nitride, and / or combinations thereof, although the barrier layer 256 may alternatively include other materials. The ILD / IMD material 258 may include one or more low-k dielectric materials, such as silicon oxide (SiO). The stop layer 260, configured to stop at least one of the etching process or the polishing process, may include a dielectric material, such as silicon nitride (SiN). The LLO layer 262 can be utilized as a bonding layer for attaching the first semiconductor die 250 to a carrier wafer (shown in FIG. 3). Furthermore, LLO layer 262 can be induced by thermal chemical dissociation upon application of a laser, thereby allowing for subsequent removal of first semiconductor die 250 from the carrier wafer (shown in FIG. 8). In some embodiments, LLO layer 262 can comprise a silicon-based dielectric material, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, and can be deposited or thermally grown.

[0034] Corresponding to operation 104 of FIG. 1, FIG. 3 is a cross-sectional view of a semiconductor package 200 having multiple first semiconductor dies 250 bonded to a sacrificial wafer 300 at various stages of fabrication, according to various embodiments.

[0035] In some embodiments, the first semiconductor die 250 can be bonded to a sacrificial wafer 300 to form a reconstructed wafer. It should be noted that the reconstructed wafer at this stage may not be completely complete, i.e., one or more components may be removed or added. For example, in FIG. 3 , each of the first semiconductor dies 250 is inverted and attached to the sacrificial wafer 300, with their respective metallization layers 254 and overlying layers 256-262 interposed between them. Furthermore, the first semiconductor die 250 can be bonded to the sacrificial wafer 300 via a fusion bonding process. The fusion bonding process may involve bringing the first semiconductor die 250 and the sacrificial wafer 300 into intimate contact, which holds them together due to atomic attractive forces (i.e., van der Waals forces). The first semiconductor die 250 and the sacrificial wafer 300 may undergo an annealing process, after which a solid bond may be formed between the first semiconductor die 250 and the sacrificial wafer 300. The temperature of the annealing process can be any suitable temperature, such as about 250° C. to about 350° C. The fusion bonding process can result from SiO (oxide) / Si bonding, Si / Si bonding, and / or other suitable bonding. In some embodiments, an optional bonding layer 320 (e.g., formed of silicon oxide) can be formed on the sacrificial wafer 300.

[0036] Corresponding to operation 106 of FIG. 1, FIG. 4 is a cross-sectional view of semiconductor package 200 in one of various stages of fabrication, in which a polishing process 401 is performed from the backside of first semiconductor die 250, according to various embodiments.

[0037] 3, when each of the first semiconductor dies 250 has a respective thickness (or height), the polishing process 401 may polish the first semiconductor dies 250 from their backsides. Thus, a flat (virtual) surface may be formed by the polished bottom surfaces of each of the first semiconductor dies 250, as shown in FIG. 4. The polishing process 401 may include a chemical mechanical polishing (CMP) process in some embodiments.

[0038] Corresponding to operation 108 of FIG. 1, FIG. 5 is a cross-sectional view of a semiconductor package 200 in which an encapsulation layer 500 may be formed over a first semiconductor die 250 at one of various stages of fabrication according to various embodiments.

[0039] The encapsulation layer 500 formed on the reconstituted wafer 300 may be continuous around each of the semiconductor dies 250. In some embodiments, the encapsulation layer 500, which may be deposited or thermally grown at high temperatures (e.g., above 250° C.), may include epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or combinations thereof, with or without a filler embedded therein. The filler may include a carbon filler or a glass filler. In some embodiments, the encapsulation layer 500 may include a silicon-based dielectric material, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or multilayers thereof.

[0040] Corresponding to operation 110 of FIG. 1, FIG. 6 is a cross-sectional view of a semiconductor package 200 in which a polishing process 601 may be performed on an encapsulation layer 500 at one of various stages of fabrication, according to various embodiments.

[0041] 5, the encapsulation layer 500 may exhibit a non-planar surface when formed. In order to bond the reconstructed wafer to another wafer (e.g., a support wafer, as shown below), the non-planar surface of the encapsulation layer 500 may be polished using a polishing process 601. Thus, the surface of the encapsulation layer 500 opposite the other surface that contacts the sacrificial wafer 300 may be flat. In some embodiments, the polishing process 601 may include a laser polishing process. Such a laser polishing process may include the application of a pulsed laser beam having a very high power density, which is typically performed at high temperatures (e.g., above 250°C).

[0042] Corresponding to operation 112 of FIG. 1, FIG. 7 is a cross-sectional view of a semiconductor package 200 in which a reconstructed wafer (including a first semiconductor die 250 bonded to a sacrificial wafer 300) is attached to a support wafer 700 at one of various stages of fabrication, according to various embodiments.

[0043] The reconstructed wafer may be bonded to the support wafer 700 via a fusion bonding process. The fusion bonding process may involve bringing the reconstructed wafer and the support wafer 700 into intimate contact, which holds them together due to atomic attractive forces (i.e., van der Waals forces). The reconstructed wafer and the support wafer 700 may undergo an annealing process, after which a solid bond may be formed between the reconstructed wafer and the support wafer 700 (e.g., between the encapsulation layer 500 and the support wafer 700). The temperature of the annealing process may be any suitable temperature, such as about 250°C to about 350°C. The fusion bonding process may result from a SiO2 (oxide) / Si bond, a Si / Si bond, and / or other suitable bond. In some embodiments, an optional bonding layer 720 (e.g., formed of silicon oxide) may be formed between the encapsulation layer 500 and the support wafer 700.

[0044] Corresponding to operation 114 of FIG. 1, FIG. 8 is a cross-sectional view of semiconductor package 200 at various stages of fabrication with sacrificial wafer 300 removed from the remainder of the reconstructed wafer, according to various embodiments.

[0045] The sacrificial wafer 300 may be removed via a laser lift-off (LLO) process. In such an LLO process, optical energy (e.g., a laser beam) 810 irradiates the reconstructed wafer through a first surface of the sacrificial wafer 300, and the irradiation passes through the sacrificial wafer 300 to the interface between the opposite second surface of the sacrificial wafer 300 and the first semiconductor die 250, e.g., between the second surface of the sacrificial wafer 300 and the LLO layer 262 ( FIG. 2 ) disposed on each of the first semiconductor die 250. In various embodiments, the sacrificial wafer 300 may be optically transparent to the wavelength of the optical energy 810. As a non-limiting example, the laser irradiation incident on the sacrificial wafer 300 may be 248 nm irradiation from a KrF pulsed excimer laser having a pulse width of 38 ns. The energy passing through the sacrificial wafer 300 is then absorbed by the LLO layer 262, which causes thermal chemical dissociation in the LLO layer 262. The first semiconductor die 250 (while still bonded to the support wafer 700) can be peeled, cut, or separated from the sacrificial wafer 300. Thus, the LLO layer 262 is sometimes referred to as a release layer. The LLO process may be performed in either a vacuum, air, or other ambient environment, and is generally performed at high temperatures (e.g., above 250° C.).

[0046] Corresponding to operation 116 of FIG. 1, FIG. 9 is a cross-sectional view of a semiconductor package 200 in which a polishing process 901 may be performed on a first semiconductor die 250 until its stop layer 260 is exposed, in one of various stages of fabrication, according to various embodiments.

[0047] The polishing process 901 may include a chemical-mechanical polishing (CMP) process, and in some embodiments, the chemical-mechanical polishing (CMP) process may not be stopped until the stop layer 260 is exposed. For example, after separation from the sacrificial wafer 300 ( FIG. 8 ), remaining portions of each of the LLO layers 262 may still be present on the first semiconductor die 250. The polishing process 901 may polish such remaining portions until the stop layer 260 is exposed. In other words, the stop layer 260 may be configured to stop the polishing process 901. Once exposed, the stop layer 260 may be removed to expose the ILD material 258. Next, as shown in FIG. 10 , a plurality of metal connectors (e.g., bond pads and corresponding vias) may be formed through the ILD material 258 and the barrier layer 256 to contact interconnect structures disposed in the top metallization layer Mx of each first semiconductor die 250.

[0048] 10 illustrates a cross-sectional view of one of the first semiconductor dies 250 bonded to the support wafer 700, with multiple vias 1070 and multiple bond pads 1072 formed on the top metallization layer Mx. The vias 1070 and bond pads 1072 may each be formed of one or more conductive materials, such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers or combinations thereof. The vias 1070 and bond pads 1072 may be formed by one or more damascene processes performed on the re-exposed ILD material 258. After forming the bond pads 1072 (as shown in FIG. 10 ), the first semiconductor die 250 may have a bond surface 1050 that includes both at least one dielectric material (e.g., the ILD material 258) and at least one metal material (e.g., the bond pads 1072). Such hybrid bonding surfaces along each of the first semiconductor dies 250 enable the reconstructed wafer (first semiconductor die 250 bonded to support wafer 700) to be bonded to another wafer, which may also include multiple (e.g., second) semiconductor dies, by a hybrid bonding process that is typically performed at relatively low temperatures (e.g., 250° C. or less). Thus, the metal connectors can be spared from possible heat damage.

[0049] 11 is a cross-sectional view of semiconductor package 200 at various stages of fabrication in which first semiconductor die 250 is bonded to semiconductor wafer 1100, which may also include multiple second semiconductor dies, according to various embodiments. For clarity, the second semiconductor dies bonded, attached, or integrated with semiconductor wafer 1100 are not shown, but it should be understood that each such second semiconductor die is substantially similar to first semiconductor die 250. For example, each second semiconductor die may have a hybrid bonding surface (e.g., a combination of dielectric and metallic materials), which collectively form bonding surface 1150. Thus, bonding surface 1050 and bonding surface 1150 may be connected (bonded) to each other by a hybrid bonding process.

[0050] In the foregoing description, specific details have been set forth, such as the particular configuration of the processing system and a description of the various components and processes used in the system. However, it should be understood that the technology herein may be practiced in other embodiments that deviate from these specific details, and that such details are for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numerical values, materials, and configurations have been set forth to provide a thorough understanding. However, embodiments may be practiced without such specific details. Components having substantially the same functional structure are designated by similar reference numerals, and therefore, some redundant description may be omitted.

[0051] To facilitate understanding of various embodiments, various techniques have been described as multiple separate operations. The order of description should not be construed as to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The operations described may be performed in a different order than in the described embodiments. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0052] As used herein, "substrate" or "target substrate" generally refers to an object to be processed in accordance with the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer, e.g., a thin film, on or overlying the base substrate structure. Thus, substrate is not limited to any particular base structure, underlying or overlying layer, patterned or unpatterned, but rather is intended to include any such layer or base structure, and any combination of layers and / or base structures. While the present specification may refer to particular types of substrates, this is for illustrative purposes only.

[0053] Those skilled in the art will appreciate that many variations can be made in the operation of the techniques described above while still achieving the same objectives of the present invention. Such variations are intended to be within the scope of the present disclosure. Accordingly, the above description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the present invention are presented in the following claims.

Claims

1. 1. A method for manufacturing a semiconductor package, comprising: providing a first semiconductor die including a plurality of metallization layers; applying a barrier layer on top of the metallization layer; sequentially overlaying the barrier layer with a stop layer and a laser lift-off layer; attaching a first side of the first semiconductor die to a first wafer through at least the laser lift-off layer; attaching a second side of the first semiconductor die to a second wafer; removing the first wafer from the first semiconductor die through the laser lift-off layer; forming a plurality of connectors on the first side of the first semiconductor die and electrically coupling to the top metallization layer; bonding the first semiconductor die to a third wafer containing a second semiconductor die; A method comprising:

2. The method of claim 1 , wherein the second semiconductor die includes a plurality of second metallization layers and a plurality of second connectors.

3. 3. The method of claim 2, wherein bonding the first semiconductor die to a third wafer includes connecting at least one connector of the plurality of connectors to a corresponding one of the plurality of second connectors.

4. 2. The method of claim 1, further comprising, prior to forming the plurality of connectors, forming a plurality of vias extending through the barrier layer and contacting the top metallization layer, each of the plurality of vias being contacted to a corresponding one of the plurality of connectors.

5. 10. The method of claim 1, wherein removing the first wafer further comprises applying a laser from the first side of the first semiconductor die to cause thermochemical dissociation of the laser lift-off layer.

6. 6. The method of claim 5, further comprising polishing away any remaining portions of the laser lift-off layer until the stop layer is exposed.

7. The step of attaching the second side of the first semiconductor die to a second wafer further includes: forming a first bonding layer on the second side of the first semiconductor die; planarizing the first bonding layer using a laser; forming a second bonding layer on the second wafer; bonding the first bonding layer to the second bonding layer; 2. The method of claim 1, comprising:

8. 8. The method of claim 7, wherein forming a first bonding layer, planarizing the first bonding layer, and bonding the first bonding layer to the second bonding layer are each performed at an elevated temperature.

9. 10. The method of claim 1, wherein the steps of attaching a first side of the first semiconductor die to a first wafer and removing the first wafer from the first semiconductor die are each performed at an elevated temperature.

10. 10. The method of claim 1, wherein forming a plurality of connectors on the first side of the first semiconductor die is performed at a temperature of about 250°C or less.

11. 1. A method for manufacturing a semiconductor package, comprising: bonding a plurality of semiconductor dies to a first wafer on their respective first sides; bonding the plurality of semiconductor dies on their second sides to a second wafer; separating the first wafer from the plurality of semiconductor dies; forming a plurality of first connectors in electrical contact with the plurality of semiconductor dies disposed on the second wafer; bonding the plurality of semiconductor dies to the third wafer by connecting the plurality of first connectors to a plurality of second connectors disposed on the third wafer, respectively; A method comprising:

12. 12. The method of claim 11 , wherein forming the plurality of first connectors is performed after any of bonding the plurality of semiconductor dies to a first wafer, bonding the plurality of semiconductor dies to a second wafer, or separating the first wafer from the plurality of semiconductor dies.

13. 13. The method of claim 12, wherein each of the steps of bonding the plurality of semiconductor dies to a first wafer, bonding the plurality of semiconductor dies to a second wafer, and separating the first wafer from the plurality of semiconductor dies is performed at an elevated temperature.

14. 12. The method of claim 11, wherein separating the first wafer from the plurality of semiconductor dies further comprises applying a laser through the first wafer to the first sides of the semiconductor dies.

15. Prior to the step of forming the plurality of first connectors, each of the semiconductor dies comprises: multiple metallization layers; a barrier layer completely overlying an uppermost layer of said plurality of metallization layers; a dielectric layer overlying the barrier layer; a stop layer overlying the dielectric layer; and a laser lift-off layer overlying the stop layer; 12. The method of claim 11, comprising:

16. following the step of separating the first wafer from the plurality of semiconductor dies, polishing the first side of the semiconductor die until the stop layer of at least one of the semiconductor die is exposed; forming a plurality of vias extending through the barrier layer and the dielectric layer; and The method of claim 15 , wherein the plurality of first connectors are each electrically coupled to the top metallization layer through the plurality of vias.

17. 12. The method of claim 11, wherein the step of bonding the plurality of semiconductor dies to a third wafer is performed by a hybrid bonding technique.

18. 1. A method for manufacturing a semiconductor package, comprising: providing a plurality of semiconductor dies, each of the plurality of semiconductor dies including, on a first side, a plurality of metallization layers, a dielectric layer completely overlying a top layer of the metallization layers, a stop layer overlying the dielectric layer, and a laser lift-off layer overlying the stop layer; bonding the plurality of semiconductor dies to a first wafer using the first sides of each; bonding the plurality of semiconductor dies to a second wafer using their second sides; separating the first wafer from the plurality of semiconductor dies based on generating thermochemical dissociation of the laser lift-off layer of each of the plurality of semiconductor dies; forming a plurality of vias, each extending through the dielectric layer and contacting the top metallization layer; forming a plurality of first connectors, each of which contacts the plurality of vias; bonding the plurality of semiconductor dies to the third wafer by connecting the plurality of first connectors to a plurality of second connectors disposed on the third wafer, respectively; A method comprising:

19. 20. The method of claim 18, wherein each of the steps of bonding the plurality of semiconductor dies to a first wafer, bonding the plurality of semiconductor dies to a second wafer, and separating the first wafer from the plurality of semiconductor dies is performed at an elevated temperature.

20. 20. The method of claim 18, wherein each of the steps of forming the plurality of vias and forming the plurality of first connectors is performed at a temperature of about 250°C or less.

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