New package substrate with interposer function and its manufacturing method

Abstract

The present invention relates to a new type of package substrate with interposer functionality and a manufacturing method thereof. Specifically, the new type of package substrate with interposer functionality includes a package substrate including substrate wiring and an interposer layer integrally integrated on the package substrate. Accordingly, fine wiring is provided on and / or within the interposer layer. If necessary, the fine wiring is electrically connected to the substrate wiring of the package substrate to establish electrical connection between the package substrate and a bare chip attached to the interposer layer. In this way, the interposer layer directly interconnects the bare chip and the new type of package substrate of the present invention, thereby achieving the function of an interposer in the conventional sense. The present application also discloses a manufacturing method for the new type of package substrate with interposer functionality.

Description

[Technical Field]

[0001] The present invention relates to the field of integrated circuit (IC) package substrates. Specifically, the present invention relates to the fabrication of a new type of package substrate that has multiple layers of finer wiring and functions as an interposer by using photosensitive / non-photosensitive insulating materials as medium layers and metal materials such as copper as conductive lines. The present invention also relates to a method for fabricating this new type of package substrate. [Background technology]

[0002] Currently, conventional package substrates (also called carrier substrates) contain wiring with an accuracy of several microns to tens of microns, while chips, such as bare chips (or dies), contain nanometer-level wiring. To realize the electrical connection between the package substrate and the die, an interposer is usually used to realize the conversion connection function between wiring of different quantity levels. (Interposer) must be placed between the two.

[0003] Interposers, such as silicon interposers, play an important role as an intermediate layer for interconnections between dies and between dies and package substrates, connecting the wiring on the dies to the wiring on the package substrate. To achieve this, the interposer must have silicon through-holes (TSVs) for fine wiring and substrate connection (see Figure 1). However, the TSV process is not only expensive, but also expensive because the interposer's substrate layer is fabricated from silicon wafers (or glass). Furthermore, because it is fabricated using semiconductor wafer equipment, there are size limitations on the silicon interposer, making it impossible to fabricate one with a relatively large size. These issues are hindering the further application of interposers.

[0004] To address the technical limitations and high cost of silicon interposers, Intel has proposed EMIB (Embedded Multi-Die Interconnect Bridge) technology, which realizes the relatively narrow linewidth of die-die bridging with a single relatively small silicon bridge, which is embedded in the substrate (see Figure 2). Compared to silicon interposers, the EMIB silicon bridge has reduced dimensions, reduced costs, and improved yields. However, this technology requires an additional process of embedding the EMIB silicon bridge in the substrate, and the silicon bridge is still manufactured using the semiconductor wafer process, so there are still issues that need to be improved in terms of cost and yield. Summary of the Invention [Problem to be solved by the invention]

[0005] To better solve the problems of silicon interposers and silicon bridges, provide greater design flexibility for interconnections between dies and package substrates, and between dies, and to increase the wiring of package substrate wiring to finer areas to meet future needs for finer wiring packaging, the present invention provides a new type of package substrate with interposer functionality. Such a substrate does not require connections via a separate interposer or silicon bridge, but directly connects to one or more dies, and allows the line width and spacing of the substrate to be increased to the submicron level. Specifically, according to the present invention, the functionality of a silicon interposer or silicon bridge can be achieved using conventional substrate materials, such as BF (e.g., ABF, NBF, etc.), BT, FR4, etc., without using a silicon wafer (or glass). [Means for solving the problem]

[0006] In one embodiment, an insulating material paste, for example, a polyimide (PI) paste, is applied to a conventional substrate material such as BF, BT, or FR4, or an insulating material film, for example, a PI film, is pressed onto the substrate, and then the insulating material paste is subjected to photolithography. (Photolithography) By using the etching method, substrates with the ability to interconnect signals between chips and between chips are manufactured. Such substrates have ultra-fine line widths at the submicron level, meeting the high-precision needs of ICs and reducing the need for multiple interposer wiring and solder ball welding. The process is also advanced, meeting the requirements for shorter signal transmission distances in chipsets, high-speed signal transmission between multiple chips, high-speed signal transmission between the substrate and each chip, and low cost.

[0007] The present invention provides a method for manufacturing a new type of package substrate. First, a substrate having one or more layers, such as BT, BF, or FR4, is provided, and each layer of the substrate is provided with substrate wiring. Next, in the substrate with the substrate wiring, a PI paste is applied to a layer that functions to connect chips to the substrate or to interconnect chips, or a PI film is pressed onto the substrate to provide one or more PI film layers to form an interposer layer. Thus, the interposer layer and the package substrate integrated therewith together constitute the new type of package substrate of the present invention. Optionally, the interposer layer may be the top layer, the bottom layer, the middle layer, or a combination thereof. Wiring with a line width of several hundred nanometers or more according to needs, and vias for interconnection, are formed in the interposer layer. Because the wiring is already very fine, a fully additive method is used here. The seed layer of the fully or semi-additive process may be fabricated by chemical copper plating, sputtering, or ion implantation plating. When there is a problem with the bonding strength between the copper wiring and the underlying substrate, it is preferable to process it by ion implantation plating, which has a unique advantage in terms of bonding strength, or the seed layer is preferably processed by ion implantation plating. Finally, after the necessary wiring layers and vias are completed, the new package substrate of the present invention is finally soldered to a chip, such as a die.Without changing the manufacturing process of the conventional substrate, the present invention improves wiring capacity performance and provides interposer functions, while also providing a manufacturing method that is simpler, more reliable, and more advanced than the conventional interposer process, replacing expensive silicon wafers.

[0008] Meanwhile, the present invention also provides a new package substrate processing method and structure. Specifically, by eliminating the use of a conventional silicon substrate, the processing method of the present invention eliminates at least one solder ball welding step and reduces signal transmission paths, thereby achieving or improving higher signal transmission speeds and lower signal loss compared to conventional chipsets. Furthermore, by drilling grooves and / or holes in the interposer layer, the present invention combines the RDL (redistributed layer) process with high-precision lithography and etching processes to produce substrates with extremely fine wiring. This allows the RDL process to be directly used on a standard substrate to fabricate the interposer functional layer, thereby increasing the linewidth in the package substrate industry to the hundreds of nanometer level, meeting the trend toward finer substrate linewidths and addressing the issue of conventional package substrates stagnating at linewidths of a few microns. Compared to conventional silicon wafer interposer processes, the present invention is more economical.

[0009] According to the present invention, a new type of package substrate with an interposer function is provided. The new type of package substrate includes a package substrate including substrate wiring and an interposer layer integrally integrated with the package substrate, with fine wiring provided on and / or within the interposer layer. Here, the fine wiring of the interposer layer is electrically connected to the substrate wiring of the package substrate to establish electrical connection between the package substrate and a chip device attached to the interposer layer. In one embodiment, the interposer layer includes a photosensitive PI adhesive film or a photosensitive PI paste. In one embodiment, the interposer layer includes a non-photosensitive PI adhesive film or a non-photosensitive PI paste. In one embodiment, the package substrate is made of one or more materials selected from the group consisting of BF, BT, and FR4. In one embodiment, the interposer layer includes grooves and / or holes for forming connecting wiring.

[0010] According to the present invention, there is further provided a method for manufacturing a new type of package substrate having an interposer function, the method comprising: providing a package substrate including substrate traces; providing a photosensitive PI film layer on a surface of the package substrate; forming vias and gaps in the photosensitive PI film layer by exposure and development; forming a conductive seed layer on the surface of the photosensitive PI film layer, in the vias and in the line gaps, thereby obtaining a pre-packaged substrate; applying a dry film or photoresist to the surface of the prepackaged substrate to form a wiring pattern, exposing both the locations where via filling and wiring placement are required; performing an electroplating process on the pre-packaged substrate so that an electroplated layer covers the via filling and wiring placement locations; stripping the dry film or photoresist from the pre-packaged substrate and performing flash etching to remove the exposed portions of the conductive seed layer, thereby achieving interconnection between the wiring of the photosensitive PI film layer and the substrate wiring of the package substrate.

[0011] In one embodiment, the steps of providing a photosensitive PI film layer, stripping the dry film or photoresist, and performing flash etching are repeated one or more times to form an interposer layer of the new package substrate. In one embodiment, the interposer layer forms an interposer functional layer including one or more layers of fine wiring. In one embodiment, the thickness of the conductive seed layer is 80 nm to 2000 nm.

[0012] According to the present invention, there is further provided a method for manufacturing a new type of package substrate having an interposer function, the method comprising: providing a package substrate including substrate traces; providing a non-photosensitive PI film layer on a surface of the package substrate; applying a first dry film or photoresist to the non-photosensitive PI film layer, and then exposing and developing the first dry film or photoresist to form vias and gaps; etching and removing the non-photosensitive PI film layer at locations not protected by the first dry film or photoresist; removing the first dry film or photoresist on the non-photosensitive PI film layer using a stripping process; forming a conductive seed layer on the surface of the non-photosensitive PI film layer, in the vias and in the line gaps, thereby obtaining a pre-packaged substrate; applying a second dry film or photoresist to the surface of the prepackaged substrate to expose the areas where via filling and wiring placement are required, and forming a pattern by exposure and development; performing an electroplating process on the pre-packaged substrate so that an electroplated layer covers the via filling and wiring placement locations; stripping the second dry film or photoresist from the pre-packaged substrate and performing flash etching to remove the exposed portions of the conductive seed layer, thereby achieving interconnection between the wiring of the non-photosensitive PI film layer and the substrate wiring of the package substrate.

[0013] In one embodiment, the steps of providing a non-photosensitive PI film layer, stripping the second dry film or photoresist, and flash etching are repeated one or more times to form an interposer layer of the new package substrate. In one embodiment, the interposer layer forms an interposer functional layer including one or more layers of fine wiring. The conductive seed layer has a thickness of 80 nm to 2000 nm.

[0014] Variations and modifications to the above technical solutions are within the scope and spirit of the present invention and are further described herein. [Brief explanation of the drawings]

[0015] The present invention will be described in detail below with reference to the drawings and examples. The advantages and embodiments of the present invention will become clearer. The contents shown in the drawings are for the purpose of illustrating the present invention only and are not intended to limit the present invention in any way. The drawings are schematic and not drawn to scale. The drawings are as follows: [Figure 1] 1 is a schematic cross-sectional view showing a conventional technique for interconnecting dies and for interconnecting a die and a package substrate using a silicon interposer. [Figure 2] 1 is a schematic cross-sectional view showing a conventional technique for interconnecting dies and for interconnecting a die and a package substrate using an EMIB; [Figure 3] 1 is a schematic cross-sectional view showing a new type of package substrate having the function of an interposer according to one embodiment of the present invention. [Figure 4] 2A to 2C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a first embodiment of the present invention. [Figure 5] 2A to 2C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a first embodiment of the present invention. [Figure 6] 2A to 2C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a first embodiment of the present invention. [Figure 7] 2A to 2C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a first embodiment of the present invention. [Figure 8] 2A to 2C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a first embodiment of the present invention. [Figure 9] 2A to 2C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a first embodiment of the present invention. [Figure 10] 2A to 2C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a first embodiment of the present invention. [Figure 11] 5A to 5C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a second embodiment of the present invention. [Figure 12] 5A to 5C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a second embodiment of the present invention. [Figure 13] 5A to 5C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a second embodiment of the present invention. [Figure 14] 5A to 5C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a second embodiment of the present invention. [Figure 15] 5A to 5C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a second embodiment of the present invention. [Figure 16] 5A to 5C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a second embodiment of the present invention. [Figure 17] 5A to 5C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a second embodiment of the present invention. [Figure 18] 5A to 5C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a second embodiment of the present invention. [Figure 19] 5A to 5C are schematic cross-sectional views illustrating steps for manufacturing a new type of package substrate by a method according to a second embodiment of the present invention. [Figure 20] 1 is a flow diagram illustrating a method for manufacturing a new type of package substrate according to a first exemplary embodiment of the present invention. [Figure 21] FIG. 6 is a flow diagram illustrating a method for manufacturing a new type of package substrate according to a second exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] The present invention will now be described in detail with reference to embodiments thereof, one or more of which are illustrated in the drawings. Each embodiment is provided to illustrate, not limit, the invention. Indeed, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the invention. For example, features illustrated or described as part of one embodiment can be used in combination with another embodiment to yield still a further embodiment. It is therefore intended that the present invention include such modifications and variations as come within the scope of the appended claims and their equivalents.

[0017] 3 is a schematic cross-sectional view showing a new type of package substrate with an interposer function according to one embodiment of the present invention. The new type of package substrate mainly includes a package substrate 10 and an interposer layer 40 integrated with the package substrate 10. In one embodiment, the package substrate 10 is a laminated plate and includes one or more layers. In each layer of the substrate 10, hole processing, Copper plating by ion implantation plating (or chemical copper plating),Substrate wiring can be obtained on one or both sides by selectively performing processes such as copper electroplating and etching. Electrical interconnections of substrate wiring between layers of the substrate 10 may be formed as needed. Accordingly, the interposer layer 40 also includes one or more layers, each of which has fine wiring. If necessary, the fine wiring in the interposer layer 40 is electrically connected to the substrate wiring of the package substrate 10 to establish electrical connections between the package substrate 10 and bare chips attached to the interposer layer 40, such as the first die 1 and the second die 2. As a result, the interposer layer 40 serves as an intermediate layer between the package substrate 10 and Die 1, Die 2, and interconnects the package substrate 10, thereby achieving the traditional interposer function. In one embodiment, the interposer layer 40 includes an insulating material substrate. Preferably, the interposer layer is fabricated using a PI film layer as the insulating material substrate. Compared to other insulating materials, PI materials have a certain degree of fluidity and surface planarization function, which gives them the advantage of being able to manufacture finer wiring.

[0018] In one embodiment, Die1 and Die2 are each connected to the new package substrate, particularly the interposer layer 40, by a solder ball welding method. Preferably, the method used for opening the implanted solder balls may be the PI film opening method described herein. Optionally, solder ball welding may be performed using a conventional solder mask opening method. Optionally, the connection between Die1 and Die2 and the interposer layer 40 may be performed using a conventional solder mask opening method. , Gold ball (Au ball) A connection method using a conductive film having such properties, for example, a material having ACF characteristics, may also be used. This method is also widely used for interconnecting display module ICs or FPCs with components.

[0019] Although FIG. 3 shows the interconnection of two chip dies, this is merely exemplary. In practice, according to the present invention, a single chip die may be connected to a substrate, or multiple chip dies may be interconnected. Optionally, multiple chip dies of different types and different sizes may be interconnected. Optionally, both sides of a substrate may be connected to the chip die. Also, in FIG. 3, the chip die pins and the wiring of the substrate with conversion connection functions are exemplary, and they may have different densities and different sizes. Also, although FIG. 3 shows two similar chip dies, in reality, these chip dies may be of various types. For example, the chip dies may include, but are not limited to, any chip with a computing function, such as a CPU, GPU, or ASIC. If other interconnection needs exist, a chip die may not be used, and a different chipset or circuit board may be used accordingly.

[0020] Compared with the conventional substrate manufacturing process, the new package substrate of the present invention does not require a separate interposer or silicon bridge connection, but directly connects to the die, and the substrate line width and line spacing can be increased to the submicron level, thereby improving the wiring capacity performance of the new package substrate of the present invention, providing the functionality of an interposer, and eliminating the need for expensive silicon wafers.

[0021] Next, several examples of the manufacturing method for the new package substrate of the present invention will be described.

[0022] 20 is a flow chart showing a method for manufacturing a new type of package substrate according to a first exemplary embodiment of the present invention. The method for manufacturing this new type of package substrate includes the following steps: Step S00: providing a package substrate 10 including substrate wiring (not shown); Step S10: providing a photosensitive PI film layer 14 on the surface of the package substrate 10; Step S20: forming vias 42 and line gaps 44 in the photosensitive PI film layer 14 by exposure and development, and then curing the film to fix the shape; Step S30: forming a conductive seed layer 46 on the surface of the photosensitive PI film layer 14, in the vias 42 and in the line gaps 44, thereby obtaining a pre-packaged substrate; Step S40: applying a dry film or photoresist 48 to the surface of the prepackaged substrate to expose the positions where via filling and wiring placement are required, and forming a pattern by exposure and development; Step S50: performing an electroplating process on the developed pre-packaged substrate so that an electroplated layer 50 covers the locations where via filling and wiring placement are required; Step S55: stripping the dry film or photoresist 48 from the electroplated prepackaged substrate, and performing flash etching to remove a portion of the conductive seed layer 46 to realize interconnections between the wiring of the photosensitive PI film layer 14 and the underlying substrate wiring; Step S10 to step S55 may be repeated one or more times to provide one or more photosensitive PI film layers 14 to form interposer layers 40, thereby manufacturing a new type of package substrate with chipset interconnection functions.

[0023] Optionally, after step S60, layers may be added onto the interposer layer 40 of the resulting new package substrate to provide one or more additional layers of substrate wiring.

[0024] In step S00, a package substrate 10 including board wiring (not shown) is provided. The package substrate 10 is a laminate and includes one or more layers. In each layer of the substrate 10, board wiring is selectively printed on one or both sides. If necessary, the board wiring between each layer of the substrate 10 may be electrically interconnected. The package substrate 10 and the board wiring fabricated thereon are fabricated using conventional board manufacturing processes, which will not be described here for the sake of brevity.

[0025] In step S10, a photosensitive PI film layer 14 is provided on the surface of the package substrate 10. Exemplarily, this surface refers to the surface of the package substrate 10 that will typically be welded to a chip, such as the top surface, bottom surface, or both. FIG. 4 is a schematic cross-sectional view of a completed package substrate with a photosensitive PI film layer 14 applied thereto, according to a typical manufacturing process of one embodiment of the present invention. Herein, the term "photosensitive PI film layer" refers to a photosensitive insulating material substrate on which an interposer layer 40 is formed, including, but not limited to, a photosensitive PI film layer, such as a PIC adhesive film or PSPI paste. In one embodiment, providing the photosensitive PI film layer 14 may involve thermocompression bonding (e.g., vacuum thermocompression bonding) of the photosensitive PI film onto the surface of the package substrate 10. The photosensitive PI film is a thermocompression-bondable dry film material, such as a PIC adhesive film. In one embodiment, the photosensitive PI film can be attached to the surface of the substrate after exposure, development, and thermal drying. However, if the analytical characteristics of the photosensitive PI film do not satisfy the exposure analytical capability, a wiring having the required resolution manufactured according to the method for manufacturing a new package substrate according to a second exemplary embodiment of the present invention, which will be described later, may be used. Optionally, to provide the photosensitive PI film layer 14, a photosensitive PI paste may be directly applied to the surface of the package substrate 10. Photosensitive PI paste, such as PSPI paste, has properties of being coatable and dryable. In one embodiment, the photosensitive PI paste can be attached to the substrate surface after exposure, development, and thermal drying. However, if the analytical characteristics of the photosensitive PI paste do not satisfy the exposure analytical capability, a wiring having the required resolution manufactured according to the method for manufacturing a new package substrate according to a second exemplary embodiment of the present invention, which will be described later, may be used. Preferably, a thermal drying process may be used to promote the formation of the photosensitive PI film layer 14, if necessary.

[0026] In step S20, the photosensitive PI film layer 14 is exposed and developed to form vias 42 and line gaps 44, and then cured to fix the shape. FIG. 5 is a schematic cross-sectional view of the photosensitive PI film layer 14 on the package substrate 10 after exposure, development, and curing according to one embodiment of the present invention. Exemplarily, the photosensitive PI film layer 14 is directly exposed using a film, a mask, or LDI. After exposure, the photosensitive PI film layer 14 is developed to form vias 42 with diameters of 1 μm or more and line gaps 44 with dimensions of several hundred nanometers or more. In one embodiment, the shape of the photosensitive PI film layer may be fixed by high-temperature curing. For example, in one embodiment, the photosensitive PI film layer 14 is dried and cured, which causes the photosensitive PI material to undergo a polymerization reaction, thereby ensuring the stability of its properties.

[0027] In step S30, a conductive seed layer 46 is formed on the surface of the photosensitive PI film layer 14, in the vias 42, and in the line gaps 44, thereby obtaining a pre-packaged substrate. FIG. 6 is a schematic cross-sectional view of forming a conductive seed layer 46 on a package substrate 10 according to one embodiment of the present invention. For example, the conductive seed layer 46 is formed on the surface of the photosensitive PI film layer 14, in the vias 42, and in the line gaps 44 by chemical copper plating, thereby obtaining a pre-packaged substrate. In another embodiment, sputtering is used. or ion implantation plating The conductive seed layer 46 is formed on the photosensitive PI film layer 14, in the vias 42, and in the line gaps 44 using the above method. In another embodiment, the conductive seed layer 46 is formed on the photosensitive PI film layer 14, in the vias 42, and in the line gaps 44 using an ion implantation plating method. Preferably, the thickness of the conductive seed layer is in the range of 80 nm to 2000 nm. In the present invention, when mass production is difficult due to roughness or insufficient adhesive strength of the material, the ion implantation plating method may be preferably used.

[0028] In step S40, a dry film or photoresist 48 is applied to the surface of the prepackaged substrate to expose the locations where via filling and wiring placement are required, and a pattern is formed by an exposure and development method. FIG. 7 is a schematic cross-sectional view of a prepackaged substrate after applying a dry film or photoresist 48 to the surface, exposing it, and developing it according to one embodiment of the present invention. Exemplarily, a dry film is attached to the surface of the prepackaged substrate, and a wiring pattern is formed by an exposure and development method. Optionally, the wiring pattern may be formed by applying a liquid photoresist to the surface of the prepackaged substrate. The wiring pattern thus formed is then exposed at the locations where via filling and wiring placement are required for electroplating.

[0029] In step S50, the developed prepackaged substrate is subjected to an electroplating process so that the electroplated layer 50 covers the areas where via filling and wiring placement are required. Preferably, the prepackaged substrate needs to be pretreated before the electroplating process. Pretreatment methods may include surface cleaning, such as wiping the substrate surface with alcohol-soaked gauze to remove dirt, or immersing the substrate in a cleaning solution for ultrasonic cleaning. FIG. 8 is a schematic cross-sectional view of forming an electroplated layer 50 on a prepackaged substrate according to one embodiment of the present invention. Illustratively, the prepackaged substrate with an exposed wiring pattern is electroplated, e.g., copper-plated, to cover the exposed wiring pattern with the electroplated layer 50, thereby increasing the thickness of the electroplated layer 50 to the required thickness. In one embodiment of the present invention, if the uniformity of the electroplated copper thickness does not meet product requirements, polishing may be performed to achieve a uniform copper thickness. Optionally, this polishing process or step may be performed after the electroplating process and before the stripping step described below.

[0030] In step S55, the dry film or photoresist 48 is stripped from the electroplated prepackaged substrate, and flash etching is performed to remove portions of the conductive seed layer 46, thereby achieving interconnections between the wiring in the photosensitive PI film layer 14 and the underlying substrate wiring. FIG. 9 is a schematic cross-sectional view of a prepackaged substrate after stripping and flash etching according to one embodiment of the present invention. Illustratively, an alkaline or organic stripping solution is used to strip the dry film or photoresist 48 from the electroplated prepackaged substrate. Furthermore, flash etching is used to etch the thicker conductive seed layer 46 that has not been electroplated, resulting in the desired pattern. This allows interconnections between the desired pattern of wiring and the underlying holes.

[0031] In step S60, steps S10 to S55 are repeated one or more times to provide one or more photosensitive PI film layers 14 to form an interposer layer 40, thereby manufacturing a new package substrate with a chipset interconnection function. FIG. 10 is a schematic cross-sectional view of a new package substrate according to one embodiment of the present invention. As shown in FIG. 10, the new package substrate includes a package substrate 10 and an interposer layer 40 integrated therewith. Illustratively, the interposer layer 40 includes two layers of fine wiring to achieve the interposer function. Of course, if necessary, the interposer layer 40 may include one or more layers of fine wiring to achieve the interposer function. Furthermore, as shown in FIG. 3, the interposer layer 40 serves as an intermediate layer between the die and the package substrate, interconnecting the die and the package substrate, thereby achieving the conventional interposer function.

[0032] The thickness of the conductive seed layer is strongly related to the pre-treatment before electroplating in the subsequent manufacturing process, the electroplating process, and flash etching. In one embodiment, the thickness of the conductive seed layer of the present invention is in the range of 80 nm to 2000 nm. If the thickness of the conductive seed layer is too thin, it will be etched by the electroplating pre-treatment or electroplating process, and will not be able to achieve the conductive effect of the electroplating process. If the thickness of the conductive seed layer is too thick, a large amount of flash etching will be required in the end, and the line width and line spacing will not be as expected. Since the thickness of the conductive seed layer is strongly related to the three steps of the electroplating pre-treatment, electroplating, and flash etching, the thickness is limited to the range of 80 nm to 2000 nm. Preferably, the thickness of the conductive seed layer of the present invention is 200 The metal forming the conductive seed layer may be one or more of Cu, Ta, TaN / Ta alloy, TiN, TiW, Cr, Ti, Mo, MoTi alloy, Ni, NiCu, or a combination thereof. In one embodiment, when a chemical copper plating method is used as a method for forming the conductive seed layer, preferably, a single-layer conductive seed layer may be formed using metallic Cu. In another embodiment, the method for forming the conductive seed layer is Ion implantation plating method Alternatively, if other dry plating methods are used, metals other than Cu may be used as the underlayer metal in combination with Cu to form a bilayer structure of the conductive seed layer. Preferably, in one embodiment of the present invention, a bilayer structure of a bottom layer Ni and a top layer Cu is used to form the conductive seed layer, and the total thickness is 200 It may be nm. Considering the cost of ion implantation plating, it is recommended to deposit a relatively thin Ni / Cu layer to a thickness of 80 nm and then electroplat it to a thickness of 200 nm. The thickness can be increased to up to 100 nm, and can be adjusted depending on production capacity, cost, and process window.

[0033] 21 is a flow chart showing a method for manufacturing a new type of package substrate according to a second exemplary embodiment of the present invention. Step S000 provides a package substrate 100 including substrate wiring (not shown); Step S100: providing a non-photosensitive PI film layer 140 on the surface of the package substrate 100; Step S200: applying a dry film or photoresist 480 to the non-photosensitive PI film layer 140, and then performing exposure and development to form vias 420 and line gaps 440; Step S300: completely etching the non-photosensitive PI film layer 140 at locations not protected by the dry film or photoresist 480 using dry etching; Step S350: removing the dry film or photoresist 480 on the non-photosensitive PI film layer 140 using a stripping process; Step S400: forming a conductive seed layer 460 on the surface of the non-photosensitive PI film layer 140, in the vias 420 and in the line gaps 440, thereby obtaining a pre-packaged substrate; Step S500: applying a dry film or photoresist 580 to the surface of the prepackaged substrate to expose the positions where via filling and wiring placement are required, and forming a pattern by exposure and development; Step S600: performing an electroplating process on the developed pre-packaged substrate so that an electroplated layer 500 covers the locations where via filling and wiring placement are required; Step S650: stripping the dry film or photoresist 580 from the electroplated pre-packaged substrate, and performing flash etching to remove a portion of the conductive seed layer 460 to realize interconnections between the wiring of the non-photosensitive PI film layer 140 and the underlying substrate wiring; Steps S100 to S650 may be repeated one or more times to provide one or more non-photosensitive PI film layers 140 to form an interposer layer 400, thereby manufacturing a new type of package substrate with chipset interconnection functions.

[0034] Optionally, after step S700, layers may be added to the resulting new package substrate on top of interposer layer 400 to provide one or more additional layers of substrate wiring.

[0035] In step S000, a package substrate 100 including substrate wiring (not shown) is provided. In this specification, the package substrate 100 is similar to the package substrate 10 described above, and for the sake of brevity, a description thereof will not be repeated here.

[0036] In step S100, a non-photosensitive PI film layer 140 is provided on the surface of the package substrate 100. Exemplarily, this surface refers to the surface of the package substrate 100 that is typically to be welded to a chip, such as the top surface, bottom surface, or both. FIG. 11 is a schematic cross-sectional view of a completed package substrate with the non-photosensitive PI film layer 140 applied thereto through a typical manufacturing process according to one embodiment of the present invention. In one embodiment, providing the non-photosensitive PI film layer 140 may involve thermocompression bonding (e.g., vacuum thermocompression bonding) of the non-photosensitive PI film onto the surface of the package substrate 100. The non-photosensitive PI film is a thermocompression-bondable dry film material, such as a pressure-bondable non-photosensitive PI material. In one embodiment, the non-photosensitive PI film can be adhered to the surface of the substrate after being thermally dried. Optionally, providing the non-photosensitive PI film layer 140 may involve applying a non-photosensitive coating film to the surface of the package substrate 100. The non-photosensitive coating film, such as a non-photosensitive PI paste, has properties of being coatable and dryable. In one embodiment, the non-photosensitive PI paste can be applied to the surface of the substrate after being thermally dried. In the present invention, the PI film layers 14 and 140 are The adhesive film and paste described herein are not limited to photosensitive acrylic adhesive films and adhesive films. These materials are also widely used as planarization layer materials for display panels. Other coatable and curable organic materials may also be used, such as Ajinomoto build-up film (ABF), ABF-based materials, bismaleimide triazine (BT), BT-based materials, and p-phenylene benzobisoxazole (PBO), which are used as media layers.

[0037] In step S200, a dry film or photoresist 480 is applied to the non-photosensitive PI film layer 140, and then exposed and developed to form vias 420 and line gaps 440. Figure 12 is a schematic cross-sectional view of the non-photosensitive PI film layer 140 on the package substrate 100 after it has been exposed and developed according to one embodiment of the present invention. Exemplarily, a photoresist is applied to the non-photosensitive PI film layer 140, or a dry film is attached, and then exposure is performed. After exposure, the photoresist or dry film is subjected to a development process, thereby forming vias 420 with diameters of 1 μm or more and line gaps 440 with dimensions of several hundred nanometers or more.

[0038] In step S300, dry etching is used to completely etch away the non-photosensitive PI film layer 140 at locations not protected by the dry film or photoresist 480. In one embodiment, carbon tetrafluoride (CF4) and oxygen (O2) may be used as etching gases for the dry etching. FIG. 13 is a schematic cross-sectional view of the non-photosensitive PI film layer 140 on the package substrate 100 after dry etching according to one embodiment of the present invention. As shown in FIG. 13, the non-photosensitive PI film layer 140 at locations not protected by the dry film or photoresist has been completely etched away, exposing a portion of the surface of the package substrate 100. In other words, the vias 420 and the line gaps 440 have been etched deep to the surface of the package substrate 100. In the present invention, the PI etching is not limited to dry etching. Optionally, wet etching may be used to remove the non-photosensitive PI film layer 140 under conditions that allow for precision.

[0039] In step S350, a stripping process is used to remove the dry film or photoresist 480 on the non-photosensitive PI film layer 140. In one embodiment, the stripping process is performed using NaOH and an organic stripping solution selected depending on the type of dry film or photoresist. FIG. 14 is a schematic cross-sectional view of the non-photosensitive PI film layer 140 after being stripped from the dry film or photoresist 480 according to one embodiment of the present invention. As shown in FIG. 14, the dry film or photoresist covering the photosensitive PI film layer 140 has already been removed. As shown in FIG. 5, the non-photosensitive PI film layer 140 has vias 420 with diameters of 1 μm or more and line gaps 440 with dimensions of several hundred nanometers or more formed therein.

[0040] In step S400, a conductive seed layer 460 is formed on the surface of the non-photosensitive PI film layer 140, in the vias 420, and in the line gaps 440, thereby obtaining a pre-packaged substrate. FIG. 15 is a schematic cross-sectional view showing the conductive seed layer 460 formed on the non-photosensitive PI film layer 140 on the package substrate 100 according to one embodiment of the present invention. For example, the conductive seed layer 460 is formed on the surface of the non-photosensitive PI film layer 140, in the vias 420, and in the line gaps 440 by chemical copper plating, thereby obtaining a pre-packaged substrate. In another embodiment, the conductive seed layer 460 is formed on the non-photosensitive PI film layer 140 in the vias 420 and in the line gaps 440 by sputtering. In another embodiment, the conductive seed layer 460 is formed on the non-photosensitive PI film layer 140 in the vias 420 and in the line gaps 440 by ion implantation plating. Preferably, the thickness of the conductive seed layer is in the range of 80 nm to 2000 nm.

[0041] In step S500, a dry film or photoresist 580 is applied to the surface of the prepackaged substrate to expose the locations where via filling and wiring placement are required, and a pattern is formed by an exposure and development method. FIG. 16 is a schematic cross-sectional view of a prepackaged substrate after applying a dry film or photoresist 480 to the surface, exposing, and developing the dry film or photoresist 480 according to one embodiment of the present invention. Exemplarily, a dry film is attached to the surface of the prepackaged substrate, and a wiring pattern is formed by an exposure and development method. Optionally, this wiring pattern may be formed by applying a liquid photoresist to the surface of the prepackaged substrate. The wiring pattern thus formed is exposed in the locations where via filling and wiring placement are required for electroplating.

[0042] In step S600, the developed prepackaged substrate is subjected to an electroplating process so that the electroplated layer 500 covers the areas where via filling and wiring placement are required. Preferably, the prepackaged substrate needs to be pretreated before the electroplating process. Pretreatment methods may include surface cleaning, such as wiping the substrate surface with alcohol-soaked gauze to remove dirt, or ultrasonically cleaning the substrate by immersing it in a cleaning solution. FIG. 17 is a schematic cross-sectional view illustrating the formation of an electroplated layer 500 on a prepackaged substrate according to one embodiment of the present invention. Illustratively, the prepackaged substrate with an exposed wiring pattern is electroplated, e.g., copper-plated, to cover the exposed wiring pattern with the electroplated layer 500, thereby increasing the thickness of the electroplated layer 500 to the required thickness. In one embodiment of the present invention, if the uniformity of the electroplated copper thickness does not meet product requirements, polishing may be performed to achieve a uniform copper thickness. Optionally, this polishing process or step may be performed after the electroplating process and before the stripping step described below.

[0043] In step S650, the dry film or photoresist 580 is stripped from the electroplated prepackaged substrate, and flash etching is performed to remove portions of the conductive seed layer 460, thereby achieving interconnections between the wiring in the non-photosensitive PI film layer 140 and the underlying substrate wiring. FIG. 18 is a schematic cross-sectional view of a prepackaged substrate after stripping and flash etching according to one embodiment of the present invention. Illustratively, an alkaline or organic stripping solution is used to strip the dry film or photoresist 580 from the electroplated prepackaged substrate. Furthermore, flash etching is used to etch the thicker conductive seed layer 460 that has not been electroplated, resulting in the desired pattern. This allows interconnections between the desired pattern of wiring and the underlying holes.

[0044] In step S700, steps S100 to S650 are repeated one or more times to provide one or more non-photosensitive PI film layers 140 to form an interposer layer 400, thereby manufacturing a new package substrate with a chipset interconnection function. FIG. 19 is a schematic cross-sectional view of a new package substrate according to one embodiment of the present invention. As shown in FIG. 19, the new package substrate includes a package substrate 100 and an interposer layer 400 integrated therewith. Illustratively, the interposer layer 400 includes two layers of fine wiring to achieve the interposer function. Of course, if necessary, the interposer layer 400 may include one or more layers of fine wiring to achieve the interposer function. Furthermore, as shown in FIG. 3, the interposer layer 40 serves as an intermediate layer between the die and the package substrate, interconnecting the die and the package substrate, thereby achieving the conventional interposer function.

[0045] It should be noted that the multiple layers of the substrate having the interconnection function of the chipset disclosed in the present invention are not limited to the last multiple layers of the substrate, but may be the first multiple layers, the middle multiple layers, or any multiple layers in the substrate as needed. In the present invention, only multiple layers having the function of a conventional interposer are described.

[0046] Compared with conventional methods that place wiring only on a PI film or other medium, the present invention allows wiring to be embedded in the middle of the PI film through openings in the PI film. This has the advantage of reducing the thickness of the product compared to conventional processes. Furthermore, the use of a PI material according to the present invention provides a certain degree of fluidity and surface planarization. This allows for the advantageous production of finer wiring.

[0047] The new package substrate of the present invention not only integrates the interposer and the substrate, but also reduces the number of times that the implanted solder balls need to be welded. Furthermore, the new package substrate of the present invention reduces signal loss and signal reflection during signal transmission, and also reduces the potential impact of alpha rays in the solder balls on high-frequency signals, greatly contributing to the transmission of high-frequency signals.

[0048] This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention. This includes making and using any device or system, and performing any combination of methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. To the extent that these other examples have structural elements that differ from the literal language of the claims, or include equivalent structural elements that differ substantially from the literal language of the claims, those other examples are deemed to be within the scope of the claims.

Claims

1. A new type of package substrate with an interposer function, a package substrate including substrate wiring; an interposer layer integrally integrated with the package substrate, wherein fine wiring is provided on and / or within the interposer layer; wherein the micro wiring of the interposer layer is electrically connected to the substrate wiring of the package substrate in order to establish electrical connection between the package substrate and the chip element attached to the interposer layer; New package substrate.

2. The interposer layer includes a photosensitive PI adhesive film or a photosensitive PI paste; The new package substrate according to claim 1.

3. The interposer layer comprises a non-photosensitive PI adhesive film or a non-photosensitive PI paste; The new package substrate according to claim 1.

4. The package substrate is made of one or more of BF, BT, and FR4. The new package substrate according to claim 1.

5. For the production of connecting wires, the interposer layer contains grooves and / or holes. The new package substrate according to claim 1.

6. A manufacturing method of a new type package substrate having an interposer function, the manufacturing method comprising: providing a package substrate including substrate traces; providing a photosensitive PI film layer on a surface of the package substrate; forming vias and line gaps in the photosensitive PI film layer by exposure and development; forming a conductive seed layer on the surface of the photosensitive PI film layer, in the vias and in the line gaps, thereby obtaining a pre-packaged substrate; applying a dry film or photoresist to the surface of the prepackaged substrate to form a wiring pattern, exposing both the locations where via filling and wiring placement are required; performing an electroplating process on the pre-packaged substrate so that an electroplated layer covers the via filling and wiring placement locations; stripping the dry film or photoresist from the pre-packaged substrate and performing flash etching to remove the exposed portion of the conductive seed layer, thereby achieving interconnection between the wiring of the photosensitive PI film layer and the substrate wiring of the package substrate; Manufacturing method.

7. Repeating the steps from providing one or more photosensitive PI film layers to stripping the dry film or photoresist and performing flash etching one or more times to form an interposer layer of the new package substrate; The method of claim 6.

8. The interposer layer forms an interposer functional layer including one or more layers of fine wiring. The method of claim 7.

9. the conductive seed layer has a thickness of 80 nm to 2000 nm; The method of claim 6.

10. A manufacturing method of a new type package substrate having an interposer function, the manufacturing method comprising: providing a package substrate including substrate traces; providing a non-photosensitive PI film layer on a surface of the package substrate; applying a first dry film or photoresist to the non-photosensitive PI film layer, and then exposing and developing the first dry film or photoresist to form vias and line gaps; etching and removing the non-photosensitive PI film layer at locations not protected by the first dry film or photoresist; removing the first dry film or photoresist on the non-photosensitive PI film layer using a stripping process; forming a conductive seed layer on the surface of the non-photosensitive PI film layer, in the vias and in the line gaps, thereby obtaining a pre-packaged substrate; applying a second dry film or photoresist to the surface of the prepackaged substrate to expose the areas where via filling and wiring placement are required, and forming a pattern by exposure and development; performing an electroplating process on the pre-packaged substrate so that an electroplated layer covers the via filling and wiring placement locations; stripping the second dry film or photoresist from the pre-packaged substrate and performing flash etching to remove the exposed portions of the conductive seed layer, thereby achieving interconnection between the wiring of the non-photosensitive PI film layer and the substrate wiring of the package substrate; Manufacturing method.

11. Repeating the steps from providing one or more non-photosensitive PI film layers to stripping the second dry film or photoresist and flash etching one or more times to provide one or more non-photosensitive PI film layers to form an interposer layer of the new package substrate; The method of claim 9.

12. The interposer layer forms an interposer functional layer including one or more layers of fine wiring. The method of claim 9.

13. the conductive seed layer has a thickness of 80 nm to 2000 nm; The method of claim 9.

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