Quantum computing system and error detection method

Abstract

The present invention discloses a quantum computing system and quantum error detection method for performing fault-tolerant quantum operations without the need for computationally intensive quantum error correction, provided by the detectability of certain logical errors in initialization, syndrome measurement, and state measurement. A quantum circuit of logical qubits is converted into an instruction set for execution of a quantum circuit of physical qubits. The instruction set includes a plurality of instruction blocks, each including at least one instruction for executing at least one quantum gate in the quantum circuit of n qubits by a quantum computing system. The quantum computing system performs fault-tolerant initialization of the logical states of k logical qubits using the quantum circuit of n qubits, a first ancillary quantum bit, and a quantum error detection code, and executes each instruction block of the plurality of instruction blocks in the quantum circuit of n physical qubits. After each instruction block, the quantum computing system performs fault-tolerant syndrome measurement of the stabilizer for the n physical qubits using the first ancillary quantum bit and the second ancillary quantum bit, respectively. After all instruction blocks of the plurality of instruction blocks have been applied to the n physical qubits, the quantum computing system performs fault-tolerant state measurements of each logical operator in Equation 1 using the first ancilla qubit and the second ancilla qubit by measuring the n physical qubits. If the measurement of either the first ancilla or the second ancilla indicates a failure during any of the initialization, syndrome measurement, or fault-tolerant steps of performing state measurements, the calculation result is discarded and the quantum operation is restarted.

Description

[Technical Field]

[0001] The present disclosure relates to quantum computing systems, e.g., hybrid computing devices including a combination of a classical binary computer connected to a quantum computer. Additionally, the present disclosure relates to methods of operating a quantum computing system, where operations are prepared by a classical computer and quantum operations are performed by the quantum computer. Additionally, the present disclosure relates to software products recorded on machine-readable media, where the software product includes program code executable to control the operation of a quantum computing system. [Background technology]

[0002] A long-standing problem in the development of quantum computers has been how to maintain quantum performance (e.g., maintaining quantum coherence) despite noise affecting the devices used to perform quantum operations, causing failures during processing. Quantum computers have recently become available as noisy intermediate-scale quantum (NISQ) devices, allowing classical computers to simulate quantum computing. A technical issue associated with NISQ devices is that the number of available qubits limits the available resources that can be allocated to protocols to mitigate the effects of errors introduced by noise. Summary of the Invention [Problem to be solved by the invention]

[0003] Various methods for detecting and correcting errors that occur when performing computations on NISQ devices have been proposed in the open scientific literature. However, despite recognition by some authors that quantum error correction is essential for fault tolerance, typical NISQ devices are not sufficiently advanced to continuously perform resource-intensive quantum error correction, preventing fully fault-tolerant systems. The traditional definition of fault tolerance is that a fault-tolerant circuit is one in which no single component, the failure of which would generate an undetectable logical error, exists. Traditionally, errors are characterized as unintended single-qubit Pauli gates, which are detected and corrected to maintain the quantum performance of noisy quantum computers. Existing quantum computers can implement quantum error correction protocols only for very few logical qubits and simple states due to the scalability and precision limitations of NISQ devices. Quantum algorithms must therefore be carefully constructed to take these limitations into account. [Means for solving the problem]

[0004] Disclosure Overview The present disclosure aims to provide a technical solution to the technical problem of implementing resource-consuming protocols to mitigate the impact of errors in NISQ devices with limited available resources. It is an object of the present disclosure to provide an improved, resource-efficient method for detecting the occurrence of errors when performing quantum operations using a quantum computing system, which may include a classical computer and a quantum computer. A first method involves efficient error detection combined with efficient error rejection (which may include simply discarding the results of the execution instance of the failed quantum circuit), allowing the quantum operation to be repeated until acceptable accuracy in the quantum operation is achieved. This can eliminate the need for computationally expensive error correction, at least for quantum computing systems with high-quality physical qubits, such as existing ion trap quantum computers. It is also an object of the present disclosure to provide a technical solution for an improved quantum computing system, including a classical computer and a quantum computer, that implements an improved method for detecting and rejecting errors that occur when performing quantum operations on quantum hardware. The inventors of the present invention have determined that detecting and efficiently rejecting quantum operation errors can provide a practically useful level of fault tolerance with greater computational efficiency than known methods of both error detection and correction. The present invention provides an encoding of logical qubits in a quantum circuit to actual physical qubits, allowing quantum error detection by measuring the physical qubits. It has been found that efficiently discarding erroneous partial results and then restarting the quantum operation is an efficient way to handle identified errors. This can provide an adequate level of quantum performance in the presence of noise, particularly when implemented in quantum computing systems using high-quality quantum circuits based on ion traps, and where initialization and syndrome measurement are fault-tolerant steps. In some embodiments, fault-tolerant initialization requires that an even number k of logical qubits be encoded onto n=k+2 physical qubits, where k is any even number k≧2. In some other embodiments, an odd number k of logical qubits are encoded onto an even number of physical qubits, including a redundant qubit d, which is used for circuit optimization. Logical operators then operate on the qubits without fault tolerance. Then, fault-tolerant syndrome measurements using two ancillaries and fault-tolerant measurements of all qubits are performed. This process allows for single-qubit error detection with only four qubits of overhead. The circuit is also fault-tolerant in the sense that a single fault does not cause an undetectable logical error. The present invention has the potential to make quantum computers or hybrid quantum-classical computer systems operate more reliably and efficiently. Furthermore, efficient detection and discarding of computational errors can be achieved by combining quantum operations with the repetition of quantum operations until the quantum operation error falls below an error threshold. The present invention trades the ability to perform all operations without error for reduced quantum resource requirements. Instead of performing all operations without error, some steps are performed in a non-fault-tolerant manner. This raises the question of how to select the non-fault-tolerant operations. Non-fault-tolerant operations can be implemented using a universal set of logical quantum gates. The inventors have recognized that the selection of an "iceberg" code for the error detection code offers advantages when implemented in devices with all-to-all connections between physical qubits and high-fidelity two-qubit interactions, such as in trapped ion quantum computers. Furthermore, trapped ion systems are typically excellent at performing intermediate circuit measurements and reinitialization of qubits, which are used to perform syndrome extraction operations during logical operations. Similarly, intermediate circuit syndrome extraction has proven advantageous not only in theory but also in practice, as it reduces the effects of noise. The present invention provides a method for performing quantum operations including quantum error detection, wherein a quantum error detection code is used to convert an operation defined by k logical qubits into an instruction set for executing a quantum circuit of n physical qubits, where n=k+2, and the quantum error detection code encodes the k logical qubits into n physical qubits, which have stabilizers for the physical qubits, and which have first and second ancilla qubits used for error detection. The method includes performing, by a quantum computing system, fault-tolerant initialization of the logical states of k logical qubits using a quantum circuit of n qubits, a first auxiliary quantum, and a quantum error detection code; executing, by the quantum computing system, instructions in a quantum circuit of n physical qubits to perform a computation; performing, by the quantum computing system, fault-tolerant syndrome measurements of a stabilizer for the n physical qubits using the first auxiliary quantum and the second auxiliary quantum; performing, by the quantum computing system, fault-tolerant state measurements of each logical operator by measuring the n physical qubits using the first ancillary qubit and the second ancillary qubit; and, in response to one of the syndrome measurement or the state measurement of the first ancillary qubit or the second ancillary qubit indicating a failure, abandoning the computation of the quantum circuit and restarting the quantum operation.

[0005] According to a first aspect of the present invention, there is provided a method of performing quantum operations including unitary operations of interest including quantum error detection, the method comprising: obtaining an approximation of a finite gate decomposition of a unitary operation of interest for a quantum circuit of k logical qubits; converting, using a quantum error detection code, a finite gate decomposition for a quantum circuit of k logical qubits into an instruction set for executing a quantum circuit of n physical qubits, where n=k+2 and the n physical qubits include physical qubit t and physical qubit b, and wherein the quantum error detection code is a stabilizer code that encodes the k logical qubits onto the n physical qubits and includes two stabilizers for the physical qubits; JPEG2025540634000002.jpg21118The logical qubit operator of the code JPEG2025540634000003.jpg1518 is JPEG2025540634000004.jpg19117, where: JPEG2025540634000005.jpg1421 is a Pauli X and Z single logical qubit operator for logical qubit q, where the set of instructions includes a plurality of instruction blocks, each instruction block including at least one instruction for executing, by a quantum computing system, at least one quantum gate in a quantum circuit of n qubits; performing, with the quantum computing system, fault-tolerant initialization of the logical states of the k logical qubits using the n qubit quantum circuit, the first ancilla qubit, and the quantum error detection code; executing, by the quantum computing system, each instruction block of the plurality of instruction blocks on a quantum circuit of n physical qubits; The quantum computing system calculates S for the n physical qubits using the first ancilla qubit and the second ancilla qubit, respectively. Z Stabilizer and S X performing a fault-tolerant syndrome measurement of the stabilizer; After all instruction blocks of the plurality of instruction blocks have been applied to the n physical qubits, the quantum computing system measures the n physical qubits using a first ancilla qubit and a second ancilla qubit to perform a logical operation on each of the n physical qubits. and performing fault-tolerant state measurement of JPEG2025540634000006.jpg11124; Based on a measurement of the first ancilla qubit or the second ancilla qubit indicating a failure during any of the fault-tolerant steps of performing initialization, syndrome measurement, or state measurement, the computation result is discarded and the quantum operation is restarted. A circuit or an operation performed by a circuit is fault tolerant if the failure of the circuit does not have a single component that produces an undetectable logic error. The quantum circuit for syndrome measurement may be based on a quantum error detection code. The quantum circuit for initialization may be based on a quantum error detection code. The quantum circuit for state measurement may be based on a quantum error detection code. Preferably, the quantum computing system is a trapped ion quantum computer with all-to-all connections between qubits. Preferably, the finite gate decomposition is composed of unitary gates of a universal gate set, the universal gate set including gates that can be encoded in physical qubits using only two-qubit Molmer-Sørensen gates and up to four Clifford group gates, and optionally the universal gate set includes global rotations on k or k-1 logical qubits. Preferably, the universal gate set includes only single-qubit logical rotations, two-qubit logical rotations, and global rotations for k or k-1 logical qubits. Preferably, each logical operator The fault-tolerant state measurement of JPEG2025540634000007.jpg1322 is S XMeasure the stabilizer, measure n physical qubits, and post-process the results to obtain S Z Stabilizers and logical operators After the last instruction block is executed by decoding JPEG2025540634000008.jpg1416, combined with the last syndrome measurement, the quantum computing system is configured to discard the calculation result and resume the quantum operation based on the decoded stabilizer value indicating a failure during the fault-tolerant step. According to a second aspect of the present invention, there is provided a system for performing quantum operations including unitary operations of interest including quantum error detection, said system comprising: Classical computing systems, a quantum computing system including k physical qubits, one physical qubit t, one physical qubit b, a first ancilla qubit, and a second ancilla qubit, the quantum computing system being configured to implement a quantum circuit for the k physical qubits, the physical qubit t, and the physical qubit b using the first ancilla qubit and the second ancilla qubit; The classical computing system comprises: configured to obtain an approximation of a finite gate decomposition of a unitary operation of interest for a quantum circuit of k logical qubits; and converting the finite gate decomposition for a quantum circuit of k logical qubits into an instruction set for executing the quantum circuit of the n physical qubits in the quantum computing system using a quantum error detection code, wherein the quantum error detection code encodes the k logical qubits into the n physical qubits and is configured to encode two stabilizers for the physical qubits. This is the stabilizer code containing JPEG2025540634000009.jpg20118, logical qubit operators of said quantum error detection code JPEG2025540634000010.jpg1518 is is defined by JPEG2025540634000011.jpg21118, where: JPEG2025540634000012.jpg1421 is the Pauli X and Z single logical qubit operators on the logical qubit q, the instruction set includes a plurality of instruction blocks, each instruction block including at least one instruction for executing, by the quantum computing system, at least one quantum gate in an n-qubit quantum circuit; configured to transmit the set of instructions to the quantum computing system; The quantum computing system includes: receiving the instruction set; performing fault-tolerant initialization of the logical states of the k logical qubits using the n qubit quantum circuit, the first ancilla qubit, and the quantum error detection code; Executing each instruction block of the plurality of instruction blocks in the quantum circuit of n physical qubits; After each instruction block, the first ancillary and the second ancillary are used to calculate S for the n physical qubits. Z Stabilizer and S X Perform fault-tolerant syndrome measurements of stabilizers; After all of the instruction blocks of the plurality of instruction blocks are applied to the n physical qubits, measuring the n physical qubits using a first ancilla qubit and a second ancilla qubit to obtain each logical operator Perform fault-tolerant state measurement of JPEG2025540634000013.jpg11124, The quantum computing system includes: Based on a measurement of either the first ancilla qubit or the second ancilla qubit indicating a failure, the quantum computation is configured to discard the computation result and resume the quantum operation during any of the fault-tolerant steps of performing initialization, syndrome measurement, or state measurement. Preferably, the quantum computing system is a trapped ion quantum computer with all-to-all connections between qubits. Preferably, the qubits of the quantum computing system include only n physical qubits and 2 ancilla qubits. Preferably, the finite gate decomposition is composed of unitary gates of a universal gate set, the unitary gates including gates that can be encoded onto physical qubits using only two-qubit Molmer-Sørensen gates and up to four Clifford group gates, and optionally the universal gate set includes global rotations on k or k-1 logical qubits. Preferably, the universal gate set includes only single-qubit logical rotations, two-qubit logical rotations, and global rotations for k or k-1 logical qubits. Preferably, the quantum computing system further comprises: X After the last instruction block is executed, each logical operator Combine the fault-tolerant measurements of JPEG2025540634000014.jpg1322 with the last syndrome measurement, configured to transmit the results to a classical computing system; The classical computing system further post-processes the transmitted results to generate the S Z Stabilizers and logical operators JPEG2025540634000015.jpg1416 and transmitting an indicator of the decoded stabilizer value to the quantum computing system; The quantum computing system is further configured to discard the computation result and restart the operation based on a value of the decoded stabilizer indicating a failure. According to a third aspect of the present invention, there is provided a quantum computing system for performing quantum operations including unitary operations of interest including quantum error detection, comprising: the quantum computing system includes k physical qubits, a physical qubit t, a physical qubit b, a first ancilla qubit, and a second ancilla qubit; the quantum computing system is configured to implement a quantum circuit at k physical qubits, physical qubit t, and physical qubit b using the first ancilla qubit and the second ancilla qubit; The quantum computing system includes: receiving an instruction set including a plurality of instruction blocks, each instruction block including at least one instruction for executing, by the quantum computing system, at least one quantum gate in a quantum circuit of n qubits; performing fault-tolerant initialization of the logical states of the k logical qubits using a quantum circuit of n physical qubits, a first ancillary, and the quantum error detection code; Executing each instruction block of the plurality of instruction blocks in the quantum circuit of the n physical qubits; After each instruction block, the first ancilla qubit and the second ancilla qubit are used to respectively perform S Z Stabilizer and S X Perform fault-tolerant syndrome measurements of stabilizers; After all of the instruction blocks of the plurality of instruction blocks are applied to the n physical qubits, each logical operator is calculated using the first ancilla qubit and the second ancilla qubit by measuring the n physical qubits. configured to perform fault-tolerant state measurements of JPEG2025540634000016.jpg11124; The quantum computing system is configured to discard the computation result based on an ancillary measurement indicating a failure, and is configured to discard the computation result and restart the quantum operation during any of the fault-tolerant steps of performing initialization, syndrome measurement, or state measurement. Preferably, at least one quantum gate in the n-qubit quantum circuit of each instruction block is a two-qubit Molmer-Sorensen gate or one of four Clifford group gates. Preferably, the quantum computing system further comprises: measuring stabilizers for the n physical quantum bits; and measuring the n physical quantum bits to determine whether each logical operator is a stabiliser for the n physical quantum bits after the last instruction block is executed. The fault-tolerant measurement of JPEG2025540634000017.jpg1322 is combined with the last syndrome measurement, Sending the results to a classical computing device; receiving a decoded stabilizer value indicator; Based on the decoded stabilizer value indicating failure, the computation result is discarded and the operation is restarted. According to a fourth aspect of the present invention, there is provided a quantum computing system including a quantum computing device connected to a classical computing device, the classical computing device configured to receive input data therefrom and to transmit output data therefrom; the classical computing device is configured to process at least one computational task included in the input data by generating a corresponding Ansatz that defines initial values ​​for k quantum bits, and that, when executed, configures a quantum circuit within the quantum computing device that operates on the k quantum bits; the quantum computing device is configured to execute a quantum circuit starting from the Ansatz to generate a computation result for the k qubits, the k qubits being measured by the quantum computing device to generate measured k qubit values; the quantum computing device is configured to transmit the measured k qubit values ​​to the classical computing device for use in other computations in the quantum computing system and / or for inclusion in the output data; the quantum computing device is configured to complement k qubits with e ancilla qubits and ansatz qubits in the quantum circuit; the quantum computing device is configured to include additional gates in the quantum circuit for coupling intermediate states of the k qubits to e ancilla qubits with quantum error detection during execution of the quantum circuit; the quantum computing device is configured, upon completion of execution of the quantum circuit, to measure e ancilla qubits to generate measured e ancilla qubit values; the quantum computing system is configured to process the measured values ​​of the e ancilla qubits to determine whether an error occurred during execution of the quantum circuit; The quantum computing system is configured to discard the measured values ​​of the k quantum bits and repeat the Ansatz and quantum circuit calculations if the quantum circuit is executed in an error state that exceeds an error threshold of the quantum operation.

[0006] Optionally, the quantum computing system includes two e ancillary qubits that complement the quantum circuit.

[0007] Optionally, in the quantum computing system, the error detection functionality is configured to generate values ​​of the measured e ancilla qubits as a function of intermediate states of all k qubits during execution of the quantum circuit.

[0008] Optionally, in the quantum computing system, the error detection functionality is configured to generate values ​​of the measured e ancilla qubits as a function of pairs of intermediate states of the k qubits during execution of the quantum circuit.

[0009] Optionally, in the quantum computing system, the error detection functionality is configured to generate values ​​of the measured e ancilla qubits according to a subset of intermediate states of the k qubits during execution of the quantum circuit.

[0010] Optionally, in the quantum computing system, the e ancilla qubits include an X qubit and a Z qubit; X is all the qubits It works on JPEG2025540634000018.jpg1046, and Z is all the qubits Works on JPEG2025540634000019.jpg946.

[0011] Optionally, in a quantum computing system, the error detection function uses a code having the property that large weight products of logical operators reduce to encoded operations of small weight. Optionally, in a quantum computing system, the error detection function Contains one or more products of pairs JPEG2025540634000020.jpg125114. The above example assumes an even number k of logical qubits. However, an odd number k of logical qubits is also possible by including a redundant qubit d. In that case, some modifications are required to equations (c), (d), (g), (h), (J), (k), and (l) to utilize the state of qubit d, as shown below. JPEG2025540634000021.jpg124114

[0012] According to a fifth aspect of the present invention, there is provided a method of configuring a quantum computing system to detect errors in quantum operations, comprising: the quantum computing system includes a quantum computing device connected to a classical computing device; the classical computing device is configured to receive input data therefrom and transmit output data therefrom; The method comprises: (a) configuring the classical computing device to process at least one computational task contained in input data by generating corresponding Ansatzes that define initial values ​​for k quantum bits, and configuring a quantum circuit within the quantum computing device that, when executed, operates on the k quantum bits; (b) configuring the quantum computing device to execute the quantum circuit starting from the Ansatz to generate a computation result for the k qubits, the computation result for the k qubits being measured by the quantum computing device to generate measured k qubit values; (c) configuring the quantum computing device to transmit the measured k qubit values ​​to the classical computing device for use in other computations in the quantum computing system and / or for inclusion in the output data; The method further comprises: (d) configuring the quantum computing device to complement the k qubits with e ancilla qubits and ansatz qubits in the quantum circuit; (e) configuring the quantum computing device to include additional gates in the quantum circuit for coupling intermediate states of the k qubits to the e ancilla qubits with qubit error detection during execution of the quantum circuit; (f) configuring a quantum computing device to, upon completion of execution of the quantum circuit, measure the e ancilla qubits and generate values ​​for the e measured ancilla qubits; (g) configuring a quantum computing system to process the measured e ancilla qubit values ​​to determine whether an error occurred during execution of the quantum circuit; (h) configuring the quantum computing system to, if the quantum circuit is executed in an error state that exceeds an error threshold of the quantum operation, discard the measured k quantum bit values ​​and repeat the Ansatz and quantum circuit calculations.

[0013] Optionally, the method is implemented to include two e ancillary qubits to complete the quantum circuit.

[0014] Optionally, the method includes configuring the error detection function to generate values ​​of the measured e ancilla qubits as a function of intermediate states of all k qubits during execution of the quantum circuit.

[0015] Optionally, the method is implemented by configuring the error detection function to generate values ​​of the e ancilla qubits measured in response to pairs of the k qubits during execution of the quantum circuit.

[0016] Optionally, the method includes configuring the error detection function to generate measured values ​​of the e ancilla qubits in response to a subset of intermediate states of the k qubits during execution of the quantum circuit.

[0017] Optionally, this method is implemented such that the e ancilla qubits include X qubits and Z qubits; X is all the qubits It works on JPEG2025540634000022.jpg1046, and Z is all the qubits Works on JPEG2025540634000023.jpg946.

[0018] Optionally, the method is implemented to use a code that has the property that large weight products of logical operators reduce to encoded operations with smaller weights.

[0019] Optionally, the method further comprises: and configuring the error detection function to include one or more products of pairs of JPEG2025540634000024.jpg121115.

[0020] According to a third aspect, there is provided a software product for execution in a quantum computing system including a quantum computing device connected to a classical computing device, the software product configured, when executed, to implement the method of the second aspect.

[0021] According to a fourth aspect, there is provided a quantum circuit for execution in a quantum computing apparatus of a quantum computing system, the quantum circuit configured to include an additional e ancilla qubits for implementing the method of the second aspect.

[0022] Additional aspects, advantages, features and objects of the present disclosure will become apparent from the following drawings and detailed description of exemplary embodiments taken in conjunction with the appended claims.

[0023] It will be understood that features of the present disclosure can be combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims. [Brief explanation of the drawings]

[0024] Embodiments of the present disclosure will now be described, by way of example only, with reference to the following drawings: [Figure 1]FIG. 1 is a diagram of a quantum computing system that includes a classical computing device connected to a quantum computing device, where the classical and quantum computing devices work in conjunction to perform computational tasks, including creating and executing quantum circuits. [Figure 2] FIG. 2 is a diagram of a qubit, ansatz, quantum circuit, and qubit measurement device used in the quantum computing system of FIG. [Figure 3A] FIG. 3A is a flowchart of method steps according to one embodiment of the present invention. [Figure 3B] FIG. 3B is a flow chart illustrating one example approach for carrying out the method of FIG. [Figure 4] FIG. 4 is a diagram of qubits 1 through k being mapped to qubits t and b by an error detection function. [Figure 5] FIG. 5 is a diagram of an initialization quantum circuit used for the initial values ​​of qubits when the quantum circuit begins execution. [Figure 6] FIG. 6 is a diagram of syndrome extraction from a quantum circuit. [Figure 7] FIG. 7 is a diagram of measuring the value of a qubit after executing a quantum circuit to perform a quantum operation. [Figure 8] FIG. 8 is a diagram of a portion of a quantum circuit that may be used in implementing embodiments of the present disclosure. [Figure 9] FIG. 9 is a diagram of a portion of a quantum circuit that may be used in implementing embodiments of the present disclosure. [Figure 10] FIG. 10 is a diagram of a portion of a quantum circuit that may be used in implementing embodiments of the present disclosure. [Figure 11] FIG. 11 is a diagram of the initialization, syndrome extraction, and measurement performed in the quantum computing device of the quantum computing system of FIG. [Figure 12] FIG. 12 shows a method for testing the performance of a system for performing quantum operations and example data for the method of FIG. 3A. [Figure 13]Figure 13 shows two examples of quantum circuits for compiling quantum rotation operations. [Figure 14] FIG. 14 is a graph of data from a numerical simulation of the performance of the example method of FIG. 3A. [Figure 15] FIG. 15 shows an alternative method for testing the performance of the example method of FIG. 3A. [Figure 16] FIG. 16 is a flow chart of the steps of the method of the present disclosure. [Figure 17] FIG. 17 is a graph of data from a numerical simulation of the performance of the example method of FIG. 3A. [Figure 18] FIG. 18 is a schematic example of a circuit for testing systems and methods for performing quantum operations. [Figure 19] FIG. 19 is a graph of experimental results for the example test of FIG. [Figure 20] Figure 20 shows an uncoded quantum Fourier transform (QFT)-free QPE circuit. [Figure 21] FIG. 21 shows the control unitary operation u of FIG. [Figure 22] FIG. 22 shows the control unitary operation v of FIG. [Figure 23] FIG. 23 is a sketch of the entire coded QPE circuit. [Figure 24] FIG. 24 shows the compilation of the controlled unitary operation u of FIG. 21 into a logic gate. [Figure 25] FIG. 25 shows the encoding format of FIG.

[0025] In the accompanying figures, underlined numbers are used to indicate the item in which the underlined number is located or the item to which the underlined number is adjacent. When a number is not underlined and has an associated arrow, the ununderlined number is used to identify the general item to which the arrow is pointing. DETAILED DESCRIPTION OF THE INVENTION

[0026] 1, quantum computing system 100 is shown including classical computing device 110 connected to quantum computing device 120, such that, during use, data is exchanged between classical computing device 110 and quantum computing device 120. Classical computing device 110 is advantageously implemented using a computing device based on silicon integrated circuit binary logic devices. Quantum computing device 120 is advantageously implemented as a photonics quantum computer, a trapped ion quantum computer, a cryogenically cooled Josephson junction quantum computer, or the like, where entanglement and superposition of qubits occurs during use of quantum computing device 120.

[0027] In operation, input data Din is received by classical computing device 110, which includes one or more computational tasks to be performed by quantum computing system 100. Classical computing device 110 processes the one or more computational tasks and determines corresponding parameters to configure quantum computing device 120. These parameters include defining Ansatz 130, which determines the parameterized unitary implemented in quantum computing device 130, and quantum circuit 140 is applied to process qubits in Ansatz 130. Quantum computing device 120 also includes measurement device 150, which measures the value of a qubit after quantum circuit 140 is performed on the qubit. In use, quantum computing device 120 transmits qubit measurements to classical computing device 110, which outputs the qubit measurements as output data Dout and / or stores the qubit measurements for use in future computations performed by quantum computing system 100.

[0028] In the operation of quantum computing system 100, quantum noise, stochastic thermal noise, decoherence, and crosstalk occur when creating quantum computing device 130, when executing quantum circuit 140, and when measuring the values ​​of qubits when quantum circuit 140 is executed. The noise may vary from one “shot” through quantum computing device 120 to another. Embodiments of the present disclosure relate to an implementation of quantum computing system 100 where, if an error is detected in qubit measurement 150 for execution of quantum circuit 140 in a given “shot,” the “shot” is repeated until no error is detected in qubit measurement 150. The qubit measurement 150 for a given “shot” in which an error is detected may be advantageously discarded by quantum computing system 100.

[0029] 2 , in an embodiment of the present disclosure, Ansatz 130 is complemented by e ancilla qubits, e.g., two (2) ancilla qubits X and Z. During execution of quantum circuit 140, additional quantum gates included in quantum 140 perform error detection functions that operate on the e ancilla qubits Z and Z. When the values ​​of the k qubits and the e qubits are measured at 150, the values ​​of the e qubits indicate whether an error occurred when applying quantum circuit 140 to the k qubits. As shown in FIG. 3, we present a method 300 for performing quantum operations including quantum error detection. Typically, a quantum operation may be performed by initializing one or more qubits in a quantum state, e.g., a computational state, and performing a particular unitary operation on the one or more qubits, where the unitary operation at least partially characterizes the quantum operation, and by performing a measurement on at least a portion of the one or more qubits, and the quantum operation may be performed in a quantum computer by a quantum computer implementing a quantum circuit. A unitary operation of interest may be performed in a quantum circuit by executing a finite number of quantum gates that form an approximation to the unitary of interest. Quantum error detection introduces the problem of how and when to perform quantum operations to detect errors. The use of quantum error detection code enables syndrome measurements that can detect errors that may be introduced by specific operations prior to the syndrome measurement. The syndrome measurement itself is fault-tolerant; in other words, no single component used to perform the syndrome measurement introduces undetectable logic errors. Because the syndrome measurement required only two additional ancillary qubits, the physical qubit overhead for implementing the logic circuit is reduced to four additional qubits. If an error is detected, the computation result is discarded and the operation is restarted. This provides lower overhead at the expense of a predicted completion time based on the discard rate. This code enables fault-tolerant initialization of quantum states and quantum measurement of quantum states. Therefore, syndrome measurements can be used to detect errors introduced between initialization and the first syndrome measurement, between the final syndrome measurement and the final quantum measurement of the quantum state, and between multiple syndrome measurements. Subsequent fault-tolerant steps can also detect a different type of error, a flipped stabilizer error, output from a preceding fault-tolerant operation. The operations in the quantum circuit performed by the quantum computing system during syndrome measurement are composed of quantum logic gates from the universal gate set, allowing any quantum unitary gate to be executed by the circuit. Even if the gates executed during syndrome measurement are not fully fault-tolerant, the quality of the quantum operations executed by the quantum computing system, as measured by quantum volume, can be maintained. In particular, certain operations can be relied upon to be more easily executed by certain types of quantum devices, allowing for improved quantum performance. The method 300 calculates a unitary quantum circuit of interest for any real number k, for a quantum circuit of k logical qubits. The method includes step 310 of obtaining an approximation of a finite gate decomposition of JPEG2025540634000025.jpg1213. The finite gate decomposition can be composed of a predetermined subset of all unitary gates, for example, unitary gates of a minimal universal gate set. The finite gate decomposition can be calculated based on the unitary of interest to obtain the finite gate decomposition, or the finite gate decomposition can be received from an external source that performs the calculation. Method 300 further includes converting 320, using a quantum error detection code, the finite gate decomposition of the quantum circuit of k logical qubits into an instruction set for executing the quantum circuit with n physical qubits.

[0030] Here we present a quantum error-detection code that encodes k (even) logical qubits, [k]={1, 2,..., k}, with a code distance of 2 using n=k+e physical qubits, where e=2 is preferred. These n qubits [n] are labeled 1,..., k, t (most significant), b (least significant). See Figure 3. This code has two stabilizers. X is all the qubits Works on JPEG2025540634000026.jpg996. Z is all the qubits Works on JPEG2025540634000027.jpg1096. The single-qubit logical operators in this code are defined as shown in Figure 3. JPEG2025540634000028.jpg19102The Pauli X logical operator acts on the t (top) and numbered quantum bits, and the Pauli Z logical operator acts on the b (bottom) and numbered quantum bits.

[0031] For fault-tolerant operations, two additional ancilla qubits are required, which we typically refer to as a Z and a X Overall, we can implement the code in hardware with k+4 physical qubits.

[0032] The code is Error Detection Code , which means the error is detectable, but Not corrected This means that if an error is detected during execution of quantum circuit 140, the current shot of the executing circuit 140 may be discarded.

[0033] The code described above is conveniently called an "iceberg code" and has the useful property that several large-weight products of logical operators are reduced to encoded operations of smaller weight. To demonstrate this, all products of pairs of encoded qubits are shown below: JPEG2025540634000029.jpg124117These logical operators can be expressed in other notations. JPEG2025540634000030.jpg2896

[0034] It will be appreciated that the product of two logical operators among X, Y, or Z does not increase in weight and remains a product of two physical operators—(b), (f), and (j). Furthermore, it will be appreciated that global (or substantially global) logical operators are reduced to products of only two physical operators—(c), (d), (e), (h), (i), (k), and (l). This allows for the realization of multi-qubit logical unitaries, which are very difficult with k or k−1 qubits, using only two-qubit physical qubit operations. Therefore, the system must be able to provide all connections between qubits; in other words, the system must be able to provide gates between any two physical qubits. Global logical operators acting on k or k−1 logical qubits are also supported by physical operators with two physical qubits. For example, the logical operator The logical unitary generated by JPEG2025540634000031.jpg1624 is Z t Z b is supported by the corresponding physical unitary generated by Just as the logical Pauli operators for single qubits, two qubits, k-1, and k qubits are supported by the physical Pauli operators for two qubits, the logical rotation operators for single, two, k-1, and k qubits are JPEG2025540634000032.jpg2035 format, where σ∈{X, Y, Z}. Advantageously, trapped ion computers can perform such two-qubit operations with high fidelity. The steps of obtaining the finite gate decomposition and transforming the finite gate decomposition can be performed by a classical computing system. For example, this can be a classical computer with a processor capable of sending a set of instructions to a quantum computing system, where the quantum computing system includes at least k physical qubits, a most significant physical qubit, and a least significant physical qubit, and the quantum computing system, together with at least two ancilla qubits, is configured to realize a quantum circuit. Generally, a quantum computer can be implemented with any type of quantum hardware and can be applied to any type of application or algorithm. A quantum computing system uses a set of quantum gates to compute the unitary quantum state of interest according to the above decomposition. JPEG2025540634000033.jpg1516, where the instruction set includes a plurality of instruction blocks. Method 300 further comprises: receiving an instruction set for executing JPEG2025540634000033.jpg1516, where the instruction set includes a plurality of instruction blocks. Method 300 further comprises: receiving an instruction set for executing JPEG2025540634000033.jpg1516, where the instruction set includes a plurality of instruction blocks. ZThe method includes fault-tolerantly initializing the logical states of the k logical qubits using the Iceberg code and the ancillary code a. The choice of initial logical states is arbitrary and can be chosen according to the operation being performed, for example, a uniform superposition of the states of all logical qubits to implement Grover's search algorithm. However, the initialization should be fault-tolerant if performed using a quantum error detection code. This can be done using only a single ancillary code. Z Fault-tolerant initialization of states in n physical qubits corresponding to the all-zero logical state using Method 300 further includes the quantum computing system executing each instruction block of the plurality of instruction blocks (step 350). Each instruction block may include instructions that, when executed by the quantum computing system, cause a quantum circuit on n physical qubits to be executed, corresponding to a finite number of logical quantum gates for k logical qubits. Execution of all instructions in all instruction blocks executes a quantum circuit on n physical qubits corresponding to a finite quantum logical gate decomposition that implements a finite approximation of the unitary of interest. The instruction blocks do not need to be executed fault-tolerantly to implement quantum operations while preserving non-classical processing. By appropriately selecting the gate set for finite gate decomposition, at least some logical errors can be detected when executing each instruction block when using the Iceberg code. Each instruction block can include at least one instruction for executing at least one quantum gate in an n-qubit quantum circuit by a quantum computing system. These instructions are prepared using a quantum error detection code so that each gate for n physical qubits corresponds to a gate for k logical qubits. A finite approximation of a unitary can be compiled using only gates from the universal gate set. Typically, any universal gate set can be selected. However, it is preferable to use a gate set that can map global logical operations to two-qubit physical operations. In particular, a global rotation of a logical qubit is mapped to a two-qubit rotation of a physical qubit. The universal gate set of logical gates can be used to perform single-qubit rotations. JPEG2025540634000034.jpg12100 or 2-qubit logical rotation JPEG2025540634000035.jpg12149. This is particularly advantageous for quantum computing systems implemented with trapped ions. A logic circuit for implementing a unitary U of interest is compiled by a classical computing system and then transmitted to a quantum computing system for execution in its encoded physical form. A common approach to compiling a unitary U of interest into a logic circuit is to first compile U into a gate set that includes only single-qubit rotations -(RX(θ)=exp(-iθX / 2) and RZ(θ)=exp(-iθZ / 2)) and two-qubit logical rotations -(RXX(θ)=exp(-iθXX / 2), RYY(θ)=exp(-iθYY / 2), RZZ(θ)=exp(-iθZZ / 2)). This can be done using a TKET compiler, as described in U.S. Patent 11,144,689, "System and Method for Generating a Quantum Circuit." Expressed in terms of single-qubit and two-qubit logical gates, each gate in the circuit can be expressed as a gate set, as described by Molmar Sørensen, MS ij (θ), can be directly compiled into an encoded physical form using gates, where JPEG2025540634000036.jpg14101Involves up to four single-qubit Clifford gates: H, S, S†, and CNOT. This is MS ij (θ) X after the gate i X j , Y i Y or Z i Z j It is not fault-tolerant, since a two-qubit Pauli error of the form i,j∈[n] produces an undetectable logical error for any pair i,j∈[n]. However, single-qubit Pauli errors and two-qubit Pauli errors where the two Pauli operators differ from each other are detectable, thereby reducing the number of undetectable errors compared to not using the Iceberg code. Furthermore, MS ij Physical gates of the form Any logical rotation from the set of logical rotations in the JPEG2025540634000037.jpg1334 format can be used, where θ∈(0,2π), JPEG2025540634000038.jpg1518, for example, It is one of the operators (a) to (l) including JPEG2025540634000039.jpg1339. The universal gate set is The compiled circuit can be defined as a set of logical rotations of the form JPEG2025540634000040.jpg1334, where θ∈(0,2π). Thus, global rotations for k and k-1 logical qubits are included in the universal gate set without requiring costly physical operators. Thus, the performance of systems implementing the compiled circuit can be improved without the additional cost of physical resources. After each instruction block is executed and before the next instruction block is executed, the method 300 includes step 360, in which the quantum computing system executes a first ancillary Z and the second ancilla a X Using each, S Z Stabilizer and S X Implement a fault-tolerant syndrome measurement of the stabilizer. The syndrome measurement can be performed using only two ancillaries. The syndrome measurement can be performed at a predetermined step during the execution of the circuit, or at a predetermined time. The size of each block of instructions can be different from other blocks. These blocks can also be the same size, e.g., describing the same number of gates, but this is necessary to maintain arbitrary logic operations, e.g., Hadamards and JPEG2025540634000041.jpg1384 MS ij (θ) can be adjusted so that no syndrome measurements are inserted between gates. Syndrome measurement allows for readout of the stabilizer's eigenvalues ​​without disturbing the logical information. The quantum circuit for syndrome measurement can be based on a quantum error detection code. For example, before a quantum computing system is configured to implement a quantum circuit for syndrome measurement, the syndrome measurement circuit for n physical qubits is checked using a quantum error detection code to determine the quantum circuit that maps to k logical qubits and to check that this circuit does not disturb the logical information. This can also be done for initialization and / or state measurement. Fault-tolerant, non-disturbing syndrome measurement can be performed by implementing a quantum circuit that performs a CNOT gate between the physical qubits and an ancillary element to generate a measurement of a single qubit in the ancillary element. The ancillary element can be reset and reused between multiple measurements. Circuit instructions can configure ancillary elements to act as flag qubits for each other, allowing for the detection of errors in the ancillary element that may propagate to other qubits. A variety of circuits can be used for syndrome measurement; one example is described below in conjunction with the description of FIG. 6. After all of the instruction blocks of the plurality of instruction blocks have been applied to the quantum circuit, the method includes step 370, in which the quantum computing system performs measurements of the k logical qubits by performing all fault-tolerant measurements of the n physical qubits. The final measurements of all qubits can be combined with a final syndrome measurement performed after the last block of instructions. The final fault-tolerant measurement of the stabilizer and each qubit, e.g., Measurement of a logical qubit operator, such as JPEG2025540634000042.jpg1041, occurs after any preceding non-fault-tolerant operations. An example of fault-tolerant measurement of a quantum circuit is described below in connection with the description of FIG. The quantum computing system is configured to discard the computation result (step 390) based on any measurement of the ancillary element indicating a failure and resume the operation of the quantum operation. The code space can be defined as the combined subspace of +1 for both stabilizers, such that a reading of -1 for either the first or second ancillary element indicates the presence of an error. The probability that an attempt to perform a computation will continue until a measurement depends, at least in part, on the probability of a detectable failure occurring in a non-fault-tolerant operation during syndrome measurement. The probability of detecting a failure can be increased by increasing the number of syndrome measurements during the operation. The more failures detected, the better the quality of performance by the quantum computing system when performing a quantum operation. Therefore, increasing the frequency of syndrome measurements in the circuit has a positive effect. However, the discard rate increases accordingly. Thus, the present invention provides a trade-off between the performance of a quantum operation and the number of required iterations based on the discard rate.

[0035] Next, we will explain fault-tolerant computation. In the embodiment of the present disclosure, we perform the following tasks: -Logical Code Status|0 L > initialization, where JPEG2025540634000043.jpg1487-Stabilizer S X and Stabilizer S Z Syndrome extraction for simultaneously and non-destructively measuring both -Stabilizer S X Non-destructive measurement and Stabilizer S Z A final measurement that includes all destructive measurements of n qubits in the Z basis that can reconstruct Regarding (A), we have identified a fault-tolerant quantum circuit, which will be described later. The quantum circuits specified for these tasks are fault-tolerant in the sense that there are no single faults that would cause undetectable logic errors. A single fault is defined as a localized Pauli error caused by the failure of a component of a quantum circuit, such as quantum circuit 140. Tests were conducted to verify fault tolerance, as detailed in (B).

[0036] Logical Rotation It will be appreciated that the general logic operations of code such as JPEG2025540634000044.jpg1333 are not implemented in a fault-tolerant manner. Furthermore, the finite gate set decomposition can further be chosen for ease of implementation in a trapped ion quantum computer.

[0037] (A) Circuit Initialization: An example of a circuit for fault-tolerant initialization for k logical qubits is shown in Figure 5. The logical qubits are initialized to the all-zero code state. JPEG2025540634000045.jpg1324, which puts the physical qubit into a Greenberger-Horn-Zeilinger (GHZ) state. JPEG2025540634000046.jpg1254, where all i∈[k], and its generation is well known. From the definitions of the stabilizers and logical operators, it follows that the all-zero code state is the GHZ state of n physical qubits. In embodiments of the present disclosure, fault-tolerant quantum circuits are used to achieve this. Typically, an H gate operates on the most significant physical qubit, and a CNOT gate is applied between adjacent pairs of physical qubits {t,1}, {1,2}, {2,3},...{k,b} to control the first qubit of the pair. Next, a CNOT gate is performed between the most significant qubit and the first ancillary qubit, and then between that ancillary qubit and the least significant qubit before the Z-basis measurement of the first ancillary qubit, the result of which corresponds to {+1,-1}. If a fault occurs, the ancillary qubit a z The measurement of returns to -1 or is measured as +1. When a fault is detected, the execution result of quantum circuit 140 is discarded.

[0038] Syndrome Extraction: An example of a circuit for fault-tolerant syndrome measurement for k+2 physical qubits is shown in Figure 6. Advantageously, S Z and S X The stabilizer eigenvalues ​​of S are extracted simultaneously and non-destructively. Z The eigenvalues ​​of an ancilla a z is obtained by reading out S X The eigenvalues ​​of an ancilla a X A measurement a of one ancillary element a being -1 means that we discard that result. In the embodiment of the present disclosure, a flagging scheme (see [Chao2020] below) is used, which allows the ancillary element a X But, a Z acts as a flag qubit for , and vice versa.

[0039] In embodiments of the present disclosure, syndrome extraction circuits with an AB...BA structure are advantageously used, where A and B represent different measurements of CNOT gates on physical qubits. The order of CNOT gates in these circuits must be respected to maintain fault tolerance. A and B blocks for k+2 physical qubits are shown in FIG. 6. Typically, the A block is first applied to the most significant physical qubit, the [1] physical qubit, and two ancillaries; then the B block is applied k-2 times; and then the A block is again applied to the last k physical qubit, the least significant qubit, and two ancillaries. The B block is applied to the two ancillaries and the adjacent qubit pair for each pair of adjacent qubits {2,3}, {3,4}... {k-1,k}.

[0040] Final Measurement: Figure 7 shows an example of a final fault-tolerant measurement, where the final syndrome measurement is combined with the logical qubit measurements for k logical qubits / k+2 physical qubits. X is measured, then all qubits are destructively measured, and in a post-processing step, S Z and all logical Z operators are evaluated. By destructive measurement of the physical code qubits in all n=k+2 bases Z, the logical operators JPEG2025540634000047.jpg1215 and the stabilizer can be reconstructed using the flagged circuit described in [Chao2020]. X is advantageously prefixed by non-destructively extracting the eigenvalues ​​of z is S X Encode the reading of a x acts as a flag qubit for the readout value. z or a x Measurement of either S Z Reconstructing the eigenvalues ​​of the stabilizer (-1) means that the results are discarded, as shown in Figure 7. (B) Fault tolerance verification

[0041] As mentioned above, the circuit revealed in (A) is fault-tolerant in the sense that there is no single fault that causes an undetectable logic error. If a single fault is defined as a localized Pauli error caused by a failure of a circuit element, then there are considered to be the following sets of single faults, as shown in Figures 8, 9, and 10. These figures show a SPAM (State Preparation and Measurement) error, a one-qubit gate error, and a two-qubit gate error, respectively.

[0042] 11, embodiments of the present disclosure have been tested (up to code size k=16) to exhaustively verify that there are no single faults that cause undetectable logic errors. As an example, the inventors show that the impact of all single faults affecting k=16 pieces of code is classified into six classes that describe the impact.

[0043] Referring to Figure 11, it will be seen that local errors are categorized based on whether they generate a detection qubit (three bars on the left) or not (three bars on the right). Within these groups, errors may correspond to no error (e.g., stabilizer operation), an inverted stabilizer, or a logic error. Shading is used to order these cases based on whether they represent ideal behavior (stripes) or non-ideal behavior that is not a failure or failure (solid gray). These three circuits are shown to be fault-tolerant because the number of undetectable logic errors is zero. Provided herein is a method for testing the performance of a method for performing quantum operations including quantum error detection. In particular, the provided method is suitable for testing methods and systems for performing operations including quantum error detection of the present invention. To test the methods and systems of the present invention, a test unitary is assigned as a target unitary. The present invention can be implemented using the test unitary for k logical qubits, and corresponding experiments are then performed, in which the k qubits are initialized to the same states as the k logical qubits, and then the same test unitary is applied without the encoding of the present invention. In each experiment, the final state is measured. The experiments are repeated until a survival probability can be calculated. The survival probability is the probability of measuring the expected final state from the target unitary applied to the initial state. The survival probability of the method using encoding, i.e., the present invention, is compared with the survival probability of the method not using encoding, i.e., the control. The present invention and the control can be compared for different values ​​of k, and these are compared for different numbers of syndrome measurements. The test unitary can be implemented by compiling the gate of interest into a quantum circuit of finite gates, in which case the same gate decomposition should be used for the present invention and control. Preferably, the test unitary is equivalent to an identity and is decomposed into a mirror circuit, where a randomly selected unitary is run as part of the quantum circuit, and then the inverse of the randomly selected unitary is run, and the expected final state is the same as the initial state. An example test methodology is provided, and data obtained from an embodiment of the exemplary test methodology is included. A parameterized mirror circuit, derived from a highly expressive family of random circuits, can be used as a unitary for testing. An example of a random circuit configuration and its correspondence to physical and logical operators is shown in FIG. 12(ab). A physical compilation of the mirror circuit for eight logical qubits using the Iceberg code is shown in FIG. 12(a). This circuit implements a parameterized physical unitary and its inverse. The unitary has a hierarchical structure, where in each layer, physical qubits [n]={1,...,k}∪{t,b} are randomly paired, and for each pair i,j∈[n], a random physical rotation exp(-iθσ i σ j / 2) applies, where θ∈(0,2π) and σ∈{X,Y,Z}. We show this in one layer, where the physical rotations in each layer are labeled with a rotation basis. Figure 12(b) shows the logical mirror circuit corresponding to that of Figure 12(a). The shading is the physical rotation of each two qubit in (a) and the logical operator Logical rotation by JPEG2025540634000048.jpg1229 It is used to show the correspondence with JPEG2025540634000049.jpg1239. The final logical operator Note that JPEG2025540634000050.jpg1319 physically supports only two physical qubits, but operates globally on all logical qubits. Figure 12(c) shows experimental data, plotting the survival probability (symbols) and discard probability (bars) against the number of layers. The number of layers includes unitary and inverse layers. The survival probability is the probability of measuring the initial logical quantum state |0> on all logical qubits, which is expected to be noise-free. As shown in Figure 12(a), the logical unitary An encoded circuit, where JPEG2025540634000051.jpg1416 is compiled using Iceberg code, is compared to an unencoded circuit, where logical unitaries are compiled into phase gadgets, as described in the supplemental information below. A distinction is made between logic circuits with global logic gates and logic circuits without global logic gates. Figure 13 shows Rotation produced by JPEG2025540634000052.jpg1252 Figure 13(a) shows the compilation of JPEG2025540634000053.jpg1261. Figure 13(b) shows the compilation using the Iceberg code, where the rotation is realized with a single two-qubit operation. tb (θ) gate and four single-qubit Hadamard gates. Figure 13(b) shows the compiled version of the unencoded circuit. JPEG2025540634000054.jpg1231 shows an example, where the physical circuit for the same rotation makes use of the Phase gadget. The logical generator for the rotation is the global operator JPEG2025540634000055.jpg1325, so it's a single MS k(k-1) Before applying the (θ) gate, a ladder of CNOT gates is used to calculate the parity, and another CNOT ladder is used to reverse the parity. Additionally, Hadamard gates for all qubits at the beginning and end apply a basis change. The number of layers varies, e.g., from 4 to 256, and the survival probability of unencoded circuits is compared with that of circuits encoded using the Iceberg code. In other words, it is the probability of measuring the initial logic state after implementing a logical unitary and its inverse. In the absence of noise, the survival probability is 1 and decreases with the number of errors in the circuit. Two types of logic circuits are analyzed: those containing global logic gates and those without global logic gates. This analysis separates the effects of global gate compression from the effects of encoding and error detection. Experiments are performed on at least two randomly selected circuits: those containing global rotations and those without global rotations. In the Supplementary Information, we provide numerical evidence showing that these are representative examples. Using global logic gates effectively implements a more favorable scenario for the Iceberg code. Indeed, compilation of global logic gates using the code is performed with a single two-qubit MS gate, while unencoded compilation requires two staircases of CNOT gates for all qubits. These compilations are described in more detail in the,Supplementary Information.,The left panel of Fig. 12(c) shows that the Iceberg code,significantly improves the survival probability for circuits containing,global rotations. Without global rotations, the unencoded circuit is much simpler than the encoded circuit, eliminating the overhead of initialization, syndrome measurement, and measurement circuitry. For example, at 128 layers, the unencoded circuit has a depth of 331, containing 372 two-qubit gates, while the encoded circuit, when compiled to native hardware gates, has a depth of 549, containing 657 two-qubit gates. In the right panel of Figure 12(c), we can see that the Iceberg code provides sufficient survival probability even for a circuit without global rotations. It is important to emphasize that this is the worst-case scenario for the Iceberg code, but the encoding and error detection still yield good results. Without global rotations, the unencoded circuit is much simpler than the encoded circuit, eliminating the overhead of initialization, syndrome measurement, and measurement circuitry. For example, at 128 layers, the unencoded circuit has a depth of 331, containing 372 two-qubit gates, while the encoded circuit, when compiled to native hardware gates, has a depth of 549, containing 657 two-qubit gates. In the right panel of Figure 12(c), we can see that the Iceberg code provides sufficient survival probability even for a circuit without global rotations. It is important to emphasize that this is the worst-case scenario for the Iceberg code, but the encoding and error detection still yield good results. Numerical simulations can be performed to explore the impact of adding multiple layers and logical qubits on performance. An example of data from a numerical simulation of the performance of a random mirror circuit for more logical qubits is shown in Figure 14, where eight logical qubits are encoded into a 12-qubit Quantinuum H1-2 trapped-ion quantum computer. We simulate 32 instances of the random circuit with global rotation described in Figure 2. The median survival probability of a is plotted against the number of layers for encoding circuits (filled symbols) and non-encoding circuits (open symbols) with various numbers of logical qubits. The median discard rate of b is plotted for the encoding circuits in each case. An intermediate circuit round of syndrome measurements is applied every 16 layers. The error bars in (a) and (b) indicate 99% confidence intervals around the median values ​​obtained from bootstrap resampling. For numerical simulations, it is preferable to include global rotation in the universal gate set. Simplified error models may be used based on the properties of the model in which it is implemented. For example, the sample data shown in Figure 14 was discovered using a simplified error model based on the properties of Quantinuum H1-2

[12] . More details are provided in the Supplementary Information. Figure 14(a) shows that for a constant survival probability, an encoding circuit (filled symbols) can have approximately four times as many layers as a non-encoding circuit (open symbols). For a small number of layers, adding qubits increases the performance gap between the encoding and non-encoding circuits. The cost of using Iceberg codes is given by the discard rate. Figure 14(b) shows that the discard rate increases with the addition of qubits and layers. This can be compensated for by increasing the number of circuit iterations. In summary, this analysis demonstrates the utility of Iceberg codes for a large family of critical circuits and for the current generation of trapped ion quantum computers. Provided herein is an alternative method for testing the performance of a method for performing quantum operations using quantum error detection. In particular, the provided method is suitable for testing methods and systems performing operations involving quantum error detection of the present invention. The method includes an example of an efficient randomized sampling scheme for verifying that non-classical processing is occurring in a noisy quantum computer. The non-classical processing test can be applied to various numbers of syndrome measurements and logic qubits. Examples and data illustrating the application of the test to an example of the present invention are provided using quantum volume (QV) testing. The QV test is a commonly used global benchmark for quantum processors. It utilizes random circuits with an equal number of qubits and layers. Each layer randomly pairs qubits and applies a general SU(4) gate to each pair. Each circuit is measured in a computational basis, and a statistic called the HeavyOutput Frequency (HOF) is calculated from the results. The test passes if the mean lower uncertainty bound of the HOF, averaged over many random circuits, is greater than 2 / 3. The bound on the HOF can be calculated using bootstrapping techniques

[32] . Figure 15 shows the 2 8Figure 15(a) shows an example of a QV test showing the logical QV of 10 qubits, demonstrating the positive effect of increasing the number of syndrome measurements when using the Iceberg code. In Figure 15(a), an 8-qubit logic circuit for quantum volume testing is encoded into 10 physical qubits and two ancillaries (a1 and a2). This circuit includes initialization of all logical qubits in the |0〉 state, syndrome measurements of various numbers of intermediate circuits, a final partial syndrome measurement, and measurements of all qubits. The case of 2x syndrome measurements of intermediate circuits is depicted. In Figure 15(b), the average HeavyOutput frequency is plotted against the discard rate. The pass threshold of 2 / 3 is indicated by a dashed black horizontal line. The vertical error bars indicate the bounds on the average estimate of the HeavyOutput frequency. The horizontal axis plots the average discard rate, and the error bars indicate the sample standard deviation. For the 100 circuits required to pass the QV test, 2x syndrome measurements, indicated by stars, are performed. For other QV tests, we run 45 circuits instead.,Figure 15(c) shows the experimental results for individual circuits,for the 2x syndrome measurement.,On the left axis (drawn in red), we plot the HeavyOutput,frequency of each circuit after discarding, the cumulative average (increasing,upward) and its bounds.,The pass threshold 2 / 3 is shown as a dashed line, and the,right axis (drawn in blue bars) shows the discard rate. QV circuits can be generated using Qiskit and compiled into a universal gate set in Iceberg code. Figure 4 shows an example circuit implemented when k = 8. The circuit can be partitioned to insert various numbers of intermediate syndrome measurements. For 0x, 1x, and 3x rounds of syndrome measurements, a simple QV test is performed that stops at 45 circuits, where the average HOF appears to stabilize. For 2x, it continues to the full 100 circuits to demonstrate a passing QV test. Figure 15(c) plots the HOF of individual circuits, along with their cumulative average and bootstrap bounds, for the 2x case. As shown in Figure 15(b), adding syndrome measurements increases the HOF and, consequently, increases the confidence in passing the QV test. This improvement comes at the cost of an increased discard rate.

[0044] 16, steps 400 through 470 of a method for performing error detection in quantum computing system 100 using the code described above are shown. The method includes configuring quantum computing system 100 to provide error detection for quantum operations. Quantum computing system 100 includes quantum computing device 120 connected to classical computing device 110, which is configured to receive input data therefrom and transmit output data therefrom. In step 400 of the method, step 400 includes configuring a classical computing device 110 to process at least one computational task contained in input data by generating corresponding Ansatz 130 that define initial values ​​for the k quantum bits, and configuring a quantum circuit 140 in the quantum computing device 120 that operates on the k quantum bits when executed. In step 410 of the method, step 410 includes configuring quantum computing device 100 to execute quantum circuit 140 starting from Ansatz 130 to generate values ​​for the k measured quantum bits, thereby generating a computational result for the k quantum bits measured by the quantum computing device. In step 420 of the method, step 420 includes configuring quantum computing device 120 to transmit the values ​​of the k measured qubits to classical computing device 110 for use in other computations in the quantum computing device and / or for inclusion in output data. Once error detection is performed, the following additional steps are performed: In step 430 of the method, step 430 includes configuring a quantum computing device to complement k qubits with e ancilla qubits in a quantum circuit and an ansatz. In step 440 of the method, step 440 includes configuring the quantum computing device to include additional gates in the quantum circuit to couple intermediate states of the k qubits during execution of the quantum circuit to the e ancilla qubits using quantum error detection functionality. In step 450 of the method, step 450 includes configuring the quantum computing device to measure the e ancilla qubits upon completion of execution of the quantum circuit to generate values ​​of the e measured ancilla qubits. In step 460 of the method, step 460 includes configuring the quantum computing system to process the measured values ​​of the e ancilla qubits to determine whether an error occurred during execution of the quantum circuit. In step 470 of the method, step 470 includes configuring the quantum computing system to discard the measured values ​​of the k qubits and repeat the Ansatz and quantum circuit calculations if the quantum circuit executes with an error condition that exceeds an error threshold for the quantum operation.

[0045] Modifications to the embodiments of the present disclosure described above are possible without departing from the scope of the disclosure, which is defined by the appended claims. Terms such as "including," "comprising," "incorporating," "consisting," "having," and "being" used to describe and claim the present invention are intended to be interpreted in a non-exclusive manner; in other words, there may be items, components, or elements not expressly recited. References to the singular are to be construed as relating to the plural; for example, "at least one of" refers to "one" in one instance and "plurality" in another. Furthermore, "one or more" is to be interpreted similarly.

[0046] Phrases such as "in an embodiment," "according to an embodiment," and the like generally mean that the particular feature, structure, or characteristic that follows the phrase is included in at least one embodiment of the present disclosure, and may be included in multiple embodiments of the present disclosure. Importantly, such phrases do not necessarily refer to the same embodiment.

[0047] The terms "computer" or "computing-based device" are used herein to refer to any device that has processing capability to execute instructions. Those skilled in the art will recognize that such processing capability is incorporated into many different devices, and thus the terms "computer" and "computing-based device" each include personal computers (PCs), servers, mobile phones (including smartphones), tablet computers, set-top boxes, media players, game consoles, personal digital assistants, wearable computers, and many other devices.

[0048] The methods described herein may, in some examples, be implemented by software in machine-readable form on a tangible, non-transitory storage medium, e.g., in the form of a computer program including computer program code configured to perform one or more operations of the methods described herein when the program is run on a computer, and the computer program may be embodied in a non-transitory computer-readable medium. The software may be suitable for execution on a parallel or serial processor such that the operations of the method are performed in any suitable order, or simultaneously.

[0049] This recognizes that software is a valuable, separately tradable commodity. It is intended to encompass software that runs on or controls "dumb" or standard hardware to perform a desired function. It is also intended to encompass software that "describes" or defines the configuration of hardware, such as HDL (Hardware Description Language) software used to design silicon chips or configure universal programmable chips to perform a desired function.

[0050] Those skilled in the art will understand that storage devices used to store program instructions are optionally distributed across a network. For example, a remote computer can store an example of a process written as software. A local or terminal computer can access a remote computer and download some or all of the software to execute the program. Alternatively, a local computer can optionally download some of the software, or execute some software instructions at a local terminal and some at a remote computer (or computer network). Those skilled in the art will also understand that, by utilizing conventional techniques known to those skilled in the art, all or some of the software instructions can be executed by dedicated circuitry such as a digital signal processor (DSP), programmable logic array, etc.

[0051] Any ranges or device values ​​given herein may be expanded or modified without losing the effect sought, as will be apparent to those skilled in the art.

[0052] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0053] It will be understood that the above benefits and advantages may relate to one embodiment or to multiple embodiments. Embodiments are not limited to those that solve any or all of the described problems or have any or all of the described benefits and advantages. No single feature or group of features is necessary or essential to all embodiments.

[0054] As used herein, conditional language such as, inter alia, "can," "could," "may," "could," "for example," and the like, unless otherwise expressly stated or in the context used to the contrary, is generally intended to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not include certain features, elements, and / or steps. Thus, such conditional language is not generally intended to imply that features, elements, and / or steps are somehow required for one or more embodiments, or that one or more embodiments necessarily include logic for determining whether or not those features, elements, and / or steps are included in or performed in a particular embodiment, with or without author input or prompting. Terms such as "comprises," "includes," and "having" are synonymous and are used inclusively and without limitation, and do not exclude additional elements, features, acts, operations, blocks, etc. Additionally, the term "or" is used in its inclusive sense (not exclusive), so that, for example, when used to conjunctively list elements, the term "or" may refer to one, some, or all of the elements in the list. Furthermore, as used in this application and the appended claims, the articles "a," "an," and "the" shall be construed to mean "one or more" or "at least one," unless otherwise specified.

[0055] As used herein, a phrase referring to "at least one" of a list of items refers to any combination of those items, including single members. By way of example, "at least one of A, B, or C" is intended to encompass A, B, C, A and B, A and C, B and C, and A, B, and C. Unless otherwise specified, conjunctions such as "at least one of X, Y, Z" are understood in the context in which they are otherwise commonly used to convey at least one of X, Y, or Z. Thus, such conjunctions are not generally intended to imply that a particular embodiment requires that at least one of X, at least one of Y, and at least one of Z, respectively, be present.

[0056] The actions of the methods described herein may be performed in any suitable order, or simultaneously where appropriate. Furthermore, individual blocks may be eliminated, combined with other blocks, or rearranged in any manner without departing from the scope of the subject matter described herein. Aspects of any of the embodiments described above may be combined with aspects of any of the other embodiments described to form other embodiments without losing the desired effect.

[0057] It will be understood that the above description is provided by way of example only, and that various modifications may be made by those skilled in the art. The above specification, examples, and data provide a complete description of the structure and use of exemplary embodiments. While various embodiments have been described above in particular scope or with reference to one or more individual embodiments, those skilled in the art can make many modifications to the disclosed embodiments without departing from the scope of the present specification. Supplementary information Mirror circuit experiment The mirror circuit experiment uses eight logical qubits that are encoded into ten physical qubits. The experiment was conducted on the Quantinuum H1-2 ion trap quantum computer between September 13 and October 4, 2022. Below, we describe our experiments in detail. First, we provide a complete description of the random mirror circuit configuration, followed by additional experimental details. Next, we provide a detailed description of the numerical simulations presented in the text, including the simplified noise model and simulation methodology employed. Finally, we provide numerical evidence that the random circuit used in our experiments is representative of the family of random circuits we have constructed. Random circuit configuration As mentioned above, random unitary circuits are constructed from encoded physical circuits. The unitaries are organized into layers. In each layer, physical qubits are paired (i,j), where i≠j∈[n], and k / 2+1 pairs are generated. For each pair, we uniformly choose σ∈[X,Y,Z], uniformly sample the angle θ∈(0,2π), and JPEG2025540634000056.jpg1096 format, applying a two-qubit rotation to the pair. Logic gates, along with up to four single-qubit Clifford gates, JPEG2025540634000057.jpg All physically compiled using 1366 gates. R Xtb An example of a physical compilation of (θ) is shown in Figure 13(a). Once a physical random unitary is constructed, we map it to the corresponding logical unitary. All physical operators JPEG2025540634000058.jpg1233 represents the logical Pauli operators, and the complete set of relations is shown in equations (a)-(l). The logical operators can be single-bit and two-qubit rotations, or rotations with generators acting on k or k-1 qubits. Single-qubit rotations are compiled directly. Two-qubit rotations are compiled using the two-qubit rotation MS. ij (θ) and Clifford gates for up to four single qubits. A global rotation for k or k-1 single qubits is compiled using the kernel MS ij The (θ) gate is used to compile the phase gadget. Figure 13(b) shows the compiled non-encoded circuit. An example of JPEG2025540634000059.jpg1232 is shown below. Additional experimental details Using the initialization, syndrome measurement, and final measurement circuit construction shown in Figure 1 and the random circuit construction described above, the circuit is first constructed using the gate set {H, S, S †,CNOT,MS(θ)}. These circuits are then compiled into the native gate set of the Quantinuum hardware

[25] using the TKET compiler

[44] . We consider from 4 random layers up to a maximum of 256 layers. When reporting the number of layers, we count both unitary and inverse layers to calculate the total number of layers between initialization and the last measurement. In our experiments with circuits coded with Iceberg code, we insert one round of syndrome measurement between the unitary and inverse layers of 32, 64, 128, and 256 layers, while for 4, 8, and 16 layers, we do not perform intermediate syndrome measurements. These circuits were run for various numbers of iterations, and we report the total number of iterations (measurement shots) performed in each case. For non-encoding circuits with global rotation, there are 300 shots in all cases. Without global rotation, the 4-layer, 8-layer, and 16-layer circuits run 300 shots, the 32-layer circuit runs 400 shots, the 64-layer circuit runs 600 shots, the 128-layer circuit runs 800 shots, and the 256-layer circuit runs 500 shots. Both encoding circuits with and without global rotation use the same number of shots: the 4-layer, 8-layer, 16-layer, and 32-layer circuits run 200 shots, the 64-layer circuit runs 400 shots, the 128-layer circuit runs 800 shots, and the 256-layer circuit runs 500 shots. Numerical simulation Our numerical simulations cover k = 10, 12, 14, and 16 logical qubits. For each k, we consider very deep circuits, from l = 4 layers up to 128 layers. At each l, we generate 32 random mirror circuits that enable global logical rotation. A round of syndrome measurements is inserted every 16 layers. The noisy outputs of these circuits are simulated using the Monte Carlo state vector technique described below. For each circuit, we obtain 32 state vector samples from the error model. We simulate both the uncoded and coded versions of each random circuit and accurately calculate the survival probability for each state vector. Averaging the survival probabilities of these 32 state vector samples yields the estimated survival probability of the random circuit. We simulate a simplified noise model that includes a state preparation and measurement (SPAM) error and a depolarizing error that acts after the gate. The SPAM error is applied after the qubit is initialized and before the measurement. After each single (1q) and two-qubit (2q) gate, a depolarizing error channel is applied to the qubit acted upon by the gate. The operator summation formula for these depolarizing channels is JPEG2025540634000061.jpg41128, where I is the identity matrix and X, Y, and Z are Pauli matrices. Based on random benchmarks on Quantinuum H1-2 hardware, we use the following values ​​for the error channel parameters: Initialization error is the bit-flip error rate p b =4×10 -4 and the measurement error is the bit-flip error rate p b =3×10 -3 and the single-qubit gate error is due to the depolarization rate p 1q =4×10 -4 and the two-qubit gate error is due to the depolarization rate p 2q=3×10 -3 It has. Our noisy simulation is a Monte Carlo state vector simulation. For each noise channel, we randomly select one of the channel's Kraus operators with the correct probability. The noise channel is replaced by this randomly selected Kraus operator. Once this is done for all error channels, the noisy quantum evolution reverts to a unitary operator that can be learned by the state vector simulator. By repeatedly sampling different Kraus operators for the noise channels, we can approximate the full noise evolution. This allows for larger system sizes by avoiding the use of exponentially large density matrices. Our quantum error detection circuit performs measurements of intermediate circuits and post-selection. These are implemented in a computational basis, a state vector simulation using a projector. This allows us to calculate both the discard probability of measurements of intermediate circuits and the normalized post-selection state vector (assuming the discard probability is less than 1). The numerical results presented in this paper were obtained using the Qiskit

[33] state vector simulator. The circuit was constructed using the gate set {H,S,S † ,CNOT,MS(θ)}. We consider the noise model acting on the circuit of this gate set. In both the uncoded and coded cases, the survival probability is calculated exactly from each state vector. In the uncoded case, this is simply the probability amplitude of the all-zero computational basis state. In the coded case, one must first extract the full probability distribution resulting from the computational basis, then decode each computational basis state and sum their contributions to the logically all-zero state. Figure 17 shows the distribution of survival probabilities at each circuit depth using boxplots for 100 random instances with global rotation (left) and without global rotation (right). Stars indicate the performance of the random instances used in the experiments in this paper. Results are obtained from noise simulations using a simplified noise model. Typical examples of instances used in the experiment In our experimental results, we consider a single instance of the random circuit family we described. For a fixed number of layers, we generate one random circuit for the "with global rotation" case and another random circuit for the "without global rotation" case. The circuits generated with different numbers of layers are independent of each other. We numerically prove that these instances are typical instances of the random circuit family. At each depth, we generate 100 instances of two random circuit families, and the observed distribution of survival probabilities is shown as a boxplot in Figure 17. Outliers are identified as points that lie more than 1.5 times the upper (lower) interquartile range from the upper (lower) quartile. Each instance is numerically simulated using the simplified error model and state vector simulation method described in "Numerical Simulations" above. For each circuit, we average over 100 state vector samples from the error model. The random instances used in the experiments are marked with stars in Figure 17. These cases correspond to fixed seeds for the random generator. We can see that none of these instances fall into outliers, and they are spread above and below the median. Logical quantum volume experiment A logical quantum volume (QV) test of 8 qubits encoded with 10 physical qubits was performed using the Iceberg code running on Quantinum's H1-2 ion trap quantum computer. The data presented here was acquired between July 27 and October 8, 2022. Here we present the details of these experiments. First, we provide a brief review of the QV tests, then we describe the preparation of the logic circuit, including the optimizations we employed. Next, we describe the encoding of the QV circuit into Iceberg code. Finally, we present the experimental details and present additional experimental results. Figure 18(a) shows a schematic example of a quantum volume (QV) circuit for N = 8 qubits. The circuit consists of N layers, and within each layer, qubits are randomly paired and pairs are processed by random SU(4) units. Figure 18(b) shows the compression of SU(4) blocks in a QV circuit. A schematic diagram of the first two layers of a six-qubit QV test is shown, where A and B are random SU(4) unitaries. Qubits 4 and 6 are randomly paired in both layers, and A and B operate on the same qubit. These can be combined into a single SU(4) unitary. This typically results in a shorter circuit depth than applying A and B separately. QV Test Overview The QV test is an efficient random sampling scheme for verifying non-classical operations in noisy quantum computers [31, 32]. In this test, random square circuits of the form shown in Figure 18(a) are applied to k qubits. These circuits have k layers, and within each layer qubits are randomly paired and a random SU(4) unitary is applied to the pairs. Finally, all qubits are measured in the computational basis. Each random circuit is simulated without noise to obtain an ideal output distribution, and a set of Heavy Outputs is determined from this ideal distribution. These are computational basis states that occur with a probability higher than the median. The circuit is then run on a noisy quantum processor with a small number of shots (e.g., 100). The frequency of the noisy Heavy Outputs is calculated by counting the number of shots that measure the computational basis states from the set of Heavy Outputs. The frequency of the Heavy Output is averaged across the random circuit, and if the average is greater than 2 / 3, the QV test passes. If a device passes the QV test for k qubits, it is said to be 2 k The average frequency of the Heavy Output is not a measure of fidelity; for a noise-free circuit, it is about 85%, and for a fully depolarized state, it is 50%. Preparation of logical QV circuit We use a quantum volume circuit generated from Qiskit

[33] and perform the "medium" optimization method described in

[32] . Using this method, SU(4) blocks are combined when possible. An example of when this occurs is shown in Figure 18(b). After these optimizations, the SU(4) block is a single qubit rotation JPEG2025540634000062.jpg1039 and two-qubit logical rotation This is done using the TKET compiler [43,44]. At this stage, the logic rotation of a single qubit is further optimized by compressing it as much as possible. For example, a series of gates JPEG2025540634000064.jpg971 is a short series of gates that utilize the same logical rotation. JPEG2025540634000065.jpg939 can be replaced. Furthermore, the Pauli Z rotation that operates immediately after initialization and immediately before measurement can be omitted. Figure 19 shows additional experimental results showing the HeavyOutput frequency of individual quantum volume (QV) circuits in the 0x, 1x, 2x, and 3x syndrome measurements. In each panel, the left axis (depicted in red) shows the HeavyOutput frequency of each circuit after discarding, its cumulative average, and its bootstrap bounds. The pass threshold of 2 / 3 is shown with a dashed line, and 0 and 1 are highlighted with dotted lines. The right axis (depicted with blue bars) shows the number of shots retained after discarding. The 0x syndrome measurement experiment used 75 shots, the 1x syndrome measurement experiment used 100 shots, and the 2x and 3x syndrome measurement experiments used 150 measurement shots. QV circuit encoding A QV circuit, expressed in terms of single- and two-qubit logical rotations, can be directly translated into physical form using equations (a)-(l). This logical circuit is then combined with a set of initialization and measurement instructions. Note that due to the structure of the Iceberg code, where every single-qubit logical X rotation involves physical qubit t and every single-qubit logical Z rotation involves physical qubit b, the compiled physical circuit is not a parallel form of the logical QV circuit. The syndrome measurements are inserted between chunks of the same size of the QV instruction set. In doing so, the hierarchical structure of the QV circuits is not taken into account, which means that the syndrome measurement circuits may be inserted within the QV layer. However, the Hadamard gates and JPEG2025540634000066.jpg1188 MS ij Care must be taken not to split logic operations, such as inserting syndrome measurements between (θ) gates. The final feasible circuit for the k=8 logical QV test operates on 12 physical qubits and has a circuit depth of up to 700, and up to over 1000, depending on the number of syndrome measurements, including up to 350 two-qubit gates. Additional experimental details and results Following the construction of the initialization, syndrome measurement, and final measurement circuit shown in Figure 1 and the construction of the encoding QV circuit described above, the circuit is first constructed using the gate set {H, S, S † ,CNOT,MS(θ)}. These circuits are then compiled into the native gate set of the Quantinum hardware

[25] using the TKET compiler

[44] . The experiments were conducted using 0x, 1x, 2x, and 3x syndrome measurements. For the 0x round of syndrome measurement, the experiment (measurement shots) was repeated 75 times, 1x used 100 shots, and 2x and 3x performed 150 shots. The number of shots was changed with the goal of maintaining 10 to 20 shots for each circuit after discarding, while the discard rate varied depending on the number of syndrome measurements. All circuits are executed to completion, and the intermediate circuit error detection measurements are stored in classical syndrome registers. As the measurements are collected, the results for which errors are detected are discarded. The remaining results are then used to perform the logical operation JPEG2025540634000067.jpg1214 and S Z is post-processed to reconstruct the value of S Z If detects an error, it discards the result. The remaining decoded results are processed to calculate the HeavyOutput frequency. The HeavyOutput frequency and discard rate for individual QV circuits with 0x, 1x, 2x, and 3x syndrome measurements are shown in Figure 19. The reported cumulative averages are calculated using Qiskit

[33] . The bounds shown are calculated using the bootstrap technique described in

[32] . Example: Encoding and compiling a QPE circuit using [6,4,2] code The present invention has been used to demonstrate quantum phase estimation (QPE) including quantum error detection in the quantum system H1 ion trap quantum computer. A Bayesian approach to QPE has been combined with quantum error detection code for [k+2,k,2] to provide encoding and compilation of QPE circuits. This allows for the quantum circuit to be protected by limited quantum resources by discarding erroneous executions. For example, the code for [k+2,k,2] for even k has a code space of [k+2,k,2]. This is a stabilizer code stabilized by JPEG2025540634000068.jpg1036 (called the Iceberg code in

[45] ). In this work, we use a k=4 code, i.e., a [6,4,2] code, to encode four logical qubits. L={1,2,3,4} and A:={a x, a Z The logical qubit and two redundant physical qubits, denoted by}, form a 6-qubit code with T:=L∪A. More specifically, a 3-qubit QPE circuit with one dummy qubit added is encoded into 6 physical qubits. x (a Z It should be noted that the notation t (b) is the same as the most significant t (b) that represents the qubit for encoding. Two additional ancillary qubits are introduced to perform fault-tolerant state preparation, syndrome extraction, and the final measurement, for a total of eight qubits. The two stabilizers are These simultaneous eigenstates, represented by JPEG2025540634000069.jpg1297 and associated with eigenvalue +1, define a logical space of four qubits. X ,S Z Reading -1 when measuring} signals an error that does not commute with the stabilizer operator, and therefore discards the execution of such a circuit. Errors that cannot be detected by the stabilizer (syndrome) measurements cause logic errors that disrupt the encoded system. The encoded quantum state is then expressed by the logical Pauli operators It is processed by JPEG2025540634000070.jpg1395, which is interchangeable with the stabilizer, Follow JPEG2025540634000071.jpg1395. All logical operations are compiled into a universal set of logic gates, which in the form of physical gates is given by

[45] , JPEG2025540634000072.jpg1295Here, for the rotation angle θ and the Pauli operator P, the Pauli exponent operator R P (θ):=e -iθP / 2 We define the structure of the coded QPE circuit below, and explain the explicit compilation of each component. The encoding circuit begins by encoding the initial state. Two additional ancillary qubits are used only to perform fault-tolerant initialization. S of,[ science fiction ] blocks, where s∈N and f∈N represent the number of iterations and the frequency of syndrome measurements, respectively. Following the application of each block, syndrome measurements are made and the encoded state is X ,S Z} is checked to see if it has been stabilized. As soon as one syndrome measurement is read as -1, the circuit execution is stopped. Furthermore, the stabilizer S X in the middle of each block, which acts on the code space as an identity. However, it suppresses physical coherent errors in the form of single-qubit Z rotations that accumulate over time. After all logical unitary operations have been performed, a final measurement is made, ensuring that both stabilizers measure 1 and the logical Pauli expectation value is read out. Some functions of the code have been adapted to take advantage of the capabilities of Quantinuum's H1-1 trapped ion computer

[45] . State preparation, syndrome measurements, and projective measurements are performed in a fault-tolerant manner. The logical operator R is also implemented in a non-fault-tolerant implementation. Pi,Pj(θ) is the sum of the qubits from the single-qubit Clifford gate to the single Molmar-Sørensen MS gate R ZiZj (θ), which was originally implemented in a trapped ion computer, with gate infidelity of 2×10 -3 As shown below, the combination of Quantinuum's high-fidelity MS gate operations and all-to-all connections is expected to result in logic circuit execution with a low logic error rate. Finally, Quantinuum devices feature a conditional exit, or termination, function that immediately halts the execution of a circuit where a classical register is conditional. This feature allows a computation to be discarded as soon as the syndrome measurement detects an error, thereby saving processing time by avoiding the unnecessary execution of the remaining computation. In one example of a Bayesian approach to QPE, measurements are generated from the uncoded QPE circuit shown in FIG. It should be noted that in the non-encoding circuit experiment, there is no fourth qubit, but this is added so that the circuit is encoded with a code of [k+2,k,2], where k must be even. The reason it is initialized to |+> will be explained later with reference to Figure 25. The controlled unitary operations are shown in Figures 21 and 22. In the second equation of each equation, the controlled Pauli exponent operator ctrl-R P (θ) is the following identity It should be noted that JPEG2025540634000073.jpg1694 can be used to decompose it into a product of Pauli exponents. Also, ctrl-R shows only the Pauli operator P with the index where the angle θ is suppressed. P We introduce a simplified notation for the (θ) gate. Z Note that (β) can be absorbed into ctrl-v in FIG. We discuss each component of the encoding circuit in Figure 20 and how they are compiled into universal gates. The encoding circuit is shown in Figure 23. Fault-tolerant protocols are known for state preparation, syndrome measurement, and final measurement in the [k+2,k,2] QED code. Here we briefly comment on the basics and refer to prior literature for details. Exact ground state of the Hartree-Fock state |+00+>(α=-0.07113 JPEG2025540634000074.jpg1225) is fault-tolerantly encoded according to Appendix D of

[46] . ZZ ) gate and two ancillary qubits to detect faults. ·S X and S Z Fault-tolerant syndrome measurements of are performed in the form proposed in

[45] , which uses 12 two-qubit gates and two ancillary qubits. The last measurement is based on the implementation in

[46] . Z It consists of a stabilizer syndrome measurement and a destructive X measurement of all physical qubits. If no errors are detected, the measurement results are post-processed to extract the observables. The measurement circuit has eight two-qubit gates and two ancilla qubits. It is easy to convert ctrl-v in Figure 22 to ctrl-v and compile it to a logic gate. Here, we focus on how to compile ctrl-u. In the case of Figure 24, first, Take JPEG2025540634000075.jpg1067 and convert the Y operator to an X operator, which simplifies compilation. JPEG2025540634000076.jpg1067 can be absorbed in either the initial or final state without affecting the measurement results. Using JPEG2025540634000077.jpg1190, we find the encoded form of Figure 24, where the stabilizer condition S X =S Z=1 is used to reduce the weight of the Pauli operator. Furthermore, we use a fourth logical qubit to initialize it to |+>, which means X4=1. We then use the reduction operator JPEG2025540634000078.jpg1282 is found, which is Y1Y in the subspace. az and S X =S Z =X4=1 holds. Therefore, we compile all logical operators into two-qubit Pauli exponent operators, and obtain Figure 25, which is the native two-qubit gate R ZZ (θ) and is easily implemented by a single qubit gate. Each ctrl-u in Figure 25 uses six two-qubit gates. This is achieved by providing a compilation method for an odd number of logical qubits, including a redundant qubit d, and utilizing the state of qubit d for circuit optimization, as shown below. Using the same terminology as earlier in this patent specification, the error detection function includes one or more products of pairs of k qubits. JPEG2025540634000079.jpg121109 Bibliography on Quantum Computing [Chao2020] R. Chao, and BW Reichardt, 2020. Flag fault-tolerant error correction for any stabilizer code. PRX Quantum, 1(1), p.010302. [1] Gottesman, D. An introduction to quantum error correction and fault-tolerant quantum computation (2009). URL https: / / arxiv.org / abs / 0904.2557. [2] Lidar, DA & Brun, TA Quantum Error Correction (Cambridge University Press, 2013). [3] Orzel, C. Quantum Simulation. 2399-2891 (IOP Publishing, 2017). URL https: / / dx.doi.org / 10.1088 / 978-0-7503-1516-6. [4] Harrow, A. W., Hassidim, A. & Lloyd, S. Quantum algorithm for linear systems of equations. Phys. Rev. Lett.103, 150502 (2009). URL https: / / link.aps.org / doi / 10.1103 / PhysRevLett.103.150502. [5] Shor, P. Algorithms for quantum computation: discrete logarithms and factoring. In Proceedings 35th Annual Symposium on Foundations of Computer Science, 124-134 (1994). [6] Gidney, C. & Eker a, M. How to factor 2048 bit RSA integers in 8 hours using 20 million noisy qubits. Quantum 5, 433 (2021). URL https: / / doi.org / 10.22331 / q-2021-04-15-433. [7] Allcock, J. et al. The prospects of monte carlo antibody loop modelling on a fault-tolerant quantum computer. Frontiers in Drug Discovery 2 (2022). URL https: / / www.frontiersin.org / articles / 10.3389 / fddsv.2022.908870. [8] Chen, Z. et al. Exponential suppression of bit or phase errors with cyclic error correction. Nature 595, 383-387 (2021). URL https: / / doi.org / 10.1038%2Fs41586-021-03588-y. [9] Ryan-Anderson, C. et al. Realization of real-time faulttolerant quantum error correction. Phys. Rev. X 11,041058 (2021). URL https: / / link.aps.org / doi / 10.1103 / PhysRevX.11.041058.

[10] Acharya, R. & et al. Suppressing quantum errors by scaling a surface code logical qubit (2022). URL https: / / arxiv.org / abs / 2207.06431.

[11] Postler, L. et al. Demonstration of fault-tolerant universal quantum gate operations. Nature 605,675-680 (2022). URL https: / / doi.org / 10.1038%2Fs41586-022-04721-1.

[12] Ryan-Anderson, C. et al. Implementing fault-tolerant entangling gates on the five-qubit code and the color code (2022). URL https: / / arxiv.org / abs / 2208.01863.

[13] Suzuki, Y., Endo, S., Fujii, K. & Tokunaga, Y. Quantum error mitigation as a universal error reduction technique: Applications from the nisq to the faulttolerant quantum computing eras. PRX Quantum 3, 010345 (2022). URL https: / / link.aps.org / doi / 10.1103 / PRXQuantum.3.010345.

[14] Cirac, J. I. & Zoller, P. Goals and opportunities in quantum simulation. Nature physics 8, 264-266 (2012). URL https: / / doi.org / 10.1038 / nphys2275.

[15] Harrow, A. W. & Montanaro, A. Quantum computational supremacy. Nature 549, 203-209 (2017). URL https: / / doi.org / 10.1038%2Fnature23458.

[16] Lund, A. P., Bremner, M. J. & Ralph, T. C. Quantum sampling problems, BosonSampling and quantum supremacy. npj Quantum Information 3 (2017). URL https: / / doi.org / 10.1038%2Fs41534-017-0018-2.

[17] Knill, E. Fault-tolerant postselected quantum computation: Schemes (2004). URL https: / / arxiv.org / abs / quant-ph / 0402171.

[18] Knill, E. Fault-tolerant postselected quantum computation:Threshold analysis (2004). URL https: / / arxiv.org / abs / quant-ph / 0404104.

[19] Urbanek, M., Nachman, B. & de Jong, W. A. Error detection on quantum computers improving the accuracy of chemical calculations. Phys. Rev. A 102,022427 (2020). URL https: / / link.aps.org / doi / 10.1103 / PhysRevA.102.022427.

[20] Schindler, P. et al. A quantum information processor with trapped ions. New Journal of Physics 15, 123012 (2013). URL https: / / doi.org / 10.1088 / 1367-2630 / 15 / 12 / 123012.

[21] Bruzewicz, C. D., Chiaverini, J., McConnell, R. & Sage,J. M. Trapped-ion quantum computing: Progress and challenges. Applied Physics Reviews 6, 021314 (2019).URL https: / / doi.org / 10.1063 / 1.5088164.

[22] Grassl, M., Beth, T. & R¨otteler, M. On optimal quantum codes. International Journal of Quantum Information 02, 55-64 (2004). URL https: / / doi.org / 10.1142 / S0219749904000079.

[23] Molmer, K. & Sorensen, A. Multiparticle entanglement of hot trapped ions. Phys. Rev. Lett. 82, 1835-1838 (1999). URL https: / / link.aps.org / doi / 10.1103 / PhysRevLett.82.1835.

[24] Quantinuum H1-2. https: / / www.quantinuum.com / July 27-Oct 8 2022.

[25] Pino, J. M. et al. Demonstration of the trapped-ion quantum ccd computer architecture. Nature 592, 209-213 (2021).

[26] Linke, N. M. et al. Fault-tolerant quantum error detection. Science Advances 3, e1701074 (2017). URL https: / / www.science.org / doi / abs / 10.1126 / sciadv.1701074.

[27] Hines, J. et al. Demonstrating scalable randomized benchmarking of universal gate sets (2022). URL https: / / arxiv.org / abs / 2207.07272.

[28] Proctor, T. et al. Scalable randomized benchmarking of quantum computers using mirror circuits (2021). URL https: / / arxiv.org / abs / 2112.09853.

[29] Chao, R. & Reichardt, B. W. Quantum error correction with only two extra qubits. Phys. Rev. Lett. 121, 050502 (2018). URL https: / / link.aps.org / doi / 10.1103 / PhysRevLett.121.050502.

[30] Proctor, T., Rudinger, K., Young, K., Nielsen, E. & Blume-Kohout, R. Measuring the capabilities of quantum computers. Nature Physics 18, 75-79 (2022).

[31] Cross, A. W., Bishop, L. S., Sheldon, S., Nation, P. D. & Gambetta, J. M. Validating quantum computers using randomized model circuits. Phys. Rev. A 100, 032328 (2019). URL https: / / link.aps.org / doi / 10.1103 / PhysRevA.100.032328.

[32] Baldwin, C. H., Mayer, K., Brown, N. C., Ryan-Anderson, C. & Hayes, D. Re-examining the quantum volume test: Ideal distributions, compiler optimizations, confidence intervals, and scalable resource estimations. Quantum 6, 707 (2022). URL https: / / doi.org / 10.22331 / q-2022-05-09-707.

[33] Qiskit Python Package (v0.37.0) https: / / pypi.org / project / qiskit / (2022).

[34] Itoko, T. & Imamichi, T. Scheduling of operations in quantum compiler (2020). URL https: / / arxiv.org / abs / 2011.04936.

[35] Gokhale, P. et al. Quantum fan-out: Circuit optimizations and technology modeling (2020). URL https: / / arxiv.org / abs / 2007.04246.

[36] Lao, L. & Browne, D. E. 2qan: A quantum compiler for 2-local qubit hamiltonian simulation algorithms (2021). URL https: / / arxiv.org / abs / 2108.02099.

[37] Nannicini, G., Bishop, L. S., Gunluk, O. & Jurcevic, P. Optimal qubit assignment and routing via integer programming (2021). URL https: / / arxiv.org / abs / 2106.06446.

[38] Stricker, R. et al. Experimental deterministic correction of qubit loss. Nature 585, 207-210 (2020).

[39] Farhi, E., Goldstone, J. & Gutmann, S. A quantum approximate optimization algorithm (2014). URL https: / / arxiv.org / abs / 1411.4028.

[40] Amaro, D. et al. Filtering variational quantum algorithms for combinatorial optimization. Quantum Science and Technology 7, 015021 (2022). URL https: / / doi.org / 10.1088 / 2058-9565 / ac3e54.

[41] Benedetti, M., Lloyd, E., Sack, S. & Fiorentini, M. Parameterized quantum circuits as machine learning models. Quantum Science and Technology 4, 043001 (2019). URL https: / / doi.org / 10.1088 / 2058-9565 / ab4eb5.

[42] van de Wetering, J. Constructing quantum circuits with global gates. New Journal of Physics 23, 043015 (2021). URL https: / / doi.org / 10.1088 / 1367-2630 / abf1b3.

[43] Sivarajah, S. et al. t|ket>: a retargetable compiler for NISQ devices. Quantum Science and Technology 6, 014003 (2020). URL https: / / doi.org / 10.1088 / 20589565 / ab8e92.

[44] Pytket Python Package (v1.4.1) https: / / pypi.org / project / pytket / , Pytket-Quantinuum extension(v0.4.0) https: / / pypi.org / project / pytket-quantinuum / , Pytket-Qiskit extension (v0.26.0) https: / / pypi.org / project / pytket-qiskit / (2022).

[45] C. N. Self, M. Benedetti, and D. Amaro, Protecting Expressive Circuits with a Quantum Error Detection Code (2022), arXiv:2211.06703 [quant-ph].

[46] R. Chao and B. W. Reichardt, Quantum error correction with only two extra qubits, Phys. Rev. Lett. 121, 050502 (2018)

Claims

1. 1. A computer-implemented method for performing quantum operations, including unitary operations of interest, including quantum error detection, comprising: obtaining an approximation of a finite gate decomposition of a unitary operation of interest for a quantum circuit of k logical qubits; converting, using a quantum error detection code, a finite gate decomposition for a quantum circuit of k logical qubits into an instruction set for executing a quantum circuit of n physical qubits, where n=k+2 and the n physical qubits include k physical qubits corresponding to the k logical qubits, physical qubit t, and physical qubit b, where the quantum error detection code encodes the k logical qubits onto the n physical qubits, and where the quantum error detection code encodes two stabilizer decompositions for the physical qubits. a stabilizer cord including: logical qubit operators of said quantum error detection code teeth, is defined by, where: is a Pauli X and Z single logical qubit operator for logical qubit q, where the set of instructions includes a plurality of instruction blocks, each instruction block including at least one instruction for executing, by a quantum computing system, at least one quantum gate in an n-qubit quantum circuit; performing, with the quantum computing system, fault-tolerant initialization of the logical states of the k logical qubits using the n qubit quantum circuit, the first ancilla qubit, and the quantum error detection code; executing, by the quantum computing system, each instruction block of the plurality of instruction blocks on a quantum circuit of n physical qubits; After each instruction block, the quantum computing system calculates S for the n physical qubits using a first ancilla qubit and a second ancilla qubit, respectively. Ｚ Stabilizer and S Ｘ performing a fault-tolerant syndrome measurement of the stabilizer; After all instruction blocks of the plurality of instruction blocks have been applied to the n physical qubits, the quantum computing system measures the n physical qubits using a first ancilla qubit and a second ancilla qubit to perform a logical operation on each of the n physical qubits. and performing a fault-tolerant state measurement of and, based on a measurement of the first ancilla qubit or the second ancilla qubit indicating a failure during any of the fault-tolerant steps of performing initialization, syndrome measurement, or state measurement, the computation result is discarded and the quantum operation is restarted. method.

2. 10. The method of claim 1, wherein the quantum computing system is a trapped ion quantum computer having all-to-all connections between qubits.

3. 3. The method of claim 1, wherein the finite gate decomposition is composed of unitary gates of a universal gate set that includes a plurality of gates that can be encoded onto the physical qubits using one or more two-qubit Molmer-Sørensen gates and up to four Clifford group gates.

4. 4. The method of claim 3, wherein the universal gate set includes only single-qubit logical rotations, two-qubit logical rotations, and global rotations for k or k-1 logical qubits.

5. Each logical operator The fault-tolerant state measurement of Ｘ Measure the stabilizer, measure n physical qubits, and post-process the results to obtain S Ｚ Stabilizers and logical operators After the last instruction block is executed, it is combined with the last syndrome measurement by decoding The quantum computing system discards the computation result during the fault-tolerant step and returns a decrypted S indicating a failure. Ｚ The method of any one of claims 1 to 4, configured to restart the quantum operation based on a value of a stabilizer.

6. 1. A system for performing quantum operations, including unitary operations of interest, including quantum error detection, the system comprising: Classical computing systems, a quantum computing system including n primary physical qubits, a first ancilla qubit, and a second ancilla qubit, the n primary physical qubits including k physical qubits, one physical qubit t, and one physical qubit b, the quantum computing system configured to implement a quantum circuit in the n physical qubits, including the k physical qubits, the physical qubit t, and the physical qubit b, using the first ancilla qubit and the second ancilla qubit; The classical computing system comprises: configured to obtain an approximation of a finite gate decomposition of a unitary operation of interest for a quantum circuit of k logical qubits; and a quantum error detection code configured to convert the finite gate decomposition for a quantum circuit of k logical qubits into an instruction set for executing the quantum circuit of the n physical qubits in the quantum computing system, wherein the quantum error detection code encodes the k logical qubits into the n physical qubits, and the quantum error detection code is configured to convert the finite gate decomposition for a quantum circuit of k logical qubits into an instruction set for executing the quantum circuit of the n physical qubits in the quantum computing system using a quantum error detection code .... a stabilizer cord including: logical qubit operators of said quantum error detection code teeth, is defined by, where: is the Pauli X and Z single logical qubit operators for logical qubit q, the instruction set includes a plurality of instruction blocks, each instruction block including at least one instruction for executing, by the quantum computing system, at least one quantum gate in an n-qubit quantum circuit; configured to transmit the set of instructions to the quantum computing system; The quantum computing system includes: receiving the instruction set; performing fault-tolerant initialization of the logical states of the k logical qubits using the n qubit quantum circuit, the first ancilla qubit, and the quantum error detection code; executing each instruction block of the plurality of instruction blocks in the quantum circuit of n physical qubits; After each instruction block, a first ancilla qubit and a second ancilla qubit are used to respectively calculate S for the n physical qubits. Ｚ Stabilizer and S Ｘ Perform fault-tolerant syndrome measurements of stabilizers; After all of the instruction blocks of the plurality of instruction blocks have been applied to the n physical qubits, measuring the n physical qubits using a first ancilla qubit and a second ancilla qubit generates a logical operator Perform fault-tolerant state measurements of configured to discard the computation result and restart the quantum operation during any of the fault-tolerant steps of performing initialization, syndrome measurement, or state measurement based on a measurement of either the first ancilla qubit or the second ancilla qubit indicating a failure; system.

7. 7. The system of claim 6, wherein the quantum computing system is a trapped ion quantum computer having all-to-all connections between qubits.

8. 8. The system of claim 6 or 7, wherein the qubits of the quantum computing system include only the n physical qubits and two ancilla qubits.

9. The system of any one of claims 6 to 8, wherein the finite gate decomposition is composed of unitary gates of a universal gate set including a plurality of gates that can be encoded onto the physical qubits using only two-qubit Molmer-Sorensen gates and up to four Clifford group gates, and optionally the universal gate set includes a global rotation for k or k-1 logical qubits.

10. 10. The system of claim 9, wherein the universal gate set includes only single-qubit logical rotations, two-qubit logical rotations, and global rotations for k or k-1 logical qubits.

11. The quantum computing system further comprises: Ｘ After the last instruction block is executed, each logical operator and configured to combine the fault-tolerant state measurement of the first parameter with a final syndrome measurement and transmit the result to the classical computing system; The classical computing system further post-processes the transmitted results to generate the S Ｚ Stabilizers and logical operators and transmitting an indicator of the decoded stabilizer value to the quantum computing system; 11. The system of claim 6, wherein the quantum computing system is further configured to discard the computation result and restart operation based on a value of the decoded stabilizer indicating a failure.

12. 1. A quantum computing system for performing quantum operations, including unitary operations of interest, including quantum error detection, comprising: the quantum computing system includes n primary physical qubits, a first ancilla qubit, and a second ancilla qubit, the primary physical qubits including k physical qubits, physical qubit t, and physical qubit b; the quantum computing system is configured to implement a quantum circuit with n physical qubits, including k physical qubits, t physical qubits, and b physical qubits, using the first ancilla qubit and the second ancilla qubit; The quantum computing system includes: receiving a set of instructions from a classical computing system for converting a finite gate decomposition for a quantum circuit of k logical qubits into a quantum circuit of n physical qubits of the quantum computing system using a quantum error detection code, wherein the quantum error detection code is a stabilizer code that encodes the k logical qubits into the n physical qubits and includes two stabilizers for the physical qubits; wherein the instruction set includes a plurality of instruction blocks, each instruction block including at least one instruction for executing, by the quantum computing system, at least one quantum gate in an n-qubit quantum circuit; performing fault-tolerant initialization of the logical states of the k logical qubits using the n qubit quantum circuit, the first ancillary circuit, and the quantum error detection code; Executing each instruction block of the plurality of instruction blocks in the quantum circuit of the n physical qubits; After each instruction block, the first ancilla qubit and the second ancilla qubit are used to respectively calculate S Ｚ Stabilizer and S Ｘ Perform fault-tolerant syndrome measurements of stabilizers; After all of the instruction blocks of the plurality of instruction blocks are applied to the n physical qubits, each logical operator is calculated using the first ancilla qubit and the second ancilla qubit by measuring the n physical qubits. configured to perform fault-tolerant state measurement of The quantum computing system is configured to discard the computation result based on an ancillary measurement indicating a failure, and is configured to discard the computation result and restart the quantum operation during any of the fault-tolerant steps of performing initialization, syndrome measurement, or state measurement. Quantum computing system.

13. the k logical qubits are encoded into an even number of physical qubits; an odd number of logical qubits is encoded onto an even number of physical qubits by providing a redundant qubit d; 13. The quantum computing system of claim 12, wherein the state of qubit d is used for circuit optimization.

14. the ancilla qubits include an X qubit and a Z qubit; X is all the qubits It acts on Z is all the qubits 14. A quantum computing system according to claim 12 or 13, which operates on

15. The product of the logical operators is:

15. The quantum computing system of claim 14, comprising one or more products of pairs of the k logical qubits of

16. 13. The quantum computing system of claim 12, wherein the at least one quantum gate in the n-qubit quantum circuit of each instruction block comprises one of a two-qubit Molmer-Sorensen gate or a single-qubit Clifford group gate.

17. The quantum computing system further comprises: S for the n physical qubits Ｘ By measuring the stabilizer and measuring the n physical qubits, each logical operator Combine the fault-tolerant measurements of with the last syndrome measurements, Send the results to a classical computing system; The decrypted S Ｚ Receives a stabilizer value indicator, Discard the calculation result and indicate failure. Ｚ 17. The quantum computing system of claim 12, wherein the operation is resumed based on the value of the stabilizer.

18. 1. A quantum computing system including a quantum computing device coupled to a classical computing device, the classical computing device configured to receive input data therefrom and transmit output data therefrom; the classical computing device is configured to process at least one computational task included in the input data by generating a corresponding Ansatz that defines initial values ​​for k quantum bits, and that, when executed, configures a quantum circuit within the quantum computing device that operates on the k quantum bits; the quantum computing device is configured to execute a quantum circuit starting from the Ansatz to generate a computation result for the k qubits, the k qubits being measured by the quantum computing device to generate measured k qubit values; the quantum computing device is configured to transmit the measured k qubit values ​​to the classical computing device for use in other computations in the quantum computing system and / or for inclusion in the output data; the quantum computing device is configured to complement k qubits with e ancilla qubits and ansatz qubits in the quantum circuit; the quantum computing device is configured to include additional gates in the quantum circuit for coupling intermediate states of the k qubits to e ancilla qubits with quantum error detection during execution of the quantum circuit; the quantum computing device is configured, upon completion of execution of the quantum circuit, to measure e ancilla qubits to generate measured e ancilla qubit values; the quantum computing system is configured to process the measured values ​​of the e ancilla qubits to determine whether an error occurred during execution of the quantum circuit; The quantum computing system is configured to, if the quantum circuit is executed in an error state that exceeds an error threshold of the quantum operation, discard the measured values ​​of the k qubits and repeat the Ansatz and quantum circuit calculations. Quantum computing system.

19. 20. The quantum computing system of claim 18, comprising two e ancilla qubits to complete the quantum circuit.

20. 20. The quantum computing system of claim 18 or 19, wherein the error detection functionality is configured to generate values ​​of the measured e ancilla qubits as a function of intermediate states of all k qubits during execution of the quantum circuit.

21. 20. The quantum computing system of claim 18 or 19, wherein the error detection functionality is configured to generate values ​​of the measured e ancilla qubits as a function of pairs of intermediate states of the k qubits during execution of the quantum circuit.

22. 22. The quantum computing system of claim 18, 19, or 21, wherein the error detection functionality is configured to generate values ​​of the measured e ancilla qubits in response to a subset of intermediate states of the k qubits during execution of the quantum circuit.

23. the e ancilla qubits include an X qubit and a Z qubit; where X is the total number of qubits It acts on Z is all the qubits 23. A quantum computing system according to any one of claims 20, 21 or 22, operative on

24. 24. The quantum computing system of claim 23, wherein the error detection function uses a code having the property that large weight products of logical operators reduce to encoded operations of small weight.

25. The error detection function is 25. The quantum computing system of claim 24, comprising one or more products of pairs of:

26. 1. A method of configuring a quantum computing system to detect errors in quantum operations, comprising: the quantum computing system includes a quantum computing device connected to a classical computing device; the classical computing device is configured to receive input data therefrom and transmit output data therefrom; The method comprises: (a) configuring the classical computing device to process at least one computational task contained in input data by generating corresponding Ansatzes that define initial values ​​for k quantum bits, and configuring a quantum circuit within the quantum computing device that, when executed, operates on the k quantum bits; (b) configuring the quantum computing device to execute the quantum circuit starting from the Ansatz to generate a computation result for the k qubits, the computation result for the k qubits being measured by the quantum computing device to generate measured k qubit values; (c) configuring the quantum computing device to transmit the measured k qubit values ​​to the classical computing device for use in other computations in the quantum computing system and / or for inclusion in the output data; The method further comprises: (d) configuring the quantum computing device to complement the k qubits with e ancilla qubits and ansatz qubits in the quantum circuit; (e) configuring the quantum computing device to include additional gates in the quantum circuit for coupling intermediate states of the k qubits to the e ancilla qubits with qubit error detection during execution of the quantum circuit; (f) configuring a quantum computing device to, upon completion of execution of the quantum circuit, measure the e ancilla qubits and generate values ​​for the e measured ancilla qubits; (g) configuring a quantum computing system to process the measured e ancilla qubit values ​​to determine whether an error occurred during execution of the quantum circuit; (h) configuring the quantum computing system to, if the quantum circuit executes with an error condition that exceeds an error threshold of the quantum operation, discard the measured k qubit values ​​and repeat the Ansatz and quantum circuit calculation; A method comprising:

27. 27. The method of claim 26, wherein two e ancilla qubits are included to complete the quantum circuit.

28. 28. The method of claim 26 or 27, wherein the method comprises configuring an error detection function to generate values ​​of the measured e ancilla qubits in response to all intermediate states of the k qubits during execution of the quantum circuit.

29. 29. The method of any one of claims 26, 27 or 28, wherein the error detection functionality is configured to generate values ​​of the measured e ancilla qubits in response to pairs of the k qubits during execution of the quantum circuit.

30. 28. The method of claim 26 or 27, wherein the method comprises configuring an error detection function to generate values ​​of the measured e ancilla qubits in response to a subset of intermediate states of the k qubits during execution of the quantum circuit.

31. the e ancilla qubits include an X qubit and a Z qubit; X is all the qubits It acts on Z is all the qubits The method of claim 26, wherein the method acts on

32. 32. The method of claim 31, wherein the error detection function uses a code having the property that large weight products of logical operators reduce to coded operations of small weight.

33. The method comprises:

33. The method of claim 32, comprising configuring the error detection function to include one or more products of pairs of:

34. 1. A software product for execution in a quantum computing system including a quantum computing device connected to a classical computing device, comprising: The software product is configured, when executed, to perform the method of any one of claims 26 to 33. Software products.

35. 1. A quantum circuit for execution in a quantum computing device of a quantum computing system, comprising: The quantum circuit is configured to include an additional e ancilla qubits for performing the method of any one of claims 26 to 33. quantum circuit.

Images