FET DRAM with backside bitlines

Abstract

A semiconductor structure is provided that includes a backside bit line connected to a dynamic random access memory (DRAM) cell that includes a plurality of field effect transistors (FETs) and a plurality of DRAM capacitors present on the front side of the structure.

Description

[Background technology]

[0001] This application relates to semiconductor technology, and more particularly to semiconductor structures including dynamic random access memory (DRAM) cells and bit lines connected to the backside of the DRAM cells.

[0002] A conventional vertical field effect transistor (VFET) is a device in which the source-drain current flows in a direction perpendicular to the substrate surface. In such devices, a vertical semiconductor fin (or pillar) defines a channel with the source and drain located on opposite sides of the semiconductor fin (or pillar). VFETs are an attractive option for technology scaling beyond 7 nm technology, offering potential advantages over conventional FinFETs in terms of density, performance, power consumption, and integration. For example, VFETs are used in DRAM cells, especially 4F 2 It can be used as a component of a DRAM cell having the cell architecture. Summary of the Invention

[0003] A semiconductor structure is provided that includes a backside bitline connected to a DRAM cell that includes a plurality of FETs, and a plurality of DRAM capacitors present on the front side of the structure. Because the backside bitline is a conductive metal-containing material, the structure has low bitline resistance that meets current performance specifications. 2 In conventional DRAM cell architectures, the bit lines connected to the DRAM cells are doped polysilicon layers that result in high bit line resistance, which does not meet current performance specifications.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment of the present application, the semiconductor structure includes a DRAM cell including a plurality of FETs and a plurality of DRAM capacitors, and at least one bit line comprised of a conductive metal-containing material disposed on the backside of the DRAM cell. The term "backside" refers to the portion of the structure that includes backside wiring components, such as bit lines, disposed on the side of the wafer that does not include active devices, i.e., DRAM cells; the active devices are present on the front side of the wafer, and the present structure has a low bit line capacitance as mentioned above.

[0005] In the present embodiment, the DRAM cell is 2 where F is equal to the gate half pitch. In this application, F denotes the feature size of the gate structure, and the gate pitch is determined by measuring the distance from one point on a gate structure to the same point on an adjacent gate structure. Therefore, the DRAM cells of this application have a high density.

[0006] In an embodiment of the present application, each DRAM capacitor of the plurality of DRAM capacitors is a stacked capacitor, which allows a means for scaling DRAM cells and providing higher density in a smaller unit area.

[0007] In embodiments of the present application, the structure may further include a backside interconnect line (BEOL) structure contacting the at least one bitline, where the backside BEOL structure is a backside power distribution network that provides power to the FETs.

[0008] In an embodiment of the present application, each FET of the plurality of FETs is a vertical FET (VFET) including a vertical semiconductor channel material structure, a gate structure disposed on each side of the vertical semiconductor channel material structure, a first source / drain region disposed at a first end of the vertical semiconductor channel material structure, and a second source / drain region disposed at a second end of the vertical semiconductor channel material structure opposite the first end of the vertical semiconductor channel material structure. The FET including the vertical semiconductor channel material structure is the 4F2 This allows for the creation of an architecture in which current flows vertically through a vertical semiconductor channel material structure.

[0009] In some embodiments, the vertical semiconductor channel material structure, the first source / drain region, and the second source / drain region are a single structure and are composed of the same semiconductor material. In other embodiments, the first and second source / drain regions are formed (e.g., epitaxially grown) on opposite sides of the vertical semiconductor channel material structure.

[0010] In an embodiment of the present application, the structure may further include a front-side source / drain contact structure contacting the first source / drain region and connecting the first source / drain region to one of the plurality of DRAM capacitors.

[0011] In some embodiments herein, the at least one bit line is in direct contact with the second source / drain region. In other embodiments herein, the at least one bit line is in direct contact with a backside source / drain contact structure disposed on the second source / drain region.

[0012] In some embodiments of the present application, both the first source / drain region and the second source / drain region have non-faceted surfaces, the non-faceted surfaces being opposite surfaces of the first source / drain region and the second source / drain region that contact the vertical semiconductor channel material structure.

[0013] In some embodiments of the present application, the structure may further include a dielectric spacer disposed along a sidewall of the first source / drain region.

[0014] In some embodiments of the present application, each DRAM capacitor of the plurality of DRAM capacitors is embedded in a front-side interconnect (BEOL) structure. In such embodiments, the structure may further include a carrier wafer disposed on the front-side BEOL structure. In such embodiments, the carrier wafer is separated from each DRAM capacitor of the plurality of DRAM capacitors by portions of the front-side BEOL structure.

[0015] In some embodiments of the present application, each DRAM capacitor of the plurality of DRAM capacitors resides in a front-side inter-layer dielectric material layer. In such embodiments, each DRAM capacitor extends entirely through the front-side inter-layer dielectric material layer. In such embodiments, the structure may further include a carrier wafer disposed on the front-side inter-layer dielectric material layer.

[0016] In some embodiments of the present application, each FET includes a gate structure disposed on each side of the vertical semiconductor channel material structure, where the gate structure includes a gate dielectric material layer in direct contact with a sidewall of the vertical semiconductor channel material structure, and a gate electrode disposed laterally adjacent to the gate dielectric material layer, where the gate electrode includes at least a work function metal layer. In such embodiments, a gate polysilicon layer may be located between the gate dielectric material layer and the gate electrode.

[0017] In some embodiments of the present application, the structure may further include a first dielectric spacer disposed on a surface of the gate structure and contacting a sidewall of the vertical semiconductor channel material structure, and a second dielectric spacer disposed on another surface of the gate structure and contacting a sidewall of the vertical semiconductor channel material structure.

[0018] In addition to providing a semiconductor structure, the present application also provides methods for forming the same. The present methods, including both front-side and back-side processing, are described in more detail herein below. [Brief explanation of the drawings]

[0019] [Figure 1]FIG. 1 is a cross-sectional view of an exemplary structure utilized in accordance with an embodiment of the present application, the exemplary structure including a plurality of vertical semiconductor channel material structures extending upward from a surface of an etch stop layer disposed on a surface of a base semiconductor substrate.

[0020] [Figure 2] FIG. 2 is a cross-sectional view of the example structure shown in FIG. 1 after forming a first dielectric spacer, where the first dielectric spacer contacts a lower portion of each vertical semiconductor channel material structure of the plurality of vertical semiconductor channel material structures.

[0021] [Figure 3] 3 is a cross-sectional view of the exemplary structure shown in FIG. 2 after forming a gate structure material layer on the first dielectric spacers and along and above the sidewalls of each vertical semiconductor channel material structure.

[0022] [Figure 4] 4 is a cross-sectional view of the exemplary structure shown in FIG. 3 after patterning a gate structure material layer to provide a gate structure along a sidewall of each vertical semiconductor channel material structure of the plurality of vertical semiconductor channel material structures.

[0023] [Figure 5] 5 is a cross-sectional view of the exemplary structure shown in FIG. 4 after forming a first front-side inter-level dielectric (ILD) material layer laterally adjacent each gate structure.

[0024] [Figure 6] 6 is a cross-sectional view of the exemplary structure shown in FIG. 5 after removing a hard mask cap overlying each vertical semiconductor channel material structure of the plurality of vertical semiconductor channel material structures.

[0025] [Figure 7] 7 is a cross-sectional view of the exemplary structure shown in FIG. 6 after recessing respective gate structures that physically expose upper sidewall portions of each vertical semiconductor channel material structure of the plurality of vertical semiconductor channel material structures.

[0026] [Figure 8] 8 is a cross-sectional view of the exemplary structure shown in FIG. 7 after forming a second dielectric spacer laterally adjacent to a physically exposed upper sidewall portion of each vertical semiconductor channel material structure of the plurality of vertical semiconductor channel material structures and forming first source / drain regions extending upward from a top surface of each vertical semiconductor channel material structure of the plurality of vertical semiconductor channel material structures.

[0027] [Figure 9] FIG. 9 is a cross-sectional view of the exemplary structure shown in FIG. 8 after forming a second front-side ILD material layer having front-side contact structures embedded therein, each front-side contact structure contacting one of the first source / drain regions.

[0028] [Figure 10] 10 is a cross-sectional view of the exemplary structure shown in FIG. 9 after forming front-side interconnect (BEOL) structures with DRAM capacitors embedded therein, each DRAM capacitor contacting one of the front-side contact structures, and forming a carrier wafer over the front-side BEOL structures.

[0029] [Figure 11] 11 is a cross-sectional view of the exemplary structure shown in FIG. 10 after flipping the wafer 180 degrees to physically expose the backside of the base semiconductor substrate.

[0030] [Figure 12] 12 is a cross-sectional view of the exemplary structure shown in FIG. 11 after removing the base semiconductor substrate to physically expose the etch stop layer.

[0031] [Figure 13] 13 is a cross-sectional view of the exemplary structure shown in FIG. 12 after removing the etch stop layer to physically expose a horizontal surface of each vertical semiconductor channel material structure of the plurality of vertical semiconductor channel material structures.

[0032] [Figure 14]14 is a cross-sectional view of the exemplary structure shown in FIG. 13 after forming second source / drain regions on the physically exposed horizontal surfaces of each vertical semiconductor channel material structure of the plurality of vertical semiconductor channel material structures.

[0033] [Figure 15] FIG. 15 is a cross-sectional view of the example structure shown in FIG. 14 after forming backside bit lines contacting each second source / drain region and forming backside BEOL structures on the backside bit lines.

[0034] [Figure 16] FIG. 1 is a cross-sectional view of an exemplary structure utilized in another embodiment of the present application, the exemplary structure including a base semiconductor substrate, an etch stop layer disposed on the base semiconductor substrate, and a semiconductor material layer having a plurality of upper mesas disposed on the etch stop layer.

[0035] [Figure 17] 17 is a cross-sectional view of the exemplary structure shown in FIG. 16 after forming dielectric spacers along at least the sidewalls of each upper mesa portion of the semiconductor material layer.

[0036] [Figure 18] FIG. 18 is a cross-sectional view of the exemplary structure shown in FIG. 17 after patterning the semiconductor material layer using the dielectric spacers and the upper mesa portion of the semiconductor material layer as a combined etch mask, where the patterning forms a plurality of semiconductor material pillars on the remaining portion of the semiconductor material layer.

[0037] [Figure 19] 19 is a cross-sectional view of the exemplary structure shown in FIG. 18 after each semiconductor material pillar has been trimmed to provide a vertical semiconductor material channel structure, each vertical semiconductor material channel structure being disposed between an upper mesa portion of the semiconductor material layer and a remainder of the semiconductor material layer.

[0038] [Figure 20]20 is a cross-sectional view of the exemplary structure shown in FIG. 19 after forming a gate dielectric material layer and a gate polysilicon layer.

[0039] [Figure 21] FIG. 21 is a cross-sectional view of the example structure shown in FIG. 20 after performing a breakthrough etching process that removes the gate dielectric material layer, remaining portions of the semiconductor material layer, the etch stop layer, and portions of the base semiconductor substrate; the remaining semiconductor material layer that is not etched and is protected by the combined etch mask provides a bottom mesa portion of the semiconductor material layer.

[0040] [Figure 22] 22 is a cross-sectional view of the exemplary structure shown in FIG. 21 after forming a gap-fill dielectric material layer.

[0041] [Figure 23] 23 is a cross-sectional view of the exemplary structure shown in FIG. 22 after recessing a gap-fill dielectric material layer.

[0042] [Figure 24] 24 is a cross-sectional view of the exemplary structure shown in FIG. 23 after forming a gate metal layer on the recessed gap-fill dielectric material layer laterally adjacent to and in direct physical contact with the gate polysilicon layer.

[0043] [Figure 25] 25 is a cross-sectional view of the exemplary structure shown in FIG. 24 after forming a first front-side ILD material layer.

[0044] [Figure 26] 26 is a cross-sectional view of the exemplary structure shown in FIG. 25 after converting each upper mesa portion of the semiconductor material layer into a first source / drain region.

[0045] [Figure 27] FIG. 27 is a cross-sectional view of the exemplary structure shown in FIG. 26 after forming front-side source / drain contact structures on each first source / drain region.

[0046] [Figure 28] A cross-sectional view of the exemplary structure shown in Figure 27 after forming a second front-side ILD material layer, the second front-side ILD material layer including a plurality of DRAM capacitors embedded therein, where each DRAM capacitor extends entirely through the second front-side ILD material layer and directly contacts one of the front-side source / drain contact structures, and forming a front-side BEOL structure and a carrier wafer on the second front-side ILD material layer.

[0047] [Figure 29] 29 is a cross-sectional view of the exemplary structure shown in FIG. 28 after flipping the structure 180 degrees to physically expose the remaining base semiconductor substrate.

[0048] [Figure 30] 30 is a cross-sectional view of the exemplary structure shown in FIG. 29 after removing the physically exposed remaining portion of the base semiconductor substrate to physically expose at least a remaining portion of the etch stop layer.

[0049] [Figure 31] FIG. 31 is a cross-sectional view of the exemplary structure shown in FIG. 30 after physically exposing each bottom mesa portion of the semiconductor material layer by removing the physically exposed remaining portions of the etch stop layer and converting each physically exposed bottom mesa portion of the semiconductor material layer into a second source / drain region.

[0050] [Figure 32] FIG. 32 is a cross-sectional view of the exemplary structure shown in FIG. 31 after forming backside source / drain contact structures on each second source / drain region.

[0051] [Figure 33] FIG. 33 is a cross-sectional view of the exemplary structure shown in FIG. 32 after forming a backside ILD material layer.

[0052] [Figure 34]FIG. 34 is a cross-sectional view of the exemplary structure shown in FIG. 33 after forming bit lines in the backside ILD material layer, where each bit line extends entirely through the backside ILD material layer and makes direct physical contact with one of the backside source / drain contact structures.

[0053] [Figure 35] FIG. 35 is a cross-sectional view of the exemplary structure shown in FIG. 34 after forming backside BEOL structures on the backside ILD material layer. DETAILED DESCRIPTION OF THE INVENTION

[0054] The present application will now be described in more detail by reference to the following discussion and the drawings that accompany this application. It should be noted that the drawings herein are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0055] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood by those skilled in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0056] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will be understood that the element can be directly below or directly underneath the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0057] As mentioned above, aspects of the present application relate to a semiconductor structure including a DRAM cell and a backside metal-containing bit line. Note that the semiconductor structure includes a DRAM cell including a plurality of FETs and a plurality of DRAM capacitors, and at least one bit line comprised of a conductive metal-containing material disposed on the backside of the DRAM cell. As mentioned above, the term "backside" refers to a portion of the structure that includes backside wiring components, e.g., a bit line disposed on the side of the structure that does not include active devices, i.e., DRAM cells. Such a structure has low bit line capacitance as mentioned above. In an embodiment of the present application, the DRAM cell has a 4F 2 The VFET has a unit cell area defined as 4F, where F is equal to the gate half pitch. In this application, F denotes the feature size of the gate structure. Therefore, the DRAM cell of this application has a high density. In an embodiment, the FET is a vertical FET including a vertical semiconductor channel material structure. The VFET has a 4F 2 This helps shape the architecture. In embodiments, the DRAM capacitor is a stacked capacitor, allowing for a higher density of cells. These and other aspects of the present application are now described in more detail.

[0058] 1-15, which illustrate a first embodiment of the present application, begin with forming the exemplary structure shown in FIG. 1. Note that the exemplary structure shown in FIG. 1 includes a plurality of vertical semiconductor channel material structures 14 extending upward from a surface of an etch stop layer 12 disposed on a surface of a base semiconductor substrate 10. The exemplary structure shown in FIG. 1 may further include a hard mask cap 16 disposed on each vertical semiconductor channel material structure 14, and shallow trench isolation structures 18 / 20 disposed on both the etch stop layer 12 and the base semiconductor substrate 10.

[0059] The base semiconductor substrate 10 is composed of a first semiconductor material having semiconducting properties. Examples of the first semiconductor material that may be used to provide the base semiconductor substrate 10 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors.

[0060] Each vertical semiconductor channel material structure 14 is composed of a second semiconductor material. The second semiconductor material providing each vertical semiconductor channel material structure 14 can be compositionally identical to or different from the first semiconductor material providing the base semiconductor substrate 10. In some embodiments, the second semiconductor material providing each vertical semiconductor channel material structure 14 can provide high channel mobility for an nFET device. In other embodiments, the second semiconductor material providing each vertical semiconductor channel material structure 14 can provide high channel mobility for a pFET device. Each vertical semiconductor channel material structure 14 is referred to herein as a vertical channel structure, and in this first embodiment, source / drain regions are then formed on both horizontal surfaces of each vertical semiconductor channel material structure 14, and gate structures are then formed along the sidewalls of each vertical semiconductor channel material structure to form multiple VFETs.

[0061] In the present application, the vertical height of each vertical semiconductor channel material structure 14, measured from the bottom horizontal surface to the top horizontal surface, is greater than the width of each vertical semiconductor channel material structure 14, measured from one sidewall of the vertical semiconductor channel material structure 14 to the opposite sidewall of the vertical semiconductor channel material structure 14. In one example, the vertical height of each vertical semiconductor channel material structure 14 is between 10 nm and 200 nm, while the width of each vertical semiconductor channel material structure 14 is between 5 nm and 50 nm.

[0062] In some embodiments of the present application, the etch stop layer 12 may be composed of a dielectric material such as, for example, silicon dioxide and / or boron nitride. In other embodiments of the present application, the etch stop layer 12 is composed of a semiconductor material that is compositionally different from the semiconductor materials that provide both the base semiconductor substrate 10 and the vertical semiconductor channel material structures 14. In one example, the base semiconductor substrate 10 is composed of silicon, the etch stop layer 12 is composed of silicon dioxide, and each vertical semiconductor channel material structure 14 is composed of silicon. In another example, the base semiconductor substrate 10 is composed of silicon, the etch stop layer 12 is composed of silicon germanium, and each vertical semiconductor channel material structure 14 is composed of silicon.

[0063] Each hard mask cap 16 may be composed of a dielectric hard mask material, such as silicon nitride and / or silicon oxynitride, and in the illustrated embodiment, each hard mask cap 16 has a sidewall that is vertically aligned with one sidewall of the vertical semiconductor channel material structure 14.

[0064] The shallow trench isolation structure 18 / 20 includes a trench liner 18 and a trench dielectric material 20. As illustrated in FIG. 1, the trench liner 18 is present along the sidewalls and bottom wall of the trench dielectric material 20. The trench dielectric material 20 may be composed of any trench dielectric material, such as, for example, silicon oxide, while the trench liner 18 may be composed of any trench liner material, such as, for example, silicon nitride. In some embodiments, as illustrated in FIG. 1, the shallow trench isolation structure 18 / 20 extends entirely through the etch stop layer 12 and partially through the base semiconductor substrate 10. In some embodiments, the trench liner 18 may be omitted.

[0065] The exemplary structure shown in FIG. 1 is prepared by first forming a substrate including a base semiconductor substrate 10, an etch stop layer 12, and a semiconductor material layer composed of the second semiconductor material mentioned above; this semiconductor material layer is then processed into a vertical semiconductor channel material structure 14. The substrate may be formed using techniques well known to those skilled in the art. A hard mask layer composed of a dielectric hard mask material, such as the above-mentioned, is then formed on the semiconductor material layer. The hard mask layer may be formed using a deposition process such as, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). In some embodiments, the hard mask layer may be formed by a thermal process such as, for example, thermal oxidation and / or thermal nitridation. The hard mask layer and the underlying semiconductor material layer are then patterned to provide the hard mask-coated vertical semiconductor channel material structure shown in FIG. 1.

[0066] In some embodiments, patterning may include lithography and etching. Lithography involves forming a photoresist material over the material or stack of materials that needs to be patterned, exposing the deposited photoresist material to a desired pattern of radiation, and then developing the exposed photoresist material. Etching may include a dry etching process and / or a chemical wet etching process. Dry etching may include one of reactive ion etching (RIE), plasma etching, or ion beam etching.

[0067] In some embodiments, patterning may include a sidewall image transfer (SIT) process. The SIT process includes forming a mandrel material layer (not shown) over the material or material layer to be patterned. The mandrel material layer (not shown) may include any material (semiconductor, dielectric, or conductor) that is selectively removed from the structure during a subsequent etching process. In one embodiment, the mandrel material layer (not shown) may be composed of amorphous silicon or polysilicon. In another embodiment, the mandrel material layer (not shown) may be composed of a metal, such as Al, W, or Cu. The mandrel material layer (not shown) may be formed, for example, by CVD or PECVD. Following deposition of the mandrel material layer (not shown), the mandrel material layer (not shown) may be patterned by lithography and etching to form multiple mandrel structures (also not shown) on the top surface of the structure. The SIT process then forms spacers (not shown) on each sidewall of each mandrel structure. The spacers may be formed by depositing a spacer material and then etching the deposited spacer material. The spacer material may include any material having an etch selectivity different from that of the mandrel material. Examples of deposition processes used to provide the spacer material include, for example, CVD, PECVD, or atomic layer deposition (ALD). Examples of etching used to provide the spacers include any etching process, such as RIE. After the spacers are formed, the SIT process then removes each mandrel structure. Each mandrel structure may be removed by an etching process that is selective to removing the mandrel material. Following mandrel structure removal, the SIT process then transfers the pattern provided by the spacers to the underlying material or material layer. The pattern transfer may be achieved by utilizing at least one etching process. Examples of etching processes used to transfer the pattern may include dry etching and / or chemical wet etching processes. In one example, the etching process used to transfer the pattern may include one or more reactive ion etching steps.Once the pattern transfer is complete, the SIT process is completed by removing the spacers from the structure, which can be removed by etching or a planarization process.

[0068] In still further embodiments, patterning may include a dynamic self-assembly (DSA) process in which a copolymer capable of self-assembly is used. Other known patterning processes may also be used in forming the hardmask-coated vertical semiconductor channel material structure shown in FIG.

[0069] 1, shallow trench isolation structures 18 / 20 are formed utilizing conventional shallow trench isolation processes well known to those skilled in the art. The shallow trench isolation process may include forming trenches in etch stop layer 12 and base semiconductor substrate 10 by lithography and etching, and then filling the trenches with a trench dielectric liner material and a trench dielectric as mentioned above; filling the trenches may include depositing the trench dielectric liner material and the trench dielectric and recessing the deposited materials.

[0070] Referring now to FIG. 2 , the exemplary structure shown in FIG. 1 is illustrated after forming first dielectric spacers 22, which contact the lower portions of each vertical semiconductor channel material structure 14 of the plurality of vertical semiconductor channel material structures. The first dielectric spacers 22 may be referred to herein as bottom spacers. The first dielectric spacers 22 may be composed of any dielectric spacer material, including, for example, silicon dioxide, silicon nitride, or silicon oxynitride. The first dielectric spacers 22 may be formed using a deposition process, such as CVD or PECVD. In some cases, an etch-back process may follow the deposition of the dielectric spacer material to provide the first dielectric spacers 22. The first dielectric spacers 22 may have a thickness of 5 nm to 15 nm. Other thicknesses, smaller or larger than the above thickness range, may also be used herein for the thickness of the first dielectric spacers 22, as long as the height of the first dielectric spacers 22 is not greater than the height of the vertical semiconductor channel material structures 14 and sufficient space exists along the sidewalls of the vertical semiconductor channel material structures 14 for forming both the gate structure and the second dielectric spacer. First dielectric spacers 22 are formed over both the shallow trench isolation structures 18 / 20 and the etch stop layer 12, as shown in FIG.

[0071] 3, the exemplary structure shown in FIG. 2 is illustrated after forming a gate structure material layer 24L on the first dielectric spacers 22 and along and above the sidewalls of each vertical semiconductor channel material structure 14; in the illustrated embodiment, the gate structure material layer 24L is also present along the sidewalls and top surface of the hard mask cap 16. The gate structure material layer 24L is typically a conformal layer. The term "conformal" indicates that the material layer has a vertical thickness along horizontal surfaces that is substantially the same (i.e., within ±5%) as its lateral thickness along vertical surfaces.

[0072] In the present application, the gate structure material layer 24L is intended to include a gate dielectric material and a gate electrode, both of which are not separate but are present within the gate structure material layer 24L. As known to those skilled in the art, the gate dielectric material directly contacts the sidewalls of the vertical semiconductor channel material structure 14, and the gate electrode is formed on the gate dielectric material.

[0073] The gate dielectric material of the gate structure material layer 24L has a dielectric constant of 4.0 or greater. All dielectric constants referred to herein are measured in a vacuum unless otherwise specified. Illustrative examples of gate dielectric materials include, for example, silicon dioxide, hafnium dioxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium dioxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium silicon oxynitride (ZrSiO), and the like. x N y ), tantalum oxide (TaO x Examples of suitable gate dielectric materials include, but are not limited to, metal oxides such as titanium oxide (TiO), barium strontium titanium oxide (BaOSrTi), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YbO), aluminum oxide (AlO), lead tantalum scandium oxide (Pb(Sc,Ta)O), and / or lead zinc niobate (Pb(Zn,Nb)O). The gate dielectric material may further include dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg). The gate dielectric material may be formed using any conformal deposition process, such as CVD, PECVD, or ALD.

[0074] The gate electrode of the gate structure material layer 24L can include a work function metal (WFM) and, optionally, a conductive metal. The WFM can be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM can be selected to produce an n-type threshold voltage shift. "N-type threshold voltage shift," as used herein, refers to a shift in the effective work function of a work function metal-containing material toward the conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV. Examples of such materials that can produce an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM can be selected to produce a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, "threshold voltage" refers to the lowest achievable gate voltage that turns on a semiconductor device, e.g., a transistor, by making the device's channel conductive. The term "p-type threshold voltage shift" refers to a shift in the effective work function of a metal-containing material toward the valence band of silicon in a silicon-containing material. Examples of materials that can produce a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. Optional conductive metals may include, but are not limited to, aluminum (Al), tungsten (W), or cobalt (Co). The gate electrode may be formed by a deposition process, such as CVD, PECVD, sputtering, or plating.

[0075] Referring now to FIG. 4 , the exemplary structure shown in FIG. 3 is illustrated after patterning the gate structure material layer 24L to provide a gate structure 24 along the sidewall of each vertical semiconductor channel material structure 14 of the plurality of vertical semiconductor channel material structures; in the illustrated embodiment, the gate structure 24 is also present along the sidewall of the hard mask cap 16, but not on its top surface. The gate structure 24 includes the gate dielectric material and the unetched portion of the gate electrode, as mentioned above. The patterning includes the use of a gate pattern mask (not shown) that protects portions of the gate structure material layer 24L and etching. The etching may include a dry etching or chemical wet etching process, such as RIE. The gate structure 24 has a height that is less than the combined height of the hard mask-covered vertical semiconductor channel material structures.

[0076] Referring now to FIG. 5 , the exemplary structure shown in FIG. 4 is illustrated after forming a first front-side interlayer dielectric (ILD) material layer 26 laterally adjacent to each gate structure 24. In the illustrated embodiment, the first front-side ILD material layer 26 has a top surface that is coplanar with the top surface of each hard mask cap 16; thus, a portion of the first front-side ILD material layer 26 may be present above each gate structure 24. The first front-side ILD material layer 26 may be composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used throughout this application, the term “low-k” refers to a dielectric material having a dielectric constant less than 4.0. The first front-side ILD material layer 26 may be formed by deposition of a dielectric material followed by a planarization process, such as chemical mechanical polishing (CMP). Deposition of the dielectric material may include, for example, CVD, PECVD, ALD, or spin-on coating.

[0077] 6, the exemplary structure shown in FIG. 5 is illustrated after removing the hard mask caps 16 present on each vertical semiconductor channel material structure 14 of the plurality of vertical semiconductor channel material structures. Removal of the hard mask caps 16 from the exemplary structure includes an etching process that is selective in removing the hard mask material that provides each hard mask cap 16. After removal of the hard mask caps 16 from the exemplary structure, the top surface of each vertical semiconductor channel material structure 14 is physically exposed, and an opening 28 is formed above each vertical semiconductor channel material structure 14, as shown in FIG.

[0078] 7 illustrates the exemplary structure shown in FIG. 6 after recessing each gate structure 24 to physically expose an upper sidewall portion of each vertical semiconductor channel material structure 14 of the plurality of vertical semiconductor channel material structures. Recessing each gate structure 24 may be performed using a recess etch process that is selective in removing portions of each gate structure 24. This step herein provides space along the upper sidewall portion of the vertical semiconductor channel material structure 14 upon which a second dielectric spacer (or upper dielectric spacer) is subsequently formed. Here, the recessed gate structure 24 has a height that is less than the height of the vertical semiconductor channel material structure 14.

[0079] Referring now to Figure 8, the exemplary structure shown in Figure 7 is illustrated after forming a second dielectric spacer 30 laterally adjacent to the physically exposed upper sidewall portion of each vertical semiconductor channel material structure 14 of the plurality of vertical semiconductor channel material structures, and forming a first source / drain region (or upper source / drain region) 32 extending upward from the top surface of each vertical semiconductor channel material structure 14 of the plurality of vertical semiconductor channel material structures 14.

[0080] The second dielectric spacers 30 are composed of one of the dielectric spacer materials mentioned above to provide the first dielectric spacers 22. The second dielectric spacers 30 may be formed utilizing the process techniques described above in forming the first dielectric spacers 22. The second dielectric spacers 30 may have a top surface that is coplanar with or slightly offset from the top surface of the vertical semiconductor channel material structures 14. When offset, the second dielectric spacers 30 typically have a top surface that is lower than the top surface of the vertical semiconductor channel material structures 14; such an embodiment also allows for first source / drain regions 32 to be formed along the sidewalls of each vertical semiconductor channel material structure 14.

[0081] The first source / drain regions 32 include a semiconductor material and a dopant. The semiconductor material providing the first source / drain regions 32 includes one of the semiconductor materials mentioned above in providing the base semiconductor substrate 10. The semiconductor material providing the first source / drain regions 32 can be compositionally identical to or different from the second semiconductor material providing each vertical semiconductor channel material structure 14. The dopant can be either an n-type dopant or a p-type dopant. The term "n-type" refers to the addition of an impurity that contributes free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. The concentration of the first dopant in the first source / drain regions 32 is greater than or equal to 1×10 18 atoms / cm 3 From 1×10 21 atoms / cm 3 can range from 1 x 10 21 atoms / cm 3 Greater than or 1 x 10 18 atoms / cm 3Smaller dopant concentrations are also contemplated. The first source / drain regions 32 may extend above the top surface of the first front-side ILD material layer 26, and the first source / drain regions 32 may have faceted or non-faceted surfaces. In FIG. 8 , each first source / drain region 32 has a triangular surface that extends above the top surface of the first front-side ILD material layer 26. Note that the first source / drain regions 32 are formed on the second dielectric spacers 30 and on the physically exposed surfaces of the vertical semiconductor channel material structure 14. In this embodiment, both the first source / drain regions 32 and the second source / drain region (to be subsequently formed) may have non-faceted surfaces, the non-faceted surfaces being opposite the surfaces of the first source / drain regions 32 and the second source / drain region (to be subsequently formed) that contact the vertical semiconductor channel material structure 14.

[0082] The first source / drain regions 32 may be formed using a deposition process such as CVD, PECVD, or epitaxial growth. The terms "epitaxial growth" or "epitaxially growing" refer to the growth of a second semiconductor material on a growth surface of a first semiconductor material, where the grown second semiconductor material has the same crystalline properties as the first semiconductor material. In an epitaxial deposition process, chemical reactants provided by source gases are controlled, and system parameters are set so that the depositing atoms arrive at the growth surface of the first semiconductor material with sufficient energy to move around on the growth surface and orient themselves into the crystalline arrangement of the atoms on the growth surface. Examples of various epitaxial growth process equipment that can be utilized herein include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Epitaxial deposition temperatures typically range from 550°C to 900°C. Higher temperatures usually result in faster deposition, but faster deposition can lead to crystalline defects and film cracking. In some embodiments, dopants are added to the deposited semiconductor material using ion implantation or another similar dopant introduction process. In yet other embodiments, dopants are present during the deposition of the semiconductor material; for example, an epitaxial growth process can be used in which the semiconductor material reactant and dopant are introduced simultaneously.

[0083] 9 illustrates the exemplary structure shown in FIG. 8 after forming a second front-side ILD material layer 34 having front-side contact structures 36 embedded therein, each front-side contact structure 36 contacting one of the first source / drain regions 32. The second front-side ILD material layer 34 includes one of the dielectric materials mentioned above for the first front-side ILD material layer 26. The dielectric material providing the second front-side ILD material layer 34 can be compositionally identical to or compositionally different from the dielectric material providing the first front-side ILD material layer 26. The second front-side ILD material layer 34 can be formed utilizing one of the deposition processes mentioned above in forming the first front-side ILD material layer 26.

[0084] The front-side contact structures 36 are formed using any conventional metallization process. Because each such front-side contact structure 36 contacts a first source / drain region 32, the front-side contact structures 36 may be referred to as a front-side source / drain contact structure. The front-side contact structures 36 include at least a contact conductor material, such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. In embodiments, the front-side contact structures 36 may also include a silicide liner, such as TiSi, NiSi, or NiPtSi, and an adhesion metal liner, such as TiN. Each front-side contact structure 36 may be formed by forming a contact opening in the second front-side ILD material layer 34 by lithography and etching. The contact conductor material may be formed in the contact opening by any suitable deposition method, such as ALD, CVD, PVD, or plating. In some embodiments (not shown), a metal-semiconductor alloy region may be formed in each of the contact openings before forming the contact conductor material. The metal semiconductor alloy region may be composed of a silicide or a germanide. In one or more embodiments of the present application, the metal semiconductor alloy region may be formed by first depositing a metal layer (not shown) in the trench. The metal layer may include a metal, such as Ni, Co, Pt, W, Ti, Ta, a rare earth metal (e.g., Er, Yt, La), an alloy thereof, or any combination thereof. The metal layer may be deposited by ALD, CVD, or PVD. The thickness of the metal layer may be 2 nm to 10 nm, although smaller and larger thicknesses may also be utilized. Next, a diffusion barrier (not shown), such as TiN or TaN, may be formed on the metal layer. Thereafter, an annealing process may be performed at high temperature to induce reaction of the semiconductor material in the source / drain regions and provide the metal semiconductor alloy region. Next, the unreacted portions of the metal layer and, if present, the diffusion barrier, are removed, for example, by an etching process (or multiple etching processes). In one embodiment, the etching process may be a wet etch that removes the metal in the metal layer selectively to the metal semiconductor alloy in the metal semiconductor alloy region. Each front side contact structure 36 may further include one or more contact liners (not shown).In one or more embodiments, the contact liner (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. The contact liner may be formed using a conformal deposition process, including CVD or ALD. The formed contact liner may have a thickness ranging from 1 nm to 5 nm, although smaller and larger thicknesses may also be used. Each front-side contact structure 36 has a top surface that is coplanar with the top surface of the second front-side ILD material layer 34.

[0085] 10 , the exemplary structure shown in FIG. 9 after forming a front-side interconnect (BEOL) structure 40 having DRAM capacitors 38 embedded therein, each DRAM capacitor 38 contacting one of the front-side contact structures 36, and forming a carrier wafer 42 on the front-side BEOL structure 40. As shown in FIG. 10 , each DRAM capacitor 36 is electrically connected to one of the first source / drain regions 32 by the front-side contact structure 36. Also, as further shown in FIG. 10 , each DRAM capacitor 36 is separated from the carrier wafer 42 by a portion of the front-side BEOL structure 40.

[0086] The front-side BEOL structure 40 includes one or more interconnect dielectric material layers containing one or more wiring regions and an embedded DRAM capacitor 38. The front-side BEOL structure 40 is formed using BEOL processing techniques well known to those skilled in the art; the embedded DRAM capacitor 38 may be formed using well-known BEOL capacitor formation techniques well known to those skilled in the art. The DRAM capacitor 38 includes two conductive material plates (or electrodes) separated by a dielectric material. The conductive material plates may be composed of any capacitor electrode material, such as copper (Cu), tantalum (Ta), W, Al, ruthenium (Ru), rhodium (Rh), Co, molybdenum (Mo), titanium nitride (TiN), or tantalum nitride (TiN). The two conductive material plates may be composed of compositionally identical or compositionally different capacitor electrode materials. The dielectric material disposed between the two conductive plates may include one of the dielectric materials mentioned above for the gate dielectric material of the gate structure material layer 24L. DRAM capacitor 38 is typically a stacked capacitor that includes a bottom conductive plate and a top conductive plate separated from each other by a dielectric material; thus, the dielectric material is sandwiched between the bottom and top conductive plates. Such a stacked arrangement improves the density of DRAM cells.

[0087] The carrier wafer 42 may include one of the semiconductor materials mentioned above for the base semiconductor substrate 10. In the present application, the carrier wafer 42 is bonded to the front side BEOL structure 40.

[0088] 11 , the exemplary structure shown in FIG. 10 is illustrated after flipping the wafer 180° to physically expose the backside of the base semiconductor substrate 10. This flipping allows for backside processing of the exemplary structure. In the present application, the structure is flipped 180°. Flipping the structure can be performed by hand or by utilizing mechanical means such as, for example, a robotic arm.

[0089] 12, there is illustrated the exemplary structure shown in FIG. 11 after removing the base semiconductor substrate 10 to physically expose the etch stop layer 12. Removal of the base semiconductor substrate 10 may be performed utilizing a material removal process that is selective in removing the first semiconductor material that provides the base semiconductor substrate 10. Note that this removal step does not remove any portion of the shallow trench isolation structures 18 / 20.

[0090] 13 , which illustrates the exemplary structure shown in FIG. 12 after removing the etch stop layer 12 to physically expose a horizontal surface of each of the plurality of vertical semiconductor channel material structures 14. Note that the physically exposed horizontal surface of the vertical semiconductor channel material structure 14 is opposite the horizontal surface of the vertical semiconductor channel material structure 14 that forms an interface with the first source / drain region 32. Removal of the etch stop layer 12 comprises a material removal process that is selective in removing the etch stop layer 12.

[0091] 14, the exemplary structure shown in FIG. 13 is illustrated after forming second source / drain regions 44 on the physically exposed horizontal surfaces of each of the plurality of vertical semiconductor channel material structures 14. Each second source / drain region 44 is adjacent on either side to a shallow trench isolation structure 18 / 20. Each second source / drain region 44 may be referred to herein as a bottom source / drain region.

[0092] The second source / drain regions 44 are composed of the semiconductor materials and dopants mentioned above for the first source / drain regions 32. The semiconductor material providing the second source / drain regions 44 can be compositionally identical or different from the semiconductor material providing the first source / drain regions 32 and / or the second semiconductor material providing the vertical semiconductor channel material structure 14. The dopants in the second source / drain regions 44 are of the same conductivity type as the dopants present in the first source / drain regions 32. The dopant concentration in the second source / drain regions 44 is within the range mentioned above for the first source / drain regions 32. Each second source / drain region 44 can have a faceted or non-faceted surface, and each second source / drain region 44 can extend above the height of each shallow trench isolation structure 18, 20 as illustrated in FIG. 14. In FIG. 14, each second source / drain region 44 has a triangular surface. The second source / drain regions 44 may be formed using one of the techniques mentioned above in forming the first source / drain regions 32 .

[0093] 15 , the exemplary structure shown in FIG. 14 is illustrated after forming backside bit lines 46 contacting each second source / drain region 44 and forming backside BEOL structures 48 on the backside bit lines 46. In some embodiments (not shown), backside source / drain contacts (see the second embodiment of the present application) can be formed on the second source / drain regions 44 before forming the backside bit lines 46. While a single backside bit line 46 is shown, the present application contemplates forming multiple such backside bit lines 46; in FIG. 15 , for example, backside bit lines 46 exist both inside and outside the plane of the drawing sheet. The backside bit lines 46 are composed of any conductive metal-containing material, including, but not limited to, W, Co, Ru, Al, Cu, platinum (Pt), Rh, or palladium (Pd), with a thin metal adhesion layer (such as TiN or TaN) typically formed prior to conductive metal deposition; for clarity, the metal adhesion layer is not separately illustrated in the drawings of the present application. The backside bitlines 46 are typically embedded in a backside ILD material layer (not shown in the cross-sectional view) and are formed by forming backside bitline openings in the backside ILD material layer; the backside bitline openings physically expose the surfaces of the second source / drain regions 44. The backside bitline openings are then filled with at least one of the conductive materials mentioned above, and a planarization process may follow the filling of the backside bitline openings. The filling may include CVD, PECVD, ALD, sputtering, or plating. The resulting backside bitlines 46 contact the second source / drain regions 44 of each VFET. Each VFET includes a vertical semiconductor channel material structure 14, gate structures 24 disposed on each side of the vertical semiconductor channel material structure 14, and a first source / drain region 32 disposed at a first end of the vertical semiconductor channel material structure 14 and a second source / drain region 44 disposed at a second end of the vertical semiconductor channel material structure 14 opposite the first end. The first source / drain region 32 of each VFET is electrically connected by one of the front-side contact structures 36 to a DRAM capacitor 38 present in the front-side BEOL structure 40. In this application, current flows vertically in the vertical semiconductor channel material structure 14 of each VFET.In this application, the DRAM capacitor 38 and the VFET together provide a DRAM cell; the DRAM capacitor functions as the storage node of the DRAM cell. The DRAM cell is typically a 4F as mentioned above. 2 It is a cell.

[0094] The backside BEOL structure 48 may be a backside power distribution network that provides power to the VFETs. The backside BEOL structure 48 includes one or more interconnect dielectric material layers (represented as element 50 in FIG. 15 ) that contain one or more wiring regions (represented by element 52 in FIG. 15 ). The backside BEOL structure 48 may be formed using techniques well known to those skilled in the art.

[0095] Reference is now made to Figures 16-35, which illustrate a second embodiment of the present application. This second embodiment begins by forming the exemplary structure shown in Figure 16. Note that the exemplary structure shown in Figure 16 includes a base semiconductor substrate 10, an etch stop layer 12 disposed on the base semiconductor substrate 10, and a semiconductor material layer 14L having a plurality of upper mesas 14U disposed on the etch stop layer 12. The exemplary structure of this embodiment of the present application may also include a hard mask cap 16 disposed on each upper mesa 14U of the semiconductor material layer 14L.

[0096] The base semiconductor substrate 10, the etch stop layer 12, and the hard mask cap 16 are the same as those defined above in the first embodiment of the present application. The semiconductor material layer 14L having the plurality of upper mesas 14U is composed of the second semiconductor material mentioned above in providing the vertical semiconductor channel material structure 14 of the first embodiment of the present application.

[0097] The exemplary structure shown in FIG. 16 may be prepared by first forming a substrate including a base semiconductor substrate 10, an etch stop layer 12, and a semiconductor material layer 14L, each composed of the second semiconductor material mentioned above. The substrate may be formed using techniques well known to those skilled in the art. For example, substrate preparation may include epitaxial growth of the etch stop layer 12 and the semiconductor material layer 14L. A hard mask layer composed of the dielectric hard mask material mentioned above is then formed on the semiconductor material layer. The hard mask layer may be formed using the deposition process or thermal process mentioned above. The hard mask layer and the underlying semiconductor material layer 14L are then patterned to provide the structure shown in FIG. 16. In this embodiment, patterning typically includes lithography and etching. Etching, which may include dry etching processes and chemical wet etching processes, etches the hard mask layer entirely and the semiconductor material layer 14L partially, thereby providing the structure illustrated in FIG. 16. The term "mesa portion" is used herein to describe a portion of material having a width greater than the width of the base material.

[0098] 17 illustrates the exemplary structure shown in FIG. 16 after forming dielectric spacers 60 along at least the sidewalls of each upper mesa portion 14U of semiconductor material layer 14L; dielectric spacers 60 are also present along the sidewalls of each hard mask cap 16, with dielectric spacers 60 typically having a top surface that is coplanar with hard mask cap 16. Dielectric spacers 60 are composed of any dielectric spacer material, including the dielectric spacer materials mentioned above in forming first dielectric spacers 22. Dielectric spacers 60 may be formed by deposition of a dielectric spacer material followed by a spacer etch.

[0099] 18 illustrates the exemplary structure shown in FIG. 17 after patterning the semiconductor material layer 14L using the dielectric spacers 60 and the upper mesa portion 14U of the semiconductor material layer 14L as a combined etch mask, where the patterning forms a plurality of semiconductor material pillars 14P on the remaining portion of the semiconductor material layer 14L; an upper mesa portion 14U is disposed above each semiconductor material pillar 14P. The patterning includes etching that is selective in removing the second semiconductor material that provides the semiconductor material layer 14L. This etching stops below the surface of the semiconductor material layer 14L, as shown in FIG. 18. It was noted that each semiconductor material pillar 14P may have a width substantially equal (±10%) to the width of the overlying upper mesa portion 14U.

[0100] 19 illustrates the exemplary structure shown in FIG. 18 after trimming each semiconductor material pillar 14P to provide a vertical semiconductor material channel structure 14, with each vertical semiconductor material channel structure 14 disposed between an upper mesa portion 14U of the semiconductor material layer 14L and the remainder of the semiconductor material layer 14L. In some embodiments, trimming of the semiconductor material pillars 14P may be performed using a combination of oxidation and etching (this step may be repeated multiple times to provide a desired width for each vertical semiconductor material channel structure 14). In other embodiments, this trimming may be performed by a dry etching process.

[0101] 20 illustrates the exemplary structure shown in FIG. 19 after forming a gate dielectric material layer 62 and a gate polysilicon layer 64. The gate dielectric material layer 62 includes one of the gate dielectric materials mentioned above for the gate structure material layer 24L in the previous embodiment of this application. The gate polysilicon layer 64 is composed of polysilicon, which may have n-type or p-type dopants present therein. The gate dielectric material layer 62 and the gate polysilicon layer 64 are formed by first depositing a dielectric material (e.g., by CVD, PECVD, or ALD) and second depositing polysilicon (e.g., by CVD, PECVD, or PVD), and then using etching to remove any polysilicon extending beyond the outermost surface of the dielectric spacers 60. The gate dielectric material layer 62 is a conformal layer present on the exposed surfaces of each vertical semiconductor material channel structure 14 and the remaining semiconductor material layer 14L, and the gate polysilicon layer 64 is disposed on the gate dielectric material layer 62.

[0102] 21 illustrates the exemplary structure shown in FIG. 20 after performing a breakthrough etch process that removes at least a portion of gate dielectric material layer 62, a remaining portion of semiconductor material layer 14L, etch stop layer 12, and a portion of base semiconductor substrate 10; the remaining unetched semiconductor material layer, protected by the combined etch mask, provides bottom mesa portion 14B of semiconductor material layer 14L. Note that in addition to the portion of semiconductor material layer 14L that remains after this etch, a portion of etch stop layer 12 and a portion of base semiconductor substrate 10 also remain after this breakthrough etch is performed. In one embodiment, the breakthrough etch is an RIE etch.

[0103] 22 , the exemplary structure shown in FIG. 21 is illustrated after forming a gap-fill dielectric material layer 66. The gap-fill dielectric material layer 66 is composed of any gap-fill dielectric material, including, for example, one of the dielectric materials mentioned above for the first front-side ILD material layer 26 of the first embodiment of the present application. The gap-fill dielectric material layer 66 may be formed by utilizing a deposition process, including one of the deposition processes mentioned above in forming the first front-side ILD material layer 26 of the first embodiment of the present application. A planarization process may follow the deposition of the dielectric material that provides the gap-fill dielectric material layer 66. At this junction of the present application, the gap-fill dielectric material layer 66 has a top surface that is coplanar with the top surfaces of the dielectric spacers 60 and the hard mask cap 16.

[0104] 23, which illustrates the exemplary structure shown in FIG. 22 after recessing gapfill dielectric material layer 66. Recessed gapfill dielectric material layer 66 typically, but not always, has a top surface that is coplanar with the top surface of bottom mesa portion 14B of semiconductor material layer 14L. Recessing gapfill dielectric material layer 66 may be performed utilizing a recess etch process that is selective in removing the dielectric material that provides gapfill dielectric material layer 66.

[0105] 24 , the exemplary structure shown in FIG. 23 is illustrated after forming a gate metal layer 68 on the recessed gap-fill dielectric material layer 66 and laterally adjacent and in direct physical contact with the gate polysilicon layer 64; the gate metal layer 68 also makes direct physical contact with, for example, the edge walls of the gate dielectric material layer 62 shown in FIG. 24 . The gate metal layer 68 may include one of the WFM or optional conductive metals mentioned above for the gate electrode present in the gate structure material layer 24L. The gate metal layer 68 may be formed by a deposition process such as, for example, CVD, PECVD, sputtering, or plating. An etch-back process may follow the deposition of the gate metal material to provide the gate metal layer 68.

[0106] 25, the exemplary structure shown in FIG. 24 after forming a first front-side ILD material layer 70 is illustrated. The first front-side ILD material layer 70 is composed of one of the dielectric materials mentioned above for the first front-side ILD material layer 26 of the first embodiment of the present application. The first front-side ILD material layer 70 may be formed by utilizing a deposition process, including one of the deposition processes mentioned above in forming the first front-side ILD material layer 26 of the first embodiment of the present application. A planarization process may follow the deposition of the dielectric material that provides the first front-side ILD material layer 70. At this junction of the present application, the first front-side ILD material layer 70 has a top surface that is coplanar with the top surfaces of the dielectric spacers 60 and the hard mask cap 16.

[0107] 26 illustrates the exemplary structure shown in FIG. 25 after converting each upper mesa portion 14U of the semiconductor material layer 14L into a first source / drain region 15. Prior to this conversion, each hard mask cap 16 is removed from the structure using a material removal process, such as a planarization process (CMP) and / or grinding. During the planarization process, upper portions of both the dielectric spacers 60 and the first front-side ILD material layer 70 may be removed along with each hard mask cap 16, thereby physically exposing the upper mesa portion 14U. Converting the upper mesa portion 14U into the first source / drain region 15 includes introducing a dopant (n-type or p-type, as mentioned above) into the physically exposed upper mesa portion 14U. Introducing the dopant may include one of ion implantation, vapor-phase doping, or diffusion of dopants from a dopant source material. The concentration of the dopant introduced into each upper mesa portion 14U is within the dopant range mentioned above in forming the first source / drain regions 32 of the first embodiment of the present application.

[0108] 27 is a cross-sectional view of the exemplary structure shown in FIG. 26 after forming front-side source / drain contact structures 72 on each first source / drain region 15. The front-side source / drain contact structures 72 include any of the materials, e.g., contact conductor materials, mentioned above for the front-side contact structures 36 in previous embodiments of the present application. In the exemplary embodiment shown in FIG. 27, the front-side source / drain contact structures 72 may be formed by recessing (i.e., etching) an upper portion of each first source / drain region 15 and then forming the front-side source / drain contact structures 72 in the recessed areas. In some embodiments (not shown), the front-side source / drain contact structures 72 may be formed on the non-recessed surfaces of each first source / drain region 15 by deposition and etching.

[0109] 28 illustrates the exemplary structure shown in FIG. 27 after forming a second front-side ILD material layer 74 including a plurality of DRAM capacitors 76 embedded therein, where each DRAM capacitor 76 extends entirely through the second front-side ILD material layer 74 and is in direct contact with one of the front-side source / drain contact structures 72, and forming front-side BEOL structures 40 and carrier wafer 42 on the second front-side ILD material layer 74. In this embodiment, the DRAM capacitors 76 contact the front-side BEOL structures 40.

[0110] The second front-side ILD material layer 74 may include one of the dielectric materials mentioned above for the first front-side ILD material layer 26 of the first embodiment of the present application. The second front-side ILD material layer 74 may include a dielectric material that is compositionally the same or compositionally different from the first front-side ILD material layer 70. The second front-side ILD material layer 74 may be formed by utilizing a deposition process including one of the deposition processes mentioned above in forming the first front-side ILD material layer 26 of the first embodiment of the present application.

[0111] DRAM capacitors 76 are then formed in second front-side dielectric material layer 74 by first forming capacitor openings in second front-side dielectric material layer 74 by lithography and etching. Each capacitor opening is then filled with materials that provide a capacitor, such as a first conductive plate material, a dielectric material, and a second conductive plate material, as mentioned above for DRAM capacitor 38 in the previous embodiment of this application. Filling may include deposition of various materials followed by a planarization process. DRAM capacitors 76 may be referred to as trench capacitors.

[0112] The front-side BEOL structure 40 of this embodiment includes one or more interconnect dielectric material layers with one or more wiring regions embedded therein. The front-side BEOL structure 40 can be formed using BEOL processing techniques well known to those skilled in the art. The carrier wafer 42 of this embodiment is the same as that described in the previous embodiment of this application. The carrier wafer 42 can be bonded to the front-side BEOL structure 40.

[0113] 29, the exemplary structure shown in FIG. 28 is illustrated after flipping the structure 180° to physically expose the remaining base semiconductor substrate 10. This flipping allows for backside processing of the exemplary structure. In the present application, the structure is flipped 180°. Flipping the structure can be performed by hand or by utilizing mechanical means, such as, for example, a robotic arm.

[0114] 30 illustrates the exemplary structure shown in FIG. 29 after removing the physically exposed remaining portions of the base semiconductor substrate 10 to physically expose at least the remaining portions of the etch stop layer 12, with the gap fill dielectric material layer 66 also being physically exposed after removing the remaining portions of the base semiconductor substrate 10. The remaining portions of the base semiconductor substrate 10 may be removed utilizing an etching process that is selective in removing the base semiconductor substrate 10.

[0115] 31 illustrates the exemplary structure shown in FIG. 30 after physically exposing each bottom mesa portion 14B of semiconductor material layer 14L by removing the physically exposed remaining portions of etch stop layer 12 and converting each physically exposed bottom mesa portion 14B into a second source / drain region 17. Removal of the physically exposed remaining portions of etch stop layer 12 comprises a selective etching process. The conversion of bottom mesa portion 14B into second source / drain region 17 is identical to the conversion of upper mesa portion 14A into first source / drain region 15. In this embodiment, first source / drain region 15, vertical semiconductor material channel structure 14, and second source / drain region 16 are a single structure (i.e., a single workpiece) and are composed of the same semiconductor material. In this embodiment, the VFET includes a vertical semiconductor material channel structure 14, a first source / drain region 15 disposed at a first end of the vertical semiconductor material channel structure 14, a second source / drain region 17 disposed at a second end (opposite the first end) of the vertical semiconductor material channel structure 14, and a gate structure including a gate dielectric material layer 62, a gate polysilicon layer 64, and a gate metal layer 68. In this embodiment, the first source / drain region 15 and the second source / drain region 17 have faceted surfaces for contacting the front side and back side, respectively.

[0116] 32 , the example structure shown in FIG. 31 is illustrated after forming backside source / drain contact structures 78 on each second source / drain region 17. The backside source / drain contact structures 78 include the materials mentioned above for the frontside source / drain contact structures 36. In the example embodiment shown in FIG. 32 , the backside source / drain contact structures 78 may be formed by recessing (i.e., etching) an upper portion of each second source / drain region 17 and then forming the backside source / drain contact structures 78 in the recessed areas. In some embodiments (not shown), the backside source / drain contact structures 78 may be formed on the non-recessed surfaces of each second source / drain region 17 by deposition and etching.

[0117] 33, illustrated is the exemplary structure shown in FIG. 32 after forming a backside ILD material layer 80. The backside ILD material layer 80 may include one of the dielectric materials mentioned above for the first frontside ILD material layer 26 of the previous embodiments of the present application. The backside ILD material layer 80 may be formed utilizing one of the deposition processes mentioned above in forming the first frontside ILD material layer 26 of the previous embodiments of the present application.

[0118] 34 , illustrated is the exemplary structure shown in FIG. 33 after forming bitlines 46 in backside ILD material layer 80, where each bitline 46 extends entirely through backside ILD material layer 80 and makes direct physical contact with one of the backside source / drain contact structures 78. The bitlines 46 of this embodiment include any of the conductive metal-containing materials mentioned in the first embodiment of this application, and the bitlines 46 of this embodiment may be formed utilizing the techniques mentioned above in forming the bitlines in the previous embodiments of this application.

[0119] 35 , which illustrates the exemplary structure shown in FIG. 34 after forming a backside BEOL structure 48 on the backside ILD material layer 80 and on each bitline 46. The backside BEOL structure 48 of this embodiment is identical to the backside BEOL structure 48 in the previous embodiment; it should be noted that the interconnect dielectric material layer and various wiring layers are not shown in the backside BEOL structure 48 shown in FIG.

[0120] While the present application has been particularly shown and described in connection with its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. a dynamic random access memory (DRAM) cell including a plurality of field effect transistors (FETs) and a plurality of DRAM capacitors; and At least one bit line comprised of a conductive metal-containing material disposed on the backside of the DRAM cell. A semiconductor structure comprising:

2. The DRAM cell is 4F ２ 2. The semiconductor structure of claim 1, having a unit cell area defined as: where F is equal to the gate half pitch.

3. 2. The semiconductor structure of claim 1, wherein each DRAM capacitor of said plurality of DRAM capacitors is a stacked capacitor.

4. 10. The semiconductor structure of claim 1, further comprising a backside interconnect (BEOL) structure contacting said at least one bitline, wherein said backside BEOL structure is a backside power distribution network.

5. 2. The semiconductor structure of claim 1, wherein each FET of the plurality of FETs is a vertical FET including a vertical semiconductor channel material structure, a gate structure disposed on each side of the vertical semiconductor channel material structure, a first source / drain region disposed at a first end of the vertical semiconductor channel material structure, and a second source / drain region disposed at a second end of the vertical semiconductor channel material structure opposite the first end of the vertical semiconductor channel material structure.

6. 6. The semiconductor structure of claim 5, wherein the vertical semiconductor channel material structure, the first source / drain region, and the second source / drain region are a unitary structure and comprise the same semiconductor material.

7. 6. The semiconductor structure of claim 5, further comprising a front side source / drain contact structure contacting said first source / drain region and connecting said first source / drain region to one of said plurality of DRAM capacitors.

8. 8. The semiconductor structure of claim 7, wherein said at least one bit line directly contacts said second source / drain region.

9. 8. The semiconductor structure of claim 7, wherein the at least one bit line is in direct contact with a backside source / drain contact structure disposed on the second source / drain region.

10. 6. The semiconductor structure of claim 5, wherein both the first source / drain region and the second source / drain region have non-faceted surfaces, the non-faceted surfaces being opposite surfaces of the first source / drain region and the second source / drain region that contact the vertical semiconductor channel material structure.

11. 6. The semiconductor structure of claim 5, further comprising a dielectric spacer disposed along a sidewall of said first source / drain region.

12. 10. The semiconductor structure of claim 1, wherein each DRAM capacitor of said plurality of DRAM capacitors is embedded in a back-end-of-line (BEOL) structure.

13. 13. The semiconductor structure of claim 12, further comprising a carrier wafer disposed on the back-end of line (BEOL) structure.

14. 14. The semiconductor structure of claim 13, wherein the carrier wafer is separated from each DRAM capacitor of the plurality of DRAM capacitors by a portion of the front-side BEOL structure.

15. 10. The semiconductor structure of claim 1, wherein each DRAM capacitor of said plurality of DRAM capacitors resides in a front-side inter-level dielectric material layer.

16. 16. The semiconductor structure of claim 15, wherein each DRAM capacitor extends entirely through said front-side inter-level dielectric material layer.

17. 17. The semiconductor structure of claim 16, further comprising a carrier wafer disposed on the front-side interlayer dielectric material layer.

18. 10. The semiconductor structure of claim 1, wherein each FET includes a gate structure disposed on each side of a vertical semiconductor channel material structure, wherein the gate structure includes a gate dielectric material layer in direct contact with a sidewall of the vertical semiconductor channel material structure, and a gate electrode disposed laterally adjacent to the gate dielectric material layer, wherein the gate electrode includes at least a work function metal layer.

19. 20. The semiconductor structure of claim 18, further comprising a gate polysilicon layer located between said gate dielectric material layer and said gate electrode.

20. 20. The semiconductor structure of claim 18, further comprising: a first dielectric spacer disposed on a surface of the gate structure and contacting the sidewalls of the vertical semiconductor channel material structure; and a second dielectric spacer disposed on another surface of the gate structure and contacting the sidewalls of the vertical semiconductor channel material structure.

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