Automatic Memory Overclocking

Abstract

Automatic memory overclocking is described. According to the described technique, one or more sets of overclocked memory configurations of a memory are automatically selected for memory performance and stability testing. The one or more sets of overclocked memory configurations are tested for memory performance, and a performance indication is output for each of the one or more sets of overclocked memory configurations. The one or more sets of overclocked memory configurations are tested for memory stability, and a stability indication is output for each of the one or more sets of overclocked memory configurations. One of the one or more sets of overclocked memory configurations is selected as the optimized overclocked memory configuration for the memory.

Description

[Technical Field]

[0001] (Related Applications) This application claims priority to U.S. patent application Ser. No. 18 / 147,963, entitled "Automated Memory Overclocking," filed Dec. 29, 2022, the entire disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0002] Memory, such as random access memory (RAM), stores data used by a computing device's processor. Memory performance generally depends on its operating frequency and its latency characteristics, often referred to as "timing." Memory can be "overclocked" by modifying certain parameters of the memory to achieve faster operating speeds that improve the computing device's performance. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of a non-limiting exemplary system having a memory and a memory controller operable to implement automatic memory overclocking. [Figure 2] FIG. 1 illustrates a non-limiting example in which memory settings are tested for performance and stability as part of automating memory overclocking. [Figure 3] FIG. 1 illustrates a non-limiting example of a user interface in one or more embodiments. [Figure 4] FIG. 1 illustrates a non-limiting example of a user interface in one or more embodiments. [Figure 5] FIG. 1 illustrates a non-limiting example of a user interface in one or more embodiments. [Figure 6] FIG. 1 illustrates a procedure for an exemplary embodiment of automatic memory overclocking. DETAILED DESCRIPTION OF THE INVENTION

[0004] (overview) Traditional approaches to memory overclocking utilize target memory setting profiles that are often generated based on a "worst case" perspective. While these memory setting profiles can exceed default memory capabilities, they are still fairly conservative and are not customized based on specific computing system parameters. Users who wish to further optimize memory beyond these default settings are often forced to rely on third-party software that generates target settings based on historical data. However, this historical data is based on the capabilities of other computing systems and does not take into account the hardware capabilities of a particular computing system.

[0005] To solve these problems, automated memory overclocking is described. The described techniques automate the process of determining optimal overclock settings for a computing system. To do so, the described techniques test both the performance and stability of memory settings for operating the memory, such as to test the performance and stability of one or more sets of overclocked memory settings. For example, the techniques described herein allow various overclocked memory settings to be adjusted and performance tests to be run using the adjusted overclocked memory settings. In one or more embodiments, a memory controller runs a performance test on the memory (e.g., by running a workload on the memory), which generates performance values ​​using the overclocked memory settings (or using the adjusted overclocked memory settings). This process is automatically repeated multiple times for various memory settings and various overclock values ​​for those memory settings. The performance values ​​generated by running the performance tests are used to generate a performance indication that identifies how sensitive the memory's performance is to one or more overclocked memory settings. The performance indication identifies which one or more overclocked memory settings will most impact memory operation for a particular optimization of interest to the user, thereby allowing the user to focus solely on selecting optimizations that will improve memory performance, reduce power usage, reduce latency, etc. This frees the user from having to guess or take a trial-and-error approach to determining which one or more memory settings to adjust to achieve the user's desired optimization.

[0006] The memory controller also tests the stability of overclocked memory settings that affect memory operation for a specified optimization according to one or more performance tests. This ensures that, to achieve the specified optimization, the controller sets overclocked memory settings within a range of values ​​that keep the memory system stable (e.g., within a guard band of memory margins). This allows the controller to select one or more overclocked memory settings that best affect the desired optimization of memory operating system performance while reducing or eliminating the risk that the selected settings will render the memory system non-functional.

[0007] In some aspects, the techniques described herein relate to a system that includes a memory; a performance scoring component for testing an overclocked memory configuration for the memory and outputting a performance indication for the overclocked memory configuration; a stability testing component for testing the overclocked memory configuration and outputting a stability indication that predicts stability of the memory over time when the memory is configured to operate at the overclocked memory configuration; and a setting selector component configured to output an optimized overclocked memory configuration based on the performance indication output by the performance scoring component and the stability indication output by the stability testing component.

[0008] In some aspects, the technology described herein relates to a system in which the configuration selector component is further configured to control testing by the performance scoring component and the stability testing component until an optimized overclocked memory configuration is determined.

[0009] In some aspects, the technology described herein relates to a system in which the configuration selector component is further configured to provide the overclocked memory configuration to a performance scoring component and a stability testing component for testing.

[0010] In some aspects, the techniques described herein relate to a system in which the configuration selector component is further configured to provide additional overclocked memory configurations to the performance scoring component and the stability testing component for testing based on at least one of a performance indication or a predicted stability of the memory.

[0011] In some aspects, the techniques described herein relate to a system where the setting selector component is further configured to provide additional overclocked memory settings to the performance scoring component and the stability testing component for testing in response to a prediction indicating that the memory will be too unstable when the memory is configured to operate at the overclocked setting, and where the additional overclocked memory settings provided by the setting selector component are configured to overclock the memory less aggressively than the overclocked memory settings.

[0012] In some aspects, the techniques described herein relate to a system in which the setting selector component is configured to operate the memory at an overclocked setting, and is further configured to provide an additional overclocked memory setting to the performance scoring component and the stability testing component for testing in response to a prediction indicating the memory is stable if the predicted stability is outside a marginal stability guard band, and the additional overclocked memory setting provided by the setting selector component is configured to overclock the memory more aggressively than the overclocked memory setting.

[0013] In some aspects, the technology described herein relates to a system in which a performance scoring component and a stability testing component test overclocked memory settings during the system boot-up process.

[0014] In some aspects, the technology described herein relates to a system in which the settings selector is further configured to automatically configure the memory to operate at optimized overclocked memory settings.

[0015] In some aspects, the technology described herein relates to a system in which the setting selector component is further configured to output the optimized overclocked memory setting to a user interface.

[0016] In some aspects, the technology described herein relates to a system in which the performance scoring component, the stability testing component, and the configuration selector component are implemented in a memory controller.

[0017] In some aspects, the techniques described herein relate to a method that includes selecting one or more sets of overclocked memory settings for memory performance and stability testing; testing the one or more sets of overclocked memory settings for memory performance and outputting a performance indication for each of the one or more sets of overclocked memory settings; testing the one or more sets of overclocked memory settings for memory stability and outputting a stability indication for each of the one or more sets of overclocked memory settings; and selecting one of the one or more sets of overclocked memory settings as an optimized overclocked memory setting for the memory.

[0018] In some aspects, the techniques described herein relate to a method further including automatically configuring the memory to operate at optimized overclocked memory settings.

[0019] In some aspects, the techniques described herein relate to a method further including outputting the optimized overclocked memory settings in a user interface.

[0020] In some aspects, the technology described herein relates to a method in which a user interface includes one or more controls for enabling adjustment of optimized overclocked memory settings.

[0021] In some aspects, the technology described herein relates to a method, during a boot-up process, selecting one or more sets of overclocked memory settings for testing, testing the one or more sets of overclocked memory settings for memory performance and outputting a performance indication for each of the one or more sets of overclocked memory settings, testing the one or more sets of overclocked memory settings for memory stability over time and outputting a stability indication for each of the one or more sets of overclocked memory settings, and selecting one of the one or more sets of overclocked memory settings as an optimized overclocked memory setting for the memory.

[0022] In some aspects, the techniques described herein relate to a computing device that includes a memory; and a memory controller for initiating a boot-up process of the computing device to automatically select an optimized overclocked memory setting for the memory; automatically identifying one or more sets of overclocked memory setting for testing during the boot-up process of the computing device; testing the one or more sets of overclocked memory setting for memory performance and outputting a performance indication for each of the one or more sets of overclocked memory setting; testing the one or more sets of overclocked memory setting for memory stability and outputting a stability indication for each of the one or more sets of overclocked memory setting; and selecting one of the one or more sets of overclocked memory setting as the optimized overclocked memory setting.

[0023] In some aspects, the technology described herein relates to a computing device, wherein the memory controller is further configured to automatically configure the memory to operate at optimized overclocked memory settings.

[0024] In some aspects, the technology described herein relates to a computing device, wherein the memory controller is further configured to output the optimized overclocked memory settings to a user interface.

[0025] In some aspects, the technology described herein relates to a computing device in which a user interface enables adjustment of optimized overclocked memory settings.

[0026] In some aspects, the technology described herein relates to a computing device in which a memory controller initiates a boot-up process in response to user input to a user interface to select an optimized overclocked memory setting.

[0027] 1 is a block diagram of a non-limiting, exemplary system 100 having a memory and a memory controller operable to implement automatic memory overclocking. In particular, system 100 includes memory 102, a memory controller 104, and a processing unit 106. According to the described technology, memory 102, memory controller 104, and processing unit 106 are coupled to one another via one or more wired or wireless connections. Exemplary wired connections include, but are not limited to, buses (e.g., data buses), interconnects, through-silicon vias, traces, and planes. Examples of devices or apparatuses into which system 100 may be integrated include, but are not limited to, servers, personal computers, laptops, desktops, game consoles, set-top boxes, tablets, smartphones, mobile devices, virtual and / or augmented reality devices, wearables, medical devices, systems-on-chips, and other computing devices or systems.

[0028] Memory 102 is a device or system used to store information, such as for immediate use within a device. In one or more embodiments, memory 102 corresponds to semiconductor memory in which data is stored in memory cells on one or more integrated circuits. In at least one example, memory 102 corresponds to or includes volatile memory, examples of which include random-access memory (RAM), dynamic random-access memory (DRAM), and static random-access memory (SRAM). Alternatively or additionally, memory 102 corresponds to or includes non-volatile memory, examples of which include flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), and non-volatile dual in-line memory modules (DIMMs) (NVDIMMs).

[0029] In one or more embodiments, memory 102 is configured as a dual in-line memory module (DIMM). DIMMs contain an array of dynamic random access memory integrated circuits, and the module is mounted on a printed circuit board. Examples of DIMM types include, but are not limited to, synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, double data rate 2 (DDR2) SDRAM, double data rate 3 (DDR3) SDRAM, double data rate 4 (DDR4) SDRAM, and double data rate 5 (DDR5) SDRAM. In at least one variation, memory 102 is configured as a small outline DIMM (SO-DIMM) according to any of the SDRAM standards mentioned above, e.g., DDR, DDR2, DDR3, DDR4, and DDR5. In one or more embodiments, memory 102 is low-power double data rate (LPDDR) (also known as LPDDR SDRAM), a type of synchronous dynamic random access memory. In variations, LPDDR consumes less power than other types of memory and / or has a form factor suitable for devices such as mobile computers and mobile phones. Examples of LPDDR include, but are not limited to, low power double data rate 2 (LPDDR2), low power double data rate 3 (LPDDR3), low power double data rate 4 (LPDDR4), and low power double data rate 5 (LPDDR5). It should be understood that memory 102 can be configured in various manners without departing from the spirit or scope of the described technology.

[0030] The memory controller 104 manages the memory 102, including the transfer of data to and from the memory 102. For example, the memory controller 104 manages the transfer of data from the processing unit 106 to the memory 102 and from the memory 102 to the processing unit 106, e.g., via a coupling between the memory 102 and the processing unit 106. As previously described and as described further below, the memory controller 104 tests (e.g., during the boot-up process) the performance and stability of the settings (e.g., clock and / or power settings) at which the memory 102 is configured or can be configured to operate. In at least one variation, such settings are specified in one or more memory profiles.

[0031] Processing unit 106 is a component that requests access to data from memory 102, e.g., to perform one or more operations related to such data in connection with executing an application (not shown). Examples of processing units include, but are not limited to, central processing units, parallel acceleration processors (e.g., graphics processing units), digital signal processors, hardware accelerators, microcontrollers, processing-in-memory (PIM) components, and systems-on-chips. In variations, different types of processing units can be used within a system in accordance with the described techniques.

[0032] In the illustrated example, memory controller 104 is shown having an auto-configuration system 108 and memory control data 110. Auto-configuration system 108 is shown including various components, which will be described in more detail below. It should also be understood that auto-configuration system 108 (and / or one or more of its components) is not included in memory controller 104 but is implemented remotely from memory controller 104. Memory control data 110 includes one or more non-overclocked memory profiles 112 and one or more overclocked memory profiles 114. The non-overclocked memory profiles 112 are implemented using memory settings 116, and the overclocked memory profiles 114 are implemented using overclocked memory settings 118.

[0033] According to the described techniques, the overclocked memory configuration 116 includes at least one memory configuration that is overclocked. In one or more scenarios, not all memory configurations in the overclocked memory profile 114 are overclocked. However, in other scenarios, all memory configurations in the overclocked memory profile 114 are overclocked. In one or more embodiments, an “overclocked” memory configuration exceeds the certified value of the configuration. For example, a clock rate that is set to exceed a clock rate certified by the manufacturer of the memory 102 is “overclocked.” In contrast, a “non-overclocked” memory configuration does not exceed the certified value of the configuration; for example, a “non-overclocked” clock rate does not exceed a clock rate certified by the manufacturer of the memory 102. Generally, use of the overclocked memory configuration 118 and / or use of the overclocked memory profile 114 allows the memory 102 to operate in an overclocked mode.

[0034] In one or more embodiments, the memory configuration 116 and overclocked memory configuration 118 include various clock and / or power settings. Exemplary settings include data rate (e.g., megatransfers per second), the number of cycles between sending a column address to the memory and the start of data in response (e.g., CAS or tCAS), the minimum number of clock cycles to open a row and access a column (e.g., tRCD), a measure of latency between issuing a precharge command to idle or close an opened column and issuing a activate command to open a different row (e.g., tRP), the minimum number of clock cycles between issuing a row active command and a precharge command (e.g., tRAS), an active-to-active delay within the same bank group (e.g., tRRDL), an active-to-active delay to a different bank group (e.g., tRRDS), a 4-active window time (e.g., tFAW), a write recovery time (e.g., tWR), These may include, but are not limited to, column address strobe (CAS) latency time (e.g., tAA), active-to-active / refresh delay time (e.g., tRC), refresh recovery delay time in normal refresh mode (tRFC1), refresh recovery delay time in fine-grained refresh mode (tRFC2), refresh recovery delay time in same bank refresh mode (tRFCs), write-to-read command delay in seconds within the same bank group (tWTRL), write-to-read command delay in seconds within different bank groups (tWTRS), read-to-precharge delay (tRTP), nominal power supply voltage (e.g., VDD), output stage drain power voltage (e.g., VDDQ), programming power voltage (e.g., VPP), etc. It should be understood that memory setting 116 and / or overclocked memory setting 118 specify values ​​for one or more of those settings and / or various other settings associated with the operating memory without departing from the spirit or scope of the described technology.

[0035] According to the described techniques, the auto-configuration system 108 of the memory controller 104 and / or another component of the system 100 (e.g., the physical layer (PHY)) is configured to test the performance and stability of memory settings for operating the memory 102, such as testing the performance and stability of memory settings 116 of one or more non-overclocked memory profiles 112 and / or overclocked memory settings 118 of one or more overclocked memory profiles 114. For example, the auto-configuration system 108 tests the performance of the memory settings to determine which memory settings, when adjusted, will most effectively affect the operation of the memory 102 to achieve one or more optimization objectives, such as optimized performance of the memory 102, reduced power usage by the memory 102, reduced latency of the memory 102, etc. The auto-configuration system 108 also tests the stability of the memory settings, such as by testing the stability of one or more overclocked values ​​of the memory settings identified to most effectively affect the operation of the memory 102 in relation to achieving one or more specified optimization objectives. The auto-configuration system 108 tests the performance and stability of such memory configurations during the boot-up phase of the system 100. In one or more embodiments, the auto-configuration system 108 iteratively tests one or more sets of overclocked memory configurations 118 for performance and tests one or more sets of overclocked memory configurations 118 for stability. In at least one variation, all sets of overclocked memory configurations that have been performance-tested are also stability-tested. However, in at least one other variation, fewer than all sets of overclocked memory configurations that have been performance-tested are also stability-tested. Rather than stability-testing all sets, for example, a subset of the performance-tested set of overclocked memory configurations is also stability-tested, such as a set of overclocked memory configurations that have performance values ​​that indicate they will sufficiently affect memory operation (e.g., above a threshold) to achieve one or more optimization objectives.

[0036] In this example, auto-configuration system 108 is illustrated as including a configuration selector component 120, a performance scoring component 122, and a stability testing component 124. In variations, these components are configured as firmware or intellectual property (IP) cores running on or otherwise accessible to memory controller 104. Alternatively, one or more of these components are implemented in hardware. While illustrated as part of memory controller 104, in one or more embodiments, auto-configuration system 108 and / or one or more of configuration selector component 120, performance scoring component 122, and stability testing component 124 are implemented remotely from memory controller 104. Additionally or alternatively, auto-configuration system 108 may, in variations, include more, fewer, or different components to implement the described techniques.

[0037] The illustrated example also includes an optimization request 126. As described in more detail below, in one or more embodiments, the optimization request 126 is received. For example, the optimization request 126 is received in response to user input selecting an option via a user interface to optimize the memory 102. In at least one variation, such a user interface presents (e.g., displays) one or more optimization objectives from which the user can select to optimize the memory 102. Examples include optimizing the performance of the memory 102 (e.g., increasing the number of read / write accesses processed, increasing the frequency at which read / write accesses are processed, etc.), optimizing power usage by the memory 102, optimizing the latency of the memory 102, and performing a default optimization in which one or more optimizations are weighted / combined to achieve an overall optimization, to name a few.

[0038] Thus, in one or more embodiments, optimization request 126 includes or otherwise indicates the specified optimization. While user input is described above as triggering optimization request 126, in at least one variation, optimization request 126 is triggered by an application, such as when the application is launched, installed, or updated. In response to optimization request 126, system 100 is powered down and then undergoes a boot-up process during which the overclocked memory configuration is tested (e.g., iteratively) for performance and stability by memory controller 104 and / or one or more of its various components.

[0039] In at least one variation, the configuration selector component 120 selects one or more sets of configurations to be performance tested by the performance scoring component 122 and stability tested by the stability testing component 124. By way of example, the configuration selector component 120 selects at least a first set of overclocked memory configurations 118 to be tested. In one or more scenarios, after this first set is tested, the configuration selector component 120 selects at least a second set (e.g., a next set) of overclocked memory configurations 118 to be tested based on performance indications and stability indications generated in association with testing the first set.

[0040] In one or more embodiments, the setting selector component 120 selects the next set of overclocked memory settings 118 for testing until the performance and stability indications meet one or more thresholds and / or ranges. By way of example and not limitation, the next set of settings is selected, and iterations of performance and stability testing are performed until the performance indications of the set of settings meet the threshold performance (or threshold improvement) and the stability indications of the set of settings fall within a marginal stability range (e.g., a range indicating that operation of the memory 102 is “stable enough” when operated according to the set of settings). In one or more embodiments, the marginal stability range is based on identifying values ​​of the settings that cause unstable operation of the memory 102 and buffering those values ​​(e.g., using a guard band) so that the overclocked memory settings are not set to values ​​within the buffer (or at a level determined to be unstable) that cause unstable operation of the memory 102. Furthermore, the marginal stability range is within the threshold stability of the guard band. Thus, in one or more variations, the guard band defines a minimum level of stability in the marginal stability range, and the threshold stability added to the guard band defines a maximum level of stability in the marginal stability range. In one or more embodiments, the settings selector component 120 causes the next set of settings to be selected if the tested set is "not stable enough" (e.g., the stability indication reaches the instability level or is within the guard band of the instability level).

[0041] In at least one variation, during the boot-up process of the system 100, the performance scoring component 122 tests the performance of overclocked memory configurations 118 to operate the memory 102 according to the following description. The performance scoring component 122 runs performance tests using at least one set of overclocked memory configurations 118, making various read and write requests to the memory 102. As described above and below, in one or more variations, the performance tests run by the performance scoring component 122 include or otherwise correspond to running one or more workloads with the memory 102. For example, different workloads are designed to test the performance of the memory 102 in relation to different optimizations and generate performance values ​​that identify settings that achieve (or improve performance toward) such optimizations, such as memory 102 latency, memory 102 bandwidth, memory 102 power usage (e.g., battery life for a notebook or other portable device, performance-per-power calculations for a desktop computer), etc. When executed on memory 102, a workload generates one or more performance values ​​that are provided to (or recorded by) performance scoring component 122.

[0042] The performance scoring component 122 evaluates these performance values ​​and generates a performance indication that indicates how sensitive the performance of the memory 102 is to the one or more memory settings tested. The performance indication is output to any of a variety of different devices or entities. For example, the performance indication may be output to the settings selector component 120 and / or the stability testing component 124, which may use the performance indication to automatically (e.g., without user input) determine which memory settings to adjust to improve performance of the memory 102 (e.g., to overclock the memory 102 to achieve one or more optimization objectives). In at least one embodiment, the performance indication is output via a display device (e.g., after the system 100 has completed its boot-up process) so that a user can see which memory settings will have the greatest or least effect on achieving the optimization. Additionally or alternatively, an indication derived from the performance indication (e.g., a grade, a heat map, etc., as described in more detail below) showing the general sensitivity of the memory to one or more changed memory settings is output to a display device or another application or system.

[0043] In one or more embodiments, the performance scoring component 122 adjusts one or more of the multiple different memory settings multiple times, and one or more workloads executed during the performance test generate one or more performance values ​​for the new overclocked memory setting 118 (or set thereof) after each adjustment, thereby enabling the performance scoring component 122 to generate one or more performance indications identifying to which overclocked memory setting 118 the memory 102 is most (and least) sensitive for the workloads executed during the performance test.

[0044] It should be noted that while a single workload may be executed as part of a performance test performed by performance scoring component 122, in one or more embodiments performance scoring component 122 executes two or more workloads. In one or more embodiments, performance scoring component 122 generates one or more performance indications for each different workload. Additionally or alternatively, performance scoring component 122 generates one or more comprehensive or combined performance indications for multiple different workloads.

[0045] By determining through performance testing which particular memory settings, when overclocked, have the most or least effect on the memory 102 with respect to achieving optimization goals, stability testing can then be used to determine how much those memory settings can be adjusted (e.g., overclocked) to maintain operation of the memory 102 within a stable range, e.g., within marginal stability.

[0046] In at least one variation, the stability testing component 124 tests the stability of a set of overclocked memory settings 118 (e.g., overclocked memory profile 114) for operating memory 102 during the boot-up process of system 100. For example, the setting selector component 120 assigns a set of overclocked memory settings 118 to the stability test based on a previous performance test. For example, the setting selector component 120 assigns a set of settings during the boot-up process, e.g., a set of settings previously performance tested by the performance scoring component 122 during that boot-up process. During the boot-up process of system 100, the stability testing component 124 of the memory controller 104 also tests the stability of the overclocked memory settings 118. In at least one variation, the stability testing component 124 performs one or more initial stability tests on the set of overclocked memory configurations 118, and if the memory configurations "pass" the initial stability tests, e.g., if the configurations are shown via the initial stability tests to be stable or at least marginally stable, performs one or more additional stability tests.

[0047] After performing one or more stability tests on the memory 102, one or more stability indications are returned, for example, to the configuration selector component 120. Using the one or more stability indications, the configuration selector component 120 determines whether to continue to perform repeated performance and stability tests or to proceed to operate the memory 102 using the tested configurations. In a scenario in which the configuration selector component 120 determines to proceed to operate the memory 102 using the tested memory configurations, an optimization result 128 is returned indicating a selected set of overclocked memory configurations 118, e.g., optimized overclocked memory configurations. In at least one variation, the memory controller 104 causes one or more change signals to modify operation of the memory 102 to operate according to the overclocked memory configurations 118 included in the optimization result 128. In this manner, the memory controller 104 automatically tests various combinations of overclocked memory settings and automatically selects a set of overclocked memory configurations for operating the memory 102 to optimize performance of the memory 102 to achieve at least one optimization objective. As used herein, "automatically testing" refers to performance and stability testing of various combinations of settings and their values ​​without receiving user input to select which specific memory settings to test or at what values, and "automatically" selecting refers to selecting values ​​to set overclocked memory settings to without receiving user input specifying how to specifically set them.

[0048] In one or more embodiments, human-understandable information indicative of the optimization results 128 (e.g., the adjusted settings and one or more descriptions of those adjusted values) is presented (e.g., displayed) via a user interface. Generally, the results of the one or more stability tests are predictive of the stability of the memory 102 over a subsequent period of time when the memory 102 is configured to operate with an overclocked set of memory settings. Alternatively or additionally, the memory controller 104 is configured to test the stability of settings for operating the memory 102 during a phase different from the boot-up phase, such as while the system 100 is in a "sleep" state.

[0049] In one or more embodiments, the stability test component 124 performs one or more stability tests on the memory 102 during the boot-up phase. While the stability tests described above and below are described herein as being performed by the memory controller 104, it should be understood that they can be performed by the stability test component 124 and / or another component in variations. The tests performed are configured to test the stability of at least one memory configuration set (e.g., an overclocked memory configuration set selected or adjusted by the configuration selector component 120), e.g., the stability of the memory 102 operating using the at least one memory configuration set. By way of example, during training of the memory 102, the stability test component 124 determines stability margins for the bitlines of the memory 102 to operate and uses those margins to determine optimal settings for initializing the hardware. In accordance with the described techniques, the stability test component 124 uses the stability margins to determine the stability of the memory 102 over a subsequent period of time, e.g., long-term hardware stability.

[0050] Examples of one or more tests that the stability testing component 124 and / or other components may perform on the memory 102 during boot-up to test the stability of the memory 102 under various settings include, but are not limited to, performing a reference voltage (Vref) and / or delay-locked loop (DLL) shmoo (e.g., generating one or more "eye diagrams" of the memory 102 or portions of the memory 102), performing virtual timing and signal analysis (vTSA), adjusting different voltage and / or delay levels to generate visualizations of memory data eyes of different bits of the memory, checking one or more portions of the memory 102 for row hammering, and performing one or more RSC tests. In one or more embodiments, the stability testing component 124 generates one or more eye diagrams of the memory 102 using a combination (e.g., a multi-dimensional combination) of a reference voltage (Vref) and a DLL shmoo. In at least one variation, a reference voltage (Vref) is shmooed to determine whether a signal is a "1" or a "0" in conjunction with generating a memory eye diagram. For example, based on the generated eye diagram, the stability test component 124 obtains a margin within which the memory 102 can perform predetermined changes in the environment in which the memory 102 operates. In variations, different tests are performed to test the stability of the memory 102 without departing from the described techniques.

[0051] In contrast to the described stability testing techniques, traditional approaches involve running one or more "stress tests" using software, such as through an operating system. Such tests can take hours (up to days) to determine the stability of a system. This is at least in part because traditional tests are run through software, which involves access (e.g., by the operating system) through one or more cores (of a processing unit), then through the system's data fabric, and then to the memory being stress tested—a slower path than a direct path to memory. Furthermore, traditional stress tests are limited to determining the stability of a system relative to the environmental variables and workloads at the time the test is run, but the tests do not guarantee that the system will perform stably over the long term, especially when memory operation approaches its margins.

[0052] According to the described technology, the stability testing component 124 (e.g., as part of the memory controller 104) directly accesses the memory 102. In other words, the stability tests are performed on the memory 102 directly from the memory controller 104. As a result, the stability tests performed on the memory 102 to determine the stability of the overclocked memory configuration 118 are faster than traditional stress tests. By performing one or more of the tests during boot-up, the stability testing component 124 bypasses refresh and other periodic background activities that cannot be performed in various scenarios where the system is already started (e.g., running software). Furthermore, by performing the performance and stability tests during boot-up by directly accessing the memory 102, the performance scoring component 122 and the stability testing component 124 avoid background latencies that occur in the operating system and / or other software after the system has booted up.

[0053] The illustrated example shows clock and power 130 inputs to memory 102 and memory controller 104. According to the described techniques, memory controller 104 and / or another component is configured to set the clock and power 130 inputs to operate memory 102 according to a set of memory settings, such as a set of overclocked memory settings 118 or a set of overclocked memory profiles 114, as shown in optimization results 128.

[0054] For example, memory controller 104 causes memory 102 to operate according to the set of overclocked memory settings 118 by sending one or more modification signals to a voltage generator (not shown) to adjust a supply voltage (e.g., VDD) such that the clock input and power 130 input subsequently include the supply voltage adjusted according to the modification signals. Additionally or alternatively, memory controller 104 sends modification signals to a reference clock generator (not shown) to change the frequency of the clock rate such that the clock and power 130 inputs subsequently include the reference clock signal adjusted according to the modification signals. Memory controller 104 is operable to adjust the clock and power 130 inputs in various ways to operate memory 102, for example, to generate the settings specified in optimization results 128.

[0055] 2 illustrates a non-limiting example implementation 200 in which memory settings are tested for performance and stability as part of automating memory overclocking. Example implementation 200 includes memory 102, memory controller 104, and processing unit 106 of FIG. 1. Additionally, memory controller 104 is illustrated as including setting selector component 120, performance scoring component 122, and stability testing component 124. While shown as including these components, it should be understood that in one or more embodiments, memory controller 104 (or some other component) is considered to perform the operations described herein as being performed by setting selector component 120, performance scoring component 122, and / or stability testing component 124.

[0056] Example 200 includes various exemplary communications and operations between controller 104, memory 102, and processing unit 106 over time. In this example 200, the communications and operations are arranged vertically based on time, with communications and operations closer to the top of the example occurring before communications or operations further from the top of the example. Also, communications or operations closer to the bottom of the example will occur after communications or operations further from the bottom. Example 200 also illustrates various phases and / or states of system 100 or portions of system 100. These phases and / or states are also arranged vertically based on time in example 200, such that phases or states closer to the top of the example occur before phases, states, or communications further from the top.

[0057] Here, the illustrated example 200 shows memory controller 104 receiving optimization request 126. In one or more embodiments, optimization request 126 is received based on user input, such as user input received via a displayed control (e.g., a button), to optimize operation of memory 102. As described above and below, in variations, the described systems optimize operation of memory 102 to achieve optimization objectives such as optimized performance of memory 102, reduced power usage by memory 102, reduced latency of memory 102, etc.

[0058] The illustrated example 200 also shows a boot-up phase 202 of the system 100. In one or more embodiments, the system 100 enters the boot-up phase 202 based on receiving an optimization request 126. While a power-off phase is not shown, in one or more such embodiments, the system 100 is powered off based on the optimization request 126, and then the system 100 is triggered to boot up. During the power-off phase, the system 100 (and memory 102) is powered off, examples of which include a soft off (e.g., a G2 / S5 state specified by the Advanced Configuration and Power Interface (ACPI)) and a hard off (e.g., a G3 state specified by ACPI), which require a reboot to return to an operational state (e.g., a G0 / S0 state specified by ACPI). During the boot-up phase 202, the system 100 performs various operations, such as hardware initialization, to advance the system 100 to an operational state.

[0059] In accordance with the described techniques, the boot-up phase 202 includes a performance test 204 and a stability test 206 of the memory 102. Generally, the setting selector component 120 controls the testing by the performance scoring component 122 and the stability testing component 124 until an optimized overclocked memory setting is determined. As part of this, for example, the memory controller 104 (e.g., the setting selector component 120) selects a first overclocked memory setting 208 for the performance test 204 and the stability test 206. The memory controller 104 (e.g., the performance scoring component 122) tests the performance of the first overclocked memory setting 208 for operating the memory 102. In one or more embodiments, the performance scoring component 122 performs the performance test 204, at least in part, by executing one or more workloads with the memory 102, the workloads including various read and / or write accesses to the memory 102.

[0060] When the performance scoring component 122 runs a performance test 204 on the memory 102, one or more workloads executed as part of the test generate performance values ​​210 that describe the performance of the memory 102 with respect to completing one or more memory-based tasks or operations when configured according to the first overclocked memory setting 208. The performance values ​​210 are then used individually or in combination to generate one or more performance indications for the first overclocked memory setting 208.

[0061] Additionally, the memory controller 104 (e.g., stability test component 124) tests the stability of the first overclocked memory setting 208 for operating the memory 102. As part of the stability test 206, in one or more embodiments, the stability test component 124 tests the stability of operating the memory 102 with the first overclocked memory setting 208 by performing a reference voltage (Vref) and / or a delay-locked loop (DLL) shmoo and / or by generating one or more "eye diagrams" of the memory 102 or portions of the memory 102. The memory controller 104 obtains a margin within which the memory 102 can perform, for example, based on the stability test 206.

[0062] When the stability test component 124 performs stability tests 206 on the memory 102, the memory controller 104 (e.g., the configuration selector component 120 and / or the stability test component 124) receives stability notifications 212 (e.g., signals) indicative of the memory 102's response to the stability tests performed during the boot-up phase 202. For example, when the stability test component 124 performs a reference voltage (Vref) and / or a DLL shmoo within the memory 102, the memory controller 104 receives stability notifications 212 indicative of the operation and / or margin of operation of the memory 102 under various combinations of voltage and / or delay levels.

[0063] In one or more scenarios, the setting selector component 120 causes the next set of overclocked memory configurations 118 to be tested, e.g., using the performance test 204 and the stability test 206. As described above and below, for example, the setting selector component 120 controls the testing by the performance scoring component 122 and the stability test component 124 until an optimized overclocked memory configuration is determined. By way of example, the setting selector component 120 selects an additional set of overclocked memory configurations that do not overclock the memory 102 more aggressively than the first overclocked memory setting 208, such as in a scenario where the stability notification 212 is processed to generate a prediction that the memory 102 would be too unstable if configured to operate at the first overclocked memory setting 208. Alternatively, the setting selector component 120 selects an additional set of overclocked memory settings that overclock the memory 102 more aggressively than the first overclocked memory setting 208, such as in a scenario where the stability notification 212 is processed to generate a prediction that the memory 102 is stable when configured to operate at the first overclocked memory setting 208 and the predicted stability is outside the marginal stability range (i.e., the first overclocked memory setting 208 is “too stable”). In other words, the setting selector component 120 performs setting adjustments 214 on the first overclocked memory setting 208 and adjusts them to generate a second overclocked memory setting 216 that differs from the first overclocked memory setting 208.

[0064] The memory controller 104 (e.g., the setting selector component 120) then provides the second overclocked memory setting 216 for the performance test 204 and the stability test 206. The memory controller 104 (e.g., the performance scoring component 122) tests the performance of the second overclocked memory setting 216 for operating the memory 102. By way of example, the performance scoring component 122 performs the performance test 204 on the second overclocked memory setting 216, at least in part, by executing one or more workloads with the memory 102, the workloads including various read and / or write accesses to the memory 102. When the performance scoring component 122 performs the performance test 204 using the second overclocked memory setting 216, the one or more workloads executed as part of the test generate a performance value 218 that describes the performance of the memory 102 with respect to completing one or more memory-based tasks or operations when configured according to the second overclocked memory setting 216. The performance values ​​218 are then used individually or in combination to generate one or more performance indications for the second overclocked memory setting 216 .

[0065] Additionally, the memory controller 104 (e.g., the stability test component 124) tests the stability of the second overclocked memory setting 216 for operating the memory 102. As part of the stability test 206, in one or more embodiments, the stability test component 124 tests the stability of operating the memory 102 with the second overclocked memory setting 216 by performing a reference voltage (Vref) and / or a delay-locked loop (DLL) shmoo and / or by generating one or more "eye diagrams" of the memory 102 or portions of the memory 102. Based on the stability test 206, the memory controller 104 obtains the margin within which the memory 102 is capable of performing when configured according to the second overclocked memory setting 216.

[0066] When the stability test component 124 performs the stability test 206 on the memory 102 for the second overclocked memory setting 216, the memory controller 104 (e.g., the setting selector component 120 and / or the stability test component 124) receives a stability notification 220 (e.g., a signal) indicating the response of the memory 102 to the stability test performed during the boot-up phase 202, for example, when the memory 102 is configured according to the second overclocked memory setting 216. For example, when the stability test component 124 performs a reference voltage (Vref) and / or a DLL shmoo on the memory 102, the memory controller 104 receives the stability notification 220 indicating the operation and / or margin of operation of the memory 102 with the second overclocked memory setting 216 under various combinations of voltage and / or delay levels.

[0067] The illustrated example 200 illustrates an ellipsis in the boot-up phase 202, indicating that in a variant, the configuration selector component 120 performs three or more iterations of selecting a set of settings, performance testing the set of settings 204, stability testing the set of settings 206, and adjusting those settings to generate the next set of settings for testing. As described above, for example, the configuration selector component 120 controls testing by the performance scoring component 122 and stability testing component 124 until an optimized overclocked memory configuration is determined.

[0068] In response to determining the optimized overclocked memory configuration, an optimization result 128 is output. In one or more embodiments, the optimization result 128 includes or otherwise indicates the optimized overclocked memory configuration. In at least one variation, the memory controller 104 (e.g., the setting selector component 120) outputs the optimization result 128, causing the memory 102 to operate according to the optimized overclocked memory configuration. For example, the memory controller 104 causes the memory 102 to operate according to the optimized overclocked memory configuration by sending one or more modification signals to a voltage generator (not shown) to adjust a supply voltage (e.g., VDD) such that the clock and power 130 input subsequently includes the supply voltage adjusted according to the modification signals. Additionally or alternatively, the memory controller 104 sends a modification signal to a reference clock generator (not shown) to modify the frequency of the clock rate, such that the clock and power 130 input subsequently includes the reference clock signal adjusted according to the modification signals.

[0069] Additionally or alternatively, memory controller 104 outputs optimization results 128 by communicating them (e.g., via a handshake) to software such as an operating system (not shown). Alternatively or additionally, the operating system further provides the test results to an application running on the operating system, such as a memory management application. According to the described techniques, optimization results 128 are output (e.g., displayed) in a human-understandable format via a user interface, such as via a user interface of the operating system and / or a user interface of a memory management application. Examples of formats in which optimization results 128 may be output include, but are not limited to, a numerical score, a stoplight icon, a text label describing the hierarchical level of optimization, a graphical icon, a graph or chart illustrating memory performance and / or stability over time when the memory is configured to operate at an optimized, overclocked memory setting, and one or more visualizations of a generated eye diagram, to name a few. In variations, optimization results 128 may be output in a different human-understandable manner that illustrates the performance and / or stability of memory 102 under the tested settings without departing from the spirit or scope of the described techniques.

[0070] Also in this embodiment 200, the memory controller 104 provides one or more configured, optimized, overclocked memory settings 222 signals to the memory 102 to cause the memory 102 to operate according to an optimized overclocked memory mode 224. By selecting the optimized overclocked memory settings through iterations of the performance test 204 and the stability test 206, the described techniques automate memory overclocking such that memory overclocking can be performed without user input specifying values ​​for overclocking one or more memory settings. According to the described techniques, the memory controller 104 operates the memory 102 according to the optimized overclocked memory mode 224 in a different mode, such as a non-optimized mode, an overclocked memory mode optimized for a different optimization objective (e.g., performance vs. power usage), or following one or more settings operating according to the overclocked memory mode based on user input, to name but a few.

[0071] Additionally or alternatively, optimization results 128 may include or be used to generate recommendations for output. In one variation, for example, such recommendations may suggest that a user select an optimization objective or combination of optimization objectives and allow system 100 to automatically select overclocked memory settings to achieve those objectives. By way of example, a software application (e.g., a memory management application) may generate and output (e.g., display) a notification after a threshold time (e.g., hours, days, months, etc.) reminding a user of system 100 to select an optimization objective and allow the system to automatically optimize overclocked memory settings to achieve the optimization.

[0072] In this example 200, memory 102 is shown receiving data requests 226 originating from processing units 106 and providing data 228 to processing units 106 to service those requests in accordance with the described techniques. In particular, memory controller 104 receives one or more data requests 226 from processing units 106, and memory controller 104 schedules the data requests 226 to memory 102. Memory controller 104 then accesses (e.g., reads from) a portion of memory 102 corresponding to data request 226 (e.g., to retrieve the respective data 228). Memory controller 104 then provides the respective data 228 to processing unit 106. This process of requesting data, retrieving data from memory 102 (e.g., reading data from memory 102), and providing the read data to processing unit 106 is performed while memory 102 is operating in accordance with optimized overclocked memory mode 224. According to the described techniques, the processing unit 106 can cause the memory controller 104 to write data to the memory 102 while operating in the optimized overclocked memory mode 224 .

[0073] In particular, by performing stability tests on the automated overclocking settings, memory controller 104 can determine system stability expectations. Thus, in one or more embodiments, after an automatic memory overclocking is performed, memory controller 104 can notify the user after a period of time that a stability test should be performed again to ensure that the automatic memory overclocking settings are still stable.

[0074] Consider the following description of FIGS. 3-5 in the context of a user interface for automatic memory overclocking.

[0075] 3 illustrates a non-limiting example user interface 300 according to one or more embodiments. The example user interface 300 includes a display device 302 that outputs a memory overclocking user interface 304.

[0076] In the illustrated example 300, a user interface 304 is shown displaying a set of memory configurations 306 according to which the memory 102 can operate. In this embodiment 300, the user interface 304 includes a control 308 that is selectable (e.g., via user input) to initiate automated overclocking of the memory 102. For example, receipt of user input on the control 308 corresponds to or triggers an optimization request 126, whereby the system 100 automatically selects an optimized, overclocked memory configuration for operating the memory 102. This includes running performance tests 204 and stability tests 206 on one or more sets of configurations selected by the configuration selector component 120 during the boot-up phase 202 until an optimized, overclocked memory configuration is determined.

[0077] In one or more embodiments, the user interface 304 allows a user to provide user input to adjust one or more settings at which the memory 102 operates. Additionally or alternatively, the user interface 304 includes controls that allow a user to select to initiate such user-selected settings performance test 204 and / or user-selected settings stability test 206. Indeed, it should be understood that in variations, the user interface for automatic memory overclocking may be configured in different manners without departing from the spirit or scope of the described technology.

[0078] 4 illustrates a non-limiting example user interface 400 according to one or more embodiments. The example user interface 400 includes a display device 402 that outputs a memory overclocking user interface 404.

[0079] Similar to the illustrated embodiment 300, the illustrated embodiment 400 shows a user interface 404 that displays a set of memory configurations 406 with which the memory 102 is capable of operating. Also similar to the illustrated embodiment 300, the user interface 404 in the illustrated embodiment 400 includes a selectable control 408 (e.g., via user input) to initiate automated overclocking of the memory 102. However, in contrast to the user interface 304, the user interface 404 further includes an optimization control 410 for selecting one or more optimization objectives. For example, receiving user input on the control 410 specifies one or more optimization objectives for one or more scenarios. Examples of such optimizations are described above. In one or more embodiments, specifying one or more such optimizations includes including such optimizations in the optimization request 126, such that the memory controller 104 determines an optimized overclocked memory configuration based on the specified optimizations included in the optimization request 126. In one or more embodiments, the user interface 404 includes additional controls that allow a user to select specific settings for automatic memory overclocking. For example, the user interface 404 may include controls that allow navigation to additional customization menus, allowing the user to specify precise settings for automatically overclocking.

[0080] Thus, in one example, receiving user input on control unit 408 triggers generation of optimization request 126, such that optimization request 126 is generated to include one or more specified optimization objectives, e.g., objectives specified based on user input via optimization control unit 410. In accordance with the described techniques, optimization request 126 then causes system 100 to automatically select an optimized overclocked memory configuration for operating memory 102. This includes running performance tests 204 and stability tests 206 on one or more configuration sets selected by configuration selector component 120 during boot-up phase 202 until an optimized overclocked memory configuration is determined.

[0081] 5 illustrates a non-limiting example user interface 500 according to one or more embodiments. The example 500 includes a display device 502 that outputs a memory overclocking user interface 504.

[0082] In the illustrated example 500, the user interface 504 is shown displaying a notification 506 indicating that an optimized overclocked memory configuration has been determined (e.g., by the setting selector component 120, the performance scoring component 122, and the stability testing component 124 during the boot-up phase 202) and that the memory 102 has been adjusted to operate in accordance with the optimized overclocked memory configuration. In one or more embodiments, such a notification is displayed after the system boot-up phase 202 and when the system 100 returns to an operational state (e.g., a G0 / S0 state as specified by ACPI). As mentioned above, for example, the optimization results 128 are provided to an application (e.g., a memory management application) in one or more variations, and information in the optimization results 128 enables the application to display the notification 506 via its user interface 504. It should be understood that the notification 506 is merely an example, and that in variations, different information can be displayed after the optimized overclocked memory configuration has been automatically determined by the system 100 and the system has returned to an operational state from the boot-up phase 202. Because the optimized overclocked memory settings are determined automatically and without user input to select values, such notification is effective in informing users of system 100 as to how their system's hardware is tuned.

[0083] Having discussed an exemplary system and user interface for automatic memory overclocking, the following exemplary procedure is described.

[0084] FIG. 6 illustrates a procedure 600 for an exemplary embodiment of automatic memory overclocking.

[0085] One or more sets of overclocked memory settings are selected for the performance and stability tests of the memory (block 602). By way of example, the memory controller 104 (e.g., the setting selector component 120) selects the first overclocked memory setting 208 and / or the second overclocked memory setting 216 for the performance test 204 and the stability test 206. In some cases, this selection is automatic and may occur during the boot-up phase 202 of the system 100. In one or more embodiments, the system 100 enters the boot-up phase 202 based on receiving an optimization request 126.

[0086] The one or more sets of overclocked memory configurations are tested for memory performance, and a performance indication is output for each of the one or more sets of overclocked memory configurations (block 604). By way of example, the memory controller 104 (e.g., the performance scoring component 122) tests the performance of the first overclocked memory setting 208 and / or the second overclocked memory setting 216 for operating the memory 102. In one or more embodiments, the performance scoring component 122 performs the performance test 204, at least in part, by executing one or more workloads with the memory 102, the workloads including various read and / or write accesses to the memory 102.

[0087] When performance scoring component 122 runs performance test 204 on memory 102, one or more workloads executed as part of the test generate performance values ​​210 and / or performance values ​​218 that describe the performance of memory 102 with respect to completing one or more memory-based tasks or operations when configured according to first overclocked memory setting 208 and / or second overclocked memory setting 216, respectively. Performance values ​​210 and / or performance values ​​218 are then used individually or in combination to generate one or more performance indications for first overclocked memory setting 208 and / or second overclocked memory setting 216.

[0088] The one or more sets of overclocked memory settings are tested for memory stability, and a stability indication is output for each of the one or more sets of overclocked memory settings (block 606). As an example, the memory controller 104 (e.g., the stability test component 124) tests the stability of the first overclocked memory setting 208 and / or the second overclocked memory setting 216 for operating the memory 102. As part of the stability test 206, in one or more embodiments, the stability test component 124 tests the stability of operating the memory 102 using the first overclocked memory setting 208 and / or the second overclocked memory setting 216 by performing a reference voltage (Vref) and / or a delay-locked loop (DLL) shmoo and / or by generating one or more "eye diagrams" of the memory 102 or a portion of the memory 102. The memory controller 104 obtains a margin within which the memory 102 can perform, for example, based on the stability test 206.

[0089] When the stability test component 124 performs stability tests 206 on the memory 102, the memory controller 104 (e.g., the configuration selector component 120 and / or the stability test component 124) receives stability notifications 212 and / or 220 indicating the response of the memory 102 to the stability tests performed during the boot-up phase 202. For example, when the stability test component 124 performs a reference voltage (Vref) and / or a DLL shmoo within the memory 102, the memory controller 104 receives stability notifications 212 and / or 220 indicating the operation and / or margin of operation of the memory 102 under various combinations of voltage and / or delay levels.

[0090] In particular, the setting selector component 120 causes the next set of overclocked memory configurations 118 to be tested, e.g., using the performance test 204 and the stability test 206. For example, the setting selector component 120 controls the testing by the performance scoring component 122 and the stability test component 124 until an optimized overclocked memory configuration is determined. As an example, the setting selector component 120 may first test the first overclocked memory configuration 208 and then select an additional set of overclocked memory configurations that overclock the memory 102 less aggressively than the first overclocked memory configuration 208, such as in a scenario where the stability notification 212 is processed to generate a prediction that the memory 102 would be too unstable if configured to operate with the first overclocked memory configuration 208. Alternatively, the setting selector component 120 selects an additional set of overclocked memory settings that overclock the memory 102 more aggressively than the first overclocked memory setting 208, such as in a scenario where the stability notification 212 is processed to generate a prediction that the memory 102 is stable when configured to operate at the first overclocked memory setting 208 and the predicted stability is outside the marginal stability range (i.e., the first overclocked memory setting 208 is "too stable").

[0091] One of the one or more sets of overclocked memory settings is selected as the optimized overclocked memory setting for the memory (block 608). By way of example, the setting selector component 120 controls testing by the performance scoring component 122 and the stability testing component 124 until the optimized overclocked memory setting is determined. In response to determining the optimized overclocked memory setting, an optimization result 128 is output. In one or more embodiments, the optimization result 128 includes or otherwise indicates the optimized overclocked memory setting. In at least one variation, the memory controller 104 (e.g., the setting selector component 120) outputs the optimization result 128, causing the memory 102 to operate according to the optimized overclocked memory setting. For example, the memory controller 104 causes the memory 102 to operate according to the optimized overclocked memory setting by sending one or more modification signals to a voltage generator (not shown) to adjust a supply voltage (e.g., VDD) such that the clock and power 130 inputs subsequently include the supply voltages adjusted according to the modification signals. Additionally or alternatively, memory controller 104 sends a modification signal to a reference clock generator (not shown) to modify the frequency of the clock rate, such that the clock and power 130 input consequently includes a reference clock signal adjusted according to the modification signal.

[0092] It should be understood that many variations are possible based on the disclosure herein, and although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0093] The various functional units illustrated in the figures and / or described herein (including, where appropriate, memory 102, memory controller 104, processing unit 106, configuration selector component 120, performance scoring component 122, and stability testing component 124) may be implemented in any of a variety of different ways, such as hardware circuits, software or firmware running on a programmable processor, or any combination of two or more of hardware, software, and firmware. The provided methods may be performed in any of a variety of devices, such as a general-purpose computer, a processor, or a processor core. Suitable processors include, by way of example only, a general-purpose processor, a special-purpose processor, a conventional processor, a digital signal processor (DSP), a graphics processing unit (GPU), a parallel-accelerated processor, multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine.

[0094] In one or more embodiments, the methods and procedures provided herein are implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A computing device comprising: Memory and a memory controller; The memory controller initiating a boot-up process of the computing device to automatically select an optimized overclocked memory setting for the memory; During the boot-up process of the computing device, automatically identifying one or more sets of overclocked memory configurations for testing; testing the one or more sets of overclocked memory configurations for performance of the memory and outputting an indication of performance for each of the one or more sets of overclocked memory configurations; testing the one or more sets of overclocked memory configurations for stability of the memory and outputting an indication of stability for each of the one or more sets of overclocked memory configurations; selecting one of the one or more sets of overclocked memory settings as the optimized overclocked memory setting; configured to: Computing devices.

2. the memory controller is configured to automatically configure the memory to operate at the optimized overclocked memory settings. The computing device of claim 1.

3. the memory controller is configured to output the optimized overclocked memory configuration to a user interface. The computing device of claim 1.

4. the user interface allows adjustment of the optimized overclocked memory settings; The computing device of claim 3.

5. the memory controller initiating the boot-up process in response to a user input to a user interface to select the optimized overclocked memory configuration. The computing device of claim 1.

6. 1. A system comprising: Memory and a performance scoring component that tests overclocked memory settings for the memory and outputs a performance indication for the overclocked memory settings; a stability testing component that tests the overclocked memory configuration when the memory is configured to operate at the overclocked memory configuration and outputs a stability indication that predicts stability of the memory over time; a setting selector component configured to output an optimized overclocked memory setting based on the performance indication output by the performance scoring component and the stability indication output by the stability testing component. system.

7. the configuration selector component is configured to control testing by the performance scoring component and the stability testing component until the optimized overclocked memory configuration is determined. The system of claim 6.

8. the configuration selector component is configured to provide the overclocked memory configuration to the performance scoring component and the stability testing component for testing. The system of claim 6.

9. the configuration selector component is configured to provide additional overclocked memory configurations to the performance scoring component and the stability testing component for testing based on at least one of the performance indications or predicted stability of the memory. The system of claim 8.

10. the configuration selector component is configured to provide the additional overclocked memory configuration to the performance scoring component and the stability testing component for testing in response to a prediction indicating the memory would be too unstable when the memory is configured to operate at the overclocked configuration; the additional overclocked memory settings provided by the setting selector component are configured to overclock the memory less aggressively than the overclocked memory settings. The system of claim 9.

11. the configuration selector component is configured to provide the additional overclocked memory configuration to the performance scoring component and the stability testing component for testing in response to a prediction indicating that the memory is stable when the memory is configured to operate at the overclocked configuration and the predicted stability is outside a marginal stability guard band; the additional overclocked memory setting provided by the setting selector component is configured to overclock the memory more aggressively than the overclocked memory setting; The system of claim 9.

12. the performance scoring component and the stability testing component test the overclocked memory configuration during the system boot-up process; The system of claim 6.

13. the setting selector component is configured to automatically configure the memory to operate at the optimized overclocked memory setting. The system of claim 6.

14. the setting selector component is configured to output the optimized overclocked memory setting to a user interface. The system of claim 6.

15. the performance scoring component, the stability testing component, and the configuration selector component are implemented in a memory controller. The system of claim 6.

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