Interdigital back contact solar cell and method of manufacturing the same

Abstract

This application relates to the field of photovoltaic device manufacturing, and more particularly to an interdigitated back contact solar cell and a method for manufacturing the same. The method for manufacturing an interdigitated back contact solar cell includes the steps of: depositing a tunneling layer and an N-type polysilicon layer, in order, on the backlight side of a P-type silicon substrate to obtain a base silicon wafer; etching a predetermined blocking area on the backlight side of the base silicon wafer to obtain a patterned blocking groove, where the blocking groove separates the P-type interdigitated region from the N-type interdigitated region; doping the sidewalls and bottom surface of the blocking groove with phosphorus; removing the phosphorus-doped N-type polysilicon layer and the tunneling layer within the P-type interdigitated region to obtain a photovoltaic precursor; and performing layered passivation and metallization on the surface of the photovoltaic precursor to obtain an interdigitated back contact solar cell. According to this application, doping the blocking groove with phosphorus atoms significantly reduces the conductive ability of the sidewalls and bottom surface of the blocking groove, thereby improving the photoelectric conversion efficiency of the cell.

Description

[Technical Field]

[0001] This application claims priority from a Chinese patent application bearing application number 2023100179152 and entitled "Interdigital back-contact solar cell and manufacturing method thereof," filed with the China Patent Office on January 6, 2023, the entire contents of which are incorporated herein by reference.

[0002] This application relates to the field of photovoltaic manufacturing, and more particularly to interdigitated back contact solar cells and methods for their manufacture. [Background technology]

[0003] With the development of photovoltaic technology, interdigital solar cells have become a cutting-edge technology in the field of photovoltaic research, as they have no grid lines on their light-receiving surface, which avoids the approximately 5% light-blocking loss caused by the front grid lines of conventional cells. In addition, they have the advantage of slowing down the recombination rate of photoinduced carriers on the back surface, resulting in a high fill factor.

[0004] Specifically, in interdigital solar cells, the isolation between P-type interdigital and N-type interdigital is achieved by the isolation grooves on the backlight surface, but in conventional technology, the isolation is achieved by simply increasing the physical distance, such as by digging grooves or increasing barriers, which results in poor isolation effect, and most carriers are released directly from the P-type interdigital to the N-type interdigital through the isolation region rather than through the external circuit, increasing the internal consumption of the solar cell and reducing the output power.

[0005] Therefore, it is a problem to be solved by those skilled in the art to improve the isolation effect between the interdigits of an interdigitated back contact solar cell and thereby improve the photoelectric conversion efficiency of the cell. Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE INVENTION In order to solve the problem of poor isolation effect of interdigital back contact solar cells in the prior art, the present application aims to provide an interdigital back contact solar cell and a manufacturing method thereof. [Means for solving the problem]

[0007] In order to solve the above technical problems, the present application provides a method for manufacturing an interdigital back contact solar cell, a tunneling layer and an N-type polysilicon layer are sequentially disposed on the backlight surface of a P-type silicon substrate to obtain a base silicon wafer; Etching a predetermined blocking area on the backlight surface of the base silicon wafer to obtain a patterned blocking groove, the blocking groove separating the P-type interdigital regions from the N-type interdigital regions; doping the sidewalls and bottom surface of the blocking trench with phosphorus; removing the phosphorus-doped N-type polysilicon layer and the tunneling layer within the P-type interdigitated region to obtain a photovoltaic precursor; and applying a layer passivation and metallization to the surface of the photovoltaic precursor to obtain an interdigitated back contact solar cell.

[0008] A preferred solution is to obtain a basic silicon wafer by sequentially depositing a tunneling layer and an N-type polysilicon layer on the backlight surface of a P-type silicon substrate: disposing a tunneling layer on a backlight surface of a P-type silicon substrate; disposing an intrinsic amorphous silicon layer on a surface of the tunneling layer; The method includes a step of converting an intrinsic amorphous silicon layer provided on a P-type silicon substrate into an N-type polysilicon layer by diffusing phosphorus into the P-type silicon substrate to obtain a base silicon wafer, and generating a PSG layer to be removed on the surface of the base silicon wafer.

[0009] As a preferred solution, the method of phosphorus diffusion into a P-type silicon substrate provided with an intrinsic amorphous silicon layer is as follows: performing a double-sided phosphorus diffusion on the P-type silicon substrate having the intrinsic amorphous silicon layer thereon to produce PSG layers to be removed on both sides of the base silicon wafer.

[0010] In a preferred solution, before doping the sidewalls and bottom surface of the blocking trench with phosphorus, the manufacturing method comprises: The method further includes the step of performing alkaline polishing on the blocking groove.

[0011] As a preferred solution, the method for doping the sidewalls and bottom surface of the blocking groove with phosphorus is as follows: implanting phosphorus ions into the backlight side of the base silicon wafer and then removing the PSG layer; Annealing the base silicon wafer from which the PSG layer has been removed to complete the phosphorus doping and form a thermal silicon oxide layer on the surface of the base silicon wafer, which is to be removed.

[0012] As a preferred solution, before removing the N-type polysilicon layer and the tunneling layer that are doped with phosphorus and are in the P-type interdigital region to obtain the photovoltaic precursor, the manufacturing method includes: The method further includes a step of performing a primary texturing on the light-receiving surface of the base silicon wafer, in which both the light-receiving surface and the backlight surface of the base silicon wafer are contacted with a chemical solution for performing the primary texturing.

[0013] As a preferred solution, the method for removing the N-type polysilicon layer and the tunneling layer that are doped with phosphorus and located in the P-type interdigital regions to obtain a photovoltaic precursor includes the following steps: performing an acid etch on the P-type interdigitated regions to remove the thermal silicon oxide layer within the P-type interdigitated regions; removing the N-type polysilicon layer within the P-type interdigitated regions, and removing the thermal silicon oxide layer and tunneling layer on the backlight surface of the base silicon wafer by wet cleaning to obtain a photovoltaic precursor.

[0014] As a preferred solution, the method for removing the N-type polysilicon layer within the P-type interdigitated regions is: The step includes performing a secondary texturing on the light-receiving surface of the base silicon wafer to remove the N-type polysilicon layer within the P-type interdigitated regions using a chemical solution for performing the secondary texturing.

[0015] In a preferred solution, before depositing the tunneling layer and the N-type polysilicon layer on the backlight surface of the P-type silicon substrate, the manufacturing method includes: The method further includes a step of double-side polishing the P-type silicon substrate.

[0016] An interdigitated back contact solar cell including a P-type silicon substrate, wherein the backlight surface of the P-type silicon substrate includes P-type interdigitated regions, N-type interdigitated regions, and blocking grooves; The isolation groove separates the P-type interdigital region from the N-type interdigital region, The N-type interdigital region includes, from the inside to the outside, a tunneling layer and an N-type polysilicon layer. a phosphorus-doped neutral layer is provided on the sidewall and bottom surface of the blocking groove; The outermost surfaces of the backlight surface and the light receiving surface of the P-type silicon substrate include a passivation layer; An N-type electrode of the interdigitated back contact solar cell is provided on the N-type interdigitated region, and the N-type electrode is provided so as to penetrate the passivation layer and contact the N-type polysilicon layer; The P-type electrode of the interdigitated back contact solar cell is provided on the P-type interdigitated region, and the P-type electrode is provided through the passivation layer to contact the P-type silicon substrate. [Effects of the Invention]

[0017] The method for manufacturing an interdigitated back contact solar cell provided by the present application includes the steps of: sequentially disposing a tunneling layer and an N-type polysilicon layer on the backlight surface of a P-type silicon substrate to obtain a base silicon wafer; etching a predetermined blocking area on the backlight surface of the base silicon wafer to obtain a patterned blocking groove, where the blocking groove separates the P-type interdigitated region and the N-type interdigitated region; doping the sidewall and bottom of the blocking groove with phosphorus; removing the phosphorus-doped N-type polysilicon layer and the tunneling layer in the P-type interdigitated region to obtain a photovoltaic precursor; and performing stacked passivation and metallization on the surface of the photovoltaic precursor to obtain an interdigitated back contact solar cell.

[0018] According to the present application, the blocking groove between the P-type emitter (i.e., P-type interdigital) and the N-type emitter (i.e., N-type interdigital) is doped with phosphorus atoms having a polarity opposite to that of the P-type silicon substrate, and this reverse doping concentration increases the sheet resistance of the region and makes it intrinsic silicon, significantly reducing the conductive ability of the sidewalls and bottom of the blocking groove, significantly reducing the carrier concentration of the region, improving the electrical isolation effect between the interdigital, further reducing the internal consumption of the cell and improving the photoelectric conversion efficiency of the cell. The present application also provides an interdigital back-contact solar cell with the above beneficial effects. [Brief explanation of the drawings]

[0019] In order to clearly explain the technical solutions of the embodiments of the present application or the prior art, the following briefly introduces the drawings necessary for the description of the embodiments or the prior art. The drawings listed below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without making any efforts that amount to inventive step. [Figure 1]FIG. 1 is a flow diagram of Example 1 of the method for manufacturing an interdigital back contact solar cell provided by the present application. [Figure 2] FIG. 2 is a flow diagram of Example 2 of the method for manufacturing an interdigital back contact solar cell provided by the present application. [Figure 3] 1 is a structural schematic diagram of a specific embodiment of an interdigital back contact solar cell provided by the present application; FIG. DETAILED DESCRIPTION OF THE INVENTION

[0020] In order to help those skilled in the art better understand the solution of the present application, the present application will be described in more detail below in combination with drawings and specific embodiments. The described examples are not all examples, but only some examples of the present application. Based on the examples of the present application, all other examples obtained by those skilled in the art without any inventive effort fall within the scope of protection of the present application.

[0021] Example 1 The present application is intended to provide a method for manufacturing an interdigital back contact solar cell, and the flow diagram of a specific embodiment is shown in FIG. 1 , which is specific embodiment 1, and includes the following steps: S101: A tunneling layer and an N-type polysilicon layer are sequentially disposed on the backlight surface of a P-type silicon substrate to obtain a base silicon wafer.

[0022] In a preferred embodiment, the steps include: A1: A tunneling layer is disposed on the backlight surface of a P-type silicon substrate.

[0023] Specifically, the tunneling layer deposited on the backlight surface may be silicon oxide, nitrogen oxide or nitride, and the deposition method includes any one of LPCVD (low pressure chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition) and PEALD (plasma enhanced atomic layer deposition), and the thickness of the tunneling layer is between 0.1 nm and 5 nm.

[0024] A2: An intrinsic amorphous silicon layer is disposed on the surface of the tunneling layer.

[0025] Specifically, the method of disposing the intrinsic amorphous silicon layer includes at least one of LPCVD, PEALD, and PVD (physical deposition), and the thickness of the intrinsic amorphous silicon layer is between 30 nm and 300 nm.

[0026] A3: Phosphorus diffusion is performed on a P-type silicon substrate having an intrinsic amorphous silicon layer to convert the intrinsic amorphous silicon layer into an N-type polysilicon layer to obtain a base silicon wafer, and a PSG layer to be removed is generated on the surface of the base silicon wafer.

[0027] Specifically, the phosphorus diffusion method for the silicon wafer surface is high-temperature tubular phosphorus diffusion, with the phosphorus source being phosphoryl chloride (POCL3) or phosphorus ion implantation followed by oxidation annealing, resulting in a target sheet resistance range of 20 Ω / m to 80 Ω / m. During phosphorus diffusion into a P-type silicon substrate, a phosphorus-containing silicon oxide layer, called a PSG layer, is formed on the surface of the base silicon wafer, with a thickness ranging from 40 nm to 60 nm. The PSG layer acts as a protective layer in subsequent manufacturing processes, preventing corrosion of other underlying epitaxial layers.

[0028] Preferably, in step A3, the method of performing phosphorus diffusion on the P-type silicon substrate provided with the intrinsic amorphous silicon layer includes: The method includes performing a double-sided phosphorus diffusion on a P-type silicon substrate having an intrinsic amorphous silicon layer thereon to produce PSG layers on both sides of the base silicon wafer that are to be removed.

[0029] Specifically, this solution involves double-sided phosphorus diffusion, forming a phosphorus-doped normal emitter (i.e., the PSG layer mentioned above) on the light-receiving surface to absorb impurities, which is then removed along with the absorbed impurities in the subsequent texturing step. Before removal, the PSG layer on the light-receiving surface acts as a protective layer to prevent damage to the light-receiving surface of the P-type silicon substrate.

[0030] S102: Etching a predetermined blocking area on the backlight surface of the base silicon wafer to obtain a patterned blocking groove, which separates the P-type interdigital regions from the N-type interdigital regions.

[0031] Continuing from the previous example, after phosphorus diffusion on both sides, PSG layers, i.e., phosphorus-containing silicon dioxide layers, are formed on the front and back sides of the silicon wafer. At this time, an acidic etching material is printed (with a width ranging from 50 μm to 100 μm) according to the pattern of the blocking region using screen printing. The etching material corrodes and removes the epitaxial layer in the blocking region, exposing the underlying P-type silicon substrate.

[0032] In a specific embodiment, the acidic etching material is composed of oxalic acid, a surfactant, a thickener, modified silicon dioxide, deionized water, and sodium fluoride, and exhibits a corrosive effect on the PSG layer at room temperature or under heat. The content of each component is as follows: 5 wt% to 20 wt% oxalic acid, 5 wt% to 10 wt% surfactant, 10 wt% to 20 wt% thickener, 20 wt% to 40 wt% modified silicon dioxide, 5 wt% to 20 wt% deionized water, and 1 wt% to 10 wt% sodium fluoride. After printing the etching material, the remaining etching material is removed by washing. The PSG layer on the backlight side where the acidic etching material is not printed remains as an alkali barrier layer during the subsequent polishing process, protecting the underlying N-type doped polysilicon. In this embodiment, the PSG layer, which is a by-product of the phosphorus diffusion process, is cleverly used to provide an alkaline etching blocking effect, eliminating the need to separately deposit a silicon oxide layer or silicon nitride layer as an alkaline etching blocking layer, thereby reducing the number of process steps and costs.

[0033] S103: The sidewalls and bottom surface of the blocking trench are doped with phosphorus.

[0034] The steps specifically include: B1: Implant phosphorus ions into the backlight surface of the base silicon wafer, then remove the PSG layer.

[0035] In the ion implantation process, phosphorus ions are implanted into the backlight surface at a concentration 0.1 to 1 times that of the silicon substrate. Because the blocking groove region is not protected by the PSG layer, the phosphorus ions are directly implanted into the bottom and sidewalls of the blocking groove to a depth of 10 to 20 nm. Other regions are protected by the PSG layer, so the implanted phosphorus is not implanted into the N-type polysilicon below the PSG layer, but only exists in the surface PSG layer.

[0036] B2: The base silicon wafer from which the PSG layer has been removed is annealed to complete the phosphorus doping and form a thermal silicon oxide layer to be removed on the surface of the base silicon wafer.

[0037] In this step, the PSG layer on the light-receiving surface and backlight surface is cleaned and removed with hydrofluoric acid, and then oxidation annealing is performed at 850°C to promote and activate the phosphorus element on the blocking groove and sidewall, forming doping. In the oxidation annealing process, a thermal oxidation layer with a thickness of 20nm to 50nm is formed on the backlight surface.

[0038] Preferably, prior to this step, the manufacturing method further comprises: The method further includes the step of performing alkaline polishing on the blocking groove.

[0039] Specifically, the PSG layer in step S102 functions as an alkali barrier layer to protect the underlying N-type doped polysilicon, polish and modify the surface, and simplify the process flow to improve manufacturing efficiency.

[0040] Specifically, a polishing process is performed on a silicon wafer cleaned with an acidic etching material, i.e., a 5% to 20% solution of potassium hydroxide, sodium hydroxide, and TMAH (tetramethylammonium hydroxide), with the aid of additives. The additives protect the oxide layer, ensuring that the PSG layer is not excessively corroded, leaving a remaining PSG layer of 30 to 50 nm. A polished, flat structure is formed in the unprotected area covered by the PSG layer. That is, a polished structure with a consistent depth of 5 μm to 10 μm is formed in the blocking groove on the backlight surface. The light-receiving surface of the silicon wafer is not polished and is protected by the PSG layer.

[0041] S104: The phosphorus-doped N-type polysilicon layer and the tunneling layer in the P-type interdigital region are removed to obtain a photovoltaic precursor.

[0042] Specifically, the steps include: C1: Acid etching is performed on the P-type interdigitated regions to remove the thermal silicon oxide layer corresponding to the P-type interdigitated regions.

[0043] In this step, an acidic etching material is printed by screen printing according to the pattern of the P-type interdigital regions, with a width of 200 μm to 300 μm, and the etching material corrodes and removes the thermal oxide layer at that location, exposing the underlying N-type doped polysilicon layer.

[0044] C2: The N-type polysilicon layer in the P-type interdigital region is removed, and the thermal silicon oxide layer and tunneling layer on the backlight surface of the base silicon wafer are cleaned and removed by wet cleaning to obtain a photovoltaic precursor.

[0045] Specifically, there are many methods for removing the N-type polysilicon layer corresponding to the P-type interdigital regions, and they are not listed here. Preferably, in step C2, the N-type polysilicon layer corresponding to the P-type interdigital regions is removed by: The method includes the steps of performing a secondary texturing on the light-receiving surface of the base silicon wafer and removing the N-type polysilicon layer within the P-type interdigitated regions using a chemical solution for performing the secondary texturing.

[0046] In this embodiment, a secondary texturing process is performed directly on the silicon wafer. This process has two main purposes: first, to remove the exposed N-type polysilicon layer on the backlight side of the P-type silicon substrate after step C1 is performed; and second, to perform secondary texturing on the velvet on the light-receiving side to form a thinner velvet, which is more favorable for light capture. To remove only the exposed polysilicon layer on the backlight side without destroying the polished surface structure of the P-type silicon substrate, the secondary texturing process can remove the N-type polysilicon layer in a short time using a conventional texturing groove method, with the texturing time being 0.1 to 0.2 times the normal texturing time. Furthermore, the tunneling oxide layer beneath the N-type polysilicon layer protects the polished surface of the P-type interdigital region from texturing.

[0047] Wherein, prior to this step, the manufacturing method includes: The method further includes a step of performing a primary texturing on the light-receiving surface of the base silicon wafer, in which both the light-receiving surface and the backlight surface of the base silicon wafer are contacted with a chemical solution for performing the primary texturing.

[0048] Before texturing, the overflow coating of silicon oxide, a by-product of the silicon wafer's light-receiving surface, is removed using HF-reactive materials. The texturing process is then carried out using a 5%-20% solution of potassium hydroxide, sodium hydroxide, and TMAH, along with the addition of a texturing additive. At the same time, an additive with the function of protecting the oxide layer is added. This means that the entire light-receiving surface is a pyramidal velvet, providing light-trapping capabilities. The backlight surface is protected by a thermal oxide layer, so there is no texturing. However, the thermal silicon oxide layer on the backlight surface is still consumed during the primary texturing process. After texturing, the remaining thickness of the thermal silicon oxide layer on the backlight surface ranges from 15nm to 45nm.

[0049] S105: The surface of the photovoltaic precursor is passivated and metallized to obtain an interdigitated back contact solar cell.

[0050] Specifically, the laminate passivation method includes: A hydrogen-containing dielectric layer is deposited on the light-receiving surface and backlight surface to provide backside chemical passivation. Specifically, the backlight surface is an aluminum oxide + silicon nitride laminate passivation, with the aluminum oxide produced by PECVD, ALD, or PEALD and its thickness ranging from 2nm to 20nm. The silicon nitride is produced by PECVD, ALD, or PEALD and its thickness ranging from 60nm to 200nm. The light-receiving surface is an aluminum oxide + silicon nitride + silicon oxide laminate film, with the aluminum oxide produced by PECVD, ALD, or PEALD and its thickness ranging from 2nm to 20nm, 50nm to 80nm, and 5nm to 20nm, respectively.

[0051] Specifically, the metallization methods include: Localized openings are made in the P-type interdigital regions using a laser or acid etching material. The openings can be dotted or spaced dots, lines or line spaces, or dotted and spaced lines. The diameter or width of the openings is 10 μm to 50 μm, and the openings do not damage the underlying structure and only remove the dielectric layer. A low-corrosion silver or aluminum paste is printed above the openings in the P-type interdigital regions, with a width of 50 μm to 100 μm, to provide electrical contact with the P-type silicon. A corrosive silver paste is printed above the N-type polysilicon, and the glass in the corrosive silver paste opens the dielectric layer, bringing the silver into contact with the N-type polysilicon. Co-sintering is performed at 600°C to 800°C to form electrodes.

[0052] In this embodiment, the method for manufacturing an interdigitated back contact solar cell provided by the present application includes the steps of: sequentially disposing a tunneling layer and an N-type polysilicon layer on the backlight surface of a P-type silicon substrate to obtain a base silicon wafer; etching a predetermined blocking area on the backlight surface of the base silicon wafer to obtain a patterned blocking groove, which separates the P-type interdigitated region from the N-type interdigitated region; doping the sidewall and bottom of the blocking groove with phosphorus; removing the phosphorus-doped N-type polysilicon layer and the tunneling layer in the P-type interdigitated region to obtain a photovoltaic precursor; and performing stacked passivation and metallization on the surface of the photovoltaic precursor to obtain an interdigitated back contact solar cell.

[0053] According to the present application, the blocking groove between the P-type emitter (i.e., P-type interdigital) and the N-type emitter (i.e., N-type interdigital) is doped with phosphorus atoms having a polarity opposite to that of the P-type silicon substrate, and this reverse doping concentration increases the sheet resistance of the region and makes it intrinsic silicon, significantly reducing the conductive ability of the sidewalls and bottom of the blocking groove, significantly reducing the carrier concentration of the region, and improving the effect of electrical isolation between the interdigital, thereby further reducing the internal consumption of the battery and improving the photoelectric conversion efficiency of the battery.

[0054] Example 2 According to the specific example 1, the P-type silicon substrate is further pretreated to obtain the specific example 2, the flow diagram of which is shown in FIG. 2. The method for manufacturing the interdigital back contact solar cell includes the following steps: S201: A P-type silicon substrate is polished on both sides. S202: A tunneling layer and an N-type polysilicon layer are sequentially disposed on the backlight surface of a P-type silicon substrate to obtain a base silicon wafer. S203: Etching a predetermined blocking area on the backlight surface of the base silicon wafer to obtain a patterned blocking groove, which separates the P-type interdigital regions from the N-type interdigital regions. S204: The sidewalls and bottom surface of the blocking trench are doped with phosphorus. S205: The phosphorus-doped N-type polysilicon layer and the tunneling layer in the P-type interdigital region are removed to obtain a photovoltaic precursor. S206: The surface of the photovoltaic precursor is passivated and metallized to obtain an interdigitated back contact solar cell.

[0055] The difference between this embodiment and the first embodiment is as follows: in this embodiment, a polishing process is performed on the P-type silicon substrate in advance, and the other steps are all the same as those in the first embodiment, so they will not be described in detail here.

[0056] In this embodiment, the double-side polishing of the P-type silicon substrate may be alkaline polishing, and a specific embodiment includes 5% to 20% potassium hydroxide, sodium hydroxide, TMAH solution, etc., and the addition of polishing additives makes the surface more flat. A chemical reaction is carried out at a temperature range of 60°C to 90°C to remove cutting damage on the surface of the silicon substrate, smooth the surface, reduce surface defects, improve the growth quality of the subsequent epitaxial layer, reduce the internal resistance of the battery, and further improve the photoelectric conversion efficiency of the battery.

[0057] The following provides a complete interdigital back contact solar cell manufacturing process flow for reference in actual manufacturing, including the following steps: Step 1: Double-side polishing is performed on a P-type silicon wafer.

[0058] Specifically, both sides of a P-type silicon wafer are polished using conventional alkaline polishing. The alkaline polishing solution contains 5% to 20% potassium hydroxide, sodium hydroxide, TMAH solution, etc., and polishing additives are added to make the surface flatter. A chemical reaction takes place at a temperature of 60°C to 90°C to remove surface cutting damage, smooth the surface, and further reduce surface defects.

[0059] Step 2: Deposit a tunneling layer and an intrinsic amorphous silicon layer on the backlight surface.

[0060] Specifically, a tunneling layer is deposited on the backlight surface, and the tunneling layer is silicon oxide, nitride, or nitride. Nitride methods include LPCVD (low-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), and PEALD (plasma-enhanced atomic layer deposition). The thickness of the tunneling layer is between 0.1 nm and 5 nm, and then an intrinsic amorphous silicon layer is deposited. The deposition methods include LPCVD, PEALD, and PVD (physical vapor deposition), and the thickness of the intrinsic amorphous silicon layer is between 30 nm and 300 nm.

[0061] Step 3: Phosphorus diffusion on both sides.

[0062] Specifically, after completing step 2, the silicon wafer is subjected to double-sided phosphorus diffusion. The phosphorus diffusion method is high-temperature tubular phosphorus diffusion, and the phosphorus source is phosphoryl chloride (POCL3). Alternatively, the phosphorus diffusion method is phosphorus ion implantation + oxidation annealing. The sheet resistance is 20 Ω / m to 80 Ω / m. During this process, a silicon oxide layer containing phosphorus elements is formed on the surface, called a PSG layer, with a thickness of 40 nm to 60 nm.

[0063] Specifically, a double-sided phosphorus diffusion is performed to form a phosphorus-doped normal emitter on the light-receiving surface, which acts as an impurity absorber. In a subsequent texturing step, the emitter is removed along with the absorbed impurities. In this step, the intrinsic amorphous silicon is converted into the corresponding N-type doped polysilicon.

[0064] Step 4: Print acid etching material in the isolation groove area.

[0065] Specifically, after phosphorus diffusion on both sides, a PSG layer, i.e., a phosphorus-containing silicon dioxide layer, is formed on the front and back of the silicon wafer. An acidic etching material is then screen-printed according to the isolation groove pattern, with a width of 50 μm to 100 μm. The etching material corrodes and removes the PSG at the corresponding locations, exposing the underlying P-type silicon substrate.

[0066] Specifically, the acidic etching material is composed of oxalic acid, surfactant, thickener, modified silicon dioxide, deionized water, and sodium fluoride, and exhibits corrosion effects on the PSG layer at room temperature or under heat. The content of each component is as follows: 5 wt% to 20 wt% oxalic acid, 5 wt% to 10 wt% surfactant, 10 wt% to 20 wt% thickener, 20 wt% to 40 wt% modified silicon dioxide, 5 wt% to 20 wt% deionized water, and 1 wt% to 10 wt% sodium fluoride. After printing the etching material, the remaining etching material is removed by washing. The PSG layer on the backlight side not printed with the acidic etching material remains as an alkali barrier layer during the polishing process in step 5, protecting the underlying N-type doped polysilicon. The PSG layer acts as an auxiliary in the phosphorus diffusion process and acts as an alkaline etching stopper, eliminating the need to separately deposit a silicon oxide layer or silicon nitride layer as an alkaline etching stopper, thereby reducing process steps and costs.

[0067] Step 5: Polish the blocking groove on the backlight surface.

[0068] Specifically, a polishing process is performed on a silicon wafer cleaned with an acid etching material, i.e., a 5% to 20% potassium hydroxide, sodium hydroxide, and TMAH solution, with the aid of additives. The additives protect the oxide layer, ensuring that the PSG layer is not excessively corroded, leaving a remaining PSG layer of 30 to 50 nm. A polished, flat structure is formed in the area not covered or protected by the PSG layer. That is, a polished structure with a depth of 5 μm to 10 μm is formed in the pattern area of ​​the isolation grooves on the backlight surface. The light-receiving surface of the silicon wafer is not polished and is protected by the PSG layer.

[0069] Step 6: Phosphorus ions are implanted into the backlight surface, followed by cleaning and oxidation annealing.

[0070] Specifically, phosphorus ions are implanted into the backlight surface during the ion implantation process, with a concentration 0.1 to 1 times the doping concentration of the silicon substrate. Because the isolation trench region is not protected by a PSG layer, the phosphorus ions are implanted directly into the bottom and sidewalls of the isolation trench in the P-type silicon substrate to a depth of 10 to 20 nm. Other regions are protected by the PSG layer, so the implanted phosphorus is not implanted into the N-type polysilicon layer below the PSG layer, but remains only in the surface PSG layer. The PSG layer on the light-receiving surface and backlight surface is cleaned and removed with hydrofluoric acid, and then oxidation annealing is performed at 850°C to promote and activate the phosphorus elements in the trench and sidewalls, forming doping. The oxidation annealing process forms a thermal oxide layer with a thickness of 20 to 50 nm on the backlight surface.

[0071] Step 7: Texturing the light-receiving surface.

[0072] Specifically, after step 6, the overflow coating of the silicon oxide layer on the front surface of the silicon wafer is removed using chain HF, followed by a texturing process. Specifically, the texturing process is performed using a 5%-20% potassium hydroxide, sodium hydroxide, and TMAH solution with the aid of a texturing additive, which adds an additive with the function of protecting the oxide layer. This means that the entire light-receiving surface is a pyramidal velvet, providing light-trapping capabilities. The backlight surface is protected by the oxide layer, eliminating the texturing phenomenon. After texturing, the remaining oxide layer on the backlight surface is 15nm-45nm thick.

[0073] Step 8: Print acid etching material on the P-type silicon substrate area.

[0074] Specifically, on the silicon wafer that has completed step 7, an acidic etching material is screen-printed according to the pattern of the P-type interdigital regions of the silicon substrate, with a width of 200 μm to 300 μm, and the etching material corrodes and removes the thermal oxide layer at that location, exposing the underlying N-type doped polysilicon layer.

[0075] Step 9: Do the secondary texturing.

[0076] Specifically, a secondary texturing process is performed on the silicon wafer after Step 8. This process has two main purposes: first, to remove the polysilicon layer located on the backlight surface of the P-type silicon substrate and exposed by Step 8; and second, to perform secondary texturing on the velvet on the light-receiving surface to form a thinner velvet, which is beneficial for light capture. To remove only the exposed polysilicon layer on the backlight surface without destroying the polished surface structure of the P-type silicon substrate, secondary texturing can be performed in a short time using a conventional texturing groove method, with the texturing time being 0.1 to 0.2 times the normal texturing time. Furthermore, the tunneling oxide layer beneath the polysilicon layer protects the polished surface of the P-type interdigital region from texturing.

[0077] Step 10: Wet wash.

[0078] Specifically, the tunneling oxide layer exposed in step 9 and the thermal silicon oxide layer in other regions are removed.

[0079] Step 11: Apply passivation overlay to the light receiving surface and backlight surface.

[0080] Specifically, a hydrogen-containing dielectric layer is deposited on the light-receiving surface and backlight surface to provide backside chemical passivation. Specifically, the backlight surface is an aluminum oxide + silicon nitride laminate passivation, with the aluminum oxide produced by PECVD, ALD, or PEALD and having a thickness of 2-20 nm. The silicon nitride is produced by PECVD, ALD, or PEALD and having a thickness of 60-200 nm. The light-receiving surface is an aluminum oxide + silicon nitride + silicon oxide laminate film, with the aluminum oxide produced by PECVD, ALD, or PEALD and having a thickness of 2-20 nm, 50-80 nm, and 5-20 nm, respectively.

[0081] Step 12: Metallize the backlight surface.

[0082] Specifically, local openings are made in the P-type interdigital region using a laser or acid etching material. The openings can be dotted or spaced dots, lines or spaced lines, or dotted and spaced lines. The diameter or width of the openings is 10 μm to 50 μm. The openings remove only the dielectric layer without damaging the underlying P-type polysilicon layer. A low-corrosion silver or aluminum paste is printed above the openings in the P-type interdigital region, with a width of 50 to 100 μm, to provide electrical contact with the P-type polysilicon. A corrosive silver paste is printed above the N-type polysilicon, and the glass in the corrosive silver paste opens the dielectric layer, bringing the silver into contact with the N-type polysilicon. Co-sintering is performed at 600°C to 800°C to form electrodes.

[0083] Specifically, compared to the prior art, the isolation structure of the P-type back-contact cell proposed by this application adds a vertical recessed structure at the boundary between the P-type silicon substrate and the N-type emitter, with the recessed structure having a certain depth and width. The bottom and both vertical sidewalls of the recessed structure are doped with phosphorus atoms with a polarity opposite to that of the silicon substrate. The concentration of the phosphorus atoms is 0.1 to 1 times the doping concentration of the silicon substrate. Reverse doping at this concentration increases the sheet resistance of the region and, further, results in an intrinsic silicon base, significantly reducing the conductive ability. Secondary texturing is also performed on the light-receiving surface, improving anti-reflection (light-trapping) capabilities.

[0084] Specifically, the present application further provides an interdigitated back contact solar cell including a P-type silicon substrate 10, the structural schematic of which is shown in FIG. 3, in which the backlight surface of the P-type silicon substrate 10 includes P-type interdigitated regions, N-type interdigitated regions and blocking grooves; The isolation groove separates the P-type interdigital region from the N-type interdigital region. The N-type interdigital region includes, from the inside to the outside, a tunneling layer 20 and an N-type polysilicon layer 30; A phosphorus-doped neutral layer 40 is provided on the sidewall and bottom of the blocking groove, The outermost surfaces of the backlight surface and the light receiving surface of the P-type silicon substrate 10 include a passivation layer 50; An N-type electrode 70 of the interdigitated back contact solar cell is provided on the N-type interdigitated region, and the N-type electrode 70 is provided to penetrate the passivation layer 50 and contact the N-type polysilicon layer 30; A P-type electrode 60 of the interdigitated back contact solar cell is provided on the P-type interdigitated region, and the P-type electrode 60 is provided to penetrate the passivation layer 50 and contact the P-type silicon substrate 10 .

[0085] The solar cell of FIG. 3 includes a P-type silicon substrate 10, a tunneling layer 20, an N-type polysilicon layer 30, a phosphorus-doped neutral layer 40, a passivation layer 50, a P-type electrode 60, and an N-type electrode 70.

[0086] Specifically, the phosphorus-doped neutral layer 40 is a layer with very few carriers obtained by doping phosphorus into the sidewalls and bottom surface of the blocking groove, the P-type electrode 60 is an electrode corresponding to the P-type interdigital region, the N-type electrode 70 is an electrode corresponding to the N-type interdigital region, and the passivation layer 50 is a layer produced by a stacked passivation process and may be a stacked composite layer.

[0087] The interdigital back contact solar cell provided by the present application includes a P-type silicon substrate 10. A structural schematic diagram of a specific embodiment thereof is shown in FIG. 3. The backlight surface of the P-type silicon substrate 10 includes a P-type interdigital region, an N-type interdigital region, and a blocking groove. The blocking groove separates the P-type interdigital region from the N-type interdigital region. The N-type interdigital region includes, from inside to outside, a tunneling layer 20 and an N-type polysilicon layer 30. A phosphorus-doped neutral layer 40 is provided on the sidewalls and bottom of the blocking groove. The backlight surface and the light-receiving surface of the P-type silicon substrate 10 include a passivation layer 50 on the outermost side. An N-type electrode 70 of the interdigital back contact solar cell is provided on the N-type interdigital region, and the N-type electrode 70 penetrates the passivation layer 50 to contact the N-type polysilicon layer 30. The P-type electrode 60 of the interdigitated back contact solar cell is provided on the P-type interdigitated region, and the P-type electrode 60 penetrates the passivation layer 50 to contact the P-type silicon substrate 10. The blocking groove between the P-type emitter (i.e., P-type interdigitated) and the N-type emitter (i.e., N-type interdigitated) is doped with phosphorus atoms having a polarity opposite to that of the P-type silicon substrate 10. This reverse doping concentration increases the sheet resistance of the region and makes it intrinsic silicon, significantly reducing the conductive ability of the sidewalls and bottom of the blocking groove. This significantly reduces the carrier concentration of the region, enhancing the electrical isolation effect between the interdigitated regions, further reducing the internal consumption of the cell and improving the photoelectric conversion efficiency of the cell.

[0088] In this specification, each embodiment will be described in a step-by-step manner, and each embodiment will mainly describe the differences from other embodiments, and similar or similar parts between the embodiments may be referred to each other. Since the apparatus disclosed in the embodiments corresponds to the method disclosed in the embodiments, the description thereof will be brief, and only the relevant parts may be referred to the description of the method part.

[0089] Herein, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," "comprises," or any other variation thereof are intended to include a non-exclusive inclusion, whereby a process, method, article, or device comprising a set of elements not only includes those elements, but also includes other elements not expressly listed, or even includes the inherent elements of such process, method, article, or device. Unless further limited, elements defined by the phrase "comprises" do not exclude that the process, method, article, or device comprising the elements also includes other identical elements.

Claims

1. 1. A method for manufacturing an interdigitated back contact solar cell, comprising: Sequentially disposing a tunneling layer and an N-type polysilicon layer on the backlight surface of a P-type silicon substrate to obtain a base silicon wafer; Etching a predetermined blocking area on the backlight surface of the base silicon wafer to obtain a patterned blocking groove, the blocking groove separating the P-type interdigital regions from the N-type interdigital regions; doping a sidewall and a bottom surface of the blocking groove with phosphorus; removing the N-type polysilicon layer and the tunneling layer that are doped with phosphorus and are located within the P-type interdigitated regions to obtain a photovoltaic precursor; and applying a layer passivation and metallization to the surface of the photovoltaic precursor to obtain an interdigitated back contact solar cell.

2. The method for obtaining a basic silicon wafer by sequentially disposing a tunneling layer and an N-type polysilicon layer on the backlight surface of a P-type silicon substrate is as follows: disposing a tunneling layer on a backlight surface of a P-type silicon substrate; disposing an intrinsic amorphous silicon layer on a surface of the tunneling layer; 2. The method for manufacturing an interdigital back contact solar cell of claim 1, further comprising the steps of: performing phosphorus diffusion on the P-type silicon substrate on which the intrinsic amorphous silicon layer is provided, thereby converting the intrinsic amorphous silicon layer into an N-type polysilicon layer to obtain a base silicon wafer; and generating a PSG layer to be removed on the surface of the base silicon wafer.

3. The method for diffusing phosphorus into the P-type silicon substrate having the intrinsic amorphous silicon layer includes the steps of:

3. The method for manufacturing an interdigital back contact solar cell of claim 2, further comprising the step of performing double-sided phosphorus diffusion on the P-type silicon substrate having the intrinsic amorphous silicon layer thereon to produce PSG layers to be removed on both sides of the base silicon wafer.

4. Before doping the sidewall and bottom surface of the blocking groove with phosphorus, the manufacturing method includes: The method for manufacturing an interdigital back contact solar cell according to claim 1 , further comprising the step of performing alkaline polishing on the blocking groove.

5. The method of doping the sidewall and bottom surface of the blocking groove with phosphorus includes: implanting phosphorus ions into the backlight surface of the base silicon wafer and then removing the PSG layer; 2. The method of claim 1, further comprising the step of: annealing the base silicon wafer from which the PSG layer has been removed to complete phosphorus doping and forming a thermal silicon oxide layer to be removed on the surface of the base silicon wafer.

6. Before removing the phosphorus-doped N-type polysilicon layer and the tunneling layer located in the P-type interdigital regions to obtain a photovoltaic precursor, the manufacturing method includes:

2. The method for manufacturing an interdigital back contact solar cell of claim 1, further comprising a step of performing a primary texturing on the light-receiving surface of the base silicon wafer, wherein both the light-receiving surface and the backlight surface of the base silicon wafer are contacted with a chemical solution for performing the primary texturing.

7. The method for obtaining a photovoltaic precursor by removing the phosphorus-doped N-type polysilicon layer and the tunneling layer located within the P-type interdigital regions includes the steps of: performing an acid etch on the P-type interdigitated regions to remove the thermal silicon oxide layer within the P-type interdigitated regions; 2. The method of claim 1, further comprising the steps of: removing the N-type polysilicon layer within the P-type interdigitated regions; and removing the thermal silicon oxide layer and the tunneling layer on the backlight surface of the base silicon wafer by wet cleaning to obtain a photovoltaic precursor.

8. The method for removing the N-type polysilicon layer within the P-type interdigitated regions includes the steps of:

10. The method for manufacturing an interdigitated back contact solar cell of claim 7, further comprising the step of performing a secondary texturing process on the light-receiving surface of the base silicon wafer and removing the N-type polysilicon layer within the P-type interdigitated regions using a chemical solution for the secondary texturing process.

9. Before sequentially disposing a tunneling layer and an N-type polysilicon layer on the backlight surface of a P-type silicon substrate, the manufacturing method includes:

9. The method for manufacturing an interdigital back contact solar cell according to claim 1, further comprising the step of double-side polishing the P-type silicon substrate.

10. An interdigitated back contact solar cell including a P-type silicon substrate, wherein a backlight surface of the P-type silicon substrate includes P-type interdigitated regions, N-type interdigitated regions, and blocking grooves; the blocking groove separates the P-type interdigital region from the N-type interdigital region; The N-type interdigital region includes, from the inside to the outside, a tunneling layer and an N-type polysilicon layer; a phosphorus-doped neutral layer is provided on the sidewall and bottom surface of the blocking groove; The outermost surfaces of the backlight surface and the light receiving surface of the P-type silicon substrate include a passivation layer; an N-type electrode of the interdigitated back contact solar cell is provided on the N-type interdigitated region, and the N-type electrode is provided through the passivation layer to contact the N-type polysilicon layer; An interdigital back contact solar cell, characterized in that a P-type electrode of the interdigital back contact solar cell is provided in the P-type interdigital region, and the P-type electrode is provided so as to penetrate the passivation layer and contact the P-type silicon substrate.

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