Neural network system and implementing method thereof

Abstract

A system is provided.SOLUTION: The neural network system includes a neural network circuit 510 including first memory cells arranged in an array, and a self-reference circuit 500 electrically connected to a row line or a column line of the neural network circuit and configured to apply a current to a row line or a column line to which a plurality of target memory cells are connected to have a preset target weight, wherein the target memory cells are all memory cells located in the row line or the column line to which the self-reference circuit is connected.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a neural network system and a method for implementing the same, and more particularly to an ultra-high speed parallel programming method for transferring a trained model to a large-scale neural network and a neural network system implemented by the method. [Background technology]

[0002] Artificial neural networks mimic biological neural networks; they can be trained by inputting large amounts of data and used to estimate or approximate results that are difficult to derive using conventional techniques. Artificial neural networks contain layers of interconnected neurons that exchange signals, and synapses with weights that can be adjusted based on learning or experience.

[0003] In order for a user to train an artificial neural network, the larger the amount of training data, the more powerful the computer device that needs to be run, and the user must be able to use the trained neural network to perform additional training on an edge device.

[0004] However, to accurately implement trained deep learning models in embedded SoCs of edge devices and to mass-produce such edge devices, the accuracy of weight programming and processing speed are crucial.

[0005] The above-mentioned background art is technical information that the inventor possessed for the purpose of deriving the present invention or that he acquired in the process of deriving the present invention, and is not necessarily publicly known art that was made public to the general public prior to the filing of the present invention. Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present disclosure is to provide a neural network system and a method for implementing the same. The problems to be solved by the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description of the present disclosure and will be more clearly understood by the embodiments of the present disclosure. Furthermore, it will be understood that the problems and advantages to be solved by the present disclosure can be achieved by the means and combinations thereof set forth in the claims. [Means for solving the problem]

[0007] As a means for solving the above-mentioned technical problem, a first aspect of the present disclosure may provide a neural network system including: a neural network circuit including first memory cells arranged in an array; and a self-referencing circuit electrically connected to row lines or column lines of the neural network circuit, applying current to the connected row lines or column lines so that a plurality of target memory cells have a predetermined target weight, wherein the target memory cells are all memory cells located on the row lines or column lines to which the self-referencing circuit is connected.

[0008] A second aspect of the present disclosure may provide a method for implementing a neural network system, the method including: obtaining target weights for first memory cells included in a neural network circuit and arranged in an array; adjusting a self-referencing circuit; and electrically connecting the adjusted self-referencing circuit to row lines or column lines of the neural network circuit to adjust weights of the neural network circuit, wherein the self-referencing circuit applies current to the connected row lines or column lines so that a plurality of target memory cells have the target weights, and the target memory cells are all memory cells located on the row lines or column lines to which the self-referencing circuit is connected.

[0009] A third aspect of the present disclosure can provide a computer-readable recording medium having recorded thereon a program for causing a computer to execute the method of the second aspect.

[0010] In addition, other methods and devices for implementing the present invention, and computer-readable recording media having programs for executing the methods can also be provided.

[0011] Other aspects, features, and advantages, in addition to those described above, will become apparent from the following drawings, claims, and detailed description of the invention. [Effects of the Invention]

[0012] According to the above-described means for solving the problems of the present disclosure, it is possible to provide an apparatus and an operating method thereof for implanting a deep neural network model at ultra-high speed by programming the weights of synaptic elements in parallel in an integrated circuit having a large-scale neural network.

[0013] Furthermore, according to the solution to the problems of the present disclosure, even when synaptic elements have high-density weights, disturbance during programming of adjacent synaptic elements is minimized, thereby providing a highly accurate implantation device and its operating method.

[0014] The effects of the embodiments are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the present invention. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram illustrating an implementation of a neural network system according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating a bit-wise programming method according to an embodiment. [Figure 3] FIG. 3 is a conceptual diagram illustrating a bit-wise programming scheme according to one embodiment. [Figure 4] FIG. 4 is a conceptual diagram that schematically illustrates a self-referential programming scheme according to one embodiment. [Figure 5] FIG. 5 is an example diagram of a neural network system implemented using self-referential programming according to one embodiment. [Figure 6] FIG. 6 is a diagram for explaining the operation of the self-referencing circuit according to one embodiment. [Figure 7] FIG. 7 is an exemplary diagram of a self-referencing circuit according to one embodiment. [Figure 8] FIG. 8 is a graph illustrating the results of self-referential programming according to one embodiment. [Figure 9] FIG. 9 is a flowchart of a method for implementing a neural network system according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] In describing the present invention, if it is determined that a specific description of related publicly known technology may obscure the gist of the present invention, such detailed description may be omitted, and unless otherwise defined, all terms used in this specification have the same meaning as commonly understood by a person having ordinary knowledge in the technical field to which the present invention belongs.

[0017] The appearances of phrases such as "in one embodiment," "pertaining to one embodiment," or "in accordance with one embodiment" in this specification do not necessarily all refer to the same embodiment.

[0018] The embodiments may be modified in various ways and may have various forms, and some embodiments are shown in the drawings and described in detail. However, this is not intended to limit the embodiments to the particular disclosed form, and it should be understood that the embodiments include all modifications, equivalents, and alternatives within the spirit and technical scope of the embodiments. The terms used in the specification are used merely to describe the embodiments and are not intended to limit the embodiments.

[0019] The terms used in the embodiments have been selected based on the functions of the embodiments and are currently common terms that are widely used as much as possible, but these may change depending on the intentions of engineers engaged in the technical field to which the embodiments belong, precedents, the emergence of new technologies, etc. In addition, in certain cases, the applicant may arbitrarily select terms, and in such cases, the meanings thereof will be described in detail in the relevant sections. Therefore, the terms used in the embodiments should be defined based on the meanings of the terms and the overall content of the embodiments, rather than simply the names of the terms.

[0020] Some embodiments of the present disclosure may be expressed as functional blocks and various processing steps. Some or all of these functional blocks may be implemented in various hardware and / or software configurations that perform specific functions. For example, the functional blocks of the present disclosure may be implemented by one or more microprocessors or by circuit configurations for a given function.

[0021] Further, for example, the functional blocks of the present disclosure may be implemented in various programming or scripting languages, or may be implemented as algorithms executed on one or more processors. Further, the present disclosure may employ conventional techniques for electronic configuration, signal processing, and / or data processing, etc.

[0022] Terms such as "database," "element," "means," and "configuration" may be used broadly and are not limited to mechanical and physical configurations. Furthermore, terms such as "part," "module," etc. described in the specification refer to a unit that processes at least one function or operation, and may be realized in hardware or software, or a combination of hardware and software.

[0023] Furthermore, connecting lines or connecting members between components shown in the drawings are merely exemplary of functional and / or physical or circuit connections, and in an actual device, connections between components may be represented by various alternative or additional functional, physical, or circuit connections.

[0024] Furthermore, terms including ordinal numbers such as "first" or "second" used herein may be used to describe various components, but the components should not be limited by the terms. The terms are used only to distinguish one component from another.

[0025] In addition, the size and proportion of some components in the drawings may be slightly exaggerated. Furthermore, components shown in one drawing may not be shown in other drawings.

[0026] Throughout the specification, the term "embodiment" is an arbitrary category for easily describing the invention in the present disclosure, and each of the embodiments does not necessarily have to be mutually exclusive. For example, a configuration disclosed in one embodiment can be applied and / or embodied in another embodiment, and can be applied and / or embodied with modifications without departing from the scope of the present disclosure.

[0027] Furthermore, the terms used in this disclosure are for the purpose of describing the embodiments and are not intended to limit the embodiments. In this disclosure, the singular forms "a," "an," and "the" also include the plural forms unless otherwise specified.

[0028]

[0032] The present disclosure will be described in detail below with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. However, the present disclosure may be embodied in various different forms and is not limited to the embodiments described herein.

[0029] The invention will be explained in more detail below on this basis with reference to the drawings.

[0030] FIG. 1 is a diagram illustrating an implementation of a neural network system according to an embodiment.

[0031] Referring to FIG. 1, a trained artificial neural network model 10 and actual hardware 20 can be seen.

[0032] The term "trained" for the artificial neural network model 10 means that the weights of each layer of the artificial neural network model 10 have been determined based on multiple pieces of training data. If the weights resulting from the training of the artificial neural network model 10 are stored in a central cloud server, a cloud computing device using the artificial neural network model 10 can communicate with the central cloud server to send input values ​​to the artificial neural network model 10 and receive output values. In this case, even if the artificial neural network model 10 is very complex or large-scale, the output values ​​can be used without any problems in the cloud computing device.

[0033] However, in the case of edge computing devices that process data on their own without communicating with a central cloud server, the artificial neural network model 10, i.e., the weights determined by learning, must be accurately transferred to the actual hardware 20. This becomes problematic when the artificial neural network model 10 is very complex or large-scale.

[0034] In the artificial neural network model 10, if the state values ​​of each weight are highly diverse (e.g., 128 states), the crossbar array implemented in the actual hardware 20 will be densely packed. Each memory cell included in the neural network circuit of the actual hardware 20 will be located on the same word line (WL) and bit line (BL) as its adjacent memory cells. In this case, a program / erase operation to transfer weights to a memory cell may cause disturbances in the adjacent memory cells, resulting in broadening and shifting of currents in the adjacent memory cells. This disturbance phenomenon may cause overlapping of the state values ​​of weights in a dense crossbar array, making accurate weight placement difficult.

[0035] Furthermore, when the artificial neural network model 10 is large-scale, the number of memory cells can reach millions or even tens of millions. In order to place the artificial neural network model 10 in hardware 20, weights must be transferred to a large number of memory cells, and mass-producing such hardware 20 is extremely time-consuming.

[0036] FIG. 2 is a diagram illustrating a bit-wise programming method according to an embodiment.

[0037] Referring to FIG. 2, a neural network system 20 implemented using bit-wise programming may include a neural network circuit 200, an address decoder 210, and a controller 220.

[0038] The neural network circuit 200 may include memory cells arranged in an array.

[0039] In one embodiment, the memory cells of the neural network circuit 200 may be flash memory cells. The memory cells include a source region and a drain region formed in a semiconductor substrate, with a channel region formed between the source region and the drain region. A floating gate is formed on at least one of the source region, the drain region, and the channel region and is insulated from the region by a gate insulating film.

[0040] In one embodiment, the memory cells of the neural network circuit 200 may be split-gate memory cells. A split-gate memory cell includes source / drain regions formed on a semiconductor substrate, and a pair of floating gates are disposed on the semiconductor substrate adjacent to both sides of the source / drain regions. The upper surfaces of the floating gates are each covered with an inter-gate oxide film, and a control gate is formed covering the upper surface of the inter-gate oxide film and insulated from the floating gate. A gate insulating film is formed between the floating gate and the semiconductor substrate, and a select gate insulated by the gate insulating film is disposed above the source / drain regions. The control gate and select gate are insulated by an extension of the inter-gate oxide film formed between the floating gate and the control gate.

[0041] Meanwhile, in a split-gate memory cell, a source region or a drain region may be formed on a semiconductor substrate on both sides of the floating gate opposite the source / drain region. A cell whose source / drain region functions as a source is called an odd cell, and a cell whose source / drain region functions as a drain is called an even cell. The odd and even cells may have a mirror-symmetric structure based on the source / drain region.

[0042] In one embodiment, the memory cells of the neural network circuit 200 may have a two-layer crossbar array structure, including a crossbar array consisting of row lines or column lines and a crossbar array consisting of word lines and bit lines. The word line terminals are connected to select gates, and the bit line terminals are connected to drain regions, allowing for write (program / erase) and read operations, respectively.

[0043] In a memory cell, electrons are removed from the floating gate when a high positive voltage is applied to the word line terminal. This is called the erase operation. Specifically, when a high positive voltage is applied to the word line terminal, electrons in the floating gate tunnel from the floating gate, pass through the insulator, and are injected into the select gate, i.e., the word line terminal.

[0044] In a memory cell, electrons are injected into the floating gate by applying a positive voltage to the word line terminal and a positive voltage to the source region. This is called a programming operation. Specifically, when a positive voltage is applied to the word line terminal and source region, electron current flows from the source region to the drain region. As the electrons reach the gap between the word line terminal and the floating gate, they are accelerated and heated, and some of them pass through the insulating film due to electrostatic attraction and are injected into the floating gate.

[0045] The configuration and arrangement of the source region, drain region, channel region, floating gate and select gate of a flash memory cell can be changed depending on the structure of the flash memory.

[0046] In one embodiment, the memory cell may be not only a flash memory but also a resistive random access memory (RRAM), a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), etc., and the type of the memory cell is not limited thereto.

[0047] The address decoder 210 can include a column decoder (X-address decoder) and a row decoder (Y-address decoder). The column decoder can include a word line decoder and a bit line decoder. The row decoder can include a source line decoder and a control gate decoder. Each decoder can decode the input to the memory cell array of the neural network circuit 200. Furthermore, the source line decoder can decode the output of the memory cell array of the neural network circuit 200.

[0048] The controller 220 sends the address decoder 210 the location of the memory cell on which to perform the read / write operation; JPEG2026000980000002.jpg766 can be applied to control the write operation, and the current output from the memory cell can be received to control the read operation.

[0049] The bit-by-bit programming method will now be described.

[0050] The controller 220 transmits a signal to the address decoder 210 to designate one memory cell (for convenience of explanation, referred to as the first memory cell) in which to store the weight, and applies a program / erase voltage through a word line corresponding to the first memory cell, thereby storing the weight in the first memory cell. Before and after the program / erase operation, a read operation through a bit line can be performed.

[0051] Next, the controller 220 transmits a signal to the address decoder 210 to designate a second memory cell in which the weight is to be stored, and applies a program / erase voltage through a word line corresponding to the second memory cell, thereby storing the weight in the second memory cell. Similarly, a read operation through a bit line can be performed before or after the program / erase operation.

[0052] In this manner, the neural network system 20 can be realized by sequentially applying program / erase voltages to all memory cells of the neural network circuit 200 and storing weights determined from the trained model.

[0053] FIG. 3 is a conceptual diagram illustrating a bit-wise programming scheme according to one embodiment.

[0054] Referring to FIG. 3, when the neural network circuit has M row lines and N column lines, the bit-wise programming method described in FIG. 2 can be roughly confirmed.

[0055] In the bit-wise programming operation, weights are directly stored in M*N memory cells, which is the product of the number of row lines and the number of column lines. In other words, weight trimming (Trim) operation by program / erase operation is performed directly for each memory cell.

[0056] However, as described above, memory cells that share a word line or bit line may experience disturbances during program / erase operations of adjacent memory cells after weights are stored, causing current expansion and migration, resulting in deviation from the target weights. The disturbance phenomenon may be exacerbated by repeated program / erase operations, and in the case of a high-density crossbar array neural network circuit 200, the state values ​​of the weights may overlap. This may cause errors in the neural network system 20.

[0057] Another problem with bit-by-bit programming is that it is not suitable for mass production, since in the case of large-scale neural network systems, write / read operations must be performed on each of the millions to tens of millions of memory cells.

[0058] FIG. 4 is a conceptual diagram that schematically illustrates a self-referential programming scheme according to one embodiment.

[0059] There are various programming methods for memory cell weight programming, such as the bit-by-bit programming described above, as well as iterative programming.

[0060] The iterative programming method performs a program / erase operation, i.e., a write operation, on the entire memory cell of the neural network circuit, checks the stored weights through a read operation, and then performs a write operation again to remove errors corresponding to the difference value from the target weight.

[0061] At this time, an error correction code can be applied to the write operation to remove the error.

[0062] In this way, by repeating the write and read operations for the entire memory cell, the error value of the target current of the memory cell can be reduced, and therefore, the disturbance phenomenon of adjacent memory cells can be minimized compared to the bit-by-bit programming method described in Figures 2 and 3.

[0063] However, in the case of a high-density crossbar array, it is necessary to repeat the write / read operation several tens of times to reduce the error value so that the weight state values ​​can be sufficiently distinguished during the write / read operation. Therefore, in the case of a large-scale neural network system, the total time required for programming is long, so the iterative programming method is not suitable for mass production of products using large-scale neural network systems.

[0064] The iterative programming method is suitable for applications where the size of the neural network system is sufficiently small.

[0065] Therefore, in one embodiment of the present invention, a two-step programming method is disclosed that performs weight programming for a small embedded system and then uses the programmed small embedded system to program the entire neural network circuit.

[0066] For example, referring to FIG. 4, a weight trimming (1st Trim) operation using a program / erase operation can be performed on a small-scale crossbar array having n memory cells, and the programmed small-scale crossbar arrays can be provided in the number of row lines (M) or the number of column lines (N) and electrically connected to the row lines or column lines of a neural network circuit, and each small-scale crossbar array can perform a weight trimming (2nd Trim) operation using a program / erase operation on all the memory cells of the column lines or the memory cells of the row lines.

[0067] That is, row-by-row programming or column-by-column programming can be performed.

[0068] In the following, the self-referencing programming method according to an embodiment will be described based on row-based programming, but it can also be applied to column-based programming, and the principles are the same. Furthermore, in the above description, small-scale embedded systems and small-scale crossbar arrays can refer to self-referencing circuits.

[0069] FIG. 5 is an example diagram of a neural network system implemented using self-referential programming according to one embodiment.

[0070] Referring to FIG. 5, the neural network system can include a self-referencing circuit 500, a neural network circuit 510, and a bandgap circuit 520.

[0071] The neural network circuit 510 may include a plurality of memory cells arranged in an array. Hereinafter, the memory cells included in the neural network circuit 510 will be referred to as first memory cells.

[0072] The description of the first memory cell will be omitted if it overlaps with the description above with reference to Figure 2. That is, the first memory cell may correspond to not only a flash memory but also a resistive random access memory (RRAM), a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), etc.

[0073] The bandgap circuit 520 can provide a reference voltage so that a constant voltage is applied to the self-referencing circuits 500. The bandgap circuit 520 can operate as a reference voltage source or a reference current source because its output is not sensitive to changes in the external environment, and is also called a bandgap reference circuit. The bandgap circuit 520 is electrically connected to a plurality of self-referencing circuits 500 and can provide a reference voltage or a reference current so that a constant voltage or a constant current is applied to the self-referencing circuits 500.

[0074] In one embodiment, the self-reference circuit 500 may be electrically connected to row lines of the neural network circuit 510. When the neural network circuit 510 forms a crossbar array with M row lines and N column lines, M self-reference circuits 500 may be electrically connected to each row line of the neural network circuit 510. The self-reference circuit 500 may perform weight programming on first memory cells located on the connected row lines. Hereinafter, all memory cells located on the row lines connected to the self-reference circuit 500 among the first memory cells are defined as target memory cells.

[0075] In one embodiment, the self-reference circuit 500 can apply current to the connected row lines so that a plurality of target memory cells have a preset target weight. For example, the neural network system can further include a write circuit (not shown) that performs a programming operation on the target memory cells so that the target memory cells have a preset target weight. That is, the self-reference circuit 500 can perform a read operation on the target memory cells, specifically, deliver a precise source voltage to the target memory cells, and the write circuit (not shown) can perform a write operation on the target memory cells.

[0076] FIG. 6 is a diagram for explaining the operation of the self-referencing circuit according to one embodiment.

[0077] Referring to FIG. 6, a crossbar array circuit and a self-referencing circuit 500 embodying the neural network circuit 510 of FIG. 5 can be seen.

[0078] The neural network circuit 510 may be composed of a first crossbar array and a second crossbar array. The memory cells of the neural network circuit 510 may be composed of split-gate memory cells to realize a two-layer crossbar array structure. For convenience of explanation, the first row line (hereinafter referred to as the "first row line") 601 and the first column line (hereinafter referred to as the "first column line") 611 of the first crossbar array, and the first row line (hereinafter referred to as the "first* row line") 602 and the first column line (hereinafter referred to as the "first* column line") 612 of the second crossbar array will be described.

[0079] The first row line 601 may correspond to a source line that supplies a source voltage to the memory cell. The first column line 611 may correspond to a bit line that performs a read operation. The first* row line 602 may supply an input voltage to the memory cell. The first* column line 612 may correspond to a word line that performs a write operation.

[0080] The target memory cell 600 located on the first row line 601 and the first column line 611 of the neural network circuit can have its components electrically connected to the first column line 611, the *1st row line 602, and the *1st column line 612.

[0081] Specifically, a drain region of the target memory cell 600 may be connected to a first column line 611 and may receive a drain voltage from the first column line. A control gate of the target memory cell 600 may be connected to a first* row line 602 and may receive a gate voltage from the first* row line 602. Therefore, the first* row line 602 may perform a write operation on the target memory cell 600. A select gate of the target memory cell 600 may be connected to a first* column line 612. A source region of the target memory cell 600 may be electrically connected to the self-reference circuit 500.

[0082] In one embodiment, a cell designation circuit (not shown) can select a specific memory cell by designating a specific column line, i.e., a target line, for the self-reference circuit 500 connected to the first row line 601. The intersection of the connected row line and column line determines the address of the first memory cell, and each of the first memory cells has a preset target weight. Therefore, the cell designation circuit (not shown) can select the specified memory cell so that a current corresponding to the target weight is applied from the self-reference circuit 500 to the appropriate memory cell.

[0083] FIG. 7 is an exemplary diagram of a self-referencing circuit according to one embodiment.

[0084] Referring to FIG. 7, the self-referencing circuit 500 may include a second memory cell 710, a comparator 720, and a pass gate 730.

[0085] In one embodiment, the second memory cell 710 can have a regulated gate voltage applied to its control gate.

[0086] In one embodiment, there may be two or more second memory cells 710. When there are two or more second memory cells 710, the second memory cells 710 may be connected in parallel. In addition, the parallel-connected second memory cells 710 may have different control gate voltages applied to their control gates, and different output currents may flow. In this case, when the second memory cell 710 is turned off, no current flows, and therefore the output current may include zero.

[0087] In one embodiment, the number of second memory cells 710 may be determined based on the number of weight state values ​​that the target memory cell can have. For example, if the neural network system is configured so that the first memory cell has 256 state values, the self-reference circuit 500 may include eight second memory cells 710. Therefore, weight programming of the second memory cells 710 may be performed so that the output currents of the second memory cells 710 flow differently from each other, and the eight second memory cells 710 may be programmed depending on whether they are activated. JPEG2026000980000003.jpg1114 state value. On the other hand, if the second memory cell 710 is a split gate type memory cell, the odd and even cells can output positive and negative state values, respectively. That is, the second memory cell 710 outputs JPEG2026000980000004.jpg1114 status value can be output.

[0088] That is, the first memory cell When configuring a neural network system to have a state value of JPEG2026000980000005.jpg713, self-reference circuit 500 may include n second memory cells 710. Furthermore, as described above, weight programming of the target memory cells is performed according to a combination of output currents flowing through second memory cells 710, so that the output currents can be combined to correspond to the weight state values. As a result, the combination of output currents is applied via pass gates 730 to each target memory cell of the row line to which self-reference circuit 500 is connected, and weight programming can be performed to have a preset target weight.

[0089] In one embodiment, the comparator 720 compares the voltage across the second memory cell 710 with a preset comparator voltage For example, the comparator 720 may compare the voltage across the second memory cell 710 with a preset comparator voltage . JPEG2026000980000007.jpg710 are equal, no current may flow across the comparator 720. Specifically, when an adjustment gate voltage is applied to the second memory cell 710 and a target output current flows through the second memory cell 710, the channel conductance of the second memory cell 710 becomes equal to the potential of the bandgap circuit connected to the self-reference circuit 500. That is, since the voltage across the second memory cell 710 input to the comparator 720 becomes equal to the comparator voltage, the comparator 720 can determine, as a digital signal, that the adjustment of the second memory cell 710 is complete.

[0090] In one embodiment, the comparator 720 can determine whether weight programming is complete when the self-reference circuit 500 is connected to a neural network circuit and the target memory cell (first memory cell) has a target weight. For example, when a current is applied to the target memory cell of the neural network circuit and the target memory cell has a target weight, the channel conductance of the target memory cell becomes equal to the channel conductance of the second memory cell 710 of the self-reference circuit 500. That is, the voltage across the target memory cell input to the comparator 720 becomes equal to the comparator voltage, and the comparator 720 can determine as a digital signal that weight programming of the target memory cell is complete.

[0091] In one embodiment, the pass gate 730 allows current to pass through the second memory cell 710 in response to the digital signal.

[0092] In one embodiment, the second memory cells 710 of the self-referencing circuit 500 may be programmed using a bit-wise programming scheme or an iterative programming scheme. Specifically, the adjustment gate voltage of the second memory cells 710 may be determined using an iterative programming scheme and applied to each second memory cell 710. As described above, the self-referencing circuit 500 is a small-scale embedded system whose weights are determined according to the number of state values ​​of the first memory cells, and therefore can be quickly programmed using either the bit-wise programming scheme or the iterative programming scheme. In particular, applying the iterative programming scheme allows for highly accurate programming to be performed in a short time.

[0093] FIG. 8 is a graph illustrating the results of self-referential programming according to one embodiment.

[0094] 8, the cumulative distribution function of the weight state value of each first memory cell by current as a result of self-reference programming can be seen. It can be seen that in a high-density crossbar array, each weight state value is clearly programmed to be distinct.

[0095] Although FIG. 8 shows 7-bit states, this is merely an example, and the number of weight state values ​​is not limited to this.

[0096] FIG. 9 is a flowchart of a method for implementing a neural network system according to an embodiment.

[0097] Referring to FIG. 9, the method for implementing a neural network system can be performed by an apparatus for implementing a neural network system (hereinafter referred to as an "apparatus").

[0098] In step 910, the apparatus may obtain target weights for a first memory cell included in the neural network circuit and arranged in an array.

[0099] In step 920, the device may adjust the self-referencing circuit.

[0100] In one embodiment, the self-reference circuit may apply current to a row line or column line connected thereto so that a plurality of target memory cells have a target weight, where the target memory cells may refer to all memory cells located on the row line or column line connected thereto.

[0101] In one embodiment, the self-referencing circuit may include a plurality of second memory cells coupled in parallel to each other, with regulated gate voltages applied to their control gates.

[0102] In one embodiment, the number of the second memory cells may be determined based on the number of weighted state values ​​(State) that the target memory cell can have.

[0103] In one embodiment, the self-referencing circuit may include a comparator that outputs a comparison result between the voltage across the second memory cell and a set comparator voltage as a digital signal.

[0104] In one embodiment, the device may apply different tuning gate voltages to the control gates of the plurality of second memory cells to cause different output currents to flow through the plurality of second memory cells, where the output currents may include zero and combinations of the output currents may correspond to weighted state values.

[0105] In one embodiment, the self-referencing circuit can apply a combination of output currents to a target memory cell such that the target memory cell has a preset target weight.

[0106] In step 930, the device may electrically couple the adjusted self-referencing circuit to row or column lines of the neural network circuit to adjust the weights of the neural network circuit.

[0107] In one embodiment, the device can select a specified memory cell corresponding to the target line from among a plurality of target memory cells by specifying a target line of the neural network circuit.

[0108] In one embodiment, the device can perform a programming operation on a target memory cell such that the target memory cell has a target weight.

[0109] In one embodiment, the device can provide a reference voltage so that a constant voltage is applied to the self-referencing circuit.

[0110] Meanwhile, embodiments of the present invention may be embodied in the form of a computer program executable by various components on a computer, and such a computer program may be recorded on a computer-readable medium, which may include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program instructions, such as ROMs, RAMs, and flash memories.

[0111] Meanwhile, the computer program may be specially designed and constructed for the present invention, or may be one that is well known and available to those skilled in the art of computer software. Examples of the computer program include not only machine language code such as that produced by a compiler, but also high-level language code that can be executed by a computer using an interpreter, etc.

[0112] According to one embodiment, methods according to various embodiments of the present disclosure may be provided in a computer program product. The computer program product may be traded between a seller and a buyer as a commodity. The computer program product may be distributed in the form of a device-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)) or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices. In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored or temporarily generated in a device-readable storage medium, such as the memory of a manufacturer's server, an application store server, or an intermediary server.

[0113] Unless otherwise clearly stated or contrary to the order of steps constituting the method of the present invention, the steps may be performed in any suitable order. The present invention is not necessarily limited to the order of the steps described. The use of all examples or exemplary terms in the present invention is merely for the purpose of explaining the present invention in detail, and the scope of the present invention is not limited by the examples or exemplary terms unless otherwise limited by the claims. Furthermore, those skilled in the art will understand that various modifications, combinations, and variations may be made depending on design conditions and factors within the scope of the appended claims or their equivalents.

[0114] Therefore, the concept of the present invention should not be limited to the above-described embodiments, and all scopes equivalent to or modified equivalently from the scope of the claims, as well as the scope of the claims described below, can be said to fall within the scope of the concept of the present invention.

Claims

1. A self-referencing circuit electrically coupled to a predetermined line, the self-referencing circuit applying a current to the predetermined line such that a target memory cell coupled to the predetermined line has a predetermined target weight, comprising: the predetermined line is a row line or a column line of a neural network circuit, The target memory cells are a plurality of first memory cells, either a source region or a drain region of which is connected to the predetermined line.

2. The self-reference circuit a plurality of second memory cells connected in parallel to each other and having a regulated gate voltage applied to their control gates; 2. The self-reference circuit according to claim 1, further comprising a comparator that outputs a comparison result between the voltage across said second memory cell and a preset comparator voltage as a digital signal.

3. The plurality of second memory cells 3. The self-referencing circuit of claim 2, wherein the number is determined based on the number of state values ​​of weight that the target memory cell can have.

4. The plurality of second memory cells different control gate voltages are applied to the control gates to generate different output currents, the output currents including zero; The output current combination is:

4. The self-referencing circuit of claim 3, wherein said weights correspond to state values.

5. The self-referencing circuit 5. The self-referenced circuit of claim 4, wherein the combination of output currents is applied to the target memory cell such that the target memory cell has a preset target weight.

6. The self-referencing circuit of claim 1, wherein a constant voltage is applied to the self-referencing circuit by a bandgap circuit that provides a reference voltage.

7. A method for implementing a neural network system, comprising: obtaining a target weight for a target memory cell coupled to a given line; adjusting a self-reference circuit; and electrically connecting the adjusted self-reference circuit to the predetermined line to adjust the weight of the target memory cell, the self-referencing circuit applies a current to the predetermined line so that the target memory cell has the target weight; the predetermined line is a row line or a column line of a neural network circuit, The method, wherein the target memory cells are a plurality of first memory cells having either a source region or a drain region coupled to the predetermined line.

8. The self-referencing circuit a plurality of second memory cells connected in parallel to each other and having a regulated gate voltage applied to their control gates; 8. The method according to claim 7, further comprising a comparator that outputs a result of comparing the voltage across the second memory cell with a preset comparator voltage as a digital signal.

9. The plurality of second memory cells:

9. The method of claim 8, wherein the number is determined based on the number of state values ​​of weight that the target memory cell can have.

10. The step of adjusting the self-referencing circuit comprising: applying different adjustment gate voltages to the control gates so that different output currents, including zero, flow through the plurality of second memory cells; The output current combination is:

10. The method of claim 9, wherein the weights correspond to state values.

11. The self-referencing circuit: The method of claim 10 , further comprising applying the combination of output currents to the target memory cell such that the target memory cell has a preset target weight.

12. The method comprising: The method of claim 7 , further comprising: performing a programming operation on the target memory cell such that the target memory cell has the target weight.

13. The method comprising: The method of claim 7 further comprising the step of providing a reference voltage such that a constant voltage is applied to the self-referencing circuit.

14. A computer-readable recording medium having recorded thereon a program for executing the method according to claim 7 on a computer.

15. A neural network circuit including a target memory cell whose weight has been adjusted by the method of claim 7.

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