Method for manufacturing display device

Abstract

To provide a flexible display device having excellent display quality and high yield.SOLUTION: Forming a first organic resin layer over a first substrate, forming a first insulating film over the first organic resin layer, forming a first element layer over the first insulating film, forming a second organic resin layer over a second substrate, forming a second insulating film over the second organic resin layer, forming a second element layer over the second insulating film, and bonding the first substrate and the second substrate so that the first element layer and the second element layer are sealed; A first separation step of separating the first substrate by reducing adhesion between the first organic resin layer and the first substrate is performed, the first organic resin layer and the first flexible substrate are bonded to each other with the first bonding layer provided therebetween, a second separation step of separating the second substrate by reducing adhesion between the second organic resin layer and the second substrate is performed, and the second organic resin layer and the second flexible substrate are bonded to each other with the second bonding layer provided therebetween.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a display device including the semiconductor device, and a method for producing the same.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, devices, power storage devices, storage devices, driving methods thereof, or manufacturing methods thereof, as examples. Some examples include:

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. Display devices and electronic devices may include semiconductor devices. [Background technology]

[0004] The technology of constructing a transistor using a semiconductor film formed on a substrate with an insulating surface is attracting attention. The transistor is used in devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is widely used as a semiconductor thin film that can be applied to transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention. There are.

[0005] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are.

[0006] Furthermore, in addition to being thin and lightweight, improvements in flexibility and impact resistance are also desired for display devices. For example, Patent Document 2 discloses a film substrate on which a transistor, which is a switching element, is mounted. and a flexible active matrix light-emitting device including an organic EL element. There are. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 2] Japanese Patent Application Laid-Open No. 2003-174153 Summary of the Invention [Problem to be solved by the invention]

[0008] In the manufacturing process of flexible display devices, if a rigid substrate is used, this does not pose a problem. Small defects can expand during the process, reducing product yield. Furthermore, after the display device is completed, the defective area may expand due to bending or warping, resulting in deterioration of display quality and signal quality. This may reduce reliability.

[0009] Therefore, in a manufacturing method of a flexible display device, a combination of materials and an appropriate processing method are required. It is desirable to use a manufacturing method that does not cause minute defects in the product during the process. .

[0010] Therefore, one object of one embodiment of the present invention is to provide a display device with high display quality. Another object is to provide a highly reliable display device. One of the objects is to provide a new display device. Another object of the present invention is to provide a method for manufacturing the display device. It shall be one.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a flexible display device including a transistor using an oxide semiconductor layer, and and a method for producing the same.

[0013] One embodiment of the present invention includes a first element layer and a second element layer. One of the element layers is a pixel including a first transistor and a display element having an oxide semiconductor layer. a circuit portion including a first transistor and a second transistor including an oxide semiconductor layer; The other of the second element layer and the second element layer has a colored layer and a light-shielding layer. A first organic resin layer is formed on the first substrate, and a first insulating film is formed on the first organic resin layer. A first element layer is formed on the first insulating film, and a second organic resin layer is formed on the second substrate. forming a second insulating film on the second organic resin layer; and forming a second element layer on the second insulating film. and bonding the first substrate and the second substrate together so that the first element layer and the second element layer are sealed. The adhesiveness between the first organic resin layer and the first substrate is reduced, and the first substrate is separated. A first separation step is performed to bond the first organic resin layer and the first flexible substrate via a first adhesive layer. and a second organic resin layer is attached to the second substrate, thereby reducing the adhesion between the second organic resin layer and the second substrate, thereby separating the second substrate. The second organic resin layer and the second flexible substrate are bonded together via a second adhesive layer. The present invention relates to a method for manufacturing a display device.

[0014] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It should be noted that the numbers are added for the purpose of convenience and are not intended to be limiting in number.

[0015] The first organic resin layer and the second organic resin layer are made of epoxy resin, acrylic resin, polyimide, or the like. It may be made of a material selected from resin, polyamide resin, or polyamide-imide resin. can.

[0016] The adhesion between the first organic resin layer and the first substrate is reduced, and the adhesion between the second organic resin layer and the second organic resin layer is reduced. The adhesion between the first substrate and the second substrate is preferably reduced by irradiating a linear excimer laser beam. stomach.

[0017] The excimer laser light is a laser light obtained by combining laser lights output from a plurality of oscillators. Preferably it is light.

[0018] The second separating step is performed by bringing the first flexible substrate into contact with the curved surface of a roller and peeling it off. It is preferable to do so.

[0019] The first insulating film and the second insulating film may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a silicon nitride film. It is preferable that a silicon film or a silicon nitride oxide film is included.

[0020] The oxide semiconductor layer is made of In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, C The oxide semiconductor layer may be oriented along the c-axis. It is preferable to have crystals that

[0021] The display element can be an organic EL element.

[0022] Another aspect of the present invention is a liquid crystal display device comprising: a first flexible substrate; a first adhesive layer; a first organic resin layer; A pixel including a first insulating film, a first transistor having an oxide semiconductor layer, and a display element a first element having a circuit portion including a second transistor having an oxide semiconductor layer; a second element layer having a colored layer and a light-shielding layer; a second insulating film; and a second organic resin. a layer, a second adhesive layer, and a second flexible substrate are laminated in the above order. This is a display device.

[0023] The oxide semiconductor layer of the first transistor is a single layer, and the oxide semiconductor layer of the second transistor is a single layer. The compound semiconductor layer may be multi-layered.

[0024] The oxide semiconductor layer of the first transistor is formed by a second transistor having an oxide semiconductor layer. It is preferable that the composition of the layer be the same as that of the layer in contact with the gate insulating film of the transistor. [Effects of the Invention]

[0025] By using one embodiment of the present invention, a display device with high display quality can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device, etc. Alternatively, a method for manufacturing the display device can be provided. Alternatively, a manufacturing method for a display device with high yield can be provided.

[0026] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a top view illustrating a display device. [Figure 2] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 3] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 6] FIG. 1 is a diagram illustrating an example of a processing device using an excimer laser. [Figure 7] FIG. 1 is a diagram showing an example of a peeling device. [Figure 8] FIG. 1 is a diagram showing an example of a peeling device. [Figure 9] FIG. 1 is a diagram showing an example of a peeling device. [Figure 10] FIG. 1 is a diagram showing an example of a peeling device. [Figure 11] FIG. 1 is a diagram showing an example of a peeling device. [Figure 12] FIG. 1 is a diagram showing an example of a peeling device. [Figure 13] FIG. 1 is a diagram showing an example of a peeling device. [Figure 14] FIG. 1 is a diagram showing an example of a peeling device. [Figure 15] FIG. 1 is a diagram showing an example of a peeling device. [Figure 16] FIG. 1 is a diagram showing an example of a peeling device. [Figure 17] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 18] FIG. 2 is a diagram illustrating a display module. [Figure 19] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 20] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 21] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 22] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 23] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 24] 1A to 1C illustrate electronic devices. [Figure 25] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 26] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 27] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 28] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 29] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 30] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 31] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 32] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 33] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 34] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 35] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 36] FIG. 10 is a diagram illustrating the temperature dependence of resistivity. [Figure 37] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 38] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 39] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 40] Electron diffraction pattern of CAAC-OS. [Figure 41] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 42] Schematic diagram illustrating the film formation model of CAAC-OS and nc-OS. [Figure 43] A diagram explaining InGaZnO4 crystals and pellets. [Figure 44] Schematic diagram illustrating a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE INVENTION

[0028] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0029] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0030] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0031] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0032] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0033] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0034] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0035] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0036] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0037] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , and the second connection path is a transistor through a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. the third connection path does not have the second connection path, and the third connection path The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path; The second connection path has a connection path through a transistor, and (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , does not have a fourth electrical path, and the fourth electrical path is (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0038] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0039] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0040] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0041] (Embodiment 1) In this embodiment, a display device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. explain.

[0042] In this specification, the term "display device" refers to an image display device or a light source (such as a lighting device). Also refers to connectors such as FPC and TCP (Tape Carrier) The module has a printed wiring board at the end of the TCP. or a module in which the driver circuit is directly mounted on the display element using the COG method. All the rules are included in the display device.

[0043] A display device according to one embodiment of the present invention has flexibility. Flexibility also means that the final product can bend and flex. In some cases, the material is used as a final product, while in other cases it is used during the manufacturing process. In some cases, it may not be flexible.

[0044] FIG. 1 is a top view of a display device 300 according to one embodiment of the present invention. Note that in FIG. 1, for clarity of the drawing, For clarity, some elements may be enlarged, reduced, transparent, or omitted.

[0045] The display device 300 includes a pixel portion 302 provided on a first flexible substrate 301, and a a first circuit portion 304 and a second circuit portion 305 for driving the pixel portion 302, the first a sealant 312 disposed to surround the first circuit portion 304 and the second circuit portion 305; and a second flexible substrate 307 provided so as to face the first flexible substrate 301. The first circuit portion 304 may include, for example, a signal line driver circuit (source driver), a second The circuit section 305 may include, for example, a scanning line driver circuit (gate driver). Cut.

[0046] The first flexible substrate 301 and the second flexible substrate 307 are bonded together by a sealant 312. Although not shown in FIG. 1, the first flexible substrate 301 and the second flexible substrate 30 A display element is provided between the pixel portion 302, the first circuit portion 304, the second The circuit portion 305 and the display element are formed by the first flexible substrate 301, the sealing material 312, and the second It is sealed by a flexible substrate 307 .

[0047] The display device 300 is surrounded by a seal material 312 on the first flexible substrate 301. The pixel section 302, the first circuit section 304, and the second circuit section 305 are arranged in a region different from the region where the pixel section 302 is arranged. 5 and an FPC terminal portion 308 (FPC: Flexible Printed Circuit) d circuit).

[0048] Furthermore, an FPC 316 is connected to the FPC terminal portion 308, and the pixel portion Various signals are supplied to the first circuit section 302, the second circuit section 304, and the second circuit section 305. , a pixel section 302, a first circuit section 304, a second circuit section 305, and an FPC terminal section 308 A signal line 310 is connected to each of the FPCs 316. , the pixel section 302, the first circuit section 304, and the second circuit section 305 are connected via a signal line 310. is given to.

[0049] In addition, in FIG. 1, a configuration in which a circuit for driving the pixel portion 302 is arranged in two regions is illustrated. However, the configuration of the circuit is not limited to this. For example, the circuit may be integrated into one area. The circuit may be divided into three or more parts. Only one of the path portion 304 and the second circuit portion 305 is provided on the first flexible substrate 301. The other circuit may be externally connected.

[0050] The circuit for driving the pixel portion 302 is the same as the transistor included in the pixel portion 302. Alternatively, the semiconductor device may be formed on the first flexible substrate 301 in the same manner as above, or may be formed on a COG (Chip On Glass) substrate. It may be configured to mount an IC chip using a material such as glass. The configuration may be such that the two are connected to each other.

[0051] The pixel section 302, the first circuit section 304, and the second circuit section 305 of the display device 300 are 05 has a plurality of transistors whose channel formation regions are formed using oxide semiconductor layers. do.

[0052] A transistor using an oxide semiconductor layer has high mobility, so the area occupied by the transistor can be reduced. This can reduce the size of the transistor, thereby improving the aperture ratio. The first circuit section 304 and the second circuit section 305 are formed on the same substrate as the pixel section 302. In addition, the off-state current of the transistor is extremely small, and the retention time of an image signal or the like is short. Since the time can be extended, the frame frequency can be lowered, and the power consumption of the display device can be reduced. Power consumption can be reduced.

[0053] The oxide semiconductor layer preferably has crystals oriented in the c-axis direction. When an oxide semiconductor layer having such crystals is used in a channel formation region of a display device, When the device 300 is bent, cracks or the like are less likely to occur in the oxide semiconductor layer, and therefore reliability is improved. It can be improved.

[0054] Therefore, by using a transistor including an oxide semiconductor layer, This allows for the formation of a display device that is superior to that using silicon or polycrystalline silicon layers.

[0055] The display device 300 typically uses a liquid crystal element or a light-emitting element. can be done.

[0056] Next, a display device 300a using a liquid crystal element will be described. 2 is a cross-sectional view taken along the dashed dotted line A1-A2 shown in FIG. 1 in the case where a liquid crystal element is used.

[0057] The display device 300a includes a first flexible substrate 301, a first adhesive layer 318a, and a first organic A resin layer 320a, a first insulating film 321a, a first element layer, a second element layer, and a second The insulating film 321b, the second organic resin layer 320b, the second adhesive layer 318b, and the second flexible The conductive substrates 307 are stacked in the above order.

[0058] In FIG. 2, the first element layer includes transistors 350 and 352, insulating films 364 and 366, 368, a planarization insulating film 370, a connection electrode 360, a conductive film 372, etc. The second element layer includes a conductive film 374, an insulating film 334, and a coloring layer 336 (color filter). and a light-shielding layer 338 (black matrix). In the device layer, some of the above elements may not be included. may also be included.

[0059] Here, the first element layer and the second element layer are sealed by a liquid crystal layer 376 and a sealant 312. This forms a liquid crystal element 375 .

[0060] The first flexible substrate 301 and the second flexible substrate 307 may be, for example, a flexible substrate. thickness of glass, polyethylene terephthalate (PET), polyethylene naphthalate Polyester resins such as PEN, polyacrylonitrile resins, polyimide resins, poly Methyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (P ES) resin, polyamide resin, cycloolefin resin, polystyrene resin, polyamide resin Examples include amide resin, polyvinyl chloride resin, and polyether ether ketone (PEEK) resin. In particular, it is preferable to use a material with a low thermal expansion coefficient, such as polyamide. Suitable materials for the resin include amide resin, polyimide resin, and PET. Substrates impregnated with organic resin or substrates with a lower thermal expansion coefficient by mixing inorganic fillers into organic resin It can also be used.

[0061] The adhesive layers 318a and 318b are made of a hardening resin that hardens at room temperature, such as a two-component mixed resin. Resins such as epoxy, photo-curable resins, and thermosetting resins can be used. resin, acrylic resin, silicone resin, phenolic resin, etc. A material with low moisture permeability such as resin is preferred.

[0062] The first organic resin layer 320a and the second organic resin layer 320b may be made of, for example, epoxy. Resin, aramid resin, acrylic resin, polyimide resin, polyamide resin, or polyamide The insulating layer 10 can be made of a material selected from the group consisting of dimethyl ether and dimethyl ether.

[0063] The first insulating film 321a and the second insulating film 321b may be a silicon oxide film, an oxynitride film, or the like. A single layer of silicon film, silicon nitride film or silicon oxynitride film, or a laminate of these films is used. In particular, the first flexible substrate 301 and the first adhesive layer 318a may include To prevent impurities from diffusing into transistors, etc., a highly blocking nitride It is preferable to use a film containing an element.

[0064] The display device 300a includes a wiring portion 311, a pixel portion 302, a first circuit portion 304, and a , and an FPC terminal portion 308. The lead wiring portion 311 has a signal line 310. do.

[0065] In the display device 300a, a transistor 350 is provided in the pixel portion 302, and a first circuit portion 3 illustrates a configuration in which a transistor 352 is provided in each of the transistors 304.

[0066] In FIG. 2, transistors 350 and 352 are configured to be the same size. The transistors 350 and 352 may be of any suitable size. The channel length, channel width, etc., or the number of channels can be changed. In this case, the second circuit section 305 is not shown, but the connection destination or the connection method, etc. This allows the circuit portion 304 to have the same configuration as the first circuit portion 304.

[0067] The signal line 310 of the lead wiring portion 311 is connected to the source electrode layer of the transistor 350 and The insulating layer can be formed in the step of forming the drain electrode layer.

[0068] The FPC terminal portion 308 includes a connection electrode 360, an anisotropic conductive film 380, and an FPC 316. The connection electrode 360 ​​is connected to the source electrode layer and the drain electrode layer of the transistor 350. The connection electrode 360 ​​can be formed in the process of forming the layer. The terminals are electrically connected to the corresponding terminals via the anisotropic conductive film 380.

[0069] In addition, a signal connected to a transistor in a pixel portion and a transistor used in a driver circuit portion It is preferable to use wiring containing copper as the wire. By using wiring containing copper, This can reduce signal delays and the like caused by wiring resistance.

[0070] 2, an insulating film 364 is formed on the transistor 350 and the transistor 352. , 366, 368, and a planarizing insulating film 370 are provided.

[0071] The insulating films 364 and 366 can be made of the same material, for example, silicon oxide. The insulating film 364 may be made of silicon oxynitride or silicon oxynitride. The insulating film 366 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. It is preferable to form the insulating films 364 and 366 using a single layer of the same material. The insulating film 368 may be formed of a bromine such as oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. For example, it is preferable to use a nitride insulating film.

[0072] The planarization insulating film 370 may be made of polyimide resin, acrylic resin, or polyimide amide. Resin, benzocyclobutene resin, polyamide resin, epoxy resin, and other heat-resistant organic It is possible to use a material for the insulating film. In this way, the planarization insulating film 370 may be formed. It may also be possible to use the following.

[0073] In addition, one of the source electrode layer and the drain electrode layer of the transistor 350 has a conductive The conductive film 372 is formed on the planarization insulating film 370. The conductive film 372 functions as an electrode, that is, one of the electrodes of the liquid crystal element. In this case, it is preferable to use a light-transmitting conductive film. It is preferable to use a material containing one selected from the group consisting of In, zinc (Zn), and tin (Sn).

[0074] The liquid crystal element 375 includes a conductive film 372, a conductive film 374, and a liquid crystal layer 376. 374 is provided on the second flexible substrate 307 side and functions as a counter electrode. The display device 300a shown in FIG. 1 is configured such that a voltage is applied to the conductive film 372 and the conductive film 374 to change the liquid crystal display device 300a. By changing the orientation of the crystal layer 376, light transmission or non-transmission is controlled to display an image. It is possible.

[0075] Although not shown in FIG. 2, the conductive films 372 and 374 have a side that contacts the liquid crystal layer 376. In addition, a polarizing member, a phase difference member, an anti-reflection member, and the like may be provided. Optical members (optical substrates) such as polarizing substrates and phase Circularly polarized light from a differential substrate may also be used. may also be used.

[0076] A spacer 378 is provided between the first flexible substrate 301 and the second flexible substrate 307. The spacers 378 are columnar spacers obtained by selectively etching an insulating film. It is a spacer, and is provided to control the film thickness (cell gap) of the liquid crystal layer 376. The spacer 378 may be a spherical spacer.

[0077] The liquid crystal material that constitutes the liquid crystal layer 376 may be a thermotropic liquid crystal, a low molecular weight liquid crystal, or a high molecular weight liquid crystal. Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials can be in a cholesteric phase, smectic phase, cubic phase, or chromatic phase depending on the conditions. It shows an isotropic phase, an isotropic phase, etc.

[0078] When the in-plane switching system is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the crystalline phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. It has a short response time, is optically isotropic so alignment treatment is not required, and has little viewing angle dependency. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. This prevents electrostatic damage caused by electrostatic discharge, and prevents defects and damage to the liquid crystal display device during the manufacturing process. The loss can be reduced.

[0079] When a liquid crystal element is used as a display element, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fring e Field Switching) mode, ASM (Axially Symmetry ric aligned Micro-cell) mode, OCB (Optical C compensated birefringence mode, FLC (Ferroel etric Liquid Crystal) mode, AFLC (AntiFerro You can use modes such as electric Liquid Crystal.

[0080] Furthermore, normally black type liquid crystal display devices, for example, transparent liquid crystal display devices using a vertical alignment (VA) mode, There are several types of vertical alignment modes, for example: For example, the MVA (Multi-Domain Vertical Alignment) model mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used.

[0081] The display method in the pixel unit 302 may be a progressive method, an interlace method, or the like. In addition, the color elements controlled by pixels when displaying colors are RGB. (R represents red, G represents green, and B represents blue) For example, the R pixel and the G pixel It may be composed of four pixels: a pixel of B and a pixel of W (white). As shown above, two colors of RGB compose one color element, and two different colors are selected depending on the color element. Or you can add one or more colors such as yellow, cyan, magenta, etc. to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but also to monochrome display devices. It can also be applied to a display device.

[0082] Next, a display device 300b using a light-emitting element will be described. 1. This is a cross-sectional view taken along the dashed dotted line A1-A2 in FIG. 1 when a light-emitting element is used. A description that overlaps with the display device 300a using the liquid crystal element described above will be omitted.

[0083] The display device 300b includes a first flexible substrate 301, a first adhesive layer 318a, and a first organic The resin layer 320a, the first insulating film 321a, the first element layer 410, and the second element layer 41 1, a second insulating film 321b, a second organic resin layer 320b, and a second adhesive layer 318b. , and a second flexible substrate 307 are laminated in the above order.

[0084] In FIG. 3, the first element layer 410 includes transistors 350 and 352, insulating films 364, 66, 368, the planarization insulating film 370, the light emitting element 480, the insulating film 430, and the signal line 3 10 and a connection electrode 360. The second element layer 411 also includes an insulating film 334 and a colored The first element layer 410 and the second element layer 411 are also included. The first element layer 41 is sealed by the sealing layer 432 and the sealant 312. The first and second element layers 411 may not include some of the above elements. It may also include elements other than those mentioned above.

[0085] The light-emitting element 480 includes a conductive film 444, an EL layer 446, and a conductive film 448. The device 300b displays an image by emitting light from the EL layer 446 of the light emitting element 480. It can be shown.

[0086] An insulating film 430 is provided on the conductive film 444 on the planarization insulating film 370. The conductive film 444 is provided with a conductive layer having a high reflectivity with respect to light emitted from the EL layer. A conductive film having high light-transmitting properties to light emitted from the EL layer is used as the conductive film 448. As a result, the light-emitting element 480 can have a top-emission structure. A conductive film having a high light-transmitting property is used for the conductive film 444, and a conductive film having a high reflectance for the light is used for the conductive film 448. By using a highly conductive film, the light-emitting element 480 can have a bottom emission structure. In addition, both the conductive film 444 and the conductive film 448 are formed of a conductive film that has high light-transmitting properties. By using this, a dual emission structure can be achieved.

[0087] In addition, the coloring layer 336 is provided at a position overlapping the light-emitting element 480, and the insulating film 430 is provided at a position overlapping the coloring layer 336. A light-shielding layer 338 is provided on the position, the lead wiring portion 311, and the first circuit portion 304. The colored layer 336 and the light-shielding layer 338 are covered with a third insulating film 334. Light-emitting element The space between the insulating film 480 and the third insulating film 334 is filled with a sealing layer 432. Although the colored layer 336 is provided in the example of FIG. 0b, the present invention is not limited to this. For example, when the EL layer 446 is formed by coloring, the colored layer 336 is not provided. A different configuration may also be used.

[0088] In the display device 300b, the adhesive layers 318a and 318b may contain a desiccant. For example, chemical adsorption occurs when oxides of alkaline earth metals (such as calcium oxide and barium oxide) Alternatively, a substance that adsorbs moisture such as zeolite or silica gel can be used. It is also possible to use a substance that absorbs moisture by physical adsorption, such as This can prevent impurities such as moisture from entering the light emitting element 480, improving the reliability of the display device. It can be improved.

[0089] Furthermore, by mixing a filler with a high refractive index (such as titanium oxide) into the sealing layer 432, The light extraction efficiency from the optical element 480 can be improved.

[0090] The adhesive layers 318a and 318b may also have a scattering material that scatters light. For example, the adhesive layers 318a and 318b may contain a mixture of particles with different refractive indexes from the sealing layer 432. The particles function as a light scattering material. The difference in refractive index between the particles is preferably 0.1 or more, more preferably 0.3 or more. As the particles, titanium oxide, barium oxide, zeolite, etc. can be used. Titanium oxide and barium oxide particles are preferred because they have a strong light scattering property. When fluorite is used, it is possible to adsorb water contained in the sealing layer 432 and the like, and the reliability of the light-emitting element is improved. It can improve the performance.

[0091] The first flexible substrate 301 and the second flexible substrate 307 are each made of a highly tough material. This makes it possible to realize a light emitting device that is highly impact resistant and less susceptible to breakage. For example, the first flexible substrate 301 and the second flexible substrate 307 may be organic resin substrates. This results in a display device that is lighter and less likely to break than one that uses a glass substrate as the base material. This makes it possible to achieve this position.

[0092] Furthermore, if a material with high thermal emissivity is used for the first flexible substrate 301, the surface temperature of the display device will Therefore, the damage to the display device and the deterioration of its reliability can be suppressed. The flexible substrate 301 is made of a metal substrate and a layer with high thermal emissivity (for example, a metal oxide or ceramic material). A laminated structure of the above materials may be used.

[0093] Next, a method for manufacturing the display device 300b shown in FIG. 3 will be described with reference to FIGS. 4 and 5. 4 and 5, in order to avoid complication of the drawings, the first element layer 4 shown in FIG. 10 and the second element layer 411 are shown in a simplified form.

[0094] First, a first organic resin layer 320a, a first insulating film 321a, and a A stack of layers including a first element layer 410 and a second element layer 411 is formed in this order (see FIG. 4A).

[0095] Further, on the second substrate 463, a second organic resin layer 320b, a second insulating film 321b, and A stack of a second element layer 411 and a second element layer 412 is formed in this order (see FIG. 4B).

[0096] The first substrate 462 and the second substrate 463 should be made of a material that can withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, and quartz substrates , a sapphire substrate, etc. can be used.

[0097] The first organic resin layer 320a and the second organic resin layer 320b are made of, for example, epoxy resin. , aramid resin, acrylic resin, polyimide resin, polyamide resin, polyamideimide resin An organic resin film such as grease can be used. Among them, polyimide resin has high heat resistance. When a polyimide resin is used, the thickness of the polyimide resin is preferably 3 nm or more. The thickness of the polyimide resin is preferably 500 nm or more and 2 μm or less. It can be formed by a coating method, a dip coating method, a doctor blade method, or the like.

[0098] The first insulating film 321a and the second insulating film 321b may be a silicon oxide film, an oxynitride film, or the like. Silicon film, silicon nitride film, silicon oxynitride film, etc. can be used, and sputtering method The first insulating film 321a can be formed by a CVD method or the like. Diffusion of impurities from the first substrate 462 or the first organic resin layer 320a to the first element layer 410 can be suppressed.

[0099] When forming the first element layer 410, the formation temperature of all components including the transistor 350 The temperature is preferably from room temperature to 300° C. For example, the inorganic The insulating film or conductive film formed from the material is preferably formed at a film formation temperature of 150°C or more and 300°C or less. The temperature is set to be 200° C. or more and 270° C. or less. The insulating film formed by the method is preferably formed at a temperature between room temperature and 100°C. In addition, in the process of forming the transistor 350, for example, a heating step may be omitted. It is also possible.

[0100] The insulating film 430, the conductive film 444, the EL layer 446, and the The conductive film 448 can be formed by the following method.

[0101] The insulating film 430 may be made of, for example, an organic resin or an inorganic insulating material. Examples of organic resins include polyimide resins, polyamide resins, acrylic resins, and siloxanes. Resin, epoxy resin, phenol resin, etc. can be used as the inorganic insulating material. For example, silicon oxide, silicon oxynitride, etc. can be used for the insulating film 430. The method for forming the layer is not particularly limited, and examples thereof include lithography, sputtering, vapor deposition, and droplet ejection. Printing methods (inkjet printing, etc.), printing methods (screen printing, offset printing, etc.) When using lithography, if a photosensitive resin is used, the process of forming the insulating film 430 can be performed easily. can be simplified.

[0102] The conductive film 444 is preferably a metal film that has high reflectivity in visible light. The metal film may be made of, for example, aluminum, silver, or an alloy thereof. The conductive film 444 can be formed by, for example, a sputtering method. do.

[0103] The EL layer 446 is formed by recombination of holes and electrons injected from the conductive film 444 and the conductive film 448. In addition to the light-emitting material, a hole injection layer, a hole transport layer, and the like may be used. Functional layers such as an electron transport layer, an electron injection layer, etc. may be formed as needed. The layer 446 can be formed by, for example, a vapor deposition method or a coating method.

[0104] The conductive film 448 is preferably a conductive film that transmits visible light, for example. The conductive film may be made of, for example, indium (In), zinc (Zn), or tin (Sn). The conductive film 448 may be made of, for example, a material containing one of the selected species. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (ITO), indium zinc oxide, silicon-doped indium tin oxide, etc. In the display device of one embodiment of the present invention, a light-transmitting conductive material can be used. It is preferable to use silicon-doped indium tin oxide for the conductive film 448. When indium tin oxide containing fluorine is used, the bending resistance of the conductive film 448 is improved. The conductive film 448 is formed by using, for example, a sputtering method. It is possible.

[0105] The colored layer 336 of the second element layer 411 is a layer that transmits light in a specific wavelength range. For example, a red (R) color filter that transmits light in the red wavelength band may be used. A green (G) color filter transmits light in the green wavelength band, and a blue (B) color filter transmits light in the blue wavelength band. A blue (B) color filter that transmits light can be used. A color filter of a color (B) or white (W) may be used. Each color filter is made of various materials. It can be printed using printing, inkjet printing, or etching using lithography technology. Each is formed at a desired position.

[0106] The light-shielding layer 338 of the second element layer 411 is a layer that blocks light in a specific wavelength range. It is sufficient that the insulating film has the function of blocking the black pigment. This can be done.

[0107] The third insulating film 434 of the second element layer 411 is made of, for example, acrylic resin. The third insulating film 434 is not necessarily formed. It is not necessary, and a structure in which the third insulating film 434 is not formed may be used.

[0108] Next, the first element layer 410 and the second element layer 411 are bonded together via the sealing layer 432 ( See FIG. 4(C). Note that the sealant 312 is not shown.

[0109] The sealing layer 432 can be made of a flexible solid sealing material. Glass materials such as glass frit, hardening resins that harden at room temperature such as two-component mixed resins, and light Resin materials such as hardening resins and thermosetting resins can be used.

[0110] Next, the first substrate 462 is peeled off from the structure shown in Fig. 4(C) (see Fig. 4(D)). Note that the step of peeling off the second substrate 463 may be performed first.

[0111] The peeling step can be carried out by various methods. For example, 2, the first organic resin layer 320a is irradiated with ultraviolet light 468, weakening the layer 320a or reducing the adhesion between the first organic resin layer 320a and the first substrate 462; By lowering the substrate 462, the first substrate 462 can be peeled off. By adjusting the energy density, the adhesion between the first substrate 462 and the first organic resin layer 320a can be improved. The first substrate 462 and the first organic resin layer 320a are formed in an area where the adhesion is high and an area where the adhesion is low. The ultraviolet light source may be, for example, a 308 nm wavelength ultraviolet light source. It is possible to use an excimer laser that outputs external light. It is also possible to use a high-pressure mercury lamp or UV -LEDs and the like may also be used.

[0112] Excimer lasers are high-power pulse lasers, and the beam is shaped into a linear form using an optical system. By moving the substrate at the irradiation position of the linear laser beam, it is possible to The linear beam can be applied to one of the substrates to be used. If the length is equal to or greater than the side, the entire substrate can be irradiated with laser light by simply moving the substrate in one direction. It is possible.

[0113] Excimer laser devices include those equipped with one laser oscillator as well as those equipped with two or more laser oscillators. In the case of a device equipped with multiple laser oscillators, The laser beams output from each laser oscillator are synchronized and combined in an optical system (heavy By combining the two, a high energy density laser beam can be obtained. For applications in this form, the size of the 8th generation glass substrate (2160mm x 2460mm) or larger is In addition, in a device equipped with multiple laser oscillators, each The laser beams output from each laser oscillator compensate for each other's output variations, so This reduces the variation in strength between the individual wafers, allowing for high-yield processing. Instead of the oscillator, a plurality of excimer laser devices may be used.

[0114] Figure 6 shows an example of a processing device using an excimer laser. The laser beams 610a and 610b output from the laser device 600 are combined by an optical system 630. The laser beam 610c is then expanded horizontally by the optical system 630 and reflected by the mirror 650. The beam is then incident on the lens 670 and reduced to become a linear beam 610d. The beam 610d is irradiated onto the processing area 710 of the workpiece 700 through the substrate 720. Do so.

[0115] In this embodiment, the workpiece 700 has the structure shown in FIG. 4(C) or FIG. 5(A). In the processed region 710, the first organic resin layer 320a or the second organic resin layer 320b, The substrate 720 corresponds to the first substrate 462 or the second substrate 463 .

[0116] Then, by moving the workpiece 700 in the direction of the arrow in the figure, a linear pattern is formed over the entire processing area 710. The excimer laser can emit a beam 610d. It is preferable to use a wavelength of 308 nm or longer. For example, even when a glass substrate is used as the substrate 720, the laser beam required for processing can be sufficiently transmitted. It can be done.

[0117] In this embodiment, the interface between the first substrate 462 and the first organic resin layer 320a Although the peeling method has been exemplified, it is not limited to this. For example, when peeled, the first The separation may be performed so that a part of the organic resin layer 320a remains on the first substrate 462. The peeling may occur at the interface between the organic resin layer 320a and the first element layer 410.

[0118] In addition, the liquid is allowed to penetrate into the interface between the first substrate 462 and the organic resin layer 320a. Alternatively, the first organic resin layer 320a may be peeled off from the substrate 62. The liquid is allowed to penetrate into the interface between the first organic resin layer 320a and the first element layer 410. The element layer 410 may be peeled off. For example, water, a polar solvent, or the like may be used as the liquid. By using this liquid, static electricity generated during peeling can be suppressed. Therefore, electrostatic breakdown of a transistor or the like included in the first element layer 410 can be suppressed. do.

[0119] Next, the first organic resin layer 320a and the first flexible substrate 301 are bonded together using the first adhesive layer 318a. (See Figure 5(A)).

[0120] Next, the second substrate 463 is peeled off using the same method as above, and the second organic resin layer 320b is and the second flexible substrate 307 are bonded to each other using a second adhesive layer 318b (see FIG. 5(B)). .

[0121] Then, the FPC 316 is attached to the connection electrode 360 ​​via the anisotropic conductive film 380. If necessary, an IC chip or the like may be mounted.

[0122] In this manner, the display device 300b shown in FIG. 3 can be fabricated.

[0123] When peeling is performed at the interface between the first organic resin layer 320a and the first element layer 410, 5(C) is obtained. At this time, the display devices 300a and 300b shown in FIGS. In the case of 0b, the organic resin layer 320a is not present.

[0124] In one embodiment of the present invention, a device including a transistor or the like using an oxide semiconductor layer over an organic resin layer A layer is formed, weakening the organic resin layer or reducing the adhesive strength between the organic resin layer and the substrate. In the case of a transistor using polycrystalline silicon, The method includes a laser irradiation step for crystallizing the amorphous silicon. In this case, there will be an area where the temperature is high enough to melt the silicon, even if only for a moment. When an organic resin layer is used as in one embodiment of the present invention, heat is also transferred to the organic resin layer, and degassing Cracks and pits may occur in the inorganic film formed between the transistor and the substrate due to thermal expansion or other factors. In addition, energy is used to suppress the cracks and peeling. - With laser irradiation at a reduced density, polycrystalline silicon with sufficient crystallinity cannot be obtained. It ends up like this.

[0125] On the other hand, in the manufacturing process of a transistor using an oxide semiconductor layer, a high-temperature process is not required. Until the transistors and other components are completed, the organic resin layer is not weakened and stable processes can be carried out. This allows for the production of transistors with high yield and reliability.

[0126] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0127] (Embodiment 2) In this embodiment, a separation device according to one embodiment of the present invention will be described with reference to FIGS. 1, 12, 13, and 14. One aspect of the present invention is a first part of a processed workpiece. a structure capable of holding a workpiece and a stage capable of holding a second workpiece; and a second member, and a second member is wound up while the processed member between the structure and the stage is wound up. For example, the first member is provided with a peeling device as shown in FIG. A) is a laminate other than the second substrate 463 shown in FIG. 2, and the second member is a second substrate 463. It is possible.

[0128] By using the peeling device according to one aspect of the present invention, the processed member can be separated into the first member and the second member with a high yield. The peeling device according to one embodiment of the present invention does not have a complicated configuration, It can handle peeling of a wide range of processed parts.

[0129] The following describes an example of the configuration and operation of a peeling device and a peeling method using the peeling device.

[0130] <Configuration example 1> 7, 8, and 9, the first member 103a is peeled off from the processed member 103, An example of separating the first member 103a and the second member 103b will be shown.

[0131] First, a perspective view of the peeling device immediately before peeling is shown in FIG. 7(A), and a front view is shown in FIG. 7(B). The side view is shown in Figure 7(D).

[0132] The peeling devices shown in FIGS. 7(A), 7(B), 7(C), and 7(D) are The structure 101 has a convex surface. The stage 105 is The support surface faces the support member.

[0133] In Fig. 7(A), Fig. 7(B), Fig. 7(C), Fig. 7(D), the convex surface of the peeling device and the supporting surface A workpiece 103 is disposed therebetween.

[0134] 7(C) and 7(A), (B), and (D) show the structure 101 and the processed member 103. 7A shows a top view of a case where the arrangement of the processed member 103 is different from that of the processed member 103. As shown in the top view of FIG. 7(C), the peeling starts from the corner of the processed member 103. When peeling is started from the side of the processed member 103, peeling is started from the short side. It is preferable to peel the film in the long side direction. This makes it possible to reduce the restriction of conditions such as the rotation speed of the structure. This makes it easier to control the peeling, and the peeling yield can be increased.

[0135] The processed member 103 is in a sheet shape and includes a sheet-shaped first member 103a and a sheet-shaped second member 103b. The first member 103a and the second member 103b are respectively The processed member 103 may be a single layer or a multi-layer. This prevents peeling at the interface between the first member 103a and the second member 103b. This makes it easier to separate.

[0136] If the peeling device has a conveying means, the conveying means conveys the processed member onto the stage 105. 103 may be arranged.

[0137] As shown in the enlarged view of the area surrounded by the two-dot chain line in FIG. 7(D), the convex surface of the structure 101 is processed. A point-like or linear (including solid line, broken line, and frame-like) peeling starting point 102 formed on the member 103 Then, the structure 101 rotates, and the first member 103a is placed on the processed member 103. A force is applied to peel the first member 103a, and the first member 103a peels off from the vicinity of the peeling starting point 102. Then, the processed member 103 is separated into a first member 103a and a second member 103b.

[0138] The structure 101 may have a convex surface, for example, a cylindrical shape (a circular cylinder, a right circular cylinder, an elliptical cylinder, etc.). It can be a structure such as a part of a cylinder, a sphere, or a part of a sphere. For example, a roller such as a drum roller can be used.

[0139] The materials of the structure include metals, alloys, organic resins, etc. The structure has spaces or voids inside. It may have a sinus.

[0140] 10(C) and 10(D) show structures 151 and 152, some of which have convex surfaces. Each of the structure 151 and the structure 152 has a structure in the shape of a part of a cylinder.

[0141] The radius of curvature of the convex surface of the structure is smaller than the radius of curvature of the support surface of the stage 105. The radius of curvature of the can be, for example, 0.5 mm or more and 1000 mm or less. When peeling off the film, the radius of curvature of the convex surface may be 0.5 mm or more and 500 mm or less. Specific examples include 150 mm, 225 mm, and 300 mm. Examples of structures having such a convex surface include those with diameters of 300 mm, 450 mm, or 600 mm. mm rollers. Depending on the thickness and size of the workpiece, the radius of curvature of the convex surface may be The preferred ranges of are variable. Therefore, without being limited thereto, in one embodiment of the present invention, The structure only needs to have a convex surface with a radius of curvature smaller than the radius of curvature of the support surface of the stage 105 .

[0142] When the processed member 103 includes a laminated structure with low adhesion, peeling occurs at the interface with low adhesion. For example, if the processed member 103 is not attached to the organic EL element, the peeling yield may decrease. When the first electrode is included, the first layer is peeled off at the interface between the two layers constituting the EL layer or at the interface between the EL layer and the electrode. It may be difficult to separate the first member 103a from the second member 103b at the interface between them. The curvature radius of the convex surface is set so that peeling can occur at the interface between the first member 103a and the second member 103b. Alternatively, the rotation speed of the structure 101 may be controlled.

[0143] Furthermore, if the curvature radius of the convex surface is too small, the first member 103a wound around the convex surface may contain a large amount of cellulose. Therefore, the radius of curvature of the convex surface must be 0.5 mm or more. preferable.

[0144] In addition, if the radius of curvature of the convex surface is large, the flexibility of materials such as glass, sapphire, quartz, and silicon is low. Therefore, the curvature radius of the convex surface is, for example, For example, it is preferable that the distance is 300 mm or more.

[0145] In addition, if the curvature radius of the convex surface is large, the peeling device will become large, which will limit the installation location. Therefore, the radius of curvature of the convex surface should be, for example, 1000 mm or less. It is preferable that the distance is 500 mm or less, and more preferable that the distance is 500 mm or less.

[0146] At least a portion of the convex surface may be adhesive. For example, a portion or the entire convex surface may be adhesive. Adhesive tape or the like may be attached. Also, as shown in FIG. 10(E), at least a part of the convex surface may be The first member 103a may have an adhesive portion 104. The first member 103a may be attached to the convex surface of the first member 101 by suction.

[0147] The structure 101 and the stage 105 can move in at least one of the following directions: forward and backward, left and right, and up and down. The distance between the convex surface of the structure 101 and the support surface of the stage 105 may be variable. This is preferable because it allows peeling of processed members of various thicknesses. An example in which the stage 105 is movable in the longitudinal direction is shown.

[0148] A member or the like (for example, a processed member 103 or a second member 103b) placed on the stage 105 The holding means for holding the object are suction chuck, electrostatic chuck, mechanical chuck, etc. For example, a porous chuck may be used. The member may be fixed to a cable, heater table, spinner table, or the like.

[0149] Next, a perspective view of the peeling device during peeling is shown in FIG. 8(A), a front view is shown in FIG. 8(B), and a side view is shown in FIG. A side view is shown in FIG. 8(C). A perspective view of the peeling device after peeling is shown in FIG. 9(A). is shown in Figure 9(B) and a side view is shown in Figure 9(C).

[0150] The structure 101 has a rotation axis 109 at its center. The direction of rotation of the structure 101 is shown in FIG. As shown in (C), the structure 101 may be able to rotate in the opposite direction. The rotation axis 109 moves along the groove of the board 107, and the structure moves in the longitudinal direction of the stage 105. The body 101 can move (left and right directions in FIG. 8(C) and FIG. 9(C)).

[0151] As the structure 101 rotates, the first member 103a overlapping the convex surface of the structure 101 is peeled off. The second part is peeled off from the processed member 103 from the vicinity of the separation starting point and wound up on the convex surface. The first member 103a is held by the convex surface of the structure 101, and the stay The second member 103b is held on the base 105.

[0152] In the peeling apparatus according to one embodiment of the present invention, at least one of the stage 105 or the structure 101 By moving the stage 105, the position of the center of rotation of the structure 101 relative to the stage 105 can be moved. In the configuration example 1, an example is shown in which the rotation center of the structure 101 itself moves. Specifically, , while the stage 105 is stationary (or fixed), the structure 101 is While winding up the processed member 103a, the processed member 103 is wound from one end side to the other end side. This shows an example of how it can be moved (rotated).

[0153] The linear velocity of the convex surface of the structure 101 is the movement of the center of rotation of the structure 101 relative to the stage 105. It's more than just speed.

[0154] While applying tension to the first member 103a or the second member 103b, and the second member 103b may be separated.

[0155] As shown by arrow 108 in FIG. 8(C), the first member 103a and the second member 103b are separated. The surface may include a liquid supply mechanism that can supply liquid to the surface.

[0156] The static electricity generated during peeling may adversely affect the elements and the like included in the first member 103a ( It can prevent damage to semiconductor elements due to static electricity. The liquid may be pure water or an organic solvent, and the neutral Alternatively, an alkaline or acidic aqueous solution, or an aqueous solution containing a dissolved salt may be used.

[0157] If the peeling device has a transport means, after peeling, the wafer is transferred onto the stage 105 by the transport means. The second member 103b and the first member 103a wound around the structure 101 are transported. You can put it out.

[0158] Furthermore, as shown in FIGS. 10(A) and 10(B), the structure 101 is further rotated, Even if the sheet-like member 111 placed on the surface 105 is bonded to the first member 103a, good.

[0159] The member 111 may be a single layer or a multilayer. At least a part of the surface in contact with the member 103a has adhesiveness to the member 103a. For example, an adhesive layer may be formed.

[0160] During one rotation of the structure 101, the convex surface may take up the entire first member 103a. This prevents the first member 103a from touching the stage 105 and the first member 103a from This is preferable because it can prevent pressure from being applied by the structure 101 .

[0161] In addition, the first member 103a wound on the convex surface does not come into contact with the stage 105. It is preferable that the substrate is laminated to 111.

[0162] For example, the structure 101 is rotated by a quarter turn, and the first member 103a is wound up so that all of the convex surfaces are wound up. , the structure 101 is rotated three-quarters of a turn, and the structure 101 moves to the vicinity of the end of the member 111; The structure 101 is then rotated by a quarter turn, and the first member 103a is attached onto the member 111. It may be possible.

[0163] Alternatively, after the peeling is completed, the first member 103a wound around the structure 101 is moved to the stage. The distance between the structure 101 and the stage 105 may be adjusted so that the structure 101 does not come into contact with the stage 105 .

[0164] <Configuration example 2> In configuration example 2, the stage moves, and the position of the center of rotation of the structure relative to the stage changes. Specifically, the position of the rotation center of the structure does not move, and the stage moves in the direction of the processing. An example in which the member can move from one end side to the other opposite end side will be shown.

[0165] 11, 12, and 13, the first member 153a is peeled off from the processed member 153. 10 shows an example of separating the first member 153a and the second member 153b.

[0166] First, FIG. 11(A) shows a perspective view of the peeling device immediately before peeling, and FIG. 11(B) shows a front view. and a side view is shown in FIG. 11(C).

[0167] The peeling device shown in FIGS. 11(A), 11(B), and 11(C) includes a structure 151, a stage 155, a support 157, and a conveying roller 158. The structure 151 has a convex surface. The stage 155 has a support surface facing the convex surface. Support 1.

[0168] In Figures 11(A), 11(B), and 11(C), a pressure is applied between the convex surface and the support surface of the peeling device. A construction member 153 is arranged.

[0169] FIG. 11(A) shows a case where peeling starts from the side of the processed member 153, but the same as in the first configuration example, Similarly, peeling may start from a corner of the processed member 153.

[0170] The structure 151, the workpiece 153, and the stage 155 are the same as those of the structure 101 and the workpiece 102 in the first configuration example. Since the same configurations as the workpiece 103 and the stage 105 can be applied, The processed member 153 has a peeling starting point 162 formed therein.

[0171] The support 157 supports a rotation axis 159 of the structure 151. This allows the convex surface of the structure 151 and the stage 155 to be adjusted. The distance between the support surfaces can be variable.

[0172] The transport rollers 158 can move the stage 155. Movement of the stage 155 There are no particular limitations on the means, and a belt conveyor or a transport robot may be used.

[0173] If the peeling device has a conveying means, the conveying means conveys the processed member onto the stage 155. 153 may be placed.

[0174] Next, a perspective view of the peeling device during peeling is shown in FIG. 12(A), and a front view is shown in FIG. 12(B). A side view is shown in FIG. 12(C). A perspective view of the peeling device after peeling is shown in FIG. 13(A). A front view is shown in FIG. 13(B) and a side view is shown in FIG. 13(C).

[0175] The structure 151 has a rotation axis 159 at its center. 12(A), (C), etc., the structure 151 and the conveying roller 158 are The conveying roller 158 may be able to rotate in the opposite direction. The position of the stage 155 and the workpiece 153 on the stage 155 relative to the center of rotation of the stage 155 is (Specifically, it can move left and right in Fig. 12(C) and Fig. 13(C)).

[0176] The first member 153a held by the structure 151 is peeled off from the processed member 153 and formed into a convex surface. While being wound up, the second member 153b is separated from the second member 153b. 153b is retained.

[0177] The convex surface of the structure 151 is placed over the peeling starting point 162 formed on the processed member 153. The rotation of the structure 151 generates a force to peel off the first member 153a from the processed member 153. The first member 153a is peeled off from the vicinity of the peeling starting point 162. The first member 153a peeled off from the second member 103b is wound around the convex surface. The first member 153a is held by the convex surface of the structure 151 and is placed on the stage 155. The second member 153b is held by the second member 153a.

[0178] If the peeling device has a transport means, after peeling, the wafer is transferred onto the stage 155 by the transport means. The second member 153b and the first member 153a wound around the structure 151 are transported. You can put it out.

[0179] As shown in FIGS. 14(A) and 14(B), the structure 151 and the conveying roller 158 By rotating, the sheet-like member 161 arranged on the stage 156 and the first member 1 53a may be attached to the stage 155 on which the processed member 153 was placed. A member 161 may be disposed in the space between the first and second electrodes.

[0180] <Configuration example 3> Another configuration of a delamination device according to one embodiment of the present invention will be described with reference to FIG. 1A and 1B illustrate a configuration and operation of a separation device according to one embodiment of the present invention.

[0181] 15(A-1), 15(B-1) and 15(C-1) show a peeling device according to one embodiment of the present invention. 15(A-2), 15(B-2) and 15(C-3) are schematic diagrams illustrating the side of the device. 15(C-2) is a schematic diagram illustrating the top surface.

[0182] 15A-1 and 15A-2 show a peeling device according to an embodiment of the present invention. 10A and 10B are diagrams illustrating a state in which a step of separating a first member 103a from a substrate 103 is started.

[0183] 15(B-1) and 15(B-2) show a peeling device according to an embodiment of the present invention for peeling a processed member 10. 10 is a diagram illustrating a state in which the first member 103a is being separated from the first member 103a.

[0184] 15(C-1) and 15(C-2) show a peeling device according to an embodiment of the present invention for peeling a processed member 10. 10 is a diagram illustrating a state in which the first member 103a has been completely separated from the first member 103a.

[0185] The peeling device described in the third configuration example of this embodiment has a cylindrical structure 101. The cylindrical structure 101 is in contact with the inner wall of the cylindrical structure 101 and rotates in synchronization with the rotation of the structure 101. The fact that the rotating body 101a can be rotated is the same as that of the peeling device described with reference to FIGS. 7 to 14. The different configurations are detailed here, and similar configurations can be used. The above description is incorporated herein by reference.

[0186] The structure 101 has a cylindrical shape. The structure 101 has a member 101b on its outer periphery. (See Fig. 15(A-1) and Fig. 15(A-2)).

[0187] The member 101b can modify the physical properties of the surface of the structure 101. For example, the adhesiveness can be improved. It can be given to the surface of the structure 101. Or, it can have elasticity that can disperse stress concentrated in the uneven parts. can be applied to the surface of the structure 101.

[0188] For example, rubber, silicone rubber, resin, or natural material can be used for the member 101b.

[0189] In addition, when a joint is formed in the member 101b arranged in the structure 101, The workpiece is fed between the stage 105 and the structure 101 so that the workpiece 3 does not come into contact with the joint portion. do.

[0190] The rotating body 101a is in contact with the inner periphery of the cylindrical structure 101, and the outer periphery of the structure 101 and the stage The processed member 103 is disposed between the plates 105.

[0191] The rotating body 101a is provided so as to be rotatable about a central axis. The roller may be cylindrical or may have gears on its outer periphery.

[0192] When a rotating body 101a having a gear on its outer periphery is used, the gear that meshes with the gear is According to this configuration, the rotor 101a is driven by a driving mechanism, for example. Then, the rotation can be transmitted to the structure 101.

[0193] In the first step, the processed member 103 on which the peeling starting point 102 is formed is placed on the stage 10. 5 and the structure 101 (see FIG. 15(A-1) and FIG. 15(A-2)). In the case where the processed member 103 has a short side and a long side, the peeling starting point 102 is provided at the corner, and the rotating body It is advisable to insert the wire 101a from the corner at an angle of θ from the direction perpendicular to the central axis of the wire 101a. The peeling starts at the peeling starting point 102, and gradually widens, so that the first member 103a and the second member 103b are separated. can be separated.

[0194] In the second step, the separation of the first member 103a and the second member 103b is advanced. (See Figure 15(B-1) and Figure 15(B-2)).

[0195] A liquid supply mechanism indicated by an arrow 108 is used to supply liquid to the first member 103a and the second member 103b. (See FIG. 15(B-1)) For example, the liquid is permeated into the separation surface. Alternatively, liquid may be sprayed on it.

[0196] Water, polar solvents, etc. can be used as the liquid to be penetrated or sprayed. By making the film transparent, it is possible to suppress the effects of static electricity and the like that are generated during peeling. Alternatively, the peeling layer may be melted to separate the film.

[0197] In the third step, the first member 103a and the second member 103b are separated (see FIG. 15). (C-1) and Figure 15(C-2)).

[0198] <Configuration Example 4> Another configuration of a delamination device according to one embodiment of the present invention will be described with reference to FIG. 1A and 1B illustrate a configuration and operation of a separation device according to one embodiment of the present invention.

[0199] 16(A-1), 16(B-1) and 16(C-1) show a peeling device according to one embodiment of the present invention. 16(A-2), 16(B-2) and 16(C-3) are schematic diagrams illustrating the side of the device. 16(C-2) is a schematic diagram illustrating the top surface.

[0200] 16(A-1) and 16(A-2) show a peeling device according to one embodiment of the present invention. 10 is a diagram illustrating a state in which a step of separating a first member 153a from a substrate 153 is started.

[0201] 16(B-1) and 16(B-2) show a peeling device according to an embodiment of the present invention for peeling a processed member 15 10 is a diagram illustrating a state in which the first member 153a is being separated from the first member 153a.

[0202] 16(C-1) and 16(C-2) show a peeling device according to an embodiment of the present invention for peeling a processed member 15 15 is a diagram illustrating a state in which the first member 153a has been completely separated from the first member 153. FIG.

[0203] The peeling device described in the fourth configuration example of this embodiment is a device for peeling a cylindrical structure 101 into a cylindrical shape. The point that is provided in place of the structure 151 is in contact with the inner wall of the cylindrical structure 101 and is The fact that the rotating body 101a that can rotate in synchronization with the rotation of the This is different from the stripping device described with reference to it.

[0204] Also, the point where the structure 101 is fixed and the stage 155 moves is shown in FIG. This is different from the stripping device described.

[0205] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0206] (Embodiment 3) In this embodiment, a structure of a display device and a display element according to one embodiment of the present invention will be described. .

[0207] The display device shown in FIG. 17A includes a region having pixels of a display element (hereinafter referred to as a pixel portion 502). ) and a circuit section (hereinafter referred to as a circuit section) that is disposed outside the pixel section 502 and has a circuit for driving the pixel. a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 506) ) and a terminal portion 507. Note that the configuration may be such that the protection circuit 506 is not provided. good.

[0208] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When the pixel portion 502 and the entire pixel portion 503 are not formed on the same substrate, the pixel portion 502 and the entire pixel portion 503 are formed on the same substrate. (Tape Automated Bonding) good.

[0209] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). A driving circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements The gate driver 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel. 04a), for supplying signals (data signals) for driving the display elements of the pixels. The pixel driver 504 includes a driving circuit such as a circuit (hereinafter referred to as a source driver 504b).

[0210] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via the slave unit 507, and a signal is output. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. The gate driver 504a outputs a pulse signal to a wiring to which a scanning signal is applied (hereinafter , and the scanning lines GL_1 to GL_X). A plurality of gate drivers 504a are provided, and the scanning lines GL_1 to GL_3 are driven by the plurality of gate drivers 504a. Alternatively, the gate driver 504a may control the GL_X separately. However, the gate driver 504 has a function of supplying a may also supply another signal.

[0211] The source driver 504b includes a shift register and the like. Through the slave unit 507, in addition to the signal for driving the shift register, the source of the data signal is also output. The source driver 504b outputs a signal (image signal) to the pixel circuit 504b based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 504b. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of the data signal. The data lines DL_1 to DL_Y are connected to the data lines DL_2 through DL_Y. Alternatively, the source driver 504b may have a function to supply an initialization signal. However, the present invention is not limited to this, and the source driver 504b may supply other signals. It is Noh.

[0212] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a plurality of analog switches to generate a signal. The image signal can be time-divided and output as a data signal. The source driver 504b may be configured as follows.

[0213] Each of the plurality of pixel circuits 501 is supplied with a scanning signal via one of a plurality of scanning lines GL. A pulse signal is input to the data line DL, and a data signal is given to the data line DL through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 04a controls the writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or less than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via the input terminal 504a (n is a natural number equal to or less than Y).

[0214] The protection circuit 506 shown in FIG. 17A is, for example, a gate driver 504a and a pixel circuit 50 1. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The protection circuit 504b is connected to the data line DL, which is the wiring between the protection circuit 504b and the pixel circuit 501. The circuit 506 can be connected to a wiring between the gate driver 504a and the terminal section 507. Alternatively, the protection circuit 506 may be provided on the wiring between the source driver 504b and the terminal section 507. The terminal section 507 can be connected to the display device from an external circuit. This refers to the part where terminals for inputting control signals and image signals are provided.

[0215] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 protects the wiring. It is a circuit that connects a line to another wiring.

[0216] As shown in FIG. 17A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 506. By providing a This can improve the resistance of the display device to overcurrents caused by electrical discharges, etc. However, the configuration of the protection circuit 506 is not limited to this. For example, the protection circuit 506 may be provided in the gate driver 504a. A configuration in which a protection circuit 506 is connected, or a configuration in which a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal section 507. You can also do this.

[0217] In FIG. 17(A), the gate driver 504a and the source driver 504b However, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit (IC chip) prepared separately is not formed. It may also be configured to implement a device such as a

[0218] Note that a display element, a display device which is a device having a display element, a light-emitting element, and a light-emitting element A light-emitting device, which is a device for emitting light, can take various forms or have various elements. An example of a display element, a display device, a light-emitting element, or a light-emitting device is an electroluminescent (EL) device. EL elements (including organic and inorganic materials, organic EL elements, inorganic EL elements) element), LED (white LED, red LED, green LED, blue LED, etc.), transistor transistors that emit light according to the current, electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), Display elements using MEMS (microelectromechanical systems), digital Micromirror Device (DMD), DMS (Digital Micro Shutter), MI RASOL (registered trademark), IMOD (Interference Modulation) element, Shutter-type MEMS display element, optical interference-type MEMS display element, electrowet electro-magnetic devices, such as piezoelectric ceramic displays and carbon nanotubes Display media that change contrast, brightness, reflectance, transmittance, etc. An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductive LCD (Electron-emitter Display) and other LCDs. Examples of display devices include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, etc.). LCD, reflective LCD, direct-view LCD, projection LCD Display devices using electronic ink, electronic liquid powder, or electrophoretic elements An example is electronic paper. Semi-transmissive LCD displays and reflective LCDs When realizing a display, part or all of the pixel electrodes are used as reflective electrodes. For example, a part or all of the pixel electrode may be made of aluminum. In this case, the SRAM may be formed under the reflective electrode. It is also possible to provide a memory circuit such as a memory cell. This can further reduce power consumption. This can be done.

[0219] The plurality of pixel circuits 501 shown in FIG. 17(A) may have the configuration shown in FIG. 17(B), for example. This can be done.

[0220] The pixel circuit 501 shown in FIG. 17B includes a liquid crystal element 570, a transistor 550, and a capacitor. and element 560.

[0221] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential ( A common potential may be applied to the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row. One of the poles may be given a different potential.

[0222] For example, the display device including the liquid crystal element 570 can be driven in TN mode, STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned Mix cro-cell mode, OCB (Optically Compensated B refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. Crystal) mode, MVA mode, PVA (Patterned Ver Artificial Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, the display device can also be driven by an ECB (Electric Carrier Board) or the like. Ally Controlled Birefringence mode, PDLC (P Polymer Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest However, the liquid crystal element and its driving method are not limited to these. A variety of materials can be used.

[0223] In the pixel circuit 501 in the mth row and the nth column, the source electrode or the drain electrode of the transistor 550 One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scan lines GL _m. The transistor 550 can be turned on or off. This has the function of controlling the writing of data of the data signal.

[0224] One of the pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, referred to as a potential supply line VL). and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0225] For example, in a display device having the pixel circuit 501 shown in FIG. 17(B), The pixel circuits 501 in each row are sequentially selected by the gate driver 504a shown in FIG. 50 is turned on to write the data of the data signal.

[0226] The pixel circuit 501 in which the data has been written is maintained by turning off the transistor 550. By repeating this process for each row, an image can be displayed.

[0227] Furthermore, the plurality of pixel circuits 501 shown in FIG. 17(A) may have the configuration shown in FIG. 17(C), for example. It is possible.

[0228] The pixel circuit 501 shown in FIG. 17C includes transistors 552 and 554 and a capacitor element 562 and a light-emitting element 572.

[0229] One of the source and drain electrodes of the transistor 552 is connected to a data signal. The transistor 55 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n). The gate electrode 2 is electrically connected to the wiring to which the gate signal is given (hereinafter referred to as the scanning line GL_m). are connected to the network.

[0230] The transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of

[0231] One of the pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, referred to as a potential supply line VL_ a), and the other is electrically connected to the source electrode and drain electrode of transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0232] The capacitor 562 functions as a storage capacitor for holding written data.

[0233] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. Furthermore, the gate electrode of transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0234] One of the anode and cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b. The other is electrically connected to the other of the source electrode and drain electrode of the transistor 554. To be continued.

[0235] The light emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this, and An inorganic EL element made of an inorganic material may also be used.

[0236] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0237] In a display device having the pixel circuit 501 of FIG. 17(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written into the ON state.

[0238] The pixel circuit 501 in which the data is written is maintained by turning off the transistor 552. Furthermore, the transistor 554 is turned on and off in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 By repeating this process for each row, an image can be displayed.

[0239] For example, in this specification, transistors having various structures are used as transistors. Therefore, there is no limitation on the type of transistor to be used. Examples include transistors with single crystal silicon, or transistors with amorphous silicon, polycrystalline silicon, etc. Silicon, microcrystalline (also called microcrystal, nanocrystal, or semi-amorphous) A transistor having a non-single-crystal semiconductor film, such as a silicon nitride film, can be used. Alternatively, thin film transistors (TFTs) made from these semiconductors can be used. There are various advantages to using TFTs. For example, they are This allows for production at extremely low temperatures, reducing production costs and enabling the use of larger production equipment. Since the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Since a large number of display devices can be manufactured, the manufacturing cost can be reduced. Therefore, a substrate with low heat resistance can be used. Alternatively, a display element can be manufactured using a transistor on a light-transmitting substrate. The thin film of the transistor allows the light transmission to be controlled. A part of the film that forms the star can transmit light, which improves the aperture ratio. It is possible.

[0240] When producing polycrystalline silicon, a catalyst (such as nickel) is used to This will further improve the crystallinity and make it possible to manufacture transistors with good electrical characteristics. As a result, the gate driver circuit (scanning line driver circuit) and the source driver circuit (signal line driver circuit) and signal processing circuits (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) on the board. It can be integrally formed.

[0241] When manufacturing microcrystalline silicon, a catalyst (such as nickel) is used to This further improves the crystallinity, making it possible to manufacture transistors with good electrical characteristics. In this case, the crystallinity can be improved by simply applying heat treatment without laser irradiation. As a result, part of the source driver circuit (analog switch, etc.) and gate The gate driver circuit (scanning line driving circuit) can be formed integrally on the substrate. Therefore, if laser irradiation is not performed, unevenness in the crystallinity of silicon can be suppressed. Therefore, it is possible to display images with improved quality. However, the catalyst (nickel, etc.) It is possible to produce polycrystalline or microcrystalline silicon without using a silicon dioxide.

[0242] In addition, improving the crystallinity of silicon to polycrystalline or microcrystalline allows the entire panel to be It is desirable to perform this in a partial area of ​​the panel, but it is not limited to this. The crystallinity of the crystalline silicon may be improved. For example, the peripheral circuit area, which is an area other than the pixel area, can be selectively irradiated. only in the gate driver circuit and the source driver circuit, or only in the source The laser light is irradiated only on a part of the driver circuit (for example, the analog switch). As a result, silicon crystallization is limited to the area where high-speed circuit operation is required. Since the pixel region does not need to operate at high speed, the crystallinity is Even if the pixel circuit is not improved, it can still operate without any problems. Since the region where the crystallinity needs to be improved is small, the manufacturing process can be shortened. This improves throughput and reduces manufacturing costs. Since fewer manufacturing devices are required, manufacturing costs can be reduced.

[0243] An example of a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). , or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O, Sn-O, Ti-O, Al-Zn-Sn-O, In-Sn-Zn-O, etc. ) or the like. Alternatively, a transistor having these compound semiconductors or Alternatively, a thin film transistor in which these oxide semiconductors are thinned can be used. These allow the manufacturing temperature to be lowered, so that, for example, transistors can be manufactured at room temperature. As a result, it is possible to use a substrate with low heat resistance, such as a plastic substrate or a film substrate. It is possible to form transistors directly on the substrate. Oxide semiconductors are not only used in the channel portion of transistors, but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistor elements, etc. They can be used as a transistor, a pixel electrode, or a light-transmitting electrode. Since it can be deposited or formed simultaneously with the transistor, costs can be reduced.

[0244] An example of a transistor is a transistor formed by an ink-jet method or a printing method. These can be used for manufacturing at room temperature, manufacturing at low vacuum, or Therefore, it can be manufactured without using a mask (reticle). This allows for easy modification of the transistor layout. Alternatively, it can be manufactured without using resist, which reduces material costs and the number of processes. It is also possible to apply the film only to the required areas, so it is possible to reduce the cost of applying the film to the entire surface. This method wastes less material and is less costly than the method of etching afterwards.

[0245] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. These allow transistors to be mounted on flexible substrates. It is possible to form transistors using organic semiconductors and carbon nanotubes. The device used can be shock resistant.

[0246] Note that as the transistor, transistors with various other structures can also be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A MOS type transistor can be used. This allows the size of the transistor to be reduced. It is possible to mount a bipolar transistor. This allows a large current to flow, which allows the circuit to operate at high speed. It is also possible to mix MOS transistors and bipolar transistors on the same substrate. This makes it possible to achieve low power consumption, miniaturization, high-speed operation, etc. come.

[0247] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0248] (Fourth embodiment) In this embodiment, a display module in which the display device of one embodiment of the present invention can be used will be described. Explanations will be given.

[0249] The display module 8000 shown in FIG. 18 is made up of an upper cover 8001 and a lower cover 8002. In between, touch panel 8004 connected to FPC8003, and touch panel 8005 connected to FPC8005 Display panel 8006, backlight 8007, frame 8009, printed circuit board 8010 , has battery 8011.

[0250] The display device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0251] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel. The shape and dimensions can be changed as needed to fit the size of the upper cover. The bar 8001 and the lower cover 8002 may be flexible.

[0252] The touch panel 8004 is a resistive or capacitive touch panel. 8006. In addition, the opposing substrate (sealing substrate) of the display panel 8006 ) can also be equipped with a touch panel function. It is also possible to provide an optical sensor in each pixel of the touch panel to create an optical touch panel. The touch panel 8004 may be flexible.

[0253] The backlight 8007 has a light source 8008. In FIG. Although the configuration in which the light source 8008 is arranged on the 8007 has been exemplified, the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light emitting element such as an organic EL element is used, or when a reflective In the case of a panel or the like, the backlight 8007 may not be provided. The backlight 8007 may be flexible.

[0254] The frame 8009 protects the display panel 8006 and also prevents the operation of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. The frame 8009 may have a function as a heat sink. It may be flexible.

[0255] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. 1 can be omitted if a commercial power supply is used. The printed circuit board 8010 is an FPC. It's okay to have it.

[0256] In addition, the Display Module 8000 adds components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided as follows.

[0257] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0258] (Embodiment 5) In this embodiment, a transistor and a semiconductor device that can be used in a display device of one embodiment of the present invention will be described. The materials constituting the transistor will be described. are the transistors 350, 352, 550, 552, 554, etc., described in the previous embodiments. Note that the transistor described in this embodiment can be transferred onto a flexible substrate. This is the configuration before installation.

[0259] FIG. 19A illustrates an example of a transistor that can be used in a display device that is one embodiment of the present invention. The transistor is formed by an organic resin layer 910 formed on a substrate 900. , an insulating film 915, a gate electrode layer 920, an insulating film 931, and an insulating film 932 are formed in this order. The gate insulating film 930 and the oxide semiconductor layer 940 are connected to a part of the oxide semiconductor layer. The gate electrode layer 950 and the drain electrode layer 960 are connected to each other. The gate insulating film 930, the oxide semiconductor layer 940, the source electrode layer 950, and the drain electrode layer An insulating film 970 , an insulating film 980 , and an insulating film 990 may be formed on the pole layer 960 .

[0260] In addition, as shown in FIG. 19B, the transistor of one embodiment of the present invention includes an insulating film 980 or The conductive layer 990 is formed on the insulating film 990 so as to overlap the gate electrode layer 920 and the oxide semiconductor layer 940. The conductive film may be used as a second gate electrode layer (back gate). By using this, it is possible to increase the on-current and control the threshold voltage. To increase the potential, for example, the gate electrode layer 920 and the conductive film 921 are set to the same potential, and a double gate In order to control the threshold voltage, the gate A constant potential different from that of the electrode layer 920 may be supplied to the conductive film 921 .

[0261] Furthermore, the transistor of one embodiment of the present invention has a channel protection layer as shown in FIGS. Here, the insulating film 933 protects the channel region. Therefore, the insulating film 933 is disposed only in a region overlapping with the channel region. As shown in FIGS. 25(A) and 25(B), they may also be arranged in other areas. It may be done.

[0262] Furthermore, the transistor of one embodiment of the present invention has a self-alignment function as shown in FIGS. In the structure of FIG. 26(A), the source region 9 51 and the drain region 961 are the contacts of the source electrode layer 950 and the drain electrode layer 960. The generation of oxygen defects by contact, and the gate electrode layer 920 is used as a mask to etch away boron, phosphorus, and aluminum. It can be formed by doping with impurities such as fluorine. In the structure of B), the source region 951 and the drain region 961 are doped as described above. Instead, a hydrogen-containing insulating film 9 such as a silicon nitride film is formed so as to be in contact with a part of the oxide semiconductor layer 940. 75 and then diffusing hydrogen into part of the oxide semiconductor layer 940. Cut.

[0263] Furthermore, the transistor of one embodiment of the present invention may have a self-aligned structure as shown in FIG. In the structure of FIG. 27(A), the source region 951 and The source electrode layer 950 and the drain electrode layer 960 are connected to each other. The generation of oxygen defects and the ion implantation of boron, phosphorus, argon, etc. using the gate insulating film 930 as a mask. In the structure of FIG. The source electrode layer 950, the drain electrode layer 960 and the gate electrode layer 920 are formed in the same process. It can be formed in a process.

[0264] Furthermore, the transistor of one embodiment of the present invention may have a self-aligned structure as shown in FIG. In the structure of FIG. 27(B), the source region 951 and The drain region 961 is formed by ion implantation of boron, phosphorus, argon, etc. using the gate insulating film 930 as a mask. In addition to the doping of the impurities, a nitride semiconductor layer is formed in contact with part of the oxide semiconductor layer 940. An insulating film 975 containing hydrogen, such as a silicon dioxide film, is formed to absorb hydrogen into part of the oxide semiconductor layer 940. In this configuration, the lower resistance source region 951 and a drain region 961. Alternatively, the insulating film 975 may not be formed.

[0265] Note that an element that forms oxygen vacancies in the oxide semiconductor layer is used as an impurity (an impurity element). Typical examples of impurity elements are boron, carbon, nitrogen, fluorine, aluminum, Silicon, phosphorus, chlorine, and rare gas elements are examples of rare gas elements. Neon, argon, krypton and xenon.

[0266] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by adding an impurity element, the oxygen vacancies are Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide semiconductor The conductivity of the oxide semiconductor increases and it becomes a conductor. An oxide semiconductor that has become a conductor is called an oxide conductor. Generally, oxide semiconductors have a large energy gap and are therefore resistant to visible light. On the other hand, oxide conductors are oxide semiconductors that have donor levels near the conduction band. Therefore, the influence of absorption by the donor level is small, and the oxidized It has the same level of transparency as semiconductors.

[0267] Here, the resistance of a film formed of an oxide conductor (hereinafter referred to as an oxide conductor layer) The temperature dependency of the rate will be explained with reference to FIG.

[0268] Here, a sample having an oxide conductor layer was prepared. The oxide conductor layer (OC_SiN) formed by the contact of the conductor layer with the silicon nitride film x ), In a doping device, argon is added to the oxide semiconductor layer and the oxide semiconductor layer is in contact with the silicon nitride film. The oxide conductor layer (OC_Ar doped + SiN x ), or Pla In the plasma processing apparatus, the oxide semiconductor layer is exposed to argon plasma, and the silicon nitride film is The oxide conductive layer formed by contacting with the Ar plasma and SiNx ) The silicon nitride film contains hydrogen.

[0269] Oxide conductor layer (OC_SiN x The method for preparing a sample containing the SiO2 is as follows: After forming a silicon oxynitride film with a thickness of 400 nm by plasma CVD, By exposing the silicon oxynitride film to a magnetic field and adding oxygen ions to the film, oxygen is released by heating. Next, a silicon oxynitride film that releases oxygen when heated was formed. A sputtering target with an atomic ratio of In:Ga:Zn=5:5:6 was used on the film. A 100 nm thick In-Ga-Zn oxide film was formed by sputtering, and then heated at 450°C in nitrogen. After heat treatment in a nitrogen atmosphere, it was heat treated in a nitrogen and oxygen mixed gas atmosphere at 450°C. Next, a silicon nitride film with a thickness of 100 nm was formed by plasma CVD. The heat treatment was carried out in a mixed gas atmosphere of nitrogen and oxygen at 0°C.

[0270] Oxide conductor layer (OC_Ar doped + SiN x The method for preparing the sample containing A 400 nm thick silicon oxynitride film is formed on a glass substrate using plasma CVD. After that, the silicon oxynitride film is exposed to oxygen plasma to add oxygen ions to the film. Next, a silicon oxynitride film that releases oxygen by heating was formed. On the silicon oxynitride film, a sputtering tantalum with an atomic ratio of In:Ga:Zn=5:5:6 was deposited. A 100 nm thick In-Ga-Zn oxide film was formed by sputtering using a target. After heat treatment in a nitrogen atmosphere at 450°C, the specimen was placed in a nitrogen and oxygen mixed gas atmosphere at 450°C. Next, the In-Ga-Zn oxide film was subjected to a heat treatment in a doping device. The voltage is 10 kV and the dose is 5 × 10 14 / cm 2 Add argon to In-G Oxygen vacancies were formed in the α-Zn oxide film. Next, a 100 nm thick film was deposited by plasma CVD. A silicon nitride film was formed. Next, the film was heated at 350°C in a mixed gas atmosphere of nitrogen and oxygen. I understood.

[0271] Oxide conductor layer (OC_Ar plasma + SiN x The preparation method for the sample containing A silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate by plasma CVD. After formation, the silicon oxynitride film is exposed to oxygen plasma and released oxygen by heating. Next, a silicon oxynitride film having an atomic ratio of In was formed on the silicon oxynitride film which releases oxygen by heating. :Ga:Zn=5:5:6 sputtering target was used to form a A 100 nm thick In-Ga-Zn oxide film was formed and then heat-treated in a nitrogen atmosphere at 450°C. After that, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450°C. In the device, argon plasma is generated and accelerated argon ions are injected into the In-Ga-Z Next, a 1 mm thick film was prepared by plasma CVD. Next, a silicon nitride film with a thickness of 0.1 nm was formed in a nitrogen and oxygen mixed gas atmosphere at 350°C. It was heat treated in air.

[0272] Next, the resistivity of each sample was measured and the results are shown in Figure 36. Here, the resistivity was measured using a four-terminal In Figure 36, the horizontal axis indicates the measurement temperature, and the vertical axis indicates the The resistivity of the oxide conductor layer (OC_SiNx ) measurement results are shown by squares, and Compound conductor layer (OC_Ar dope+SiN x The measurement results of ) are shown by triangles, and the oxide Electric layer (OC_Ar plasma+SiN x ) measurement results are indicated by circles.

[0273] Although not shown, the oxide semiconductor layer that is not in contact with the silicon nitride film has a high resistivity. Therefore, the oxide conductor layer has a lower resistivity than the oxide semiconductor layer. It is clear that

[0274] As can be seen from FIG. 36, the oxide conductor layer (OC_Ar doped+SiN x ) and acid Compound conductor layer (OC_Ar plasma+SiN x ) contains oxygen vacancies and hydrogen Typically, the resistivity changes little between 80K and 290K. The resistance change is less than ±20% between 150K and 250K. The mobility is less than ±10%. That is, oxide conductors are degenerate semiconductors, and the conduction band edge and It is estimated that the electric potential of the oxide conductor layer is equal to or almost equal to the Elmi level. By using it as the source and drain regions of a transistor, the oxide conductor layer and the source The contact with the conductive film that functions as the source electrode and drain electrode is an ohmic contact, and the oxide The contact resistance between the conductive layer and the conductive film that functions as the source electrode and the drain electrode can be reduced. In addition, since the resistivity of oxide conductors has low temperature dependency, the oxide conductor layer and the source The fluctuation of the contact resistance with the conductive film that functions as the electrode and drain electrode is small, and the reliability is high. It is possible to fabricate a low-cost transistor.

[0275] Furthermore, as shown in FIGS. 28A and 28B, the transistor of one embodiment of the present invention has a gate insulating layer. A conductive film 921 may be provided so as to overlap with the oxide semiconductor layer 940 with the insulating film 935 interposed therebetween. 28(A) and (B), the transistors shown in FIGS. 26(A) and (B) are electrically conductive. 27A and 27B. It can also have 1.

[0276] In the display device of one embodiment of the present invention, an oxide semiconductor is used for an active layer as described above. Transistors using a carbide semiconductor layer have higher mobility than transistors using amorphous silicon. Because of the high capacitance, it is easy to make the transistors smaller, and the pixels can be made smaller. Furthermore, a transistor including an oxide semiconductor layer is highly reliable and suitable for flexible display devices. However, one aspect of the present invention is not limited to this. Depending on the circumstances, the active layer may contain a semiconductor other than an oxide semiconductor.

[0277] As shown in FIGS. 19A and 19B, the width of the gate electrode layer 920 is It is preferable that the width of the layer 940 is larger than that of the layer 940. In a display device having a backlight, The gate electrode layer serves as a light-shielding layer, and the electrical characteristics of the oxide semiconductor layer 940 are reduced when the oxide semiconductor layer 940 is irradiated with light. In addition, in EL display devices, top gate transistors By using a transistor, the gate electrode layer can be used as a light-shielding layer.

[0278] Components of a transistor according to one embodiment of the present invention will be described in detail below.

[0279] The substrate 900 is preferably a rigid substrate in order to facilitate the transfer process to a flexible substrate. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, a metal substrate, etc. The substrate 900 corresponds to the first substrate 462 shown in Embodiment 1. do.

[0280] The organic resin layer 910 may be made of, for example, epoxy resin, aramid resin, acrylic resin, or polyimide. For example, an organic resin film such as a polyamide resin, a polyamideimide resin, or the like can be used. The organic resin layer 910 corresponds to the organic resin layer 320a shown in the first embodiment.

[0281] The insulating film 915 may be, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or A single layer of a silicon nitride oxide film or a laminate of these films can be used. The film 915 corresponds to the first insulating film 321a shown in the first embodiment.

[0282] The gate electrode layer 920 and the conductive film 921 may be made of chromium (Cr), copper (Cu), aluminum (Al), or the like. Aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum ( Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), A metal element selected from iron (Fe) and cobalt (Co), or a material containing the above-mentioned metal elements as a component. The metal layer can be formed by using an alloy of the above metal elements or an alloy combining the above metal elements. The gate electrode layer 920 may have a single-layer structure or a stacked structure of two or more layers.

[0283] The gate electrode layer 920 and the conductive film 921 are formed of indium tin oxide, tungsten oxide, or the like. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide, indium zinc oxide A conductive material having light transmission properties, such as an indium tin oxide material or an indium tin oxide material containing silicon oxide, is used. In addition, the conductive material having the light-transmitting property and the metal element may be laminated. It is also possible to do so.

[0284] In addition, an In—Ga—Zn-based oxynitride semiconductor is formed between the gate electrode layer 920 and the insulating film 932. film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride nitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN , ZnN, etc.) may be provided.

[0285] The insulating films 931 and 932 that function as the gate insulating film 930 are formed by plasma chemical vapor deposition. Product(PECVD:(Plasma Enhanced Chemical Vapor Silicon oxide film, silicon oxynitride film, etc. are formed by deposition, sputtering, etc. film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, hafnium oxide film, acid yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film An insulating layer containing one or more of a sodium film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. The gate insulating film 930 can be formed by using insulating films 931 and 932. Instead of the laminated structure, a single layer insulating film selected from the above materials or an insulating film with three or more layers may also be used.

[0286] Note that the insulating layer in contact with the oxide semiconductor layer 940 which functions as a channel formation region of the transistor The insulating film 932 is preferably an oxide insulating film containing oxygen in excess of the stoichiometric composition. In other words, the insulating film 932 has a region containing oxygen (an oxygen-excess region). The insulating film 932 is an insulating film capable of releasing oxygen. To prevent this, the insulating film 932 may be formed in an oxygen atmosphere, for example. Oxygen may be introduced into the insulating film 932 to form an oxygen-excess region. ion implantation, ion doping, plasma immersion ion implantation, plasma Processing methods etc. can be used.

[0287] Furthermore, when hafnium oxide is used for the insulating films 931 and 932, the following effects are achieved. Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the physical film thickness can be increased relative to the equivalent oxide film thickness, so the equivalent oxide film thickness is set to 10 nm. Even when the thickness is set to 5 nm or less, the leakage current due to the tunnel current must be reduced. That is, a transistor with a small off-state current can be realized. Hafnium oxide with a crystalline structure has a higher specific resistance than hafnium oxide with an amorphous structure. Therefore, in order to make a transistor with a small off-state current, the crystal structure It is preferable to use hafnium oxide having a crystal structure of monoclinic or cubic. However, one embodiment of the present invention is not limited to these.

[0288] In this embodiment, a silicon nitride film is formed as the insulating film 931, and a silicon nitride film is formed as the insulating film 932. The silicon nitride film has a lower dielectric constant than the silicon oxide film. The thickness required to obtain the same capacitance as a silicon oxide film is large, so The gate insulating film 930 of the gate electrode is made thicker by including a silicon nitride film. Therefore, the dielectric strength of the transistor can be improved, and the static electricity of the transistor can be reduced. Destruction can be suppressed.

[0289] The oxide semiconductor layer 940 is typically an In-Ga oxide, an In-Zn oxide, an In-Mn oxide, or an In-GaAs oxide. -Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf In particular, the oxide semiconductor layer 940 may be an In-M-Zn oxide (where M is Al , Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf) are preferably used.

[0290] The oxide semiconductor layer 940 is an In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, Zr, or L). In the case of In-M-Zn oxides (In, Ce, Nd, Sn or Hf), The atomic ratio of the metal elements in the sputtering target preferably satisfies In≧M, Zn≧M. The atomic ratio of the metal elements in such a sputtering target is In:M:Z. n=1:1:1, In:M:Zn=5:5:6, In:M:Zn=3:1:2 are preferred The atomic ratio of the oxide semiconductor layer 940 to be formed is determined by the above-mentioned sputtering method. The atomic ratio of the metal elements contained in the target varies by ±40%. nothing.

[0291] When the oxide semiconductor layer 940 is an In-M-Zn oxide, the The atomic ratio of In to M is preferably 25 atomic % or more for In and 75 atomic % or more for M. mic%, more preferably In is 34 atomic % or more and M is 66 atomic % or more It must be less than %.

[0292] The oxide semiconductor layer 940 has an energy gap of 2 eV or more, preferably 2.5 e V or more, more preferably 3 eV or more. By using a compound semiconductor, the off-state current of a transistor can be reduced.

[0293] The thickness of the oxide semiconductor layer 940 is 3 nm to 200 nm, preferably 3 nm or more. The thickness is set to at most 100 nm, and more preferably at least 3 nm and at most 50 nm.

[0294] In addition, an oxide semiconductor layer with low carrier density is used as the oxide semiconductor layer 940. For example, the oxide semiconductor layer 940 has a carrier density of 1×10 17 pieces / cm 3 The following is preferably is 1 x 10 15 pieces / cm 3 or less, more preferably 1 × 10 13 pieces / cm 3 Below, more preferred Preferably 1 x 10 11 pieces / cm 3 The following applies.

[0295] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the carrier density and impurity of the oxide semiconductor layer 940 are controlled. The material concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. are set appropriately. It is preferable.

[0296] In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component are For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Moreover, silicon forms impurity levels in the oxide semiconductor layer. The impurity levels act as traps and can degrade the electrical characteristics of transistors. It is preferable to reduce the impurity concentration in the semiconductor layer and at the interface with other layers.

[0297] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, In order to achieve this, the impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is But 1×10 17 / cm 3 preferably less than 1 x 10 15 / cm 3 is less than More preferably, 1×10 13 / cm 3 less than 8 × 10 11 / cm 3 less than 1×10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 It means that it is more than that.

[0298] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, SIMS (Secondary Induction Measuring Machine) is used. In the analysis of oxide semiconductors, for example, The silicon concentration at a certain depth in the semiconductor layer or in a certain region of the oxide semiconductor layer is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1 × 1018 atoms / cm 3 It will have a portion that is less than The hydrogen concentration may vary, for example, at a certain depth in the oxide semiconductor layer or at a certain depth in the oxide semiconductor layer. In a region of the body layer, 2 × 10 20 atoms / cm 3 Less than or equal to 5 x 10 1 9 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 Below, further Preferably 5 x 10 18 atoms / cm 3 It shall have the following parts: The nitrogen concentration may be, for example, at a certain depth in the oxide semiconductor layer or at a certain depth in the oxide semiconductor layer. In a certain area, 5×10 19 atoms / cm 3 Less than 5 x 10 18 at oms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Below are some more preferred Or 5 x 10 17 atoms / cm 3 It shall have the following parts:

[0299] In addition, when the oxide semiconductor layer contains crystals, if silicon or carbon is contained at a high concentration, the oxide The crystallinity of the oxide semiconductor layer may be reduced. For example, at a certain depth in the oxide semiconductor layer or in a certain region in the oxide semiconductor layer. In this case, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 less than 1×1018 atoms / cm 3 Less than In addition, for example, at a certain depth of the oxide semiconductor layer, or , in a region of the oxide semiconductor layer, the carbon concentration is set to 1×10 19 atoms / cm 3 less than , preferably 5 x 10 18 atoms / cm 3 less than 1×10 18 at oms / cm 3 It shall have a portion that is less than

[0300] Specifically, the present invention relates to an on-chip transistor using a highly purified oxide semiconductor layer in a channel formation region. The low flicker current can be proven by various experiments. For example, 6 Even if the device has a channel length of 10 μm, the voltage between the source and drain electrodes ( In the drain voltage range of 1V to 10V, the off-state current is Below the measurement limit of the isa, i.e., 1 × 10 -13 A characteristic of less than A can be obtained. In this case, the off-state current normalized by the channel width of the transistor is 100 zA / μm or less. In addition, by connecting the capacitance element and the transistor, the flow into or capacitance The off-state current is measured using a circuit that controls the charge flowing out of the capacitor with the transistor. In this measurement, a highly purified oxide semiconductor layer was used as a channel type transistor. The off-state current of the transistor is calculated from the change in the charge amount per unit time of the capacitor. As a result, when the voltage between the source electrode and the drain electrode of the transistor was 3 V, It was found that an even lower off-state current of several tens of yA / μm can be obtained when Therefore, a transistor using a highly purified oxide semiconductor layer for a channel formation region has an off-state current The current is significantly lower than that of a transistor using crystalline silicon.

[0301] The source electrode layer 950 and the drain electrode layer 960 are formed of a material that extracts oxygen from the oxide semiconductor layer. It is preferable to use a conductive film with good electrical properties. For example, Al, Cr, Cu, Ta, Ti, M O, W, Ni, Mn, Nd, Sc, etc. can be used. In addition, alloys and the like of the above materials can be used. Conductive nitrides of the above materials may also be used. The material may be a laminate of a plurality of materials selected from the group consisting of conductive nitrides of materials. The high melting point of Ti is a key factor in the process, as it can be easily bonded to other metals and the subsequent process temperature can be relatively high. It is more preferable to use W. Also, low-resistivity Cu or Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) or the above materials with Cu or Cu-X alloys A layer of gold may also be used.

[0302] Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) In the case of the insulating film, the coating film is formed in a region in contact with the oxide semiconductor layer or the insulating film by heat treatment. The coating film may be formed from a compound containing X. Examples of compounds containing X include: Examples include X oxide, In-X oxide, Ga-X oxide, In-Ga-X oxide, In -Ga-Zn-X oxides, etc. By forming a coating film, the coating film acts as a blocking film. As a result, it is possible to prevent Cu in the Cu-X alloy film from penetrating into the oxide semiconductor layer. Cut.

[0303] The conductive film has a property of extracting oxygen from the oxide semiconductor layer. The oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed in the oxide semiconductor layer. The oxygen vacancies bond with the corresponding regions, making them significantly n-type. The resulting region can act as the source or drain of a transistor.

[0304] The insulating films 970, 980, and 990 function as protective insulating films. Reference numeral 70 denotes an insulating film that can transmit oxygen. The insulating film 980 also functions as a film for mitigating damage to the oxide semiconductor layer 940 when forming the insulating film 980. do.

[0305] The insulating film 970 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm. Silicon oxide, silicon oxynitride, etc. having a thickness of 1 m or less can be used. In this case, a silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. A silicon nitride oxide film is a film whose composition contains more nitrogen than oxygen. vinegar.

[0306] Furthermore, it is preferable that the insulating film 970 has a small number of defects. , the spin density of the signal appearing at g=2.001 due to the silicon dangling bond is 3×10 17 spins / cm 3 This is because the insulating film 970 contains If the density of defects contained in the insulating film 970 is high, oxygen will bond to the defects, and the amount of oxygen in the insulating film 970 will increase. This is because the amount of transmission decreases.

[0307] The insulating film 980 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition is formed by heating. Heat causes some of the oxygen to be released. Acids containing more oxygen than the stoichiometric composition The oxide insulating film was analyzed by TDS and found to have an oxygen desorption of 1.0 x 10 18 a toms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3 Oxidation The surface temperature of the film during the TDS analysis was 100°C or higher. The temperature is preferably in the range of 00°C or lower, or 100°C or higher and 500°C or lower.

[0308] The insulating film 980 has a thickness of 30 nm to 500 nm, preferably 50 nm to 400 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 00 nm or less can be used.

[0309] Furthermore, it is preferable that the insulating film 980 has a small number of defects. , the spin density of the signal appearing at g=2.001 due to the silicon dangling bond is 1.5×10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 Below The insulating film 980 is preferably made of an oxide semiconductor, as compared with the insulating film 970. Since it is farther away from the layer 940 , it may have a higher defect density than the insulating film 970 .

[0310] In addition, the insulating films 970 and 980 can be made of the same material. It may be difficult to clearly confirm the interface between the insulating film 970 and the insulating film 980. In this embodiment, the interface between the insulating film 970 and the insulating film 980 is shown by a broken line. In the embodiment, the two-layer structure of the insulating film 970 and the insulating film 980 has been described. However, the present invention is not limited to this, and may be embodied in various ways, such as a single layer structure of the insulating film 970, a single layer structure of the insulating film 980, or a three-layer structure. A laminated structure of more than one layer may also be used.

[0311] The insulating film 990 is a blocking material for oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the insulating film 990, oxygen from the oxide semiconductor layer 940 can be removed. This can prevent the diffusion of hydrogen, water, and the like into the oxide semiconductor layer 940 from the outside. For example, a nitride insulating film can be used as the insulating film 990. The insulating film may be silicon nitride, silicon oxynitride, aluminum nitride, or aluminum oxynitride. In addition, blocking elements such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals are Instead of a nitride insulating film with a blocking effect, a film with a blocking effect for oxygen, hydrogen, water, etc. An oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. The films include aluminum oxide, aluminum oxynitride, gallium oxide, and gallium oxynitride. hafnium, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. There is.

[0312] The oxide semiconductor layer 940 may have a structure in which a plurality of oxide semiconductor layers are stacked. For example, as in the transistor illustrated in FIG. 20A, the oxide semiconductor layer 940 may be formed by replacing the first oxide semiconductor layer The first oxide semiconductor layer 941a and the second oxide semiconductor layer 941b may be stacked. The metal oxide semiconductor layer 941a and the second oxide semiconductor layer 941b are formed by using metal oxides having different atomic ratios. may be used. For example, one of the oxide semiconductors containing two types of metals, three types of metals, or four types of metals may be used for one oxide semiconductor layer, and an oxide semiconductor containing two types of metals different from those of the one oxide semiconductor layer, three types of metals, or four types of metals may be used for the other oxide semiconductor layer. For example, one of the oxide semiconductors containing two types of metals, three types of metals, or four types of metals may be used for one oxide semiconductor layer, and an oxide semiconductor containing two types of metals different from those of the one oxide semiconductor layer, three types of metals, or four types of metals may be used for the other oxide semiconductor layer. For example, one of the oxide semiconductors containing two types of metals, three types of metals, or four types of metals may be used for one oxide semiconductor layer, and an oxide semiconductor containing two types of metals different from those of the one oxide semiconductor layer, three types of metals, or four types of metals may be used for the other oxide semiconductor layer. For example, one of the oxide semiconductors containing two types of metals, three types of metals, or four types of metals may be used for one oxide semiconductor layer, and an oxide semiconductor containing two types of metals different from those of the one oxide semiconductor layer, three types of metals, or four types of metals may be used for the other oxide semiconductor layer.

[0313] Also, the constituent elements of the first oxide semiconductor layer 941a and the second oxide semiconductor layer 941b may be the same, and the atomic ratios of the two may be different. For example, the atomic ratio of one oxide semiconductor layer may be In:Ga:Zn = 1:1:1, 5:5:6, or 3:1:2, and the atomic ratio of the other oxide semiconductor layer may be In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1:4:5, Also, the constituent elements of the first oxide semiconductor layer 941a and the second oxide semiconductor layer 941b may be the same, and the atomic ratios of the two may be different. For example, the atomic ratio of one oxide semiconductor layer may be In:Ga:Zn = 1:1:1, 5:5:6, or 3:1:2, and the atomic ratio of the other oxide semiconductor layer may be In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1:4:5, In:Ga:Zn = 1:1:1, 5:5:6, or 3:1:2, and the atomic ratio of the other oxide semiconductor layer may be In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1:4:5, In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6. The atomic ratio of each oxide semiconductor layer includes a variation of plus or minus 20% of the above atomic ratio as an error. 1:6:4, or 1:9:6. The atomic ratio of each oxide semiconductor layer includes a variation of plus or minus 20% of the above atomic ratio as an error. 1:6:4, or 1:9:6. The atomic ratio of each oxide semiconductor layer includes a variation of plus or minus 20% of the above atomic ratio as an error.

[0314] At this time, of one oxide semiconductor layer and the other oxide semiconductor layer, the atomic ratio of In and Ga in the oxide semiconductor layer closer to the gate electrode (channel side) is set to In ≥ Ga (In is greater than or equal to Ga), and the atomic ratio of In and Ga in the oxide semiconductor layer farther from the gate electrode (back channel side) is set to In < Ga, whereby a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic ratio of In and Ga in the oxide semiconductor layer on the channel side to In < Ga and the atomic ratio of In and Ga in the oxide semiconductor layer on the back channel side to In ≥ Ga (In is greater than or equal to Ga), the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test can be reduced. At this time, of one oxide semiconductor layer and the other oxide semiconductor layer, the atomic ratio of In and Ga in the oxide semiconductor layer closer to the gate electrode (channel side) is set to In ≥ Ga (In is greater than or equal to Ga), and the atomic ratio of In and Ga in the oxide semiconductor layer farther from the gate electrode (back channel side) is set to In < Ga, whereby a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic ratio of In and Ga in the oxide semiconductor layer on the channel side to In < Ga and the atomic ratio of In and Ga in the oxide semiconductor layer on the back channel side to In ≥ Ga (In is greater than or equal to Ga), the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test can be reduced. At this time, of one oxide semiconductor layer and the other oxide semiconductor layer, the atomic ratio of In and Ga in the oxide semiconductor layer closer to the gate electrode (channel side) is set to In ≥ Ga (In is greater than or equal to Ga), and the atomic ratio of In and Ga in the oxide semiconductor layer farther from the gate electrode (back channel side) is set to In < Ga, whereby a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic ratio of In and Ga in the oxide semiconductor layer on the channel side to In < Ga and the atomic ratio of In and Ga in the oxide semiconductor layer on the back channel side to In ≥ Ga (In is greater than or equal to Ga), the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test can be reduced. At this time, of one oxide semiconductor layer and the other oxide semiconductor layer, the atomic ratio of In and Ga in the oxide semiconductor layer closer to the gate electrode (channel side) is set to In ≥ Ga (In is greater than or equal to Ga), and the atomic ratio of In and Ga in the oxide semiconductor layer farther from the gate electrode (back channel side) is set to In < Ga, whereby a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic ratio of In and Ga in the oxide semiconductor layer on the channel side to In < Ga and the atomic ratio of In and Ga in the oxide semiconductor layer on the back channel side to In ≥ Ga (In is greater than or equal to Ga), the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test can be reduced. At this time, of one oxide semiconductor layer and the other oxide semiconductor layer, the atomic ratio of In and Ga in the oxide semiconductor layer closer to the gate electrode (channel side) is set to In ≥ Ga (In is greater than or equal to Ga), and the atomic ratio of In and Ga in the oxide semiconductor layer farther from the gate electrode (back channel side) is set to In < Ga, whereby a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic ratio of In and Ga in the oxide semiconductor layer on the channel side to In < Ga and the atomic ratio of In and Ga in the oxide semiconductor layer on the back channel side to In ≥ Ga (In is greater than or equal to Ga), the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test can be reduced. At this time, of one oxide semiconductor layer and the other oxide semiconductor layer, the atomic ratio of In and Ga in the oxide semiconductor layer closer to the gate electrode (channel side) is set to In ≥ Ga (In is greater than or equal to Ga), and the atomic ratio of In and Ga in the oxide semiconductor layer farther from the gate electrode (back channel side) is set to In < Ga, whereby a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic ratio of In and Ga in the oxide semiconductor layer on the channel side to In < Ga and the atomic ratio of In and Ga in the oxide semiconductor layer on the back channel side to In ≥ Ga (In is greater than or equal to Ga), the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test can be reduced. At this time, of one oxide semiconductor layer and the other oxide semiconductor layer, the atomic ratio of In and Ga in the oxide semiconductor layer closer to the gate electrode (channel side) is set to In ≥ Ga (In is greater than or equal to Ga), and the atomic ratio of In and Ga in the oxide semiconductor layer farther from the gate electrode (back channel side) is set to In < Ga, whereby a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic ratio of In and Ga in the oxide semiconductor layer on the channel side to In < Ga and the atomic ratio of In and Ga in the oxide semiconductor layer on the back channel side to In ≥ Ga (In is greater than or equal to Ga), the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test can be reduced. At this time, of one oxide semiconductor layer and the other oxide semiconductor layer, the atomic ratio of In and Ga in the oxide semiconductor layer closer to the gate electrode (channel side) is set to In ≥ Ga (In is greater than or equal to Ga), and the atomic ratio of In and Ga in the oxide semiconductor layer farther from the gate electrode (back channel side) is set to In < Ga, whereby a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic ratio of In and Ga in the oxide semiconductor layer on the channel side to In < Ga and the atomic ratio of In and Ga in the oxide semiconductor layer on the back channel side to In ≥ Ga (In is greater than or equal to Ga), the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test can be reduced.

[0315] In addition, the semiconductor film of the transistor is formed of a first oxide semiconductor layer, a second oxide semiconductor layer, a third oxide semiconductor layer, and a third oxide semiconductor layer. In this case, the first to third oxide semiconductor layers may have a three-layer structure. The constituent elements may be the same, but the atomic ratio of each may be different. The structure of the transistor is shown in FIG. 20(B) and FIG. 29(A) and (B). The structure in which the semiconductor film has a multilayer structure is the same as that of the other transistors shown in this embodiment. This can also be applied to the

[0316] In the transistor type shown in FIG. 20(B) and FIG. 29(A), (B), the third oxide semiconductor The oxide semiconductor layer 942a, the second oxide semiconductor layer 942b, and the first oxide semiconductor layer 942c are They are stacked in order from the gate insulating film side.

[0317] The first oxide semiconductor layer 942c and the third oxide semiconductor layer 942a are made of the following materials: InM 1x Zn y O z (x≧1 (x is 1 or more), y>1, z>0, M1=Ga, Hf, etc.) The second oxide semiconductor layer 942b is made of a material that can be expressed as I nM 2x Zn y O z (x≧1 (x is 1 or more), y≧x (y is x or more), z>0, M2=G Use materials that can be expressed as a formula (e.g., a, Sn).

[0318] The conduction band minimum of the first oxide semiconductor layer 942c and the conduction band minimum of the third oxide semiconductor layer 942a The conduction band minimum of the second oxide semiconductor layer 942b is the deepest from the vacuum level compared to the band minimum. The materials of the first, second, and third oxide semiconductor layers are selected so as to form a well structure. Select as appropriate.

[0319] For example, the first oxide semiconductor layer 942c and the third oxide semiconductor layer 942a are formed in an atomic ratio of 0.1 to 0.2. In:Ga:Zn=1:1:1, 1:3:2, 1:3:4, 1:3:6, 1:4:5, The second oxide semiconductor layer 9 is formed of an oxide semiconductor layer having a ratio of 1:6:4 or 1:9:6. The atomic ratio of 42b is In:Ga:Zn=1:1:1, 5:5:6, or 3:1:2. The insulating film can be formed using an oxide semiconductor layer.

[0320] The first to third oxide semiconductor layers 942c to 942a contain the same constituent elements. Therefore, the second oxide semiconductor layer 942b has a low conductivity at the interface with the third oxide semiconductor layer 942a. In detail, the defect level (trap level) is The defect levels are fewer than those at the interface between the gate insulating film and the third oxide semiconductor layer 942a. Therefore, by stacking oxide semiconductor layers as described above, the transistor This can reduce the amount of variation in threshold voltage due to scaling and reliability testing.

[0321] In addition, the conduction band minimum of the first oxide semiconductor layer 942a and the third oxide semiconductor layer 942c The conduction band minimum of the second oxide semiconductor layer 942b is the deepest from the vacuum level compared to the conduction band minimum of the first oxide semiconductor layer 942b. The first, second, and third oxide semiconductor layers are arranged to form a well structure such that By selecting the appropriate materials, it is possible to increase the field-effect mobility of transistors. Both aim to reduce the amount of variation in threshold voltage due to aging and reliability testing of transistors. can be done.

[0322] In addition, the first to third oxide semiconductor layers 942a to 942c have different crystallinity. An oxide semiconductor having a thickness of at least 100 nm may be used. The oxide semiconductor layer 942b is preferably a crystalline film, and the oxide semiconductor layer 942b has a thickness perpendicular to the surface. It is more preferable that the film is c-axis oriented in the direction.

[0323] In addition, in the channel formation region of the top gate type transistor shown in FIG. The cross section in the channel width direction preferably has a configuration as shown in FIG. The gate electrode layer 920 electrically surrounds the oxide semiconductor layer 940 in the channel width direction. This transistor structure is called a surrounded This is called the channel (s-channel) structure.

[0324] In addition, in the structure having the conductive film 921 as shown in FIGS. When the electrode layer 920 and the conductive film 921 are set to the same potential, as shown in FIG. 35(B), The two may be connected via a contact hole.

[0325] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0326] (Sixth embodiment) In this embodiment, a transistor included in a display device according to one embodiment of the present invention will be described. do.

[0327] The transistors included in the display device of one embodiment of the present invention do not need to have the same structure. For example, a transistor included in a pixel portion of a display device and a driving circuit for driving the pixel portion By using different transistors for the path, appropriate electrical characteristics can be given to each. This makes it possible to improve the reliability of the display device.

[0328] In addition, the transistors included in the driver circuit section have a double gate structure, which reduces the electric field It is also possible to make a transistor with high effective mobility.

[0329] The channel lengths of the transistors included in the driver circuit portion and the pixel portion may be different. In practice, the channel length of the transistor 194 included in the driving circuit section is set to less than 2.5 μm. On the other hand, the transistor included in the pixel portion can be set to a thickness of 1.45 μm or more and 2.2 μm or less. The channel length of the resistor 190 is set to 2.5 μm or more, or 2.5 μm or more and 20 μm or less. It is possible.

[0330] The channel length of the transistor included in the driving circuit section is set to less than 2.5 μm, preferably 1.4 By making the size between 5 μm and 2.2 μm, the current is reduced compared to the transistors included in the pixel area. It is possible to increase the field effect mobility and increase the on-current. A driver circuit portion capable of high-speed operation can be manufactured.

[0331] In addition, the high field effect mobility of the transistors included in the driver circuit section allows for the number of input terminals to be reduced. It can be reduced.

[0332] FIG. 30 shows a transistor included in the pixel portion of the liquid crystal display device shown in FIG. 2. The transistor shown in FIG. 29(A) is used as a transistor included in the driver circuit portion. 31 shows an example of applying a transistor to the EL display device shown in FIG. This is an example in which different transistors are used in the pixel section and the driver circuit section. As the transistor, the transistors shown in FIG. 26(B), FIG. 27(A), and FIG. 27(B) are used. The transistors included in the driver circuit section can also be the transistors shown in FIG. 27(A) and 27(B), and the transistor having a multilayer structure of oxide semiconductor layers shown in FIGS. can also be applied.

[0333] The transistors included in the pixel section receive light from the backlight or EL element. For example, the atomic ratio of In:Ga:Zn=1:1:1 The oxide semiconductor layer formed by sputtering using the material as a target is used as a channel formation region. By using the compound semiconductor in the region, a transistor having high reliability against light irradiation can be formed.

[0334] On the other hand, transistors included in the drive circuit section are desired to have high field-effect mobility. In addition to the above-mentioned configuration, for example, a material having an atomic ratio of In:Ga:Zn=3:1:2 can be used. The oxide semiconductor layer formed by sputtering using a material as a target is used for the channel formation region. By doing so, a transistor with high field effect mobility can be formed.

[0335] In this embodiment, the oxide semiconductor layer of one of the transistors has a stacked structure. A method for easily fabricating two types of transistors on the same substrate is shown in Figure 32 and Figure 33. 33 is used in the pixel portion. 1 illustrates a cross section in the channel length direction of a transistor A having a similar configuration to the transistor (A). Also, on the right side of the drawing, the transistor shown in FIG. 29(A) is used as a transistor in the driving circuit section. 1 shows an example of a cross section in the channel length direction of a transistor B having a similar configuration to that of the transistor B. The common symbols for transistors A and B are assigned to only one of them. The method for manufacturing a transistor described in this embodiment includes the steps of forming a transistor on a flexible substrate described in Embodiment 1. This includes a method for fabricating elements (such as organic resin layers) for transposition.

[0336] The substrate 900 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, it is possible to use a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On In) It is also possible to use a silicon insulator substrate, and semiconductor elements are mounted on these substrates. The one provided may be used.

[0337] The organic resin layer 910 may be made of, for example, epoxy resin, aramid resin, acrylic resin, or polyimide. For example, an organic resin film such as a polyamide resin, a polyamideimide resin, or the like can be used. Among these, polyimide resin is preferred because of its high heat resistance. In this case, the thickness of the polyimide resin is 3 nm or more and 20 μm or less, preferably 500 nm or more and 200 μm or less. The polyimide resin can be applied by spin coating, dip coating, doctor blade coating, etc. It can be formed by a braiding method or the like.

[0338] The insulating film 915 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a nitride oxide film. A silicon nitride film or the like can be used, and can be formed by a sputtering method, a CVD method or the like.

[0339] The insulating layer 935 is formed by a method such as plasma CVD or sputtering, and is made of aluminum oxide, oxide Magnesium, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, acid yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide insulating films such as tantalum oxide, silicon nitride, silicon nitride oxide, aluminum nitride, The insulating film is made of a nitride such as aluminum, nitride oxide, or a mixture of the above materials. Alternatively, the insulating film may be a stack of the above materials, and may include at least an oxide semiconductor layer. The upper layer in contact with the oxide semiconductor layer is formed of a material containing excess oxygen that can supply oxygen to the oxide semiconductor layer. It is preferable to do so.

[0340] The insulating layer 935 may be formed by ion implantation, ion doping, plasma immersion ion implantation, or the like. Oxygen may be added by implantation, plasma treatment, or the like. By adding the insulating layer 935, oxygen can be more easily supplied from the insulating layer 935 to the oxide semiconductor layer. It is possible.

[0341] Note that the surface of the substrate 900 is an insulator, and the influence of impurity diffusion into an oxide semiconductor layer to be formed later is small. If there is no influence, the insulating layer 935 may not be provided. As shown in the example of (B), a conductive film 921 is formed on an insulating film 915, and an insulating film is formed on the conductive film. A border layer 935 may be formed.

[0342] Next, a first oxide semiconductor layer 942 of the driver circuit transistor is formed over the insulating layer 935. a first oxide semiconductor film 940c which becomes a second oxide semiconductor layer 942b; The nitride semiconductor film 940b is formed by sputtering, CVD, MBE, or the like.

[0343] Next, a resist mask 801 is formed in the driver circuit region using lithography (FIG. 32). Then, the first oxide semiconductor film 940c and the second oxide semiconductor film 940d are formed using the resist mask. The second oxide semiconductor film 940b is selectively etched to form the first oxide semiconductor layer 942c. and a second oxide semiconductor layer 942b are formed (see FIG. 32B).

[0344] Next, a third oxide semiconductor film to be the third oxide semiconductor layer 942a was formed so as to cover the stack. 940a is deposited.

[0345] The first oxide semiconductor film 940c, the second oxide semiconductor film 940b, and the third oxide semiconductor film The conductive film 940a can be made of the material described in the fifth embodiment. In this example, for example, the first oxide semiconductor film 940c and the third oxide semiconductor film 940 In a, In-Ga-Zn oxide with In:Ga:Zn=1:1:1 [atomic ratio], second oxide The compound semiconductor film 940b is formed of In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=3:1:2. Note that the first oxide semiconductor film 940c, the second oxide semiconductor film 940b, The atomic ratios of the oxide semiconductor film 940a and the oxide semiconductor film 940b are calculated by adding the above atomic ratios as an error. Also, if sputtering is used for film formation, the above The material can be used as a target for film deposition.

[0346] The first oxide semiconductor film 940c, the second oxide semiconductor film 940b, and the third oxide semiconductor film The oxide semiconductor that can be used for the oxide semiconductor film 940a is at least indium It is preferable that the material contains In or zinc (Zn). Alternatively, the material contains both In and Zn. Furthermore, it is preferable to reduce variations in electrical characteristics of transistors using the oxide semiconductor. It is preferable to include a stabilizer therewith to reduce the strain on the bearing.

[0347] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, other stabilizers The lanthanides are lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0348] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. , Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0349] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0350] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It refers to a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and A material expressed by the formula (n is an integer) may be used.

[0351] However, the second oxide semiconductor film 940b is a first oxide semiconductor film 940c and a third oxide semiconductor film 940d. A material having a larger electron affinity than the compound semiconductor film 940a is selected.

[0352] Note that the oxide semiconductor film is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used. The uniformity of the film thickness distribution, film composition distribution, or crystallinity distribution of the oxide semiconductor film is improved. To achieve this, it is preferable to use DC sputtering or AC sputtering rather than RF sputtering. stomach.

[0353] The second oxide semiconductor film 940b is formed by the first oxide semiconductor film 940c and the third oxide semiconductor film 940b. The indium content of the oxide semiconductor film 940a is preferably higher than that of the oxide semiconductor film 940b. The s orbital of the heavy metal contributes to carrier conduction, and by increasing the In content, Therefore, the oxides with a composition where In is more abundant than Ga have a composition where In is more abundant than Ga. The mobility is higher compared to oxides with a composition equal to or less than a. By using oxide with a high indium content in the transistor formation region, a high mobility transistor can be achieved. This can be realized.

[0354] After the third oxide semiconductor film 940a is formed, first heat treatment may be performed. The treatment is carried out at a temperature of 250°C to 650°C, preferably 300°C to 500°C. This can be done in an active gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or under reduced pressure. In addition, the atmosphere of the first heat treatment is an inert gas atmosphere, and then the desorbed oxygen is removed. The first heat treatment may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas to compensate for the oxygen. As a result, the crystallinity of the first to third oxide semiconductor films 940c to 940a is improved. The insulating layer 935 and the first to third oxide semiconductor films 940c to 940d are Impurities such as hydrogen and water can be removed from the solid film 940a. The etching may be performed after etching the third oxide semiconductor film 940a, which will be described later.

[0355] Next, a resist mask 802 is formed in the pixel region by lithography. The mask 803 is used to cover the first oxide semiconductor layer 942c and the second oxide semiconductor layer 942d in the driver circuit region. The insulating layer 942 is formed on a stack of the organic semiconductor layer 942b (see FIG. 32(C)).

[0356] Next, the third oxide semiconductor film 940a is selectively etched using the resist mask. The first oxide semiconductor layer 943a is formed in the pixel region. The oxide semiconductor layer 942c, the second oxide semiconductor layer 942b, and the third oxide semiconductor layer 942 A laminate consisting of a is formed (see FIG. 32(D)).

[0357] Next, a first conductive film is formed over the oxide semiconductor layer 943a and the above stack. The films include Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and A single layer or a laminate of a material selected from the group consisting of the above-mentioned metallic materials and alloys thereof can be used.

[0358] Next, a resist mask is formed on the first conductive film, and the first conductive film is formed using the resist mask. The source electrode layer 950 and the drain electrode layer 960 are formed by selectively etching the electrode layer. At this time, the oxide semiconductor layer 943a and the first oxide Part of the stack of the semiconductor layer 942c to the third oxide semiconductor layer 942a becomes n-type.

[0359] Next, a gate insulating film 930 is formed so as to cover the pixel region and the driving circuit region (FIG. 33 (See (B)). The gate insulating film 930 is made of aluminum oxide, magnesium oxide, silicon oxide, etc. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, gallium oxide Al, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, halide oxide The gate insulating film 930 can be made of fluorine, tantalum oxide, or the like. The gate insulating film 930 may be formed by a method such as sputtering, CVD, or MBE. It can be formed by using a method such as the above.

[0360] Next, a second conductive film that will become the gate electrode layer 920 is formed on the gate insulating film 930. Conductive films include Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, and Ag. , Mn, Nd, Sc, Ta and W can be used as single layers, laminates or alloys. The conductive film can be formed by a sputtering method, a CVD method, or the like. The film may be a conductive film containing nitrogen, and the product of the conductive film and the nitrogen-containing conductive film may be Layers may also be used.

[0361] Next, a resist mask is formed over the second conductive film, and the second conductive film is The conductive film is selectively etched to form a gate electrode layer 920 .

[0362] Next, the oxide semiconductor layer 943a and the first to third oxide semiconductor layers 942c to 942d are formed. The semiconductor layer 942a is a stack of a source electrode layer 950, a drain electrode layer 960, and a gate electrode layer 962. The region not covered with the electrode layer 920 is doped with impurities 810 to make it n-type, and the source region 95 1 and a drain region 961 are formed (see FIG. 33(C)).

[0363] The impurity addition method includes ion implantation, ion doping, plasma imaging, and the like. The method may be a ion implantation method, a plasma treatment method, or the like. The impurity is added by selectively etching the gate insulating film 930 using the gate electrode layer 920 as a mask. This can also be done after chipping.

[0364] Examples of impurities that increase the conductivity of the oxide semiconductor layer include phosphorus, arsenic, antimony, and fluorine. Uron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon Selected from the group consisting of non-, indium, fluorine, chlorine, titanium, zinc, and carbon One or more may be used.

[0365] When a rare gas is added to an oxide semiconductor layer as an impurity element, the metal element in the oxide semiconductor layer The bond between oxygen and the oxide semiconductor film is broken, and oxygen vacancies are formed. The vacancies interact with hydrogen that remains in the oxide semiconductor layer or is added later, and the oxide semiconductor Specifically, hydrogen enters the oxygen vacancies in the oxide semiconductor film, and the conductivity of the conductor layer increases. This generates electrons, which act as carriers, resulting in higher electrical conductivity.

[0366] In FIG. 33C, the gate electrode layer 920 and the source electrode The width of the region that does not overlap with the layer and the drain electrode layer, the so-called offset region, is less than 0.1 μm. In this case, the doping of the above impurities is not necessary. When the thickness is less than 1 μm, the difference in the on-current of the transistor with and without impurity doping is becomes extremely small.

[0367] Next, insulating films 970, 980 and 990 are formed on the gate insulating film 930 and the gate electrode layer 920. Then, an insulating film 990 is formed (see FIG. 33(D)).

[0368] The insulating film 970 and / or the insulating film 980 may be formed by ion implantation, ion doping, Oxygen is introduced using plasma immersion ion implantation, plasma treatment, etc. By adding oxygen, the insulating film 970 and / or the insulating film 9 80 to the oxide semiconductor layer 943a and the first to third oxide semiconductor layers 942c to 942d. This makes it easier to supply oxygen to the stack of compound semiconductor layers 942a.

[0369] Next, a second heat treatment may be performed under the same conditions as the first heat treatment. By the second heat treatment, the insulating layer 935, the insulating film 970, and the insulating film 98 Excess oxygen is easily released from the oxide semiconductor layer 943a and the first oxide semiconductor layer 943b. By reducing oxygen vacancies in the stack of the conductor layer 942c to the third oxide semiconductor layer 942a, This can be done.

[0370] In addition, a transistor having the same structure as the transistor in FIG. 26(B) is used as a transistor in a pixel portion. The transistor C is used as the transistor for the driver circuit. FIG. 34 shows a manufacturing method of a transistor D having a similar structure to that of the transistor D.

[0371] First, the same steps as in the manufacturing method of the transistor described above are performed up to the step shown in FIG. 33(B). Then, a gate electrode layer 920 is formed (see FIG. 34(A)).

[0372] Next, the gate insulating film 930 is etched using the gate electrode layer 920 as a mask (FIG. 34 (See (B)).

[0373] Next, a silicon nitride film, an aluminum nitride film, or the like is formed so as to be in contact with part of the oxide semiconductor layer 940. An insulating film 975 containing hydrogen is formed, and hydrogen is diffused into part of the oxide semiconductor layer 940 (FIG. The diffused hydrogen bonds with oxygen vacancies in the oxide semiconductor layer 940 and forms doped oxide. Therefore, it is possible to form a low-resistance source region 951 and a low-resistance drain region 961. In the structure of FIG. 34C, the oxide semiconductor layer is doped with the above-described impurities. You may also use the

[0374] Next, an insulating film 970, an insulating film 980, and an insulating film 990 are formed on the insulating film 975 (FIG. 34(D)).

[0375] Through the above steps, a transistor having an oxide semiconductor layer with a stacked structure and a transistor having a single-layer structure A transistor including an oxide semiconductor layer can be easily formed over the same substrate. It has a pixel section that is capable of high-speed operation, has little deterioration due to light irradiation, and has excellent display quality. A display device can be fabricated.

[0376] The various films described in this embodiment, such as a metal film, a semiconductor film, and an inorganic insulating film, are typically The film can be formed by sputtering or plasma CVD, but other methods, such as thermal It may be formed by a CVD (Chemical Vapor Deposition) method. An example of a thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). Al Vapor Deposition (ALD) and Atomic Layer Deposition (ALD) There are methods such as the holomorphic deposition method.

[0377] The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0378] In the thermal CVD method, the source gas and oxidant are simultaneously fed into the chamber. By reacting the material near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0379] In the ALD method, the chamber is kept at atmospheric or reduced pressure, and the source gases for the reaction are sequentially introduced. The film may be formed by repeating the gas introduction sequence. , by switching between the respective switching valves (also called high-speed valves), two or more types of raw materials can be The gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. At the same time as or after the second gas, an inert gas (argon, nitrogen, etc.) is introduced. If an inert gas is introduced at the same time, the inert gas acts as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. In addition, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later, forming a thin film. This gas introduction sequence is controlled and repeated several times until the desired thickness is achieved. The thickness of the thin film can be adjusted by repeating the gas introduction sequence. The thickness can be precisely adjusted by changing the number of repetitions, and fine F It is suitable for producing ET.

[0380] The thermal CVD method such as the MOCVD method or the ALD method can be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga -ZnO X When forming a (X>0) film, trimethylindium, trimethylgallium In addition, the chemical formula of trimethylindium is , In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. The combination is not limited to the above, and triethylgallium (chemical formula Ga(C2 H5)3) can be used instead of dimethyl zinc, and diethyl zinc (chemical formula Zn(C2 H5)2) can also be used.

[0381] For example, when forming a hafnium oxide film using a film formation device that uses ALD, the solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrakis The raw material gas is vaporized trimethylsilyl dimethylamidohafnium (TDMAH) and oxidized Two types of gases are used: tetrakisdimethylamidohafnium (O3) and tetrakisdimethylamidohafnium (TDMHA). The chemical formula is Hf[N(CH3)2]4. Other material liquids include tetrakis(ethoxy) Examples include (trimethylamido) hafnium.

[0382] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, the solvent A liquid containing an aluminum precursor compound (e.g., trimethylaluminum TMA) is vaporized. Two types of gases are used: the source gas and H2O as an oxidizing agent. The chemical formula of ammonium is Al(CH3)3. Other material liquids include tris(dimethylammonium) Aluminum tris(2,2,2-triisobutylaluminum), aluminum ... 6,6-tetramethyl-3,5-heptanedionate).

[0383] For example, when forming a silicon oxide film using a film forming device that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0384] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing WF6 and B2H6 gases. The tungsten film is formed by simultaneously introducing B2H6 gas and H2 gas. Alternatively, SiH4 gas may be used.

[0385] For example, an oxide semiconductor film, such as In-Ga-ZnO, can be formed using a film formation device that uses ALD. X When forming a (X>0) film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form an In-O layer. Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. A mixed compound layer such as a Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed. In addition, H2O gas obtained by bubbling an inert gas such as Ar instead of O3 gas However, it is preferable to use O3 gas that does not contain H. In(CH3) In place of the gas In(C2H5)3, gas Ga(CH3)3 may be used. Alternatively, Ga(C2H5)3 gas may be used. That's fine.

[0386] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0387] (Embodiment 7) In this embodiment, an oxide semiconductor that can be used for a transistor according to one embodiment of the present invention will be described. The conductive film will now be described.

[0388] <Structure of oxide semiconductors> The structure of an oxide semiconductor will be described below.

[0389] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" means that two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0390] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0391] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Examples of the oxide semiconductor include conductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors.

[0392] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0393] <caac-os> First, let me explain about CAAC-OS. The oxide semiconductor with aligned nanocrystals is called It is also possible.

[0394] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0395] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by a combined analysis image (high resolution) When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly identify the CAAC-OS. It can be said that the decrease in electron mobility caused by this is unlikely to occur.

[0396] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration correction function was used to obtain a high-resolution TEM image. In particular, it is called a Cs-corrected high-resolution TEM image. This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Nippon Denshi Co., Ltd. This can be done.

[0397] FIG. 21(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 21(A). From Figure 21(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). The surface reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0398] As shown in Figure 21(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 21(B) and Figure 21(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the pellets are It can be seen that the size of the gap caused by the tilt is about 0.8 nm. The rheotomes can also be called nanocrystals (nc).

[0399] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 21(D)). The inclination between the pellets observed in FIG. 21(C) The location where the crack occurs corresponds to the area 5161 shown in FIG. 21(D).

[0400] In addition, Fig. 22(A) shows the Cs of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in Figure 22(A). Enlarged Cs-corrected high-resolution TEM images are shown in Fig. 22(B), Fig. 22(C), and Fig. 22(D), respectively. 22(D). From Fig. 22(B), Fig. 22(C) and Fig. 22(D), the pellet It can be seen that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0401] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When structural analysis is performed using the out-of-plane method, the results are as shown in Figure 23(A). A peak may appear at a diffraction angle (2θ) of around 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0402] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31° In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the center of the crystal grains indicate that some of the CAAC-OS grains do not have a c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0403] On the other hand, in-plan X-ray irradiation is performed on the CAAC-OS in a direction approximately perpendicular to the c-axis. When structural analysis is performed using the e method, a peak appears at 2θ around 56°. This peak is due to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 23(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in Figure 23(C). Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0404] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 40(A) is generated. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, electron diffraction also reveals The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately on the surface to be formed or on the upper surface. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in Figure 40(B). (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also reveals It is clear that the a-axis and b-axis of the pellets contained in the CAAC-OS do not have any orientation. The first ring in FIG. 40(B) is the (010) plane of the InGaZnO4 crystal. The second ring in Figure 40(B) is thought to be due to the (100) plane. This is thought to be due to the (110) plane.

[0405] CAAC-OS is an oxide semiconductor with a low density of defect states. Examples of defects include impurity-induced defects and oxygen vacancies. C-OS can also be considered an oxide semiconductor with a low impurity concentration. It can also be said that the oxide semiconductor has few oxygen vacancies.

[0406] Impurities contained in an oxide semiconductor can act as carrier traps or carrier generation sources. In addition, oxygen vacancies in oxide semiconductors can become carrier traps or trap water. By capturing atoms, they can become a carrier generation source.

[0407] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0408] In addition, oxide semiconductors with low defect state density (few oxygen vacancies) can reduce carrier density. Such an oxide semiconductor can be obtained by using a high-purity intrinsic or substantially high-purity intrinsic oxide. CAAC-OS has a low impurity concentration and a low density of defect states. It is easy to obtain a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. The C-OS transistor has electrical characteristics that make the threshold voltage negative (normal Also, it is rare for the acid to become pure or substantially pure. The oxide semiconductor has fewer carrier traps. The charge takes a long time to be released and behaves like a fixed charge. Therefore, transistors using oxide semiconductors with high impurity concentrations and high defect state densities are On the other hand, transistors using CAAC-OS may have unstable electrical characteristics. The resulting transistor has little fluctuation in electrical characteristics and is highly reliable.

[0409] In addition, because the density of defect states in CAAC-OS is low, the capacitance generated by light irradiation can be reduced. Therefore, the CAAC-OS transistor is less likely to be captured by the defect level. The electrical characteristics of the transistors are less affected by irradiation with visible light or ultraviolet light.

[0410] <Microcrystalline oxide semiconductor> Next, a microcrystalline oxide semiconductor will be described.

[0411] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a region in which no clear crystal part can be identified. The crystal part contained in the crystal is 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals of 1 nm to 10 nm or 1 nm to 3 nm are often present. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline nc-OS is called a high-resolution In TEM images, the grain boundaries may not be clearly visible. Therefore, in the following, we will refer to the pellets in nc-OS as the origin of the pellets. The crystalline part of S is sometimes called a pellet.

[0412] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The atomic arrangement is periodic in the region of less than 100 nm. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD device that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peak is detected. Also, for nc-OS, the probe diameter (e.g., When electron diffraction (also called selected area electron diffraction) is performed using an electron beam of, for example, 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size When nanobeam electron diffraction is performed on nc-OS, spots are observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. Multiple spots may be observed within a patchy area.

[0413] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, and therefore, nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0414] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower defect state density than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. The defect level density is higher than that of AC-OS.

[0415] <Amorphous oxide semiconductor> Next, the amorphous oxide semiconductor will be described.

[0416] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0417] In amorphous oxide semiconductors, no crystalline parts can be observed in high-resolution TEM images.

[0418] When structural analysis is performed on amorphous oxide semiconductors using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes are detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. However, when nanobeam electron diffraction is performed, no spots are observed, and only a halo pattern is observed. It is measured.

[0419] There are various views on amorphous structures. For example, A structure that does not have a crystal structure is called a completely amorphous structure. Also, the distance between the nearest neighboring atoms or the second nearest neighboring atoms is called A structure that has order but no long-range order is sometimes called an amorphous structure. Therefore, according to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called an amorphous semiconductor. Furthermore, at least oxides with long-range order cannot be called semiconductors. The semiconductor cannot be called an amorphous oxide semiconductor. For example, CAAC-OS and nc-OS can be used as amorphous oxide semiconductors or completely amorphous oxides. It cannot be called a compound semiconductor.

[0420] <Amorphous-like oxide semiconductor> Note that an oxide semiconductor may have a structure between an nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called

[0421] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portions can be identified.

[0422] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0423] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Prepare CAAC-OS (referred to as sample B) and CAAC-OS (referred to as sample C). The sample is also an In-Ga-Zn oxide.

[0424] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all of the samples have crystalline parts.

[0425] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0426] Figure 41 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of eOS grows in size according to the cumulative amount of electron irradiation. As shown in Figure 41 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was sized at 4.2 × 10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the crystals grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 41, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. You will realize something.

[0427] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC-O. It can be seen that the structure is unstable compared to S.

[0428] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC is 78.6% or more and less than 92.3% of that of the original. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0429] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0430] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, the density equivalent to a single crystal of the desired composition is estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0431] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide. The film may be a stacked film containing two or more of a semiconductor and a CAAC-OS.

[0432] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0433] FIG. 42(A) shows how a CAAC-OS film is formed by sputtering. FIG.

[0434] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130. The magnetic field is generated by the magnet. The magnetic field of the magnet is used to increase the deposition rate. The sputtering method is called magnetron sputtering.

[0435] The substrate 5120 is disposed facing the target 5130, and the distance d ( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the film deposition chamber is set to 0.02 m or more and 0.5 m or less. Most of the film deposition gas (e.g., oxygen) It is filled with a gas mixture containing hydrogen, argon, or oxygen at a ratio of 5% by volume or more, and The pressure is controlled to be in the range of 0.1 Pa to 100 Pa, preferably in the range of 0.1 Pa to 10 Pa. By applying a voltage above a certain level to the target 5130, discharge begins and plasma is generated. It is noted that a high density plasma region is formed near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 The ions 5101 are, for example, positive ions of oxygen (O + ) and argon cations (A r + ) etc.

[0436] Here, the target 5130 has a polycrystalline structure having a plurality of crystal grains, and any of the crystal grains The crystal grains include cleavage planes. The crystal structure of InGaZnO4 is shown in Fig. 43(A). This is the structure of an InGaZnO4 crystal. In the Ga-Zn-O layer, the oxygen atoms in each layer are arranged in close proximity. And because the oxygen atom has a negative charge, the two adjacent G Repulsion occurs between the a-Zn-O layers. As a result, the InGaZnO4 crystals The cleavage plane is located between the two Ga-Zn-O layers.

[0437] Ions 5101 generated in the high-density plasma region are applied to the target 5130 side by the electric field. The cleavage plane is accelerated and eventually collides with the target 5130. At this time, flat or pellet-like particles are formed from the cleavage plane. Pellets 5100a and 5100b, which are pellet-shaped sputtered particles, are peeled off and struck. The pellets 5100a and 5100b are the particles of the ions 5101. The impact of a collision can cause distortion in the structure.

[0438] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example, equilateral triangular, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, plane. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, a triangle (e.g., an equilateral triangle) may be formed. In some cases, two squares (e.g., a diamond) are joined together to form a rectangle.

[0439] The thickness of the pellet 5100 is determined depending on the type of deposition gas, etc. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferable to thick cubes. The thickness of the 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The pellet 5100 is (1) in FIG. For example, the target 51 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded onto the surface 30, a Ga-Zn-O layer and a A pellet 5100 having three layers, an In-O layer and a Ga-Zn-O layer, is exfoliated. (C) shows the structure of the exfoliated pellet 5100 observed from a direction parallel to the c-axis. The 5100 is a nano-structure having two Ga-Zn-O layers (pan) and an In-O layer (core). It can also be called a no-size sandwich structure.

[0440] The pellet 5100 may become negatively or positively charged on its sides as it passes through the plasma. The pellet 5100 may, for example, be negatively charged due to the oxygen atoms located on its sides. The sides have charges of the same polarity, which causes repulsion between the charges, forming a flat or pellet-like shape. It is possible to maintain the shape of the CAAC-OS. In the case of oxides, the oxygen atoms bonded to the indium atoms may be negatively charged. Or, an oxygen atom bonded to an indium atom, a gallium atom, or a zinc atom is negatively charged. In addition, when the pellet 5100 passes through the plasma, it may When it grows by bonding with sodium atoms, gallium atoms, zinc atoms, and oxygen atoms, etc. The difference in size between (2) and (1) in Figure 41 above corresponds to the growth in the plasma. Here, when the substrate 5120 is at room temperature, the pellets on the substrate 5120 Since the growth of 5100 is difficult to occur, it becomes nc-OS (see Figure 42(B)). Therefore, nc-OS can be deposited even on a large substrate (5120). In order to grow the pellet 5100 in plasma, the sputtering method is required. Increasing the film formation power is effective. The structure of 00 can be stabilized.

[0441] As shown in FIG. 42(A) and FIG. 42(B), for example, a pellet 5100 is formed in the plasma. It flies through the air like a kite and flutters up onto the substrate 5120. Pellet 51 Because 00 is electrically charged, it approaches an area where other pellets 5100 have already accumulated. Here, on the upper surface of the substrate 5120, a repulsive force is generated. In addition, the substrate 5120 and the target 51 Since a potential difference is applied between the substrate 5120 and the target 5130, the Therefore, the pellet 5100 is placed on the upper surface of the substrate 5120 in a magnetic The force (Lorentz force) is exerted by the action of the electric field and the electric current. This can be understood using the left-hand rule.

[0442] The pellet 5100 has a larger mass than a single atom. In order to move the object, it is important to apply some kind of force from the outside. It is possible that the force is generated by the action of the electric field and the electric current. To provide sufficient force to move the top surface of substrate 5120, The magnetic field parallel to the upper surface of the plate 5120 is 10 G or more, preferably 20 G or more, and more preferably It is advisable to provide an area where the resistance is 30 G or more, and more preferably 50 G or more. On the upper surface of the substrate 5120, a magnetic field parallel to the upper surface of the substrate 5120 is applied to the upper surface of the substrate 5120. At least 1.5 times, preferably at least 2 times, more preferably at least 3 times the magnetic field perpendicular to the surface It is preferable to provide an area where the difference is 5 times or more.

[0443] At this time, the magnet and the substrate 5120 move or rotate relative to each other. Therefore, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. On the upper surface of 5120, the pellet 5100 is subjected to forces from various directions and is moved in various directions. It can be moved.

[0444] Also, when the substrate 5120 is heated as shown in FIG. 42(A), the pellet 5100 The resistance due to friction between the substrate 5120 and the pellets is small. The pellet 5100 glides over the top surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. When the particles reach the side of the pellet 5100, the sides are joined together. The oxygen atom on the side of 0 is released. The released oxygen atom Since the electron vacancies may be filled, the CAAC-OS has a low defect level density. The temperature of the upper surface of 5120 is, for example, 100°C or more and less than 500°C, 150°C or more and less than 450°C. or 170° C. or higher and lower than 400° C. Even in this case, it is possible to form a CAAC-OS film.

[0445] Furthermore, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relaxed. 00 is almost a single crystal. Pellet 5100 is almost a single crystal, Even if the pellets 5100 are heated after being bonded together, the pellets 5100 themselves do not expand or contract. Therefore, the gaps between the pellets 5100 widen, causing the grains to shrink. It does not form defects such as boundaries or crevasse formation.

[0446] In addition, the CAAC-OS is not made of a single-crystal oxide semiconductor. The aggregates of pellet 5100 (nanocrystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between the pellets 5100. The CAAC-OS was deformed, such as shrinking, due to heating during film formation, heating after film formation, or bending. Even in such cases, it is possible to relieve local stress or release strain. This structure is suitable for use in flexible semiconductor devices. The resulting arrangement resembles randomly stacked nanocrystals.

[0447] When target 5130 is sputtered by ions 5101, not only pellet 5100 but also However, zinc oxide may peel off. Zinc oxide is lighter than pellet 5100, so Therefore, it first reaches the upper surface of the substrate 5120. A zinc oxide layer 5102 having a thickness of 0.5 nm to 2 nm is formed. A cross-sectional schematic diagram is shown in Figure 44.

[0448] As shown in FIG. 44(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the particles slide on pellet 5105b. In another aspect of 5a, a plurality of particles 5103 detached from the target along with zinc oxide. However, due to the heat from the substrate 5120, it is crystallized to form a region 5105a1. The particles 5103 may include oxygen, zinc, indium, and gallium, among others.

[0449] As shown in FIG. 44(B), the region 5105a1 is integrated with the pellet 5105a. The pellet 5105c has a side surface that is the same as that of the pellet 5105a. It is arranged so as to be in contact with another side surface of 105b.

[0450] Next, as shown in FIG. 44(C), a pellet 5105d is further formed on the pellet 5105a2. and pellet 5105b, and then on pellet 5105a2 and pellet 51 It slides on the other side of the pellet 5105c. The pellet 5105e slides over the zinc oxide layer 5102.

[0451] As shown in FIG. 44(D), the pellet 5105d has a side surface similar to that of the pellet 510. The pellet 5105e is placed so that its side faces the pellet. Also, the other side of the pellet 5105d is arranged so as to be in contact with the other side of the pellet 5105c. In the process, a plurality of particles 5103 peeled off from the target 5130 together with zinc oxide are deposited on the substrate. Heat from 5120 causes crystallization, forming region 5105d1.

[0452] As described above, the piled pellets are arranged so that they come into contact with each other, and the particles are formed on the side surfaces of the pellets. As a result of this growth, a CAAC-OS is formed on the substrate 5120. The individual pellets of C-OS are larger than those of nc-OS. The difference in size between (1) and (2) corresponds to the growth after deposition.

[0453] In addition, the gaps between the pellets become extremely small, so that one large pellet is formed. One large pellet may have a single crystal structure. The thickness is 10 nm or more and 200 nm or less, or 15 nm or more and 100 nm or less, as viewed from the top surface, or In some cases, the thickness may be between 20 nm and 50 nm. In some nitride semiconductors, the channel formation region may fit into one large pellet. That is, the region having a single crystal structure can be used as a channel forming region. As the size of the dot increases, the region having a single crystal structure becomes the channel formation region of the transistor, It may be used as a source region and a drain region.

[0454] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. This may improve the frequency characteristics of the transistor.

[0455] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. CAAC-OS can be formed even when the surface to be formed does not have a crystalline structure. This indicates that the growth mechanism is different from epitaxial growth. C-OS does not require laser crystallization and can be deposited uniformly even on large glass substrates. For example, if the structure of the upper surface (surface to be formed) of the substrate 5120 is an amorphous structure (for example, non-crystalline), It is possible to form a CAAC-OS film even on a silicon dioxide (crystalline silicon dioxide).

[0456] In addition, even if the upper surface of the substrate 5120 on which the formation is to be performed is uneven, the CAAC-OS For example, the pellets 5100 are arranged along the shape of the upper surface of the substrate 5120. If the surface is atomically flat, the pellet 5100 will be placed on a flat surface parallel to the ab plane. If the pellet 5100 has a uniform thickness, the thickness is uniform and flat, and A layer with high crystallinity is formed. Then, this layer is stacked n levels (n is a natural number). This allows the CAAC-OS to be obtained.

[0457] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510 The structure is made up of n layers (n is a natural number) of layers in which 0s are arranged along the unevenness. Since the surface 20 has unevenness, gaps tend to occur between the pellets 5100. However, even in this case, intermolecular forces act between the pellets 5100, and unevenness Therefore, even if there are unevenness, the gaps between the pellets are arranged as small as possible. A CAAC-OS having high crystallinity can be obtained.

[0458] Since the CAAC-OS film is formed using this model, the sputtered particles have a small thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0459] The film formation model shown above allows for the formation of highly crystalline films even on a surface with an amorphous structure. A CAAC-OS having the formula:

[0460] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0461] (Embodiment 8) In this embodiment, electronic devices to which one embodiment of the present invention is applied will be described with reference to FIGS. do.

[0462] By applying the display device of one embodiment of the present invention, highly reliable flexible electronic devices can be manufactured. It can be manufactured.

[0463] Examples of electronic devices include television sets, computer monitors, digital Cameras, digital video cameras, digital photo frames, mobile phones, portable games Examples include mobile phones, portable information terminals, audio playback devices, and large game consoles.

[0464] Furthermore, since the display device of one embodiment of the present invention is flexible, it can be easily attached to the inner or outer wall of a house or a building. , or can be incorporated along curved surfaces of the interior or exterior of a vehicle.

[0465] 24A shows an example of a mobile phone. The mobile phone 7100 has a housing 71 In addition to the display unit 7102 incorporated in the 01, there are operation buttons 7103 and an external connection port 7104. , a speaker 7105, a microphone 7106, a camera 7107, etc. The telephone 7100 is manufactured by using the light-emitting device of one embodiment of the present invention for the display portion 7102. According to one aspect of the present invention, a highly reliable mobile phone having a curved display is provided. can provide.

[0466] In the mobile phone 7100 shown in FIG. 24A, when the display portion 7102 is touched with a finger or the like, You can also make calls, enter text, and perform other functions. The operation can be performed by touching the display portion 7102 with a finger or the like. The application is started by touching the icon 7108 displayed in the part 7102. It is possible.

[0467] Also, by operating the operation button 7103, the power can be turned on and off, and the display unit 7102 can be displayed. For example, from the email creation screen, you can change the type of image displayed. - You can switch to the screen.

[0468] FIG. 24B shows an example of a wristwatch-type portable information terminal. 0 is a housing 7201, a display unit 7202, a band 7203, a buckle 7204, and operation buttons. 7205, input / output terminal 7206, etc.

[0469] The portable information terminal 7200 is a type of terminal that can be used for mobile phone calls, e-mails, document browsing and creation, music playback, internet connection, and other purposes. It can run various applications such as internet communication and computer games. can.

[0470] The display surface of the display unit 7202 is curved, and the display is performed along the curved display surface. The display portion 7202 is provided with a touch sensor, and can be touched with a finger or a stylus. For example, the icon 72 displayed on the display unit 7202 can be operated by touching it. You can launch the application by touching 07.

[0471] The operation button 7205 is used to set the time, turn the power on and off, and turn wireless communication on and off. Various functions such as operation, silent mode activation and deactivation, power saving mode activation and deactivation For example, the portable information terminal 7200 can have an operation The function of the operation button 7205 can also be freely set by the operating system.

[0472] In addition, the portable information terminal 7200 is capable of performing short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, hands-free You can also make calls.

[0473] The portable information terminal 7200 also has an input / output terminal 7206, and can be connected to other information terminals via a connector. Data can be exchanged directly through the input / output terminal 7206. The charging operation can be performed by wireless power supply without going through the input / output terminal 7206. You may go.

[0474] The display device of one embodiment of the present invention is applied to the display portion 7202 of the portable information terminal 7200. can be done.

[0475] FIG. 24C shows an example of a portable display device. The display device 7300 has a housing 7 301, display unit 7302, operation button 7303, drawer member 7304, control unit 7305 Equipped with.

[0476] The display device 7300 is a flexible display unit rolled up in a cylindrical housing 7301. Equipped with 7102.

[0477] The display device 7300 can receive a video signal through the control unit 7305. The control unit 7305 is provided with a battery. In addition, the control unit 7305 is provided with a terminal unit for connecting a connector, and video signals and power can be transmitted via a wired connection. Alternatively, the power may be supplied directly from the outside.

[0478] In addition, the operation button 7303 can be used to turn the power on and off and to switch the displayed image. etc. can be done.

[0479] FIG. 24D shows the display unit 7302 in a state where it is pulled out by the pull-out member 7304. In this state, an image can be displayed on the display unit 7302. The operation button 7303 arranged on the surface of the housing 7301 allows for easy operation with one hand. In addition, as shown in FIG. 24C, the operation button 7303 can be positioned at the center of the housing 7301. By placing it close to one side, it can be easily operated with one hand.

[0480] When the display portion 7302 is pulled out, the display surface of the display portion 7302 is fixed to a flat surface. To secure the display portion 7302 in place, a frame for reinforcing the display portion 7302 may be provided on the side of the display portion 7302.

[0481] In addition to this configuration, a speaker is provided on the housing, and the sound is transmitted by the audio signal received together with the video signal. The audio may be output by the audio input.

[0482] The light-emitting device of one embodiment of the present invention is incorporated in the display portion 7302. A lighter and more reliable light emitting device can be provided.

[0483] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0484] (Embodiment 9) Here, modifications of the transistor described in the above embodiment will be described with reference to FIGS. 37 to 39. The transistor shown in FIG. 37 is formed on an insulating film 824 on a substrate 821. an oxide semiconductor layer 828; an insulating film 837 in contact with the oxide semiconductor layer 828; and a conductive film 840 which is in contact with the insulating film 7 and overlaps with the oxide semiconductor layer 828. The conductive film 837 functions as a gate insulating film. It has the function of

[0485] In addition, the insulating film 846 in contact with the oxide semiconductor layer 828 and the insulating film 846 The insulating film 846 and the insulating film 847 are provided in the transistor. At the bottom, the conductive films 856 and 857 in contact with the oxide semiconductor layer 828 are The conductive films 856 and 857 are formed as a source electrode layer and a drain electrode layer. In addition, the insulating film 847 and the conductive films 856 and 857 are in contact with each other. 62 is provided.

[0486] Note that the structure of the transistor described in this embodiment and the conductive film and insulating film in contact with the structure The present invention relates to a structure of a transistor described in the above embodiment, a conductive film and an insulating film in contact with the structure, and A membrane can be used as appropriate.

[0487] In the transistor illustrated in FIG. 37A, the oxide semiconductor layer 828 overlaps with the conductive film 840. and a region 828a formed in the region including the impurity element, the region 828a being sandwiched therebetween. The conductive films 856 and 857 have the regions 828b and 828c. The region 828a functions as a channel region. The regions 828b and 828c are The resistivity is lower than that of the region 828a, and the region 828b can be called a low resistance region. 28b and 828c function as source and drain regions.

[0488] Alternatively, as in the transistor illustrated in FIG. 37B, The regions 828d and 828e in contact with the conductive films 856 and 857 are not doped with impurity elements. In this case, the regions 828d and 828e in contact with the conductive films 856 and 857 and the region 828d and 828e in contact with the conductive films 856 and 857 may be Between the region 828 and the region 828a, regions 828b and 828c containing impurity elements are provided. When a voltage is applied to the conductive films 856 and 857, the conductive films 828d and 828e are conductive. It functions as a source region and a drain region.

[0489] Note that in the transistor shown in FIG. 37B, after the conductive films 856 and 857 are formed, The impurity element is added to the oxide semiconductor layer using the conductive films 856 and 857 as a mask. By doing so, it can be formed.

[0490] The conductive film 840 may have a tapered edge. The angle θ1 between the surface where the conductive film 837 and the conductive film 840 are in contact and the side surface of the conductive film 840 is 90°. or 10° or more and 85° or less, or 15° or more and 85° or less, or 30° or more and 8 It may be 5° or less, or 45° to 85°, or 60° to 85°. The angle θ1 is set to less than 90°, or 10° or more and 85° or less, or 15° or more and 85° or less, Or 30° to 85°, or 45° to 85°, or 60° to 85° By setting the insulating film 837 and the conductive film 840 at the lower side, the insulating film 846 can be covered with the insulating film 846. It is possible to increase

[0491] Next, modified examples of the regions 828b and 828c will be described. 37(F) is an enlarged view of the oxide semiconductor layer 828 and its vicinity shown in FIG. The channel length L is the distance between the regions containing a pair of impurity elements.

[0492] As shown in FIG. 37C, in the cross section in the channel length direction, the region 828a and the region The boundary between the regions 828b and 828c is aligned with the edge of the conductive film 840 via the insulating film 837. That is, in the top view, the area 828a and the area 828b are the same or substantially the same. The boundary of 8c coincides or approximately coincides with the edge of the conductive film 840.

[0493] Alternatively, as shown in FIG. 37(D), in the cross section in the channel length direction, the region 828a However, there is a region that does not overlap with the edge of the conductive film 840. This region functions as an offset region. The length of the offset region in the channel length direction is L off In addition, If there are multiple offset areas, the length of one offset area is L off That is said. of f is included in the channel length L. Also, L off is less than 20% of the channel length L, or Less than 10%, or less than 5%, or less than 2%.

[0494] Alternatively, as shown in FIG. 37(E), in the cross section in the channel length direction, the region 828b , 828c has a region overlapping with the conductive film 840 with the insulating film 837 interposed therebetween. The overlap region in the channel length direction functions as a Length is L ov L ov is less than 20% of the channel length L, or less than 10%, or Less than 5% or less than 2%.

[0495] Alternatively, as shown in FIG. 37(F), in the cross section in the channel length direction, the region 828a and region 828b, and region 828c. The regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, the regions 828f and 828g overlap with the insulating film 837. However, the insulating film 837 and the conductive film 840 may overlap with each other.

[0496] 37(C) to 37(F), the explanation of the transistor shown in FIG. As explained above, the transistor shown in FIG. 37B also has the same structure as that shown in FIGS. ) structure can be applied as appropriate.

[0497] In the transistor shown in FIG. 38A, the edge of the insulating film 837 is located outside the edge of the conductive film 840. That is, the insulating film 837 has a shape that protrudes from the conductive film 840. Since the insulating film 846 can be separated from the insulating film 828a, the nitrogen contained in the insulating film 846 can be Therefore, it is possible to prevent atoms, hydrogen, etc. from entering the region 828a that functions as a channel region. can.

[0498] In the transistor shown in FIG. 38B, the insulating film 837 and the conductive film 840 have a tapered shape. The angles of the tapered portions are different. The angle θ1 between the contact surface and the side surface of the conductive film 840, the oxide semiconductor layer 828, and the insulating film The angle θ2 between the surface where 837 contacts and the side surface of the insulating film 837 is different. , or less than 90°, or 30° to 85°, or 45° to 70°. For example, if the angle θ2 is smaller than the angle θ1, the coverage of the insulating film 846 is improved. When the angle θ2 is greater than the angle θ1, the insulating film 846 can be spaced apart from the region 828a. Therefore, nitrogen, hydrogen, etc. contained in the insulating film 846 form a region that functions as a channel region. It can prevent the bacteria from entering 828a.

[0499] Next, regarding the modified examples of the regions 828b and 828c, we will use Figures 38(C) to 38(F). 38C to 38F show the oxide semiconductor shown in FIG. 8 is an enlarged view of the vicinity of layer 828.

[0500] As shown in FIG. 38C, in the cross section in the channel length direction, the region 828a and the region The boundary between the regions 828b and 828c is aligned with the end of the conductive film 840 via the insulating film 837. That is, in the top view, the area 828a and the area 828b are the same or substantially the same. The boundary of 28c coincides or almost coincides with the edge of the conductive film 840.

[0501] Alternatively, as shown in FIG. 38(D), in the cross section in the channel length direction, the region 828a However, there is a region that does not overlap with the conductive film 840. This region functions as an offset region. That is, in the top view, the ends of the regions 828b and 828c are aligned with the ends of the insulating film 837. The edge of the conductive film 840 is aligned or substantially aligned with the edge of the conductive film 840 and does not overlap the edge of the conductive film 840.

[0502] Alternatively, as shown in FIG. 38(E), in the cross section in the channel length direction, the region 828b , 828c has a region overlapping with the conductive film 840 with the insulating film 837 interposed therebetween. In other words, in the top view, the ends of the regions 828b and 828c are It overlaps with the conductive film 840 .

[0503] Alternatively, as shown in FIG. 38(F), in the cross section in the channel length direction, the region 828a and region 828b, and region 828c. The regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, the regions 828f and 828g overlap with the insulating film 837. However, the insulating film 837 and the conductive film 840 may overlap with each other.

[0504] 38(C) to 38(F), the explanation of the transistor shown in FIG. 38(C) to 38(F) are also applicable to the transistor shown in FIG. ) can be applied as appropriate.

[0505] In the transistor shown in FIG. 39A, the conductive film 840 has a stacked structure and is in contact with the insulating film 837. The conductive film 840a is in contact with the conductive film 840a, and the conductive film 840b is in contact with the conductive film 840a. The end of the conductive film 840a is located outside the end of the conductive film 840b. a has a shape that protrudes from the conductive film 840b.

[0506] Next, modified examples of the regions 828b and 828c will be described. 39(E) is an enlarged view of the vicinity of the oxide semiconductor layer 828 shown in FIG. 39(A).

[0507] As shown in FIG. 39B, in the cross section in the channel length direction, the region 828a and the region The boundary between the regions 828b and 828c is the end of the conductive film 840a included in the conductive film 840 and the insulating film 840b. The film 837 is aligned or substantially aligned with the region 828a. The boundaries of the regions 828b and 828c coincide or substantially coincide with the edges of the conductive film 840. There are.

[0508] Alternatively, as shown in FIG. 39C, in the cross section in the channel length direction, the region 828a However, there is a region that does not overlap with the conductive film 840. This region functions as an offset region. In addition, in the top view, the ends of the regions 828b and 828c are aligned with the ends of the insulating film 837. The edge of the conductive film 840 may be aligned or substantially aligned with the edge of the conductive film 840, and may not overlap with the edge of the conductive film 840.

[0509] Alternatively, as shown in FIG. 39(D), in the cross section in the channel length direction, the region 828b , 828c has a region overlapping with the conductive film 840, here the conductive film 840a. In other words, in the top view, the ends of the regions 828b and 828c are called overlapping regions. , overlapping with the conductive film 840a.

[0510] Alternatively, as shown in FIG. 39(E), in the cross section in the channel length direction, the region 828a and region 828b, and region 828c. The impurity element passes through the conductive film 840a and is added to the regions 828f and 828g. Therefore, the regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, the regions 828f and 828g are formed by the conductive film 840a and the Although it overlaps with the conductive film 840a and the conductive film 840b, it may also overlap with the conductive film 840a and the conductive film 840b.

[0511] Note that the edge of the insulating film 837 may be located outside the edge of the conductive film 840a.

[0512] Alternatively, the side surface of the insulating film 837 may be curved.

[0513] Alternatively, the insulating film 837 may have a tapered shape. The angle between the surface of the insulating film 837 and the side of the insulating film 837 is less than 90°, preferably 3 It may be greater than or equal to 0° and less than 90°.

[0514] As shown in FIG. 39, the oxide semiconductor layer 828 has a higher impurity concentration than the regions 828b and 828c. By having regions 828f and 828g with low concentration of silicon and high resistivity, Therefore, the threshold voltage of the transistor caused by the electric field in the drain region can be reduced. This makes it possible to reduce deterioration such as fluctuations in the value voltage.

[0515] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Explanation of symbols]

[0516] 101 Structure 101a Rotating body 101b Component 102 Starting point 103 processed parts 103a Component 103b Component 104 parts 105 Stages 107 Guide 108 Arrow 109 Rotational Axis 111 Components 151 Structure 152 Structure 153 processed parts 153a Parts 153b Materials 155 Stages 156 stages 157 Support 158 Conveyor roller 159 Rotational Axis 161 parts 162 Starting point 190 transistors 194 transistors 300 display device 300a display device 300b display device 301 Flexible substrate 302 Pixel section 304 Circuit section 305 Circuit section 307 Flexible substrate 308 FPC terminal section 310 Signal Line 311 Wiring section 312 Sealing material 316 FPC 318a adhesive layer 318b Adhesive layer 320a Organic resin layer 320b Organic resin layer 321a Insulating film 321b insulating film 334 Insulating Film 336 Colored layer 338 Light blocking layer 350 transistors 352 transistors 360 connecting electrode 364 Insulating Film 366 Insulating Film 368 Insulating Film 370 Planarization insulating film 372 Conductive Film 374 Conductive Film 375 Liquid Crystal Devices 376 Liquid Crystal Layer 378 Spacer 380 Anisotropic Conductive Film 410 Device Layer 411 Element Layer 430 Insulating film 432 Sealing layer 434 Insulating Film 444 Conductive Film 446 EL layer 448 Conductive Film 462 PCB 463 PCB 468 Ultraviolet light 480 Light-emitting element 501 pixel circuit 502 pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 transistors 552 transistor 554 Transistor 560 Capacitor 562 Capacitor 570 Liquid Crystal Devices 572 Light-emitting element 600 Excimer Laser Device 610a Laser light 610b Laser light 610c laser light 610d Linear Beam 630 Optical system 650 Mirror 670 Lens 700 Workpiece 710 Processing area 720 board 801 Resist mask 802 Resist mask 803 Resist mask 810 Impurities 821 PCB 824 insulating film 828 Oxide semiconductor layer 828a area 828b area 828c area 828d area 828e area 828f area 828g area 837 Insulating film 840 Conductive film 840a Conductive film 840b Conductive film 846 insulating film 847 insulating film 856 Conductive film 857 Conductive film 862 insulating film 900 boards 910 Organic resin layer 915 Insulating film 920 gate electrode layer 921 Conductive film 930 Gate insulating film 931 Insulating Film 932 Insulating film 933 Insulating Film 935 Insulation Layer 940 Oxide semiconductor layer 940a Oxide semiconductor film 940b Oxide semiconductor film 940c oxide semiconductor film 941a Oxide semiconductor layer 941b Oxide semiconductor layer 942a Oxide semiconductor layer 942b Oxide semiconductor layer 942c Oxide semiconductor layer 943a Oxide semiconductor layer 950 Source electrode layer 951 Source Region 960 Drain electrode layer 961 Drain Region 970 insulating film 975 insulating film 980 insulating film 990 insulating film 7100 Mobile Phone 7101 Housing 7102 Display section 7103 Operation button 7104 External connection port 7105 Speaker 7106 Microphone 7107 Camera 7108 Icon 7200 Portable Information Terminal 7201 Case 7202 Display section 7203 Band 7204 Buckle 7205 Operation button 7206 Input / output terminal 7207 Icon 7300 display device 7301 Housing 7302 Display section 7303 Operation button 7304 Materials 7305 Control Unit 5100 pellets 5100a pellets 5100b pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellets 5105a1 area 5105a2 pellets 5105b Pellets 5105c Pellets 5105d Pellets 5105d1 area 5105e Pellets 5120 board 5130 Target 5161 area 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

[Claim 1] A manufacturing method of a display device including a first element layer and a second element layer, one of the first element layer and the second element layer having a pixel portion including a first transistor having an oxide semiconductor layer and a display element, and a circuit portion including a second transistor having an oxide semiconductor layer, and the other of the first element layer and the second element layer having a coloring layer and a light-blocking layer, forming a first organic resin layer on a first substrate; forming a first insulating film on the first organic resin layer; forming the first element layer on the first insulating film; forming a second organic resin layer on a second substrate; forming a second insulating film on the second organic resin layer; forming the second element layer on the second insulating film; bonding the first substrate and the second substrate together so that the first element layer and the second element layer are sealed; performing a first separation step of separating the first substrate by reducing adhesion between the first organic resin layer and the first substrate through irradiation with linear excimer laser light; the first organic resin layer and a first flexible substrate are bonded together via a first adhesive layer; a second separation step of separating the second substrate by reducing adhesion between the second organic resin layer and the second substrate through irradiation with linear excimer laser light; a second adhesive layer formed on the second organic resin layer and a second flexible substrate;

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