Method for manufacturing semiconductor device

Abstract

An object is to suppress deterioration in characteristics of a transistor in a driver circuit.SOLUTION: The semiconductor device includes a first switch which is turned on or off in accordance with a first input signal to control whether or not a potential state of an output signal is set, and a second switch which is turned on or off in accordance with a second input signal to control whether or not the potential state of the output signal is set, and the first wiring and the second wiring are brought into a conduction state or a non-conduction state by turning on or off the first switch or the second switch.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Semiconductor device, display device, liquid crystal display device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device, a display device, and a display device having a driver circuit formed on the same substrate as a pixel portion. The present invention relates to a liquid crystal display device or a driving method thereof, or the semiconductor device, the display device, Or, the present invention relates to an electronic device having the liquid crystal display device. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single-crystal semiconductors are used to form a pixel portion. The technology of configuring drive circuits such as gate drivers on the board is expected to significantly reduce costs and improve reliability. Development is underway actively to contribute significantly to the

[0003] A transistor made of a non-single-crystal semiconductor has a fluctuation in threshold voltage or a decrease in mobility. As this transistor degradation progresses, the drive circuit becomes difficult to operate, Therefore, there is a problem that the image cannot be displayed. In Patent Document 1, the output signal of a flip-flop is lowered to L level (also called low level). To suppress deterioration of a transistor having a function of pulling down a power supply (hereinafter also referred to as a pull-down transistor), These documents disclose a shift register that can The two pull-down transistors are used in the flip-flop. It is connected between the output terminal and the wiring that supplies VSS (hereinafter referred to as the negative power supply). The pull-down transistor of the first transistor and the other pull-down transistor are alternately turned on (on state) This turns on each pull-down transistor. Since the time during which the pull-down transistor is turned off is shortened, deterioration of the characteristics of the pull-down transistor can be suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-50502 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-24350 [Non-patent literature]

[0005] [Non-Patent Document 1] Yong Ho Jang, et al., “Integrated Gate Driver Circuit Using a-Si TFT with Dual Pull-down Structure”, Proceedings of The 11th International Display Workshops 2004, pp.333-336 Summary of the Invention [Problem to be solved by the invention]

[0006] In the configuration of the conventional technology, a transistor (hereinafter referred to as The gate potential of the pull-up transistor is connected to the positive power supply voltage or the clock signal. This can cause the potential to be higher than the high level of the A large voltage may be applied to the gate of the pull-up transistor. A large voltage may be applied to the transistor being used, or the transistor may be degraded. The transistors that make up the shift register are designed so that the shift register can still operate even if the The channel width may be large. Or, if the channel width of the transistor is large, the transistor This may lead to a short circuit between the gate and the source or drain of the transistor. As the channel width of the transistor increases, the transistors that make up the shift register This may increase the parasitic capacitance of the

[0007] An object of one embodiment of the present invention is to suppress deterioration of transistor characteristics. An object of one embodiment of the present invention is to reduce the channel width of a transistor. One aspect is to suppress deterioration of the characteristics of the pull-up transistor or to reduce the channel width. Another object of one embodiment of the present invention is to increase the amplitude of an output signal. Another object of one embodiment of the present invention is to increase the on-time of a transistor included in a pixel. Another object of one embodiment of the present invention is to improve insufficient writing to pixels. Another object of one embodiment of the present invention is to shorten the fall time of an output signal. An object of one embodiment of the present invention is to shorten the rise time of an output signal. In one aspect of the invention, a video signal for pixels in one row is written to a pixel in another row. Alternatively, the object of the present invention is to prevent the fall time of the output signal from the drive circuit from being extended. The objective is to reduce the fluctuation of the image quality, or to make the effect of feedthrough on each pixel constant. Another object of the present invention is to reduce crosstalk. An object of one embodiment of the present invention is to reduce a layout area. Another object of one embodiment of the present invention is to narrow the frame of a display device. Another object of one embodiment of the present invention is to increase the yield. Another object of one embodiment of the present invention is to reduce manufacturing costs. An object of one embodiment of the present invention is to reduce distortion of an output signal. Another object of the present invention is to reduce the delay of an output signal. Another object of one embodiment of the present invention is to reduce the current supply capability of an external circuit. Another object of one embodiment of the present invention is to provide a semiconductor device having an external circuit. The object of the present invention is to reduce the size of the display device. However, one aspect of the present invention does not intend to solve all of these problems. It is not necessary to [Means for solving the problem]

[0008] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. and a pixel to which a voltage corresponding to the pixel voltage is set, and the driving circuit is turned on or off in response to a third input signal. A first switch and a second switch that are turned on and off, and a first switch that is turned on or off. Whether the first input signal is input or not is controlled by this, and the ON / OFF switch is turned on or off depending on the first input signal. a third switch that controls whether to set the potential state of the output signal by being turned on or off; The second switch is turned on or off to determine whether a second input signal is input. The potential of the output signal is controlled by turning on or off in response to the second input signal. and a fourth switch that controls whether or not to set the state.

[0009] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. a pixel to which a voltage corresponding to the voltage is set, and the driving circuit has a gate, a source, and a drain. A third input signal is input to the gate, and the first input signal is input to one of the source and the drain. a first transistor having a gate, a source, and a drain, and a third transistor connected to the gate; A second transistor to which an input signal is input and a second input signal is input to one of the source and the drain. a gate, a source, and a drain of the first transistor, the gate being connected to the source of the first transistor; The other of the source and drain is electrically connected to the output terminal, and is turned on or off to generate an output signal. a third transistor for controlling whether or not to set the potential state of the gate, source, and drain the gate is electrically connected to the other of the source and drain of the second transistor. By turning on or off, it controls whether or not to set the potential state of the output signal. and a fourth transistor.

[0010] One aspect of the present invention is a method for generating a first input signal, a second input signal, a third input signal, and a fourth input signal. A driving circuit receives an input signal and outputs an output signal, and a liquid crystal element is provided, and the liquid crystal element changes in response to the output signal. a pixel in which a voltage applied to a liquid crystal element is set, and a driving circuit receives a first input signal. a first wiring to which a second input signal is input, a second wiring to which a third input signal is input, and a third wiring to which a fourth input signal is input, a fourth wiring to which a fourth input signal is input, and a gate, a source, and a The gate is electrically connected to a third wiring, and one of the source and drain is a first transistor electrically connected to a first wiring, and a gate, a source, and a drain The gate is electrically connected to the third wiring, and one of the source and the drain is connected to the second wiring. a second transistor electrically connected to the wiring; and a second transistor having a gate, a source, and a drain. The gate is electrically connected to the other of the source and drain of the first transistor, and the source a third transistor, one of whose drains is electrically connected to a fourth wiring; a gate; a gate connected to the other of the source and drain of the second transistor; a fourth transistor electrically connected to the fourth wiring, and one of the source and the drain is electrically connected to the fourth wiring; the other of the source and drain of the third transistor and the fourth transistor The potential is electrically connected to the other of the source and drain of the transistor, and the potential to be applied is the potential of the output signal. and a fifth wiring that serves as a second wiring.

[0011] One aspect of the present invention is a method for generating a first input signal, a second input signal, a third input signal, and a fourth input signal. A driving circuit receives an input signal and outputs an output signal, and the liquid crystal element is provided, and the liquid crystal element changes in accordance with the output signal. a pixel in which a voltage applied to a liquid crystal element is set, and a driving circuit receives a first input signal. a first wiring to which a second input signal is input, a second wiring to which a third input signal is input, and a third wiring to which a fourth input signal is input, a fourth wiring to which a fourth input signal is input, and a gate, a source, and a and a drain, and the gate and one of the source and drain are electrically connected to the first wiring. a first transistor having a gate, a source, and a drain, a second transistor, one of whose source and drain are electrically connected to a second wiring; a gate connected to the source and drain of the first transistor, a second transistor electrically connected to the first wiring and one of the source and drain of the second transistor electrically connected to the third wiring; a third transistor having a gate, a source, and a drain, the gate of which is connected to the second transistor; the other of the source and drain of the fourth A fourth transistor electrically connected to the wiring and a source and a drain of the third transistor the other of the input terminals and the other of the source and drain of the fourth transistor; and a fifth wiring to which a potential applied becomes a potential of an output signal.

[0012] One aspect of the present invention is a digital signal processing device that receives a first input signal and a second input signal and outputs an output signal. The device has a drive circuit and a liquid crystal element, and the voltage applied to the liquid crystal element is set according to the output signal. a pixel, and the driving circuit includes a first wiring to which a first input signal is input and a second wiring to which a second input signal is input. A second wiring to which a signal is input, a gate, a source, and a drain, a first transistor having one of a source and a drain electrically connected to a first wiring; , a source, and a drain, and the gate and one of the source and the drain are connected to a second wiring. a second transistor electrically connected to the gate electrode; a gate electrode having a gate, a source, and a drain; and one of the source and drain of the first transistor is connected to the other of the source and drain of the second transistor. a third transistor electrically connected to the gate electrode; and one of the source and drain of the second transistor is connected to the other of the source and drain of the second transistor. a fourth transistor electrically connected to the source and drain of the third transistor; The other of the source and drain of the fourth transistor is electrically connected to the other of the source and drain of the fourth transistor. and a third wiring, the potential of which becomes the potential of an output signal.

[0013] In one embodiment of the present invention, the channel width of the third transistor is set to be equal to that of the fourth transistor. It can also be made equal to the channel width of

[0014] In one embodiment of the present invention, the channel width of the first transistor is the channel width of the second transistor is made smaller than that of the fourth transistor; It can also be smaller than the channel width.

[0015] One aspect of the present invention is a digital signal processing device that receives a first input signal and a second input signal and outputs an output signal. The device has a drive circuit and a liquid crystal element, and the voltage applied to the liquid crystal element is set according to the output signal. a pixel, and the driving circuit includes a first wiring to which a first input signal is input and a second wiring to which a second input signal is input. A second wiring to which a signal is input, a gate, a source, and a drain, a first transistor having one of a source and a drain electrically connected to a first wiring; , a source, and a drain, and the gate and one of the source and the drain are connected to a second wiring. a second transistor electrically connected to the first transistor, the second transistor having a positive electrode and a negative electrode, the positive electrode being connected to the first transistor; a first diode electrically connected to the other of the source and drain of the transistor; The positive electrode is electrically connected to the other of the source and drain of the second transistor. A second diode is connected to the negative terminal of the first diode and the negative terminal of the second diode. a third wiring electrically connected to the liquid crystal display panel, the third wiring being supplied with a potential that becomes the potential of an output signal; It is a display device.

[0016] In one embodiment of the present invention, the channel width of the first transistor is It can also be made equal to the channel width of

[0017] One embodiment of the present invention is a liquid crystal display device according to any one of the above, and a device for controlling the operation of the liquid crystal display device. and an operation switch for controlling the operation of the electronic device.

[0018] The switch may take various forms. For this purpose, an electrical switch or a mechanical switch can be used. The switch is not limited to a specific type as long as it can control the current.

[0019] An example of a switch is a transistor (e.g., a bipolar transistor, a MOS transistor, etc.). transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, -Diode, MIM (Metal Insulator Metal) diode, M IS (Metal Insulator Semiconductor) diode, These include transistors with diode connections, or logic circuits that combine these. An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. The switch has a mechanically movable electrode, and the movement of the electrode causes a conduction. It operates by controlling conduction and non-conduction.

[0020] As a switch, both N-channel and P-channel transistors are used. Alternatively, a CMOS type switch may be used.

[0021] Note that a display element, a display device which is a device having a display element, a light-emitting element, and a device having a light-emitting element are also included. A light-emitting device, which is a device that emits light, can take various forms or have various elements. An example of a display element, a display device, a light-emitting element, or a light-emitting device is an EL (electroluminescence) luminescence) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LED (white LED, red LED, green LED, blue LED, etc.), transistor (current transistors that emit light in response to light), electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices , Grating Light Valve (GLV), Digital Micromirror Device (DMD) , carbon nanotubes, etc., due to electromagnetic effects, contrast, brightness, reflectivity, Some display devices have a display medium that changes transmittance, etc. Also, display devices are called plasma displays. The display device using the EL element may be a ray or a piezoelectric ceramic display. An example of a display device using electron-emitting devices is an EL display. For this purpose, a Field Emission Display (FED) or a Surface Emission Display (SED) (onduction Electron-emitter Display) type flat type An example of a display device using liquid crystal elements is a liquid crystal display. (Transmissive LCD, Semi-transmissive LCD, Reflective LCD, Direct View LCDs (e.g., LCDs with projection), etc. Electronic ink or electrophoretic devices An example of a display device using such a device is electronic paper.

[0022] An example of a liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The element can be composed of a pair of electrodes and a liquid crystal layer. The optical modulation effect of liquid crystals is determined by the electric field (horizontal electric field, vertical electric field or diagonal electric field) applied to the liquid crystals. Specifically, a liquid crystal element is a nematic liquid crystal element. tic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal Pycnic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDL C), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma address liquid LCD (PALC), banana-shaped LCD, TN (Twisted Nematic) mode, ST N (Super Twisted Nematic) mode, IPS (In-Plane -Switching) mode, FFS(Fringe Field Switchin) g) Mode, MVA (Multi-domain Vertical Alignmen) t) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell mode, OCB (Opt ical Compensated Birefringence mode, ECB (E Controlled Birefringence) mode , FLC (Ferroelectric Liquid Crystal) mode, AF LC (AntiFerroelectric Liquid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode Some of them use guest host mode, blue phase mode, etc. However, the present invention is not limited to this, and various liquid crystal elements can be used.

[0023] Note that transistors with various structures can be used as the transistors. There is no limitation on the type of transistor. Examples of transistors include amorphous silicon, polycrystalline silicon, and Crystalline silicon, microcrystalline (also called microcrystalline, nanocrystalline, or semi-amorphous) ) Thin film transistors (TFTs) with non-single crystal semiconductor films, such as silicon can be used.

[0024] Examples of transistors include ZnO, a-InGaZnO, SiGe, and GaAs. , IZO (indium zinc oxide), ITO (indium tin oxide), SnO, TiO, Transistors containing compound semiconductors or oxide semiconductors such as AlZnSnO(AZTO) or a thin film transistor formed by thinning these compound semiconductors or oxide semiconductors. It is possible.

[0025] An example of a transistor is a transistor formed by an ink-jet method or a printing method. A transistor or the like can be used.

[0026] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. A resistor or the like can be used.

[0027] Furthermore, as the transistor, transistors with various other structures can also be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A transistor or the like can be used.

[0028] An example of a transistor is a multi-gate transistor having two or more gate electrodes. A register can be used.

[0029] An example of a transistor is a structure in which gate electrodes are arranged above and below a channel. The transistors can be applied.

[0030] An example of a transistor is a transistor having a structure in which a gate electrode is disposed above a channel region. structure in which the gate electrode is located below the channel region, normal stagger structure, inverted stagger structure , a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or A transistor having a structure in which channel regions are connected in series can be used.

[0031] In addition, as an example of a transistor, a source electrode or a A transistor having an overlapping drain electrode structure can be used.

[0032] An example of a transistor is an LDD (Lightly Doped Drain ) region can be applied to a transistor.

[0033] The type of substrate on which the transistor is formed is not limited to a specific one, and various A transistor can be formed using a substrate such as a semiconductor substrate. Solid substrates, single crystal substrates (e.g. silicon substrates), SOI substrates, glass substrates, quartz substrates, plastic Includes stick substrate, metal substrate, stainless steel substrate, stainless steel foil substrate, tungsten substrate, substrate with tungsten foil, flexible substrate, bonded substrate Examples of substrates include glass substrates, glass films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of flexible substrates include polyethylene terephthalate (PET), polycarbonate, and Polyethylene naphthalate (PEN) and polyethersulfone (PES) are representative The film is made of flexible plastic, acrylic, or other synthetic resins. Examples of suitable materials include polypropylene, polyester, vinyl, polyvinyl fluoride, and chlorine. Examples of base films include polyester, polyamide, and polyimide. In particular, semiconductor substrates, single crystal substrates, or SO By manufacturing transistors using an I substrate, etc., characteristics, size, shape, etc. can be This allows the manufacture of small-sized transistors with low variation in temperature and high current capability. When a circuit is constructed using such transistors, it is possible to reduce the power consumption of the circuit or This allows for a high degree of integration of circuits.

[0034] Note that a transistor is formed using a certain substrate and then transferred to another substrate. However, the transistor may be disposed on another substrate. As the substrate, in addition to the substrate on which the above-mentioned transistor can be formed, a paper substrate, a cellophane substrate, etc. substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, Polyurethane, polyester) or recycled fiber (acetate, cupra, rayon, recycled These substrates include raw polyester, leather substrates, and rubber substrates. This improves the electrical characteristics of the transistor and reduces the power consumption of the transistor. Furthermore, it is possible to improve the reliability of devices using transistors, improve heat resistance, and reduce weight. It is possible to achieve a reduction in weight or thickness.

[0035] All of the circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate, a plastic substrate, a single crystal substrate, an SOI substrate, etc. This reduces the number of components, thereby reducing costs, and the number of connections to circuit components. This can improve reliability.

[0036] It is possible that not all of the circuits required to realize a given function are formed on the same substrate. In other words, part of the circuitry required to achieve a given function is formed on a certain substrate. Another part of the circuitry required to achieve a given function is formed on a different substrate. For example, some of the circuits required to realize a specific function can be made of glass. Another part of the circuitry required to realize a given function is formed on the single crystal substrate. It can be formed on a substrate (or SOI substrate). The single crystal substrate on which another part of the circuit required for the semiconductor device is formed is called COG (Chip On Glass). The glass substrate is connected to the circuit board by the glass substrate. It is possible to place an IC chip on the TAB. (Tape Automated Bonding), COF (Chip On Fil) m), SMT (Surface Mount Technology), or printed circuit board It is possible to connect it to the glass substrate using a plate or the like. In this way, part of the circuit is connected to the pixel. Since it is formed on the same board as the main body, the number of parts is reduced, resulting in cost reduction and Reliability can be improved by reducing the number of connection points with circuit components. Circuits with large power consumption or circuits with high drive frequencies tend to consume large amounts of power. Therefore, such circuits are often mounted on a substrate (such as a single crystal substrate) separate from the pixel section. By using this IC chip, the increase in power consumption This can prevent further damage.

[0037] The transistor may have at least three elements including a gate, a drain, and a source. The device may have a terminal between the drain and source regions. The semiconductor device has a channel region, and a current flows through the drain region, the channel region, and the source region. Here, the source and drain are determined by the structure or operating conditions of the transistor. It is difficult to define which is the source or drain because Therefore, the region functioning as a source and the region functioning as a drain are called the source or In some cases, the drain is not called a source. In such cases, the drain may be called a source or a drain. One is referred to as a first terminal, a first electrode, or a first region, and the other is referred to as a second terminal, a second electrode, or a The gate is sometimes referred to as the third terminal or the third electrode. There is.

[0038] The transistor has at least three terminals including a base, an emitter, and a collector. In this case, the element may be, for example, an element having one of an emitter and a collector. is referred to as a first terminal, a first electrode, or a first region, and the other of the emitter and the collector is referred to as a second It may be written as a terminal, a second electrode, or a second region. When a polarized transistor is used, the term "gate" can be replaced with "base." is.

[0039] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are functionally connected, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) , wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, a predetermined connection relationship, For example, the present invention is not limited to the connection relationships shown in the drawings or text, and may include connection relationships other than those shown in the drawings or text. This also includes other things.

[0040] An example of an electrical connection between A and B is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more resistors (e.g., diodes) can be connected between A and B.

[0041] An example of a functional connection between A and B is a connection that allows the functional connection between A and B. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (boosting circuits, step-down circuits, etc., level shifters that change the potential level of signals, etc.), Pressure source, current source, switching circuit, amplifier circuit (circuit that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, One or more circuits (memory circuits, control circuits, etc.) can be connected between A and B. For example, even if there is another circuit between A and B, the signal output from A will be transmitted to B. If they are transmitted, A and B are considered to be functionally connected.

[0042] In addition, when it is explicitly stated that A and B are electrically connected, it means that A and B are electrically When A and B are directly connected (i.e., when another element or circuit is placed between A and B), A and B are functionally connected (i.e., there is no other connection between A and B) and B are functionally connected (i.e., there is no other connection between A and B). When A and B are connected functionally through a circuit) and when A and B are connected directly ( In other words, A and B are connected without any other element or circuit between them. In other words, when it is explicitly stated that something is electrically connected, it should simply be is the same as if it were expressly stated only that it is

[0043] Note that it is not possible to explicitly say that B is formed on A, or that B is formed on A. When describing, it is not limited to forming B on A in direct contact with it. This also includes cases where there is no object between A and B, i.e., there is another object between A and B. A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.) (etc.)

[0044] Therefore, for example, it is not possible to explicitly state that layer B is formed on top of layer A (or on top of layer A). When the layer is placed on top of the substrate, there are cases where layer B is formed directly on top of layer A, and cases where layer B is formed directly on top of layer A. Another layer (such as layer C or layer D) is formed adjacent to it, and layer B is formed directly on top of it. It should be noted that other layers (such as layer C and layer D) may be formed separately. It may be a single layer or multiple layers.

[0045] Furthermore, the same applies when it is explicitly stated that B is formed above A. This is not limited to B being directly on top of A, but also includes the presence of another object between A and B. For example, if layer B is formed above layer A, In this case, there are two cases: when layer B is formed directly on top of layer A, and when layer B is formed directly on top of layer A. Another layer (such as layer C or layer D) is formed, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be single layers. Alternatively, it may be multi-layered.

[0046] In addition, B is formed on A, B is formed on A, or B is formed above A. When explicitly stating that "B" is formed, this also includes the case where B is formed diagonally above. Also, if B is formed under A, or B is formed under A, The same applies to the case.

[0047] In addition, when something is explicitly stated as singular, it is preferable that it be singular. However, it is not limited to this, and plural numbers are also possible. It is preferable that the items listed are plural. However, this is not limited to this. , it is also possible that it is singular.

[0048] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0049] The diagrams are merely diagrams showing ideal examples, and are not limited to the shapes or values ​​shown in the diagrams. For example, the drawings may show variations in shape due to manufacturing techniques, variations in shape due to errors, signal, voltage, or current variations due to noise, or timing deviations; This can include variations in voltage or current.

[0050] Note that technical terms may be used to describe specific embodiments or examples. However, one aspect of the invention should not be interpreted as being limited by technical terms.

[0051] In addition, undefined terms (including scientific and technical terms such as technical terms or academic terms) are generally It can be used as a meaning equivalent to the general meaning understood by a person of ordinary skill in the art. The terms defined herein shall be construed in a manner consistent with the background of the relevant art. is preferred.

[0052] It should be noted that the terms first, second, third, etc., refer to various elements, members, regions, layers, and sections as distinct from one another. Therefore, the words "first," "second," "third," etc. are used to distinguish between elements, parts, etc. It is not intended to limit the number of materials, regions, layers, areas, etc. It is possible to replace "second" or "third" etc.

[0053] In addition, "up," "upward," "down," "downward," "sideways," "right," "left," Spatial arrangement such as "diagonally," "in the back," "in front," "inside," "outside," or "inside" The location phrases should be used to easily illustrate the relationship of one element or feature to another. However, it is not limited to this and is often used to indicate the spatial arrangement of these. The phrase "above A" can include other directions in addition to the direction shown in the drawing. For example, When explicitly indicated as B, B is not limited to being above A. can be flipped or rotated 180 degrees, so it can include B being below A. In this way, the word "upon" can be used to refer to the direction of "up" as well as the direction of "down." The devices shown may include, but are not limited to, various orientations. Since it is possible to rotate the word "on" in addition to the directions "on" and "under" "Sideways", "Right", "Left", "Diagonally", "Back", "Front", "Inside", "Outside" It is possible to include other directions such as "into" or "into"; It is possible to interpret this as:

[0054] One aspect of the present invention is a semiconductor device including a first switch connected between a first wiring and a second wiring; a second switch connected between the first wiring and a second wiring, , the first switch is turned on, the second switch is turned off, and in the second period, The first switch is turned off, the second switch is turned off, and in the third period, the first The switch is turned off, the second switch is turned on, and in a fourth period, the first switch is turned on. The first switch is turned off and the second switch is turned off.

[0055] One aspect of the present invention is a semiconductor device having a first path and a second path between a first wiring and a second wiring. During the first period, the first wiring and the second wiring are brought into a conductive state via the first path. In the second period, the first wiring and the second wiring are in a non-conductive state, and in the third period, In the fourth period, the first wiring and the second wiring are brought into a conductive state via the second path. In this case, the first wiring and the second wiring are in a non-conductive state.

[0056] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. A first terminal of the first transistor is connected to the first wiring, and a second terminal of the first transistor is connected to the second wiring. The gate of the first transistor is connected to a third wiring, and the gate of the second transistor is connected to a third wiring. A first terminal of the second transistor is connected to the first wiring, and a second terminal of the second transistor is connected to the second wiring. and the gate of the second transistor is connected to the fourth wiring.

[0057] One embodiment of the present invention includes a first transistor and a second transistor, and In this case, the first transistor is turned on and the second transistor is turned off, and the second During this period, the first transistor is turned off and the second transistor is turned on. In the third period, the first transistor is turned off and the second transistor is turned on. In the fourth period, the first transistor is turned off and the second transistor is turned on. The start is what turns on.

[0058] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a first terminal of the first transistor connected to a first wiring; The second terminal is connected to the second wiring, and the gate of the first transistor is connected to the third wiring. The first terminal of the second transistor is connected to the first wiring, and the second terminal of the second transistor is connected to the first wiring. The second terminal is connected to the second wiring, and the gate of the second transistor is connected to the fourth wiring. The first terminal of the third transistor is connected to the fifth wiring, and the third terminal of the third transistor is connected to the fifth wiring. The second terminal is connected to the second wiring, and the gate of the third transistor is connected to the sixth wiring. It is something that is done. [Effects of the Invention]

[0059] According to one embodiment of the present invention, deterioration of the characteristics of a transistor can be suppressed. This embodiment allows the channel width of the transistor to be reduced. It is possible to suppress the deterioration of the transistor characteristics or reduce the channel width. According to one embodiment of the present invention, a layout area can be reduced. Alternatively, one embodiment of the present invention is to provide a display device with high resolution. Alternatively, one embodiment of the present invention can increase the yield. According to one embodiment of the present invention, manufacturing costs can be reduced. Alternatively, one embodiment of the present invention can reduce the current supply capability of an external circuit. Alternatively, one aspect of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the size of an external circuit or a table having the external circuit. The size of the display device can be reduced. [Brief explanation of the drawings]

[0060] [Figure 1] 1A and 1B are an example of a circuit diagram of a semiconductor device according to a first embodiment and an example of a schematic diagram for explaining an operation thereof; [Figure 2] 1A to 1C are an example of a circuit diagram of a semiconductor device according to a first embodiment, an example of a schematic diagram for explaining the operation of the semiconductor device according to the first embodiment, and an example of a timing chart for explaining the operation of the semiconductor device according to the first embodiment. [Figure 3] 4 is an example of a timing chart for explaining the operation of the semiconductor device in the first embodiment. [Figure 4] 10A and 10B are an example of a circuit diagram of a semiconductor device according to a second embodiment and an example of a timing chart for explaining the operation thereof. [Figure 5] 10A and 10B are an example of a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment and an example of a circuit diagram of the semiconductor device according to the second embodiment. [Figure 6] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment. [Figure 7] 10 is an example of a timing chart for explaining the operation of the semiconductor device in the second embodiment. [Figure 8] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 9] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment. [Figure 11] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 13] 10A and 10B are an example of a circuit diagram of a semiconductor device according to a second embodiment and an example of a timing chart for explaining the operation thereof. [Figure 14] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 15] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 16] FIG. 11 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the third embodiment. [Figure 17] FIG. 11 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the third embodiment. [Figure 18] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 19] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 20] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 21]FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 22] FIG. 11 is a circuit diagram of a semiconductor device according to a third embodiment. [Figure 23] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 24] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 25] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 26] FIG. 11 is an example of a circuit diagram of a shift register according to the fourth embodiment. [Figure 27] 10 is an example of a timing chart illustrating the operation of the shift register according to the fourth embodiment. [Figure 28] 10 is an example of a timing chart illustrating the operation of the shift register according to the fourth embodiment. [Figure 29] FIG. 11 is an example of a circuit diagram of a shift register according to the fourth embodiment. [Figure 30] FIG. 13 is an example of a block diagram of a display device according to a fifth embodiment. [Figure 31] FIG. 13 is an example of a block diagram of a display device according to a fifth embodiment. [Figure 32] 13A and 13B are an example of a circuit diagram of a signal line driver circuit according to a sixth embodiment and an example of a timing chart for explaining the operation thereof. [Figure 33] 13A and 13B are an example of a circuit diagram of a pixel according to the seventh embodiment and an example of a timing chart for explaining the operation thereof. [Figure 34] FIG. 20 is an example of a circuit diagram of a pixel according to the seventh embodiment. [Figure 35] 10A and 10B are examples of a top view and a cross-sectional view of a display device in Embodiment 8. [Figure 36] FIG. 13 is an example of a cross-sectional view of a transistor according to a ninth embodiment. [Figure 37] 11A to 11C are examples of cross-sectional views illustrating a manufacturing process of a transistor in Embodiment 10. [Figure 38] FIG. 22 is an example of a layout diagram of a semiconductor device according to an eleventh embodiment. [Figure 39]12A to 12C are diagrams illustrating examples of electronic devices according to Embodiment 12. [Figure 40] 12A to 12C are diagrams illustrating examples of electronic devices according to Embodiment 12. [Figure 41] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 42] FIG. 11 is a diagram showing verification results of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0061] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms and in various ways without departing from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various modifications can be made to the design and details of the present embodiment. It should not be construed as being limited to the contents of the description below. The same reference numerals are used in different drawings to indicate the same parts or parts with similar functions. A detailed description of the portion having the symbol will be omitted.

[0062] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the above, and / or one or more other implementations The content (or part of the content) described in the form of etc. can be done.

[0063] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0064] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, , and many more diagrams can be constructed.

[0065] In addition, in a drawing or a sentence described in a certain embodiment, a part thereof may be extracted. Therefore, it is possible to construct an embodiment of the invention by using the drawings or text describing a certain part. When a chapter is described, the contents of a part of the figure or text are also considered as an aspect of the invention. and can be considered to constitute one aspect of the invention. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitance elements, resistor elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, substrates, Module, device, solid, liquid, gas, method of operation, method of manufacture, etc. Drawings (sections, plan views, circuit diagrams, block diagrams, flow charts, process diagrams, perspective views, elevation views) Diagrams, layout diagrams, timing charts, structural diagrams, schematic diagrams, graphs, tables, optical path diagrams, vector diagrams, A part of a state diagram, waveform diagram, photograph, chemical formula, etc. or text can be extracted and used to create an invention. It is possible to configure one aspect of the present invention.

[0066] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. As an example, various driving circuits such as a shift register, a gate driver, or a source driver The semiconductor device of this embodiment mode can be used as a driver circuit or a circuit. It is possible to show.

[0067] First, a semiconductor device of this embodiment will be described with reference to FIG. The semiconductor device has a plurality of switches 11_1 to 11_2. 11_1 to 11_2 are connected between the wiring 111 and the wiring 112. However, this is not a limitation. The number of switches is not limited to three, and the semiconductor device may have more than two switches.

[0068] Next, signals or voltages input to or output from each wiring will be described.

[0069] As an example, a signal OUT is output from the wiring 111. For example, the signal O may be a signal having a first potential state and a second potential state. UT is a digital signal that has two states: H level (also called high level) and L level. Therefore, the wiring 111 is often a signal, and can function as an output signal. In particular, the wiring 111 is arranged to extend to the pixel portion. The wiring 111 can be connected to the pixel. For example, in the case of a liquid crystal display device, the wiring 111 is connected to a pixel having a liquid crystal element. The voltage applied to the liquid crystal element can be set in accordance with the potential of the liquid crystal element. The line 111 is connected to a transistor (for example, a selection transistor or a switching transistor) that the pixel has. In this case, the signal OUT is , as a selection signal, transfer signal, start signal, reset signal, gate signal, or scan signal Therefore, the wiring 111 can function as a gate signal line (gate line) or a scanning line. It can function as a scanning line.

[0070] As an example, a signal CK1 is input to the wiring 112. The signal CK1 is, for example, For example, the signal CK 1 is often a digital signal that alternates between two states: H level and L level. Therefore, the wiring 112 can function as a signal line or a clock signal. However, the present invention is not limited to this, and the wiring 111, Alternatively, various other signals, voltages, or currents may be input to the wiring 112. For example, a voltage is supplied to the wiring 111 or the wiring 112, and these wirings are connected to the power supply. It can function as a source line.

[0071] As an example, the first potential state, that is, the potential of the L level signal is V1, and the second potential state is V2. The potential state, that is, the potential of the H level signal, is V2. And, V2>V1. However, the potential of the L-level signal is not limited to this, and can be lower than V1. It is possible to set the potential of the H level signal higher than V2. It can be lower than V2 or higher than V3. In some cases, even if a signal is described as being at a high level, its potential may be lower than V2, or V 2. Or, depending on the circuit configuration, it may be described as an L-level signal. However, the potential may be lower than V1 or higher than V1.

[0072] The term "generally" refers to errors due to noise, process variations, and the manufacturing process of the element. This includes various errors such as errors due to variations in process and / or measurement errors.

[0073] Generally, voltage refers to the difference in electric potential between two points (also called the potential difference). The potential is the electrostatic energy (electric potential) of a unit charge in the electrostatic field at a certain point. However, in an electronic circuit, even if there is only one point, The potential difference between the potential at a point and the reference potential (also called the reference potential) is sometimes used as a value. In addition, voltage and potential values ​​are often expressed in volts (V) in circuit diagrams, etc. Therefore, in the documents of this application (specification and claims), Unless otherwise specified, voltage may be used as a value even at only one point.

[0074] Note that the signal CK1 can be balanced or unbalanced. Equilibrium is the period during which the signal is at the H level and the period during which the signal is at the L level. The non-equilibrium state is when the period of H level and the period of L level are roughly equal. It should be noted that "different" here does not include the case where they are roughly the same. It shall not be rare.

[0075] Next, the functions of the switches 11_1 to 11_2 will be described. 2 has a function of controlling the electrical connection between the wiring 111 and the wiring 112. ), there are multiple paths 21_1 to 21_2 between the wiring 111 and the wiring 112. Alternatively, the switches 11_1 and 11_2 may be connected to the power supply of the signal OUT. However, it is not limited to this and has the function of controlling whether or not to set the switch position. 11_1 to 11_2 can have various other functions.

[0076] It should be noted that the path between the wiring A (for example, the wiring 111) and the wiring B (for example, the wiring 112) is described as In this case, a switch can be connected between the wiring A and the wiring B. However, various elements (e.g., transistors, diodes, resistors, or capacitors), or various circuits (e.g., A buffer circuit, an inverter circuit, a shift register circuit, etc.) can be connected. Therefore, for example, a resistor or a transistor may be connected in series or in parallel with the switch 11_1. Elements such as transistors can be connected.

[0077] Next, the operation of the semiconductor device in FIG. 1A will be described with reference to an example of a timing chart in FIG. However, the semiconductor device of FIG. 1A is not limited to this, and various types of It can be controlled by timing.

[0078] In the timing chart of FIG. 2(A), the signal CK1, the state of the switch 11_1 (ON or OFF) 11_1, the state of the switch 11_2 (ON or OFF), and the waveform of the signal OUT. The timing chart in FIG. 2(A) has multiple periods, and each period is divided into multiple sub-periods. For example, the timing chart in FIG. 2A includes a period T1 and a period T2. The period T1 includes a plurality of periods (hereinafter, the periods are also referred to as frame periods). 1, multiple sub-periods, namely, period B1, period C1, period D1, and period E1 (hereinafter, the sub-periods The period T2 is also called one gate selection period, and the period T2 is divided into periods A2, B2, and C2. , period D2, and period E2. However, the present invention is not limited to this, and the present invention can be applied to the following cases. The timing chart of (A) may have a period other than the period T1 and the period T2. It is possible to omit either the period T1 or the period T2. It is possible to have various periods other than the periods A1 to E1, and the periods A1 to E1 It is possible to omit any of the periods. Alternatively, the period T2 may be various periods other than the periods A2 to E2. It is possible to have a period other than the period A2, and it is possible to omit any of the periods A2 to E2. be.

[0079] Note that, for example, the semiconductor device in FIG. 1A alternates between operation in the period T1 and operation in the period T2. However, the semiconductor device of FIG. 1A may be subjected to various processes. It is possible to perform the operations in the periods T1 and T2.

[0080] Note that, for example, in the period T1, the semiconductor device in FIG. The operation in the period D1 and the operation in the period E1 are repeated until the switch is turned on. When the switch 11_1 is turned on, the semiconductor device of FIG. The operation in the period B1, the operation in the period C1, and the operation in the period C2 are performed in this order. After that, the semiconductor device of FIG. 1A remains in a state during a period D1 until the switch 11_1 is turned on again. The operation in the period E1 and the operation in the period E2 are repeated. However, the present invention is not limited to this. In the semiconductor device of FIG. 1A, the operations in the periods A1 to E1 can be performed in various orders. It is Noh.

[0081] Note that in the period T2, for example, in the semiconductor device of FIG. The operation in period D2 and the operation in period E2 are repeated until the power is turned on. When the switch 11_2 is turned on, the semiconductor device of FIG. 1A The operation in period B1, the operation in period B2, and the operation in period C2 are performed in this order. Thereafter, the semiconductor device of FIG. 1A remains in a state where the switch 11_2 is turned on again for a period D2. The operation in period E1 and the operation in period E2 are repeated. However, this is not limited to this. In addition, the semiconductor device in FIG. 1A can perform operations in the periods A2 to E2 in various orders. It is possible.

[0082] The operation of the period T1 will be described. In the period T1, the switch 11_1 is turned on or off. Therefore, the switch 11_2 is turned off.

[0083] During the period A1 of the period T1, the switch 11_1 is turned on as shown in FIG. 2(D). Therefore, as shown in FIG. 2(E), the path 21_1 is Then, the signal input to the wiring 112 is (For example, the signal CK1 at L level) is supplied to the wiring 111 via the switch 11_1. Therefore, the signal OUT becomes L level.

[0084] During the period B1 of the period T1, as shown in FIG. 2(D), the switch 11_1 remains on. Therefore, as shown in FIG. 2(E), the path The path 21_1 remains conductive, and the path 21_2 remains non-conductive. A signal (for example, a signal CK1 at H level) input to the line 112 is input via the switch 11_1. and is supplied to the wiring 111. Therefore, the signal OUT becomes H level.

[0085] During the period C1 of the period T1, the switch 11_1 is turned off as shown in FIG. 2(B). Therefore, as shown in FIG. 2(C), the path 21_ 1 becomes non-conductive, and the path 21_2 remains non-conductive. Since the wiring 112 is in a non-conductive state, the signal (for example, L level The signal CK1 is no longer supplied to the wiring 111.

[0086] In the period C1 of the period T1, the switch 11_1 is turned off at the timing when the signal This is often later than the timing when CK1 becomes L level. Before the switch is turned off, a signal (for example, a signal CK1 at an L level) input to the wiring 112 In many cases, the signal OUT is supplied to the wiring 111 via the switch 11_1. However, the present invention is not limited to this, and the wiring 111 may be provided with an L-level signal or voltage V1. It is possible to be provided.

[0087] During the period D1 and the period E1 of the period T1, as shown in FIG. 2B, the switch 11_1 The switch 11_2 remains off. Therefore, as shown in FIG. 2(C), Therefore, the wiring 111 and the wiring 11_1 and the wiring 21_2 remain in a non-conductive state. 2 is in a non-conductive state, the signal input to the wiring 112 is not supplied to the wiring 111. Therefore, the signal OUT remains at the L level.

[0088] Next, the operation during the period T2 will be described. During the period T2, the switch 11_1 is turned off. , the switch 11_2 is turned on or off.

[0089] During the period A2 of the period T2, the switch 11_1 is turned off as shown in FIG. 2(F). Therefore, as shown in FIG. 2(G), the path 21_1 is not Then, the signal input to the wiring 112 is (For example, the signal CK1 at L level) is supplied to the wiring 111 via the switch 11_2. Therefore, the signal OUT becomes L level.

[0090] During the period B2 of the period T2, as shown in FIG. 2(F), the switch 11_1 remains off. Therefore, as shown in FIG. 2(G), the path The path 21_1 remains in a non-conductive state, and the path 21_2 remains in a conductive state. A signal (for example, a signal CK1 at a high level) input to the line 112 is input via the switch 11_2. and is supplied to the wiring 111. Therefore, the signal OUT becomes H level.

[0091] During the period C2 of the period T2, as shown in FIG. 2(B), the switch 11_1 remains off. 2(C), the path 21_ 1 remains in a non-conductive state, and the path 21_2 becomes non-conductive. Since the wiring 112 is in a non-conductive state, the signal (for example, L level The signal CK1 is no longer supplied to the wiring 111.

[0092] In the period C2 of the period T2, the switch 11_2 is turned off at the timing when the signal This is often later than the timing when CK1 becomes L level. Before the switch is turned off, a signal (for example, a signal CK1 at an L level) input to the wiring 112 In many cases, the signal OUT is supplied to the wiring 111 via the switch 11_2. However, the present invention is not limited to this, and when a signal or voltage V1 of an L level is supplied to the wiring 111, It is possible to do this.

[0093] During the period D2 and the period E2 of the period T2, as shown in FIG. 2B, the switch 11_1 The switch 11_2 remains off. Therefore, as shown in FIG. 2(C), Therefore, the wiring 111 and the wiring 11_1 and the wiring 21_2 remain in a non-conductive state. 2 is in a non-conductive state, the signal input to the wiring 112 is not supplied to the wiring 111. Therefore, the signal OUT remains at the L level.

[0094] As described above, by changing the period during which each switch is on, This reduces the number of times the switch is turned on or shortens the time the switch is turned on. As a result, deterioration of the characteristics of the element or circuit used as the switch can be suppressed.

[0095] Alternatively, it is possible to suppress deterioration of the characteristics of elements or circuits used as switches. For example, the wiring 111 may be a gate signal line or When the wiring 111 has a function as a scanning line or when the wiring 111 is connected to a pixel, the pixel is protected. The video signal being held may be affected by the waveform of the signal OUT. For example, If the potential of the transistor (e.g., selection transistor) of the pixel does not rise to V2, The time that the transistor (or switching transistor) is on is shortened. This may result in insufficient writing of the video signal, resulting in a deterioration in display quality. If the fall time and rise time of T become longer, the pixels belonging to the selected row If the video signal is written to a pixel in a different row, the video signal may be written to a pixel in a different row. Or, if the fall time of the signal OUT varies, the pixel may not be held. This can result in varying feedthrough effects on the video signal being displayed. This will result in uneven display.

[0096] However, the semiconductor device of this embodiment does not include an element or circuit used as a switch. Therefore, the potential of the signal OUT is increased to V2. Therefore, the time during which the transistor in the pixel is turned on can be extended. As a result, the video signal can be written to the pixels in sufficient time, improving the display quality. Alternatively, the fall time and rise time of the signal OUT can be shortened. Therefore, the pixels belonging to the selected row can receive the video signal for the pixels belonging to another row. This prevents the writing of unwanted signals, thereby improving the display quality. Also, the variation in the fall time of the signal OUT can be suppressed. This reduces the variation in the effect of feedthrough on the video signal held by the pixel. Therefore, display unevenness can be suppressed.

[0097] In the period T1, the period B1 is called the selection period, and the periods A1, C1, D1, Similarly, in the period T2, the period B 2 is called the selection period, and periods A2, C2, D2, and E2 are called non-selection periods. It is possible.

[0098] In the period T1, the switch 11_1 is turned on (periods A1 and A2). is called a first period, and the periods in which the switch 11_1 is turned off (periods C1, D1, and Similarly, in the period T2, the periods A2 and E3 can be called the second period. The periods C2, D2, and E2 are called the fourth period. It is possible.

[0099] The periods T1 and T2 are called frame periods, and the periods A1 to E1 and A2 to E2 can be called a sub-period or one gate selection period.

[0100] Note that a period or sub-period can be replaced with a step, process, or operation. is.

[0101] In the period T1, the period D1 and the period E1 are arranged in sequence before the period A1. Similarly, in the period T2, the period D2 and the period E2 can be arranged in a repeated order. In such a case, the start of the period T1 The time from the time to the start time of period A1, and the time from the start time of period T2 to the start time of period A2 It is preferable that the time until the clock is about the same as the time until the clock is about the same, but this is not limiting.

[0102] As shown in FIG. 1C, the switch 11_1 and the switch 11_2 are turned on for the same period. In this case, as shown in FIG. 1(D), the path 21_1 and The path 21_1 and the path 21_2 are in a conductive state for the same period. , is supplied to the wiring 111 via the switch 11_1 and the switch 11_2. This is not limited to this.

[0103] As shown in FIG. 1(E), the semiconductor device includes switches 11_1 to 11_N (N is 2 or more). It is possible to have multiple switches (natural numbers above). Switches 11_1 to 11 _N is connected between the wiring 111 and the wiring 112. The switches 11_1 to 11_N are It has the same function as the switch 11_1 or the switch 11_2. As shown in the figure, there are paths 21_1 to 21_N between the wiring 111 and the wiring 112. There is.

[0104] When the semiconductor device has N switches, as shown in FIG. 3, the periods T1 to TN are For example, in the timing chart of FIG. However, the present embodiment is not limited to this. The periods T1 to TN can be arranged in various orders. It is possible to omit some of the periods T1 to TN. For example, the period Ti (i is any one of 1 to N) is divided into periods Ai to Ei. It is possible to have multiple sub-periods. Periods Ai to Ei are each periods A1 to E1 or As in the periods A2 to E2, the switches 11_1 to 11_N (for example, For example, switches 11_1 to 11_i-1 and switches 11_i+1 to 11_N are turned off. Then, in periods Ai and Bi of period Ti, switch 11_i is turned on. , during periods Ci, Di, and Ei of period Ti, the switch 11_i is turned off.

[0105] Note that by increasing N, the number of times each switch is turned on, or the number of times each The time that the switch is on can be reduced. However, if N is too large, the switch The number of N becomes too large, and the circuit scale becomes large. Therefore, N must be 6 or less. It is preferable that the number of the slits is 4 or less, and more preferable that the number of the slits is 3 or less. is preferably 2, but is not limited to this.

[0106] As shown in FIG. 1(G), the wiring 112 may be divided into a plurality of wirings 112A to 112B. The switch 11_1 can be divided into the wiring 111 and the wiring 112A. and the switch 11_2 is connected between the wiring 111 and the wiring 112B. The wirings 112A to 112B are connected to various other wirings or various elements. It is possible to do this.

[0107] As in FIG. 1G, the wiring 112 is divided into a plurality of wirings in FIG. 1E. It is possible.

[0108] (Embodiment 2) In this embodiment, an example of a semiconductor device will be described. In particular, the semiconductor device described in the first embodiment can be used. The configuration of the device will be described below when, for example, a transistor is used as a switch. However, the present invention is not limited to this, and various elements or circuits may be used as switches. It is possible to do so. The contents described in the first embodiment will not be explained here. The contents of this embodiment mode can be appropriately combined with the contents described in Embodiment Mode 1. do.

[0109] First, the semiconductor device of this embodiment will be described with reference to FIG. The semiconductor device includes a circuit 100. The circuit 100 has the structure described in Embodiment 1. In this case, the structure is the same as that in the case where a transistor is used as a switch. The transistor 101_1 is used as the switch 11_1 of the transistor 101_1 (A), and the switch 11_ 2, the transistor 101_2 is used. The transistor 101_1 has the same function as the switch 11_1, and the transistor 101_2 has the same function as the switch 11_1. However, the present invention is not limited to this and may be applied to the first embodiment. In the configuration, a transistor can be used as the switch. As the switching element, a CMOS switch or the like can be used.

[0110] The transistors 101_1 and 101_2 are N-channel transistors. In an N-channel transistor, the potential difference (Vgs) between the gate and source is It turns on when the threshold voltage (Vth) is exceeded. However, it is not limited to this. The transistor 101_1 and / or the transistor 101_2 are P-channel A P-channel transistor has a potential difference between the gate and source (Vg s) falls below the threshold voltage (Vth).

[0111] Next, the connection relationship of the semiconductor device in FIG. The first terminal of the transistor 101_1 is connected to the wiring 112, and the second terminal of the transistor 101_1 is connected to the wiring 111. A first terminal of the transistor 101_2 is connected to a wiring 112. The second terminal of the first terminal 101_2 is connected to the wiring 111.

[0112] Note that the connection point between the gate of the transistor 101_1 and the circuit 10 is indicated as a node n1. The connection point between the gate of the transistor 101_2 and the circuit 10 is indicated as a node n2. The node n1 and the node n2 can be called wires.

[0113] Next, functions of the transistor 101_1 and the transistor 101_2 will be described. do.

[0114] The transistor 101_1 changes the potential of the wiring 112 to the potential of the wiring 111 in accordance with the potential of the node n1. For example, the wiring 112 has a function of controlling the timing at which a voltage (for example, a voltage When a voltage V1 or V2 is supplied, the transistor 101_1 is connected to the potential of the node n1. In response to this, a function of controlling the timing at which the voltage supplied to the wiring 112 is supplied to the wiring 111. As another example, when a signal (for example, a signal CK1) is input to the wiring 112, The transistor 101_1 transmits a signal input to the wiring 112 in accordance with the potential of the node n1. In this case, the signal CK1 has a function of controlling the timing of supplying the signal to the line 111. When the signal CK1 is at the L level, the transistor 101_1 supplies the signal CK1 at the L level to the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the timing of supplying the signal OU. It has the function of controlling the timing when T becomes L level. Then, the transistor 101_1 supplies a signal CK1 of H level to the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the timing when the signal OUT is at H level. At this time, node n1 is in a floating state. In this case, the transistor 101_1 can be connected to the potential of the wiring 111. The transistor 101 has a function of increasing the potential of the node n1 in response to a rise in the voltage Vcc. The transistor 101_1 has a function of performing a bootstrap operation. The potential state of the signal OUT is set by turning on or off according to the signal input to the port. It has the function of controlling whether or not to set it.

[0115] The transistor 101_2 changes the potential of the wiring 112 to the potential of the wiring 111 in accordance with the potential of the node n2. For example, the wiring 112 has a function of controlling the timing at which a voltage (for example, a voltage When a voltage V1 or V2 is supplied, the transistor 101_2 is connected to the potential of the node n2. In response to this, a function of controlling the timing at which the voltage supplied to the wiring 112 is supplied to the wiring 111. As another example, when a signal (for example, a signal CK1) is input to the wiring 112, The transistor 101_2 transmits a signal input to the wiring 112 in accordance with the potential of the node n2. In this case, the signal CK1 has a function of controlling the timing of supplying the signal to the line 111. When the signal CK1 is at the L level, the transistor 101_2 supplies the signal CK1 at the L level to the wiring 111. Alternatively, the transistor 101_2 has a function of controlling the timing of supplying the signal OU. It has the function of controlling the timing when T becomes L level. Then, the transistor 101_2 supplies the signal CK1 of H level to the wiring 111. Alternatively, the transistor 101_2 has a function of controlling the switching when the signal OUT is at H level. At this time, node n2 is in a floating state. In this case, the transistor 101_2 can be connected to the potential of the wiring 111. The transistor 101 has a function of increasing the potential of the node n2 in response to a rise in the voltage Vcc. The transistor 101_1 has a function of performing a bootstrap operation. The potential state of the signal OUT is set by turning on or off according to the signal input to the port. It has the function of controlling whether or not to set it.

[0116] As shown in FIG. 4B, the semiconductor device of this embodiment mode may include a circuit 10. For example, the circuit 10 includes a wiring 113, a wiring 114, a wiring 115_1, a wiring 115_2, a wiring 116, a wiring 117, a wiring 118, a wiring 119, a wiring 120, a wiring 121, a wiring 122, a wiring 123, a wiring 124, a wiring 125, a wiring 126, a wiring 127, a wiring 5_2, wiring 116, wiring 117, the gate of transistor 101_1, transistor 10 1_2 and / or the wiring 111. However, it is not limited to this. Depending on the configuration of circuit 10, circuit 10 may be connected to other wires or other nodes. Alternatively, the circuit 10 includes the wiring 113, the wiring 114, the wiring 115_1, and the wiring 115_2. , wiring 116, wiring 117, the gate of the transistor 101_1, and the transistor 101_2 It is possible that the gate of the transistor 111 is not connected to the wiring 111.

[0117] Circuit 10 often includes one or more transistors. The polarity of the N-channel transistor is often the same as that of the N-channel transistors 101_1 and 101_2. However, the circuit 10 is not limited to this, and may be a P-channel transistor. Alternatively, the circuit 10 may have an N-channel transistor and a P-channel transistor. In other words, the circuit 10 may be a CMOS circuit. It is possible that it is a road.

[0118] As in the first embodiment, the signal OUT is output from the wiring 111. As in the first embodiment, the signal CK1 is input to the CK When the signal CK2 is written as 2, the signal CK2 is an inverted signal of the signal CK1, or a signal whose phase is 1 phase from the signal CK1. In most cases, the signal is shifted by 80°. Voltage V2 is supplied to wiring 113. Voltage V2 can function as a power supply voltage, a reference voltage, or a positive power supply voltage. Therefore, the wiring 113 can function as a power supply line. The signal SP is input. The signal SP can function as a start signal. Therefore, the wiring 114 can function as a signal line. The wiring 114 is connected to the wiring 11 of the semiconductor device in another stage (for example, the previous stage). When connected to 1, the signal SP can be used as a select signal, transfer signal, start signal, reset signal, The wiring 114 can function as a gate signal or a scanning signal. The wiring 115_1 can function as a gate signal line or a scanning line. The signal SEL1 is input every certain period (for example, every frame period). ) by repeating H level and L level, as a clock signal, selection signal, or control signal. Therefore, the wiring 115_1 can function as a signal line. The signal SEL2 is input to the wiring 115_2. , an inverted signal of signal SEL1, or a signal whose phase is shifted by 180° from signal SEL1. Therefore, the wiring 115_2 can function as a signal line. A signal RE is input to the input terminal 6. The signal RE functions as a reset signal. Therefore, the wiring 116 can function as a signal line. In this case, if the wiring 116 is connected to another stage (for example, the next stage), ) is connected to the wiring 111 of the semiconductor device, the signal RE is a selection signal, a transfer signal, It can function as a start signal, a reset signal, a gate signal, or a scan signal. In this case, the wiring 116 can function as a gate signal line or a scanning line. The wiring 117 is supplied with a voltage V1. The voltage V1 is a power supply voltage, a reference voltage, The wiring 11 can function as a voltage, a ground voltage, or a negative power supply voltage. 7 can function as a power supply line. However, it is not limited to this, and the wiring 111 , wiring 112, wiring 113, wiring 114, wiring 115_1, wiring 115_2, wiring 116 , and the wiring 117 can be supplied with various signals, various voltages, or various currents. is.

[0119] Note that the signal CK1 or the signal CK2 can be balanced or unbalanced. Similarly, the signal SEL1 or the signal SEL2 can be balanced. It is possible for the state to be non-equilibrium (also called disequilibrium).

[0120] The circuit 10 includes a voltage V1, a signal CK2, a signal SP, a signal SEL1, a signal SEL2, and a signal RE. , the potential of the node n1, the potential of the node n2, and / or the signal OUT, , the timing of supplying a signal or a voltage to the node n2 and / or the wiring 111. Alternatively, the circuit 10 may have a function of supplying a voltage V1, a signal CK2, a signal SP, a signal SEL1, , signal SEL2, signal RE, voltage V1, the potential of node n1, the potential of node n2, and / or In response to the signal OUT, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring 11 For example, the circuit 10 controls the potential of the H-level signal or voltage V2. The circuit 10 has a function of supplying a signal to the node n1 and / or the node n2. A signal or voltage V1 of the bell is supplied to the node n1, the node n2, and / or the wiring 111. Alternatively, the circuit 10 may provide a signal or voltage to the node n1 and / or the node n2. Alternatively, the circuit 10 has a function of not supplying a voltage to the node n1 and / or the node n2. Alternatively, the circuit 10 has a function of increasing the potential of the node n1, The potential of the node n2 and / or the potential of the wiring 111 is reduced or maintained. The circuit 10 has a function of keeping the node n1 and / or the node n2 in a floating state. However, the circuit 10 may have various other functions, without being limited thereto. , circuit 10 need not have all of the above functions.

[0121] Next, an example of the operation of this embodiment will be described. Here, as an example, the operation of FIG. The operation of the semiconductor device will be described with reference to the timing chart of FIG. 4(C) and FIGS. 5(A) to 5(C). 4(C) and FIG. 6(A) to FIG. 6(E). The port includes signals CK1, CK2, SP, RE, and the potential of node n1 (Va1). , the potential of the node n2 (Va2), and the signal OUT. The explanation of the parts common to the chart will be omitted. The operation can be applied to the contents described in this embodiment or the contents described in other embodiments. It is Noh.

[0122] First, in a period A1, as shown in FIG. 5A, the signal SP goes to H level, and the signal S EL1 becomes H level and signal SEL2 becomes L level. The circuit 10 supplies the signal SP or voltage V2 of the line to the node n1. After that, the potential of the node n1 is V1+Vth101_1(Vth10 1_1: The threshold voltage of transistor 101_1) + Vx, 01_1 is turned on. At this time, Vx is greater than 0. Therefore, the wiring 112 and the wiring The line 111 is in a conductive state via the transistor 101_1, so that the L-level signal C K1 is supplied from the wiring 112 to the wiring 111 via the transistor 101_1. As a result, the signal OUT goes low. After that, the potential of the node n1 rises further. Therefore, the supply of voltage or signal from the circuit 10 to the node n1 is stopped, and the circuit 10 and the node As a result, node n1 is in a floating state, and the voltage of node n1 The voltage is maintained at V1+Vth101_1+Vx.

[0123] During the period A1, the circuit 10 supplies an L-level signal or a voltage V2 to the node n2. It is possible to provide

[0124] Note that in the period A1, the circuit 10 supplies an L-level signal or a voltage V2 to the wiring 111. It is possible to provide

[0125] Next, in a period B1, as shown in FIG. 5(B), the signal SP goes to the L level, and the signal S EL1 remains at the H level, and signal SEL2 remains at the L level. 0 remains without supplying any voltage or signal to node n1. Therefore, node n1 is It remains in a floating state, and the potential of the node n1 remains V1 + Vth101_1 + Vx. That is, the transistor 101_1 remains on, so the wiring 112 and the wiring 111 At this time, the signal CK1 is kept in a conducting state through the transistor 101_1. The potential of the wiring 111 starts to rise. Since n1 remains floating, the potential of the node n1 is It rises due to the parasitic capacitance between the first terminal and the second terminal. This is known as bootstrap operation. In this way, the potential of the node n1 rises to V2+Vth101_1+Vx. , the potential of the wiring 111 can be increased to V2. T becomes H level.

[0126] During the period B1, the circuit 10 supplies an L-level signal or a voltage V2 to the node n2. It is possible to provide

[0127] In addition, during the period B1, the circuit 10 does not supply a signal or a voltage to the wiring 111. It is possible to do this.

[0128] Next, during a period C1, the signal RE goes to H level as shown in FIG. The circuit 10 supplies a low-level signal or voltage V1 to the node n1, the node n2, and / or the Then, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring Therefore, the potential of the transistor 101_1 and the transistor 10 1_2 is turned off, so that the wiring 112 and the wiring 111 are in a non-conductive state. OUT becomes L level.

[0129] In the period C1, the signal It is possible to set the timing when CK1 decreases to L level earlier. Then, as shown in FIG. 5(E), the signal CK1 at L level is transmitted from the wiring 112 to the transistor. The potential can be supplied to the wiring 111 via the transistor 101_1. The channel width of 1_1 is, for example, In this case, the channel width of the wiring 111 is often larger than that of other transistors. In other words, the fall time of the signal OUT can be shortened. Therefore, in order to decrease the potential of the wiring 111, the circuit 10 needs to generate an L-level signal or When a voltage V1 is supplied to the wiring 111, and when a signal CK1 at a low level is supplied to the transistor When the signal is supplied to the wiring 111 through the first terminal 101_1, or when the signal is supplied to the circuit 10 through the first terminal 101_2, the signal is at an L level or A voltage V1 is supplied to the wiring 111, and a signal CK1 at a low level is supplied to the transistor from the wiring 112. There are three patterns: one in which the power is supplied to the wiring 111 via the power supply 101_1;

[0130] Next, during periods D1 and E1, as shown in FIG. 5(D), the circuit 10 generates a voltage V A signal of 1 or L level is supplied to the node n1, the node n2, and / or the wiring 111. Then, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring 111 is V1 Therefore, the transistor 101_1 and the transistor 101_2 remain in the off state. Therefore, the wiring 112 and the wiring 111 remain in a non-conductive state. UT remains at the L level.

[0131] Next, in a period A2, as shown in FIG. 6A, the signal SP goes to H level, and the signal S EL1 goes to L level and signal SEL2 goes to H level. The circuit 10 supplies the signal SP or voltage V2 of the line to the node n2. After that, the potential of the node n2 is V1+Vth101_2(Vth10 1_2: The threshold voltage of transistor 101_2) + Vx, 01_2 is turned on. At this time, Vx is greater than 0. Therefore, the wiring 112 and the wiring The line 111 is in a conductive state via the transistor 101_2, so that the L-level signal C K1 is supplied from the wiring 112 to the wiring 111 via the transistor 101_2. As a result, the signal OUT goes low. After that, the potential of the node n2 rises further. Therefore, the supply of voltage or signal from the circuit 10 to the node n2 is stopped, and the circuit 10 and the node As a result, node n2 is in a floating state, and the voltage of node n2 The voltage is maintained at V1+Vth101_2+Vx.

[0132] During the period A2, the circuit 10 supplies an L-level signal or a voltage V2 to the node n1. It is possible to provide

[0133] Note that during the period A2, the circuit 10 supplies an L-level signal or a voltage V2 to the wiring 111. It is possible to provide

[0134] Next, in a period B2, as shown in FIG. 6B, the signal SP goes to the L level, and the signal S EL1 remains at the L level, and signal SEL2 remains at the H level. 0 remains without supplying any voltage or signal to node n2. Therefore, node n2 is It remains in a floating state, and the potential of node n2 remains V1 + Vth101_2 + Vx. That is, the transistor 101_2 remains on, so the wiring 112 and the wiring 111 At this time, the signal CK1 is kept in a conducting state through the transistor 101_2. The potential of the wiring 111 starts to rise. Since n2 remains floating, the potential of the node n2 is It rises due to the parasitic capacitance between the first terminal and the second terminal. This is known as bootstrap operation. In this way, the potential of the node n2 rises to V2+Vth101_2+Vx. This allows the potential of the wiring 111 to rise to V2. T becomes H level.

[0135] During the period B2, the circuit 10 supplies an L-level signal or a voltage V2 to the node n1. It is possible to provide

[0136] Note that the circuit 10 does not supply a signal or a voltage to the wiring 111 during the period B2. It is possible to do this.

[0137] Next, during a period C2, the signal RE goes to H level as shown in FIG. The circuit 10 supplies a low-level signal or voltage V2 to the node n1, the node n2, and / or the Then, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring Therefore, the potential of the transistor 101_1 and the transistor 10 1_2 is turned off, so that the wiring 112 and the wiring 111 are in a non-conductive state. OUT becomes L level.

[0138] In the period C2, the signal CK1 is lowered before the potential of the node n2 decreases. It is possible to set the timing at which the signal decreases to the L level earlier. As shown in FIG. 6(E), the signal CK1 at L level is supplied from the wiring 112 to the transistor 10 The voltage can be supplied to the wiring 111 through the transistor 101_2. For example, when other transistors are included, the channel width is set to be smaller than the channel width of the other transistors. Since the potential of the wiring 111 is large in most cases, the potential of the wiring 111 can be quickly reduced. The fall time of OUT can be shortened. For example, when the circuit 10 supplies an L-level signal or voltage V1 to the wiring 111, , the L-level signal CK1 is input from the wiring 112 to the wiring 111 via the transistor 101_2. When the signal or voltage V1 is supplied to the wiring 111, or when the circuit 10 supplies an L-level signal or voltage V1 to the wiring 111, Furthermore, the signal CK1 at the L level is supplied from the wiring 112 to the wiring 111 via the transistor 101_2. In some cases, they are supplied to

[0139] Next, during periods D2 and E2, as shown in FIG. 6(D), the circuit 10 generates a voltage V A signal of 1 or L level is supplied to the node n1, the node n2, and / or the wiring 111. Then, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring 111 is V1 Therefore, the transistor 101_1 and the transistor 101_2 remain in the off state. Therefore, the wiring 112 and the wiring 111 remain in a non-conductive state. UT remains at the L level.

[0140] As described above, in the period T1, the transistor 101_2 is turned off, and in the period T2, Since the transistor 101_1 is turned off, the transistor 101_1 and the transistor The number of times each of transistors 101_1 and 101_2 is turned on is Therefore, the time that each of the transistors 101_1 and 101_2 is turned on is reduced. Therefore, it is possible to suppress the deterioration of the characteristics of the transistors 01_1 and 101_2.

[0141] As described above, the semiconductor device of the present embodiment can suppress the deterioration of the transistor characteristics. In addition, the H level potential of the signal OUT can be raised to V2, As a result, the time that the transistor in the pixel is turned on can be extended. This allows the video signal to be written in a short time, improving the display quality. Alternatively, the fall time and rise time of the signal OUT can be shortened. Therefore, the video signal for the pixels in another row is written to the pixels in the selected row. As a result, the display quality can be improved. Since the variation in the fall time of the signal OUT can be suppressed, the pixel This reduces the variation in the effect of feedthrough on the video signal being displayed. It is possible to suppress unevenness.

[0142] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors is set to N-channel type or P-channel type. Therefore, compared to CMOS circuits, the number of processes can be reduced. It is possible to reduce the number of pixels, improve the yield, improve the reliability, or reduce the cost. When all transistors are N-channel, including the semiconductor layer of the transistor, For example, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor may be used. However, transistors using these semiconductors tend to deteriorate easily. However, the semiconductor device of this embodiment can suppress the deterioration of the transistor. .

[0143] Alternatively, the transistor may be degraded so that the semiconductor device can continue to operate. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of this embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0144] The circuit 10 includes periods C1, D1, E1, A2, B2, C2, and During the period D2 and / or the period E2, a signal or voltage V1 of L level is supplied to the node n1. It is possible to supply a voltage or signal to node n1, or not to supply a voltage or signal to node n1. However, it is not limited to this.

[0145] The circuit 10 includes periods A1, B1, C1, D1, E1, C2, and During the period D2 and / or the period E2, a signal or voltage V1 at an L level is supplied to the node n2. It is possible to supply a voltage or signal to node n2, or not to supply a voltage or signal to node n2. However, it is not limited to this.

[0146] The circuit 10 includes periods A1, C1, D1, E1, A2, C2, and During the period D2 and / or the period E2, a signal or voltage V1 of L level is supplied to the wiring 111. It is possible to supply a voltage or a signal to the wiring 111, or not to supply a voltage or a signal to the wiring 111. However, it is not limited to this.

[0147] Note that the signals CK1 and CK2 can be unbalanced. For example, if the period during which the signal is at H level is shorter than the period during which the signal is at L level, By doing so, in the period C1 or the period C2, Since the L-level signal CK1 is supplied to the wiring 111, the falling time of the signal OUT is Alternatively, when the wiring 111 is arranged to extend to the pixel portion, the wiring 111 can be shortened. It is possible to prevent writing of unauthorized video signals. However, it is not limited to this. During this period, it is possible for the period during which the H level is reached to be longer than the period during which the L level is reached.

[0148] Note that the semiconductor device of this embodiment mode can use a multiphase clock signal. For example, if n (n is a natural number) is used, then a clock signal with n+1 phases has a period of 1 It is a clock signal with n+1 clock signals that are shifted by n+1 periods. Any two of the signals can be input to the wiring 112 and the wiring 113, respectively. 7(B) shows an example of the timing when a three-phase clock signal is used in a semiconductor device. Charts include, but are not limited to:

[0149] The larger n is, the lower the clock frequency becomes, which can reduce power consumption. However, if n is too large, the number of signals increases, which increases the layout area. Therefore, n<8 is required. It is preferable that n<6. It is even more preferable that n=4. Alternatively, n=3 is preferred, but the present invention is not limited to this.

[0150] Since the transistors 101_1 and 101_2 have the same function, The channel width of the transistor 101_1 and the channel width of the transistor 101_2 are It is preferable that the transistor sizes are roughly equal. By this, the current supply capabilities of the transistors can be made roughly equal. Therefore, the degree of deterioration of the transistors can be made roughly equal. Even if the capacitor is switched, the waveform of the signal OUT can be made roughly the same. , but is not limited to this, the channel width of the transistor 101_1 and the channel width of the transistor 101_2 The channel width of the MOSFET may be different from that of the MOSFET.

[0151] When referring to the channel width of a transistor, this is the W / L (W: channel This can be rephrased as the ratio of the channel width (L: channel length).

[0152] The transistors 101_1 and 101_2 are turned on during the same period. For example, in the period B1 or the period B2, the transistor 101_ 1 and transistor 101_2 are turned on, so that only one of the transistors is turned on. Therefore, the potential of the wiring 111 can be increased more quickly than when the signal OU is turned on. The rise time of T can be shortened.

[0153] As shown in FIG. 8A, the wiring 112 may be divided into a plurality of wirings 112A to 112B. The first terminal of the transistor 101_1 can be connected to the wiring 112. A, and the first terminal of the transistor 101_2 can be connected to the wiring 112B. In addition, the wirings 112A to 112B can be connected to other wirings or nodes. It is possible to do this.

[0154] As in FIG. 8(A), in FIGS. 4(A) and 4(B), the wiring 112 is divided into a plurality of wirings ( For example, it is possible to divide the wiring into wirings 112A and 112B.

[0155] As shown in FIG. 8B, a capacitance is formed between the gate and the second terminal of the transistor 101_1. A capacitance element 121_1 is connected between the gate of the transistor 101_2 and the second terminal thereof. It is possible to connect element 121_2. By doing so, the bootstrap During operation, the potential of the node n1 or the potential of the node n2 tends to rise. The Vgs of the transistors 101_1 and 101_2 can be increased. Therefore, the channel width of these transistors can be reduced. The fall time or rise time can be shortened, but is not limited to this. It is possible to omit either the capacitor 121_1 or the capacitor 121_2. The capacitance element is connected to the gate of the transistor (node ​​n1, node n2) and the second terminal (wire 1). 12) can be connected between the capacitor element, for example, MIS capacitor. It is possible to use.

[0156] Note that the material of one electrode of each of the capacitors 121_1 and 121_2 is, for example, a transistor. It is preferable that the gate electrode is made of the same material as that of the gates of the transistors 101_1 and 101_2. The other electrodes of the capacitors 121_1 and 121_2 are preferably made of a material similar to that of the transistor. The material is the same as that of the source or drain of the transistor 101_1 and the transistor 101_2. This is preferable. By doing so, the layout area can be reduced. However, the capacitance value of the capacitor 121_1 can be increased. As the materials of one electrode and the other electrode of the capacitor 121_2, various It is possible to use materials.

[0157] The capacitance value of the capacitor 121_1 and the capacitance value of the capacitor 121_2 are approximately equal. Alternatively, it is preferable that the area where one electrode and the other electrode of the capacitor 121_1 overlap with each other is The area where one electrode of the capacitor 121_2 overlaps with the other electrode is approximately equal to By doing so, even when the transistors are switched, the transistor The Vgs of the transistor 101_1 and the Vgs of the transistor 101_2 can be made approximately equal. Therefore, the waveform of the signal OUT can be made roughly the same. However, this is not limited to this. The capacitance value of the capacitance element 121_1 and the capacitance value of the capacitance element 121_2 are different from each other. Alternatively, the area where one electrode and the other electrode of the capacitor 121_1 overlap with each other and The area where one electrode and the other electrode of the capacitor 121_2 overlap can be different. be.

[0158] As in FIG. 8(B), in FIGS. 4(A) to 4(B) and FIG. 8(A), the transistor A capacitance element 121_1 can be connected between the gate of the master 101_1 and the second terminal. Alternatively, a capacitor 121_2 is provided between the gate and the second terminal of the transistor 101_2. It is possible to connect.

[0159] As shown in FIG. 8C, the circuit 100 includes transistors 101_1 to 101_N. It is possible to have a plurality of transistors such as transistors 101_1 to 101_ The first terminals of the transistors 101_1 to 101_N are connected to the wiring 112, and the second terminals of the transistors 101_1 to 101_N are connected to the wiring 112. The terminals are connected to the wiring 111. The gates of the transistors 101_1 to 101_N are connected to the wiring 111. are nodes n1 to nN, respectively. The configuration of FIG. 8(C) is the same as that of the first embodiment. This corresponds to the configuration when a transistor is used as a switch. 1_1 to 101_N have the same functions as the switches 11_1 to 11_N.

[0160] The larger N, the more times each transistor is turned on, or The time that the transistor is on is shortened, which can suppress the deterioration of the transistor characteristics. However, if N is too large, the number of transistors increases, which increases the circuit size. Therefore, it is preferable that N<6. It is more preferable that N<4. More preferably, N=3 or N=2.

[0161] As in FIG. 8(C), in FIGS. 4(A) to 4(B) and 8(A) to 8(B), The circuit 100 includes a plurality of transistors 101_1 to 101_N. In particular, in FIG. 8A, the circuit 100 includes transistors 101_1 to When there are multiple transistors 101_N, the wiring 112 is divided into N wirings. In particular, in FIG. 8B, the circuit 100 includes transistors 101_1 to When a plurality of transistors 101_1 to 101_N are provided, the transistors 101_1 to 101_N are A capacitance element is provided between the gate of N and the second terminal of each of the transistors 101_1 to 101_N. It is possible to connect

[0162] As shown in FIG. 8D, the transistor 101_1 is connected to one terminal (hereinafter referred to as the positive terminal). The negative terminal of the negative electrode 111 is connected to the node n1, and the negative terminal of the negative electrode 111 is connected to the wiring 111. Similarly, the transistor 101_2, one terminal (hereinafter also referred to as the positive terminal) is connected to the node n2, and the other terminal (hereinafter also referred to as the negative electrode) is replaced with the diode 101a_2 connected to the wiring 111. However, it is not limited to this, and as shown in FIG. The first terminal of the transistor 101_1 is connected to the node n1. Similarly, the transistor 101_2 can be configured as a diode. By connecting the first terminal to the node n2, the transistor 101_2 is in diode connection. It is possible to have a continuous configuration.

[0163] As in Figs. 8(D) to (E), Figs. 4(A) to (B) and Figs. 8(A) to (C) Even if the transistor is a diode, it is possible to replace the transistor with a diode. can be configured in a diode-connected configuration.

[0164] As shown in FIG. 8(F), the output signal can be divided into two. The semiconductor device may further include a circuit 120. The circuit 120 may include a transistor The circuit 120 includes a plurality of transistors 122_1 to 122_2. The transistors 122_1 and 122_2 each have the same function as the transistor 1. The first terminal of the transistor 122_1 has the same function as those of the transistors 01_1 to 101_2. The first terminal of the transistor 122_1 is connected to the wiring 211, and the second terminal of the transistor 122_2 is connected to the wiring 211. The gate of the transistor 122_1 is connected to the node n1. The first terminal of the transistor 122_2 is connected to the wiring 112, and the second terminal of the transistor 122_2 is connected to the wiring 211. and the gate of the transistor 122_2 is connected to the node n2. The transistor 101_1 and the transistor 122_1 are controlled at the same timing. The transistor 101_2 and the transistor 122_2 are controlled at the same timing. Therefore, the signal output from the wiring 211 has a timing approximately equal to that of the signal OUT. The timing will be H level or L level.

[0165] Note that when the signal output from the wiring 111 functions as a gate signal or a selection signal, The signal output from the wiring 211 may be a transfer signal, a reset signal, a gate signal, or the like. In this case, the load of the wiring 111 is the load of the wiring 211. Since the channel width of the transistor 101_1 is often larger than the Preferably, the channel width of the transistor 102 is larger than that of the transistor 122_1. The channel width of the transistor 122_2 is preferably larger than the channel width of the transistor 122_2. However, it is not limited to this.

[0166] As in FIG. 8(F), in FIGS. 4(A) to 4(B) and 8(A) to 8(E), The semiconductor device can split the output signal into two by including the circuit 120. The circuit 120 includes a plurality of transistors 122_1 to 122_2. In particular, in FIG. 8C, the circuit 100 may include a transistor. When the circuit 120 has a plurality of transistors 101_1 to 101_N, the circuit 120 It is possible to have transistors.

[0167] Next, a specific example of the circuit 10 will be described. First, referring to FIG. 9(A), the circuit 10 A configuration including a circuit 200 will be described. The circuit 200 represents a part of the circuit 10. The circuit 200 includes the wiring 114, the wiring 115_1, the wiring 115_2, the node n1, and / or , and the node n2. However, this is not a limitation, and the circuit 200 may be connected to other wirings or It can be connected to other nodes.

[0168] Circuit 200 often includes one or more transistors. The polarity of the N-channel transistor is often the same as that of the N-channel transistors 101_1 and 101_2. However, the circuit 200 is not limited to a P-channel transistor. Alternatively, the circuit 200 may include an N-channel transistor. and a P-channel transistor. That is, the circuit 200 can have a C It can be a MOS circuit.

[0169] The circuit 200 receives the signal SP, the signal SEL1, the signal SEL2, the potential of the node n1, and / or , a signal or voltage is supplied to the node n1 and / or the node n2 depending on the potential of the node n2. In this way, the circuit 200 controls the timing of supplying the potential of the node n1. For example, the circuit 200 has a function of controlling the potential of the H level and / or the potential of the node n2. The function of the bell is to supply a signal or voltage V2 to the node n1 and / or the node n2. Alternatively, the circuit 200 may apply a low-level signal or voltage V1 to the node n1 and / or the node Alternatively, the circuit 200 has a function of supplying a signal or a voltage to the nodes n1 and n2. Alternatively, the circuit 200 may have a function of not supplying the voltage of the node n1 to the node n2. The circuit 200 has a function of increasing the potential of the node n1 and / or the potential of the node n2. The potential of the node n1 and / or the potential of the node n2 is reduced or maintained. The circuit 200 has a function of putting the node n1 and / or the node n2 into a floating state.

[0170] Here, an example of the circuit 200 will be described with reference to FIG. The transistor 2 has a plurality of transistors 201_1 to 201_2. A first terminal of the transistor 01_1 is connected to the wiring 115_1, and a second terminal of the transistor 201_1 is connected to the wiring 115_1. is connected to the gate of the transistor 101_1, and the gate of the transistor 201_1 is The first terminal of the transistor 201_2 is connected to the wiring 114. The first terminal of the transistor 201_2 is connected to the wiring 115_2. The second terminal of the transistor 201_2 is connected to the gate of the transistor 101_2. The gate of the transistor 201_2 is connected to the wiring 114. However, various configurations of the circuit 200 are possible.

[0171] The transistor 201_1 and the transistor 201_2 are the same as the transistors 101_1 and 101_2. The polarity of the transistor 101_1 is preferably the same as that of the transistor 101_2, and the transistor 101_2 is an N-channel type. However, the transistor 201_1 and / or the transistor 201_2 may be can be of the P-channel type.

[0172] The transistor 201_1 is connected to the wiring 115_1 and the node n1 in response to the potential of the wiring 114. Alternatively, the transistor 201_1 has a function of controlling the conduction state of the wiring 114. The potential of the wiring 115_1 is supplied to the node n1 in accordance with the potential of the transistor 115_2. The register 201_1 has a function of being turned on or off in response to the signal SP, or The register 201_1 controls whether or not the signal SEL1 is input to the transistor 101_1. Alternatively, the transistor 201_1 may be turned on or off to output a signal. The transistor 201_2 has a function of controlling whether or not to set the potential state of OUT. , a function of controlling conduction between the wiring 115_2 and the node n2 in accordance with the potential of the wiring 114. Alternatively, the transistor 201_2 changes the potential of the wiring 115_ The transistor 201_2 has a function of supplying a potential of the signal The transistor 201_2 has a function of being turned on or off depending on the SP. It has a function of controlling whether or not the signal SEL2 is input to the transistor 101_2. The transistor 201_2 sets the potential state of the signal OUT by being turned on or off. It has the function of controlling whether or not

[0173] The operation of the semiconductor device in FIG. 9A will be described. Here, the circuit of the circuit 200 will be taken as an example. The case where the circuit configuration is the circuit configuration shown in FIG. As shown in FIG. 10(A), the signal SP becomes H level, so that the transistors 201_1 and Therefore, the signal SEL1 at the H level is applied to the wiring 11. 5_1 to the node n1 via the transistor 201_1, and the L-level signal SE L2 is supplied to the node n2 from the wiring 115_2 through the transistor 201_2. Thus, the potential of the node n1 starts to rise and reaches V2. The potential of the node n1 is changed from the potential (V2) of the wiring 114 to the threshold voltage (V When the voltage rises to the value (V2-Vth201_1) obtained by subtracting Therefore, the potential of the node n1 is V2-Vth201_1. The player will then become levitating while maintaining their current position.

[0174] During the period B1 to E1, the signal SP is at the L level, so that the transistors 201_1 and Therefore, the wiring 115_1 and the node n1 are electrically disconnected. The wiring 115_2 and the node n2 are brought into a non-conductive state. 10B is a schematic diagram of the semiconductor device in the period C1. 10C is a schematic diagram of the semiconductor device in the periods D1 and E1, and FIG. Shown below.

[0175] Next, in period A2, as shown in FIG. 10(E), the signal SP goes to H level, The transistor 201_1 and the transistor 201_2 are turned on. The signal SEL1 is supplied from the wiring 115_1 to the node n1 through the transistor 201_1. The signal SEL2 at H level is supplied from the wiring 115_2 through the transistor 201_2. Thus, the potential of node n1 becomes V1, and the potential of node n2 becomes V2. After that, the potential of the node n2 changes from the potential (V2) of the wiring 114 to the potential (V3) of the transistor 116. The value obtained by subtracting the threshold voltage (Vth201_2) of the first MOS transistor 201_2 from the threshold voltage (Vth201_2) of the first MOS transistor 201_2 is (V2-Vth201_2). When the potential of the node n2 rises to The potential is maintained at V2-Vth201_2 and the potential is set to a floating state.

[0176] During the period B2 to E2, the signal SP is at the L level, so that the transistors 201_1 and Therefore, the wiring 115_1 and the node n1 are electrically disconnected. The wiring 115_2 and the node n2 are brought into a non-conductive state. 10(F) shows a schematic diagram of the semiconductor device in the period C2. 10G, and a schematic diagram of the semiconductor device in the periods D2 and E2 is shown in FIG. 10H. Shown below.

[0177] As described above, by configuring the circuit 10, any one of the transistors in the circuit 100 can be The transistors in circuit 100 can be selectively turned on or off. Even when the transistor is turned off, a potential is applied to the gate of the transistor to be turned off from the circuit 10, so that the floating It is possible to prevent the device from becoming idle.

[0178] Since the transistors 201_1 and 201_2 have the same function, The channel width of the transistor 201_1 and the channel width of the transistor 201_2 are It is preferable that the transistor sizes are roughly equal. By doing so, the current supply capacity can be made roughly equal. Therefore, by switching between transistors, In this case, the potential of the node n1 and the potential of the node n2 can be made approximately equal, so that the signal The waveform of the signal OUT can be roughly the same. The channel width of the transistor 201_1 and the channel width of the transistor 201_2 are different. It is possible to do this.

[0179] The load of the transistor 201_1 (for example, node n1) is Since the load of the transistor 201_1 is smaller than the load of the other transistor (for example, the wiring 111), The channel width is preferably smaller than the channel width of the transistor 101_1. The load of the transistor 201_2 (for example, node n2) is the load of the transistor 101_2. Since the load (for example, the wiring 111) is often smaller than the channel of the transistor 201_2, The channel width of the transistor 101_2 is preferably smaller than the channel width of the transistor 101_3. However, the channel width of the transistor 201_1 is not limited to the above. Alternatively, the channel width of the transistor 201_2 can be larger than , can be larger than the channel width of the transistor 101_2.

[0180] 9C, the circuit 100 is configured as shown in FIG. 8C. 1 to 101_N, the circuit 200 includes transistors 2 It is possible to have multiple transistors 01_1 to 201_N. The first terminals of the capacitors 201_1 to 201_N are connected to the wirings 115_1 to 115_N, respectively. The second terminals of the transistors 201_1 to 201_N are connected to the nodes n1 to nN. The gates of the transistors 201_1 to 201_N are connected to the wiring 114.

[0181] As shown in FIG. 9(D), the wiring 114 may be divided into a plurality of wirings 114A to 114B. Therefore, the wirings 114A to 114B can be divided into the same wirings as the wiring 114. The gate of the transistor 201_1 is connected to the wiring 114A. The gate of the transistor 201_2 is connected to the wiring 114B, and the gate of the transistor 201_3 is connected to the wiring 114B. Signals of approximately the same waveform are input to the line 114A and the line 114B. and separate signals can be input.

[0182] As in FIG. 9D, the wiring 114 is divided into a plurality of wirings in FIG. 9C. It is possible.

[0183] As shown in FIG. 9E, the first terminal of the transistor 201_1 and the second terminal of the transistor 201_2 The first terminal of the first terminal 01_2 can be connected to the same wiring. First terminals of the transistors 201_1 and 201_2 are connected to the wiring 115_1. However, the first terminals of the transistors 201_1 to 201_2 are not limited to this. It is possible to connect to various wirings. For example, the transistors 201_1 to 201_ The first terminal of the second transistor 112 may be connected to the wiring 113 or a wiring to which the signal CK2 is input. It is possible.

[0184] As in FIG. 9(E), in FIGS. 9(C) to 9(D), the transistors 201_1 to The first terminal of 201_2 can be connected to the same wiring. In this case, the first terminals of the transistors 201_1 to 201_N are connected to the same wiring. is possible.

[0185] As shown in FIG. 9F, the first terminal of the transistor 201_1 is connected to the wiring 114. The second terminal of the transistor 201_1 is connected to the node n1, and the second terminal of the transistor 201_2 is connected to the node n2. The gate of the transistor 201_1 can be connected to the wiring 115_1. a first terminal of the transistor 201_1 connected to the wiring 114, and a second terminal of the transistor 201_2 connected to the node n2 The gate of the transistor 201_2 can be connected to the wiring 115_2. In this case, during the period T1, the signal SEL1 is at the H level, and the signal SEL2 is at the L level. level, transistor 201_1 is turned on and transistor 201_2 Therefore, in the period A1, the signal SP at the H level is transmitted from the wiring 114. Since the voltage is supplied to the node n1 through the transistor 201_1, the potential of the node n1 rises. On the other hand, during the period T2, the signal SEL1 is at the L level and the signal SEL2 is at the H level. , the transistor 201_1 is turned off and the transistor 201_2 is turned on. Therefore, during the period A2, the signal SP at H level is transmitted from the wiring 114 to the transistor. Since the voltage is supplied to the node n2 via the capacitor 201_2, the potential of the node n2 rises.

[0186] As shown in FIG. 11A, the second terminal of the transistor 201_1 and the node n1 A diode-connected transistor 202_1 may be connected between the Similarly, a diode is provided between the second terminal of the transistor 201_2 and the node n2. The transistor 202_2 can be connected in a connected configuration. The first terminal of the transistor 202_1 is connected to the second terminal of the transistor 201_1. A second terminal of the transistor 202_1 is connected to the node n1, and a gate of the transistor 202_1 is connected to the node n1. The first terminal of the transistor 202_2 is connected to the second terminal of the transistor 201_1. , is connected to the second terminal of the transistor 201_2, and the second terminal of the transistor 202_2 is , and the gate of the transistor 202_2 is connected to the node n1. The transistor 201_1 and the transistor 201_2 are connected to the second terminal of the The transistor 201_1 can function as a diode. By doing so, a decrease in the potential of the node n1 can be prevented. 01_2 has a function of preventing a decrease in the potential of the node n2 by being in a non-conductive state. However, the present invention is not limited to this, and the second terminal of the transistor 201_1 and the node n1 may be , and / or various elements are provided between the second terminal of the transistor 201_2 and the node n2. Alternatively, the first terminal of the transistor 201_1 may be connected to the first terminal of the transistor 201_2. Between the first terminal of the transistor 201_2 and the line 115_1 and / or between the first terminal of the transistor 201_2 and the line 115_2 It is possible to connect various elements or circuits between the As shown in FIG. 1, the transistor 202_1 is connected to the first terminal of the transistor 201_1 and the wiring 1 15_1. Alternatively, the transistor 202_2 can be connected between the transistor 202_1 and the transistor 202_2. It can be connected between the first terminal of the transistor 201_2 and the wiring 115_2.

[0187] 11(A) to 11(B), in FIGS. 9(C) to 9(F), transistor 2 between the second terminal of the transistor 201_1 and the node n1, and between the second terminal of the transistor 201_2 and the node n 2, between the first terminal of the transistor 201_1 and the wiring 115_1, and / or between the first terminal of the transistor 201_2 and the wiring 115_1. Various elements or circuits are provided between the first terminal of the transistor 201_2 and the wiring 115_2. As an example, FIG. 11(C) shows the case where the A diode-connected transistor is connected between the second terminal of the transistor 201_1 and the node n1. The transistor 202_1 is connected between the second terminal of the transistor 201_2 and the node n2. 2 shows a configuration in which a diode-connected transistor 202_2 is connected. FIG. 11D shows an example of the first transistor 201_1 in FIG. A diode-connected transistor 202_1 is connected between the terminal and the wiring 114. A diode-connected transistor is provided between the first terminal of the transistor 201_2 and the wiring 114. 2 shows a configuration in which a transistor 202_1 having the same configuration is connected.

[0188] As shown in FIG. 11E, the circuit 200 includes transistors 203_1 to 203_2 It is possible to have a plurality of transistors such as transistors 203_1 to 203_3. _2 preferably has the same polarity as the transistors 201_1 to 201_2, and However, the present invention is not limited to this, and the transistors 203_1 to 203_3 are also of the same type. The first terminal of the transistor 203_1 can be a P-channel type. a second terminal of the transistor 203_1 connected to the wiring 117, a second terminal of the transistor 203_1 connected to the node n1, The gate of the transistor 203_1 is connected to the wiring 115_2. A first terminal of the transistor 203_2 is connected to the wiring 117, and a second terminal of the transistor 203_2 is connected to the The gate of the transistor 203_2 is connected to the wiring 115_1. However, the present invention is not limited to this. For example, the second terminal of the transistor 203_1 is connected to the node n 2. Alternatively, the second terminal of the transistor 203_2 can be connected to node n1.

[0189] The transistor 203_1 switches between the wiring 117 and the node n1 in response to the signal SEL2. By controlling the conduction state, the timing at which voltage V1 is supplied to node n1 is controlled. The transistor 203_2 has a function of switching the input voltage and can function as a switch. , by controlling the conduction state between the wiring 117 and the node n2 in response to the signal SEL1. , has a function of controlling the timing at which voltage V1 is supplied to node n2, and acts as a switch Thus, in the period T1, the transistor 203_2 Therefore, the voltage V1 is supplied to the node n2. Therefore, the transistor 201_2 is turned off. Similarly, in the period T2, the potential of the node n2 can be fixed. The voltage V1 is supplied to the node n1 by the transistor 203_1. Even if 201_1 is off, the potential of the node n1 can be fixed. Therefore, a semiconductor device that is resistant to noise can be obtained.

[0190] As shown in FIG. 11(F), the wiring 117 may be divided into a plurality of wirings 117A to 117B. The first terminal of the transistor 203_1 and the second terminal of the transistor 203_2 can be divided into lines. The first terminals of 203_2 can be connected to the wiring 117A and the wiring 117B, respectively. The wirings 117A to 117B are connected to various wirings, various elements, or various nodes. It is possible to do this.

[0191] As shown in FIG. 12A, the second terminal of the transistor 203_1 is connected to the wiring 115_ 1, and the second terminal of the transistor 203_2 is connected to the wiring 115_2. By doing so, the period during which the transistor 203_1 is turned off (for example, During a period T1, a signal of H level is input to the first terminal of the transistor 203_1. Therefore, a reverse bias is applied to the transistor 203_1, which suppresses deterioration. Similarly, during the period when the transistor 203_2 is turned off (for example, the period T2), In this case, an H-level signal is input to the first terminal of the transistor 203_2. Since a reverse bias is applied to the transistor 203_2, deterioration can be suppressed. .

[0192] As shown in FIG. 12B, the transistor 203_1 and the transistor 203_ 2 can be in a diode-connected configuration. For example, transistor 203 A first terminal of the transistor 203_1 is connected to the wiring 115_1, and a second terminal of the transistor 203_1 is connected to the wiring 115_1. The gate of the transistor 203_1 is connected to the node n1. Similarly, a first terminal of the transistor 203_2 is connected to the wiring 115_2. A second terminal of the transistor 203_2 is connected to the node n2, and a gate of the transistor 203_2 is connected to the node n3. In this case, during the period T1, the signal SEL2 becomes L level. Then, the signal SEL2 at L level is output from the wiring 115_2 through the transistor 203_2. Therefore, the potential of the node n2 is fixed to approximately V1. On the other hand, in the period T2, when the signal SEL1 becomes L level, The signal SEL1 of the line 115_1 is supplied to the node n1 through the transistor 203_1. Therefore, the potential of the node n1 can be fixed to approximately V1. However, the present invention is not limited to this. For example, the gate of the transistor 203_1 is connected to the wiring 1. Alternatively, the gate of the transistor 203_2 can be connected to the It can be connected to the line 115_2.

[0193] 11(E) to (F) and 12(A) to (B), as well as FIGS. 9(C) to (F), 11A to 11D, the circuit 200 includes transistors 203_1 to 203_2. For example, in FIG. 12(C), in FIG. 9(F), 12(D) shows a configuration in which the circuit 200 has transistors 203_1 to 203_2. 11A to 11E, the circuit 200 includes transistors 203_1 to 203_3. 12(F) shows a configuration in which the circuit 200 in FIG. 2 shows a configuration in which the semiconductor device has transistors 203_1 and 203_2.

[0194] The second terminal of the transistor 203_1 and the second terminal of the transistor 203_2 are It can be connected to various wirings or nodes. For example, as shown in FIG. The second terminal of the transistor 203_1 is connected to the second terminal of the transistor 201_1. Similarly, the second terminal of the transistor 203_2 can be connected to the 12(F), it can be connected to the second terminal of 01_2. The second terminal of the transistor 203_1 is connected to the first terminal of the transistor 201_1. Similarly, the second terminal of the transistor 203_2 is connected to the second terminal of the transistor 201_1. It is possible to connect it to the first terminal of _2.

[0195] As shown in FIG. 5F, the circuit 200 includes transistors 201_1 and 201_2. In addition, it is possible to have a plurality of transistors 203_1 to 203_2. The transistors 203_1 to 203_2 are the same as the transistors 201_1 to 201_ It is preferable that the polarity is the same as that of 2 and that it is an N-channel type. The transistors 203_1 to 203_2 may be P-channel type. A first terminal of the transistor 203_1 is connected to the wiring 114. The second terminal of the transistor 203_1 is connected to the node n1. The gate of the transistor 203_1 is connected to the wiring 1. A first terminal of the transistor 203_2 is connected to the wiring 114. The second terminal of the transistor 203_2 is connected to the node n2. The port is connected to a wiring 118. A signal CK2 is input to the wiring 118. Therefore, the wiring 118 can function as a signal line or a clock signal line. However, the present invention is not limited to this, and various signals, various voltages, or various currents may be applied to the wiring 118. The transistor 203_1 is connected to a line in response to the potential of the wiring 118. The transistor 203 has a function of controlling the conduction state between the line 114 and the node n1. The potential of the wiring 114 is supplied to the node n1 in accordance with the potential of the wiring 118. The transistor 203_2 is connected to the wiring 114 and the node n2 in response to the potential of the wiring 118. Alternatively, the transistor 203_2 has a function of controlling electrical continuity between the wiring 118 and the The potential of the wiring 114 is supplied to the node n2 in accordance with the potential. The transistors 203_1 to 203_2 may have various other functions. It is possible.

[0196] The first terminal of the transistor 203_1 and the first terminal of the transistor 203_2 are separate. The gate of the transistor 203_1 and the gate of the transistor 203_2 can be connected to each other. The gate of the transistor 203_2 can be connected to a separate wiring.

[0197] As in FIG. 5(F), FIGS. 9(C) to 9(F), 11(A) to 11(F), and 12( In A) to (F), transistors having the same functions as the transistors 203_1 to 203_2 are used. It is possible to add new transistors.

[0198] As shown in FIG. 13A, the transistors 101_1 and 101_2, the transistor P-channel transistors can be used as 201_1 and 201_2. The transistors 101p_1 and 101p_2 are The transistors 102p_1 and 102p_2 are P-channel transistors. 102_1 to 102_2, which are P-channel type. As shown, when the polarity of the transistor is a P-channel type, a voltage V1 is supplied to the wiring 113, and A voltage V2 is supplied to the line 117, and the potentials of the signals CK1, SP, RE, and node n1 are , the potential of the node n2 and the signal OUT are reversed compared to the timing chart of FIG. 4B. It should be noted that it is rotating.

[0199] As with FIG. 13(A), FIGS. 9(C) to 9(F), 11(A) to 11(F), and 12 In (A) to (F), a P-channel transistor is used as the transistor. It is possible to do this.

[0200] (Embodiment 3) In this embodiment, an example of a configuration different from that of the circuit 10 described in the second embodiment will be described. The contents described in the first and second embodiments will not be described here. The contents described in the embodiment may be appropriately combined with the contents described in the first and second embodiments. It is possible.

[0201] First, a specific example of the circuit 10 different from that in the second embodiment will be described with reference to FIG. The circuit 10 of FIG. 14 includes a circuit 300 in addition to the circuit 200. The circuit 300 is the same as the circuit 10 It should be noted that a part of the circuit 300 can be shared with the circuit 200. 0 can be shared with the circuit 300. The circuit 300 includes the wiring 113, the wiring 116, a wiring 117, the node n1, the node n2, and / or the wiring 111. However, the present invention is not limited to this, and the circuit 200 may be connected to other wirings or other nodes. is possible.

[0202] Circuit 300 often includes one or more transistors. The polarity of the N-channel transistor is often the same as that of the N-channel transistors 101_1 and 101_2. However, the circuit 300 is not limited to a P-channel transistor. Alternatively, the circuit 300 may include an N-channel transistor. and a P-channel transistor. It can be a MOS circuit.

[0203] The circuit 300 receives the signal RE, the potential of the node n1, the potential of the node n2, and / or the signal OU. Depending on the fall time of T, a signal is applied to the node n1, the node n2, and / or the wiring 111. In this way, the circuit 200 has a function of controlling the timing of supplying the voltage. The potential of the node n1, the potential of the node n2, and / or the potential of the wiring 111. For example, the circuit 200 supplies a signal or voltage V1 at an L level to the nodes n1, n2, and and / or the wiring 111.

[0204] Next, an example of the circuit 300 will be described with reference to FIG. In the example, the circuit 300 includes a plurality of transistors 301_1 to 301_2. , a transistor 302, and a plurality of transistors 303_1 to 303_2. , a transistor 304, a plurality of circuits called circuits 310_1 to 310_2, and a circuit 320 It has.

[0205] The transistors 301_1 to 301_2, the transistor 302, and the transistor 303 _1 to 303_2 and the transistor 304 are, for example, N-channel types. However, the present invention is not limited to this, and the transistors 301_1 to 301_2 and the transistor 3 02, the transistors 303_1 to 303_2, and / or the transistor 304 are P-channel It can be of the channel type.

[0206] As an example, as shown in FIG. 15B, circuits 310_1 to 310_2 and An inverter circuit can be used as 320, but it is not limited to this. As the circuits 310_1 to 310_2 and the circuit 320, various other circuits may be used. It is possible to do this.

[0207] Next, the connections of the circuit 300 in FIG. 15A will be described. A first terminal of the transistor 301_1 is connected to the wiring 117, and a second terminal of the transistor 301_1 is connected to the node n A first terminal of the transistor 301_2 is connected to the wiring 117. The second terminal of the transistor 301_2 is connected to the node n2. The first terminal of the transistor 302 is connected to the wiring 117, and the second terminal of the transistor 303 is connected to the wiring 111. The first terminal of the transistor 303_1 is connected to the wiring 117. The second terminal of the transistor 303_1 is connected to the node n1. The gate of the transistor 303_1 is connected to the wiring 1. A first terminal of the transistor 303_2 is connected to the wiring 117. The second terminal of the transistor 303_2 is connected to the node n2. The first terminal of the transistor 304 is connected to the wiring 116. The second terminal of the transistor 304 is connected to the wiring 117. The second terminal of the transistor 304 is connected to the wiring 111. The gate is connected to the wiring 116. The circuit 310_1 includes a wiring 113, a node n1, a wiring The circuit 310_2 is connected to the wiring 117 and the gate of the transistor 301_1. 13, the node n2, the wiring 117, and the gate of the transistor 301_2. The path 320 is connected to the wiring 113, the wiring 111, the wiring 117, and the gate of the transistor 302. Connected.

[0208] Next, functions of the circuits 310_1 to 310_2 and the circuit 320 will be described. The path 310_1 controls the potential of the gate of the transistor 301_1 in response to the potential of the node n1. By controlling the control signal, the control circuit 301_1 has a function of controlling the conduction state of the transistor 301_1. The circuit 310_2 can function as a circuit in accordance with the potential of the node n2. By controlling the potential of the gate of the transistor 301_2, the transistor 301_ Circuit 3 has a function of controlling the conduction state of circuit 2 and can function as a control circuit. 20 controls the potential of the gate of the transistor 302 in accordance with the potential of the wiring 111. This has the function of controlling the conduction state of the transistor 302 and functions as a control circuit. However, the present invention is not limited to this, and the circuits 310_1 to 310_2 and Path 320 can have a variety of other functions.

[0209] Next, the transistors 301_1 to 301_2, the transistor 302, and the transistor 303 The functions of transistors _1 to 303_2 and transistor 304 will be described. The inverter 301_1 turns on or off the wiring 117 and the node n1 in response to an output signal of the circuit 310_1. By controlling the state, the timing of supplying voltage V1 to node n1 can be controlled. The transistor 301_2 has a function of switching the input voltage and can function as a switch. The conduction state between the wiring 117 and the node n2 is controlled in response to the output signal of 310_2. Therefore, it has a function of controlling the timing of supplying voltage V1 to node n2, and functions as a switch. The transistor 302 can function as a By controlling the conduction state between the wiring 117 and the wiring 111, the voltage V1 is applied to the wiring 111. and can function as a switch. The transistor 303_1 turns on or off the electrical continuity between the wiring 117 and the node n1 in response to the signal RE. By controlling the timing of supplying voltage V1 to node n1, The transistor 303_2 is connected to the output of the signal RE In response to this, the conduction state between the wiring 117 and the node n2 is controlled, and the voltage V1 is It has the function of controlling the timing of supplying to node n2 and can function as a switch. The transistor 304 turns on or off the wiring 117 and the wiring 111 in response to a signal RE. By controlling the state, the timing of supplying the voltage V1 to the wiring 111 can be controlled. It has the function of functioning as a switch. However, it is not limited to this. Transistors 301_1 to 301_2, transistor 302, transistors 303_1 to 303_3 3_2 and the transistor 304 can have various other functions.

[0210] Next, an example of the operation of the circuit 300 in FIG. The operation of the semiconductor device has some commonalities with the operation of the semiconductor device of FIG. The following description will be given with reference to the timing chart of the first and second embodiments. Where applicable, the explanation will be omitted.

[0211] First, in a period A1, as shown in FIG. 16(A), the signal RE is at L level, The transistors 303_1 to 303_2 and the transistor 304 are turned off. The output signal 0_1 is generated when the potential of node n1 becomes, for example, V2+Vth101_1+Vx. Therefore, the transistor 301_1 is turned off. The output signal becomes H level because the potential of the node n2 is approximately V1. The transistor 301_2 is turned on. The output signal of the circuit 320 is This voltage becomes V1, which is at the H level. Therefore, the transistor 302 is turned on. As a result, the wiring 117 and the node n1 are in a non-conductive state, and the wiring 117 and the node n2 are in a non-conductive state. The wiring 117 and the wiring 111 are electrically connected via the transistor 301_2. Therefore, the voltage V1 is supplied from the wiring 117 to the transistor 30 The voltage V1 is supplied to the node n2 through the wiring 117 and the transistor 30. 2 to the wiring 111.

[0212] On the other hand, in the period A2, as shown in FIG. 16(B), the output signal of the circuit 310_1 is The potential of the node n1 becomes approximately V1, so that the potential becomes H level, and the output signal of the circuit 310_2 becomes , the potential of node n2 becomes, for example, V2+Vth101_2+Vx, so it becomes L level. However, this is different from the period A1. Therefore, the transistor 301_1 is turned on, and the transistor As a result, the wiring 117 and the node n1 are connected to the transistor 301_2. Conduction is established via 01_1, and the wiring 117 and the node n2 are brought into a non-conductive state. The voltage V1 is supplied to the node n1 via the wiring 117.

[0213] Next, during period B1, as shown in FIG. 16(C), the signal RE remains at L level. , the transistors 303_1 to 303_2 and the transistor 304 remain off. The output signal of the circuit 310_1 is, for example, V2+Vth101_1+Vx Therefore, the transistor 301_1 remains off. The output signal of the circuit 310_2 is H because the potential of the node n2 remains approximately at V1. Therefore, the transistor 301_2 remains on. The output signal of becomes L level because the potential of the wiring 111 becomes approximately V2. The transistor 302 is turned off. As a result, the wiring 117 and the node n1 are not electrically connected to each other. The wiring 117 and the node n2 remain electrically connected through the transistor 301_2. Therefore, the voltage V1 is applied to the wiring 117 and the wiring 111. 17 to the node n2 via the transistor 301_2.

[0214] On the other hand, in the period B2, as shown in FIG. 17(A), the output signal of the circuit 310_1 is Since the potential of the node n1 remains at approximately V1, it remains at the L level, and the output of the circuit 310_2 The output signal is generated because the potential of node n2 remains approximately V2 + Vth101_2 + Vx. The difference from the period B1 is that the transistor 301 remains at the L level. _1 remains on and transistor 301_2 remains off. 117 and the node n1 remain electrically connected through the transistor 301_1, and the wiring 1 Therefore, the voltage V1 is applied via the wiring 117 to the node n2. and supplied to node n1.

[0215] Next, in the periods C1 and C2, as shown in FIG. 17(B), the signal RE is at the H level. Therefore, the transistors 303_1 to 303_2 and the transistor 304 are turned on. The output signal of the circuit 310_1 is at the H level because the potential of the node n1 is approximately V1. Therefore, the transistor 301_1 is turned on. The output signal of the circuit 310_2 Since the potential of node n2 is approximately V1, it becomes H level. The output signal of the circuit 320 is generated when the potential of the wiring 111 is approximately V1 This causes the transistor 302 to turn on. The line 117 and the node n1 are connected via the transistors 301_1 and 303_1. The wiring 117 and the node n2 are electrically connected to the transistor 301_2 and the transistor 303_2, the wiring 117 and the wiring 111 are electrically connected to the transistor 302 and Therefore, the voltage V1 is applied from the wiring 117 to the transistor 304. The voltage is supplied to the node n1 via the transistor 301_1 and the transistor 303_1. The voltage V1 is applied from the wiring 117 through the transistor 301_2 and the transistor 303_2. The voltage V1 is supplied to the node n2 from the wiring 117 to the transistor 302 and the transistor The signal is supplied to the wiring 111 via the star 304.

[0216] Next, in the periods D1, D2, E1, and E2, as shown in FIG. 17(C), Since the signal RE becomes L level, the transistors 303_1 to 303_2 and the transistor The output signal of the circuit 310_1 is generated when the potential of the node n1 is approximately V1 Therefore, the transistor 301_1 remains on. The output signal of the circuit 310_2 is H because the potential of the node n2 remains approximately at V1. Therefore, the transistor 301_2 remains on. The output signal of remains at H level because the potential of the wiring 111 remains at approximately V1. Therefore, the transistor 302 remains on. As a result, the wiring 117 and the node n1 remains in a conductive state through the transistor 301_1, and the wiring 117 and the node n2 are The transistor 301_2 remains conductive, and the wiring 117 and the wiring 111 are connected to each other. Therefore, the voltage V1 is transferred from the line 117 to the The voltage V1 is supplied to the node n1 through the transistor 301_1. The voltage V1 is supplied to the node n2 through the transistor 301_2. The voltage is supplied to the wiring 111 through the transistor 302 .

[0217] Since the transistors 301_1 and 301_2 have the same functions, It is preferable that the channel widths of the transistors 303_1 to 303_3 are approximately equal. 3_2 have similar functions, so it is preferable that their channel widths are roughly equal. However, the present invention is not limited to this, and the transistors 301_1 and 301_2 may be connected to each other via channels. Alternatively, the transistors 303_1 to 303_2 may have different widths. can have a structure in which the channel widths are different from each other.

[0218] The transistors 301_1 and 301_2 supply a voltage V1 to the nodes n1 and n2. The transistor 302 has a function of controlling timing and supplies a voltage V1 to the wiring 111. The loads of the nodes n1 to n2 are the loads of the wiring 111. Therefore, the channel width of the transistors 301_1 to 301_2 is It is preferable that the channel width of the transistor 302 is smaller than that of the transistor 302. The channel width of the transistors 303_1 and 303_2 is smaller than the channel width of the transistor 304. However, it is not limited to this, and it is preferable that the transistors 301_1 to 301_2 The channel width is greater than or approximately equal to the channel width of the transistor 302. Alternatively, the channel width of the transistors 303_1 to 303_2 can be The width of the channel of the capacitor 304 may be greater than or approximately equal to the width of the channel of the capacitor 304.

[0219] As shown in FIG. 18(A), similarly to the first and second embodiments, the wiring 117 It is possible to divide the wiring into a plurality of wirings 117C to 117K. Wiring 117D, wiring 117E, wiring 117F, wiring 117G, wiring 117H, wiring 117 I, a wiring 117J, and a wiring 117K are connected to a first terminal of the transistor 303_1, a second terminal of the transistor 303_2, and a third terminal of the transistor 303_3, respectively. A first terminal of the transistor 303_2, a first terminal of the transistor 304, a circuit 310_1, A first terminal of the transistor 301_1, a circuit 310_2, and a first terminal of the transistor 301_2 , the circuit 320, and the first terminal of the transistor 302. 7C to 117K are the wiring 111, the wiring 112, the wiring 113, the wiring 114, the wiring 115_1 Various wirings such as 115_2, wiring 116, wiring 118, or wiring 211, or It is possible to connect to various nodes such as nodes n1 to n2. However, this is not limited to this. The wiring 113 can also be divided into multiple wirings.

[0220] As shown in FIG. 18B, the first terminal of the transistor 303_1 and the second terminal of the transistor 303_2 are connected to each other. A first terminal of the transistor 303_2 and a first terminal of the transistor 304 are connected to the wiring 118. It is possible to do this.

[0221] Note that, as shown in FIG. 18C, the transistor 304 can be omitted. However, the present invention is not limited to this, and the transistor 303_1 and / or the transistor 303_ 2 can be omitted.

[0222] 18(C), the transistor 303_ 1, transistor 303_2, and / or transistor 304 may be omitted. be.

[0223] Note that as shown in FIG. 19A, the circuit 320 and the transistor 302 can be omitted. However, the present invention is not limited to this, and the circuit 310_1 and the transistor 301_ 1 can be omitted, and the circuit 310_1 and the transistor 301_2 can be omitted. It is possible to do this.

[0224] 19(A), in FIGS. 18(A) to 18(C), the circuit 310_1 and The transistor 301_1 can be omitted, and the circuit 310_1 and the transistor The transistor 301_2 can be omitted, and the circuit 320 and the transistor 302 can be omitted. It can be omitted.

[0225] As shown in FIG. 19B, the transistor 301_1 is connected to one terminal (hereinafter referred to as the positive terminal) of the The other terminal (hereinafter also referred to as a negative terminal) is connected to the circuit 310_ It is possible to replace the diode 301a_1 connected to the output terminal of the first inverter. The transistor 301_2 has one terminal (hereinafter also referred to as a positive terminal) connected to the node n2. The other terminal (hereinafter also referred to as the negative terminal) of the diode is connected to the output terminal of the circuit 310_2. Alternatively, the transistor 302 can be replaced with one of the The terminal (hereinafter also referred to as the positive electrode) is connected to the wiring 111, and the other terminal (hereinafter also referred to as the negative electrode) ) can replace the diode 302a connected to the output terminal of the circuit 320. Alternatively, one terminal (hereinafter also referred to as a positive terminal) of the transistor 303_1 is connected to the node n1. and the other terminal (hereinafter also referred to as the negative electrode) of the diode 3 is connected to the wiring 116. Alternatively, the transistor 303_2 can be replaced with the transistor 303a_1. The terminal (hereinafter also referred to as the positive terminal) is connected to node n2, and the other terminal (hereinafter also referred to as the negative terminal) can be replaced with the diode 303a_2 connected to the wiring 116. One terminal (hereinafter also referred to as a positive electrode) of the transistor 304 is connected to the wiring 111. The other terminal (hereinafter also referred to as the negative terminal) of the diode 304a is connected to the wiring 116. However, it is not limited to this, and the gate of each transistor and the second By connecting this pin, it is possible to configure the transistor as a diode. Alternatively, by connecting the gate of each transistor to the first terminal, It is possible to configure the resistor in a diode-connected configuration.

[0226] As in FIG. 19(B), in FIGS. 18(A) to 18(C) and FIG. 19(A), Transistors 301_1 to 301_2, transistor 302, transistors 303_1 to 303_3 03_2 and / or transistor 304 can be replaced with a diode. Alternatively, the transistors can be configured in a diode-connected configuration.

[0227] As shown in FIG. 19C, the transistors 301_1 to 301_2 and the transistor A circuit for controlling the conduction state of the transistor 302 is made up of transistors 301_1 to 301_2, and The circuit 330 can be shared by the transistors 302 and 303. The gates of the transistors 301_1 to 301_2 and the transistor 302 are By controlling the potential of the transistors 301_1 to 301_2 and the transistor The power supply 304 has a function of controlling the conduction state of the power supply 302, and can function as a control circuit. In the periods A1, A2, B1, and B2 shown in FIG. 4C, the output of the circuit 330 The signal is at the L level because the potential of the node n1 or the potential of the node n2 is higher than V1. Therefore, the transistors 301_1 to 301_2 and the transistor 302 are turned off. In the periods C1, C2, D1, D2, E1, and E2, the circuit The output signal of 330 is H because the potential of node n1 or node n2 is approximately V1. Therefore, the transistors 301_1 to 301_2 and the transistor 302 will be turned on.

[0228] As in FIG. 19(C), in FIGS. 18(A) to 18(C) and 19(A) to 19(B), Even if the transistors 301_1 to 301_2 and the transistor 302 are turned on and off, the conduction state of the transistors 301_1 to 301_2 and the transistor 302 is controlled. It is possible to share a circuit for

[0229] As shown in FIG. 20A, the circuit 100 is similar to the transistor 10 shown in FIG. 10C. When the circuit 300 has a plurality of transistors 101 to 101_N, the transistors A plurality of transistors 301_1 to 301_N, transistors 303_1 to 303 _N and a plurality of circuits 310_1 to 310_N. The transistors 301_1 to 301_N are 1 or 301_2 and has the same function. 303_N corresponds to the transistor 303_1 or the transistor 303_2, and The circuits 310_1 to 310_N have the function of The first terminals of the transistors 301_1 to 301_N are connected to the wiring 1. 17. The second terminals of the transistors 301_1 to 301_N are connected to the node n The gates of the transistors 301_1 to 301_N are connected to the respective The transistors 303_1 to 303_N are connected to the output terminals of the transistors 303_1 to 303_N. The first terminals are connected to the wiring 117. The second terminals of the transistors 303_1 to 303_N are connected to the nodes n1 to nN, respectively. The port is connected to the wiring 116 .

[0230] As in FIG. 20(A), in FIGS. 18(A) to 18(C) and 19(A) to 19(C), However, the circuit 300 includes a plurality of transistors 301_1 to 301_N. A plurality of transistors 303_1 to 303_N and / or a circuit 31 It is possible to have multiple circuits 0_1 to 310_N.

[0231] Note that when the semiconductor device has the circuit 120 as shown in FIG. 8F, As such, the circuit 300 may include a transistor 342 and a transistor 344. The transistor 342 corresponds to the transistor 302 and has a similar function. The transistor 344 corresponds to the transistor 304 and has a similar function. A first terminal of the transistor 342 is connected to the wiring 117, and a second terminal of the transistor 342 is connected to the wiring 2. 11, and the gate of transistor 342 is connected to the gate of transistor 302. A first terminal of the transistor 344 is connected to the wiring 117. The second terminal is connected to the wiring 211, and the gate of the transistor 344 is connected to the wiring 116. will be done.

[0232] 20(B), FIGS. 18(A) to 18(C), 19(A) to 19(C), and 2 In FIG. 0(A), the circuit 300 also includes transistor 342 and / or transistor 3 It is possible to have 44.

[0233] As shown in FIG. 21, the transistors 301_1 to 301_2 and the transistor 302 , the transistors 303_1 to 303_2 and the transistor 304 are P-channel It is possible to use transistors. The transistor 302p, the transistors 303p_1 to 303p_2, and the transistor 30 4p are transistors 301_1 to 301_2, transistor 302, and transistor The transistors 303_1 to 303_2 and the transistor 304 are P-channel types. If the polarity of the transistor is P-channel, the voltage V1 is supplied to the wiring 113, and the wiring 117 is supplied with a voltage V2, and the output signal of the circuit 310_1 and the output signal of the circuit 310_2 are The output signal of the circuit 320, the potential of the node n1, the potential of the node n2, and the signal OUT are It should be noted that the polarity of the transistor is reversed compared to the N-channel type.

[0234] 21, FIGS. 18(A) to 18(C), 19(A) to 19(C), and 20(A) In the above-mentioned cases, a P-channel transistor may be used as the transistor. It is possible.

[0235] Next, specific examples of the circuits 310_1 to 310_2 and the circuit 320 will be described.

[0236] First, FIG. 22A shows an example of a circuit 310_1. The circuit 310_1 is a transistor. The first terminal of the transistor 311_1 is connected to the first terminal of the transistor 312_1. The first terminal of the transistor 311_1 is connected to the wiring 113, and the second terminal of the transistor 311_2 is connected to the wiring 113. The gate of the transistor 311_1 is connected to the wiring 113. A first terminal of the transistor 312_1 is connected to the wiring 117. The second terminal of the transistor 301_2 is connected to the gate of the transistor 301_1, and the second terminal of the transistor 312_ The gates of the transistors 311_1 and 312 are connected to the node n1. 12_1 is an N-channel type. However, it is not limited to this. 311_1 and / or transistor 312_1 may be P-channel. The transistor 311_1 is connected to the transistor 301_1 when the potential of the gate of the transistor 301_1 is approximately V When the potential of the gate of the transistor 301_1 becomes 1, the potential of the gate of the transistor 301_1 is increased. The transistor 312_1 can function as a potential regulator of the node n1. By controlling the conduction state between the wiring 117 and the transistor 301_1 in accordance with It has a function of controlling the timing of supplying the voltage V1 to the gate of the transistor 301_1. , it can function as a switch.

[0237] The operation of the circuit 310_1 shown in FIG. 22A will be described. In this case, the potential of the node n1 becomes higher than the threshold voltage of the transistor 312_1. The transistor 312_1 is turned on. Therefore, the channel width of the transistor 312_1 is By making the channel width of the transistor 311_1 larger than that of the transistor 311_1, the The potential of the gate of transistor 301_1 is approximately V1. The potential of the wiring 117 (V1) and the threshold voltage of the transistor 301_1 (Vth30 1_1) and the sum of period A2, period B2, period C1, period C2, period During periods D1, D2, E1, and E2, the potential of the node n1 is approximately V1. Therefore, the transistor 312_1 is turned off. The potential of the terminal is changed from the potential (V2) of the wiring 113 to the threshold voltage (Vt h311_1) is subtracted to get the value (V2-Vth311_1).

[0238] The channel width of the transistor 312_1 is It is preferably 2 times or more, and more preferably 4 times or more. Preferably, the ratio is 8 times or more, but is not limited to this.

[0239] Note that the gate and the first terminal of the transistor 311_1 may be connected to various wirings. For example, the gate and the first terminal of the transistor 311_1 may be connected to the wiring 112 or It can be connected to the wiring 118. However, it is not limited to this.

[0240] The first terminal of the transistor 312_1 can be connected to various wirings. For example, the first wiring of the transistor 312_1 may be connected to the wiring 115_2. It is possible, but not limited to this.

[0241] As shown in FIG. 22B, the circuit 310_1 includes a transistor 311_1 and a transistor In addition to the transistor 312_1, a transistor 313_1 and a transistor 314_1 are provided. The first terminal of the transistor 313_1 is connected to the wiring 113. The second terminal of the transistor 313_1 is connected to the gate of the transistor 301_1. The gate of the transistor 313_1 is connected to the second terminal of the transistor 311_1 and the The transistor 311_1 and the transistor 312_2 are connected to the second terminal of the transistor 311_1 and the second terminal of the transistor 312_1. The transistor 31 is an N-channel type. However, it is not limited to this. 1_1 and / or transistor 312_1 can be P-channel. The transistor 313_1 supplies the voltage supplied to the wiring 113 to the transistor 301_1. It has the function of controlling the timing of supplying power to the bootstrap transistor or switch. The first terminal of the transistor 314_1 is connected to the wiring 117. , and the second terminal of the transistor 314_1 is connected to the second terminal of the transistor 313_1. The gate of the transistor 314_1 is connected to the node n1. The transistor 314_1 changes the connection between the wiring 117 and the transistor 301_1 in response to the potential of the node n1. By controlling the conduction state, the voltage V1 is supplied to the gate of the transistor 301_1. It has the function of controlling the timing of the signal being input and can function as a switch.

[0242] The first terminal of the transistor 313_1 can be connected to various wirings. For example, the first terminal of the transistor 313_1 is connected to the wiring 112 or the wiring 118. However, it is not limited to this.

[0243] The first terminal of the transistor 314_1 can be connected to various wirings. For example, the first wiring of the transistor 314_1 may be connected to the wiring 115_2. It is possible, but not limited to this.

[0244] In FIG. 22B, as shown in FIG. 22C, the gate of the transistor 313_1 A capacitive element 315_1 can be connected between the port and the second terminal.

[0245] As shown in FIG. 22D, the circuit 300 includes a transistor 316_1. A first terminal of the transistor 316_1 is connected to the wiring 117. The second terminal of the transistor 316_1 is connected to the gate of the transistor 301_1. The gate of the transistor 316_1 is connected to the wiring 114. However, the transistor 316_1 is not limited to a P-channel type. The transistor 316_1 can be a channel type. By controlling the conduction state between 117 and the gate of the transistor 301_1, The control circuit 301_1 has a function of controlling the timing at which the voltage V1 is supplied to the transistor 301_1.

[0246] As in FIG. 22(D), the first terminal is connected to the wiring 117 in FIGS. 22(B) to 22(C). The second terminal is connected to the gate of the transistor 301_1, and the gate is connected to the wiring 11. 4. A transistor 316_1 connected to the output of ...

[0247] Next, an example of a circuit 310_2 is shown in FIG. 23A. The circuit 310_2 includes a transistor 3 The first terminal of the transistor 311_2 is , the second terminal of the transistor 311_2 is connected to the wiring 113, and the second terminal of the transistor 311_ The gate of the transistor 311_2 is connected to the wiring 113. A first terminal of the transistor 312_2 is connected to the wiring 117. The second terminal of the transistor 301_2 is connected to the gate of the transistor 312_2. The gates of the transistors 311_2 and 312 are connected to the node n2. The transistor 31 is an N-channel type. However, it is not limited to this. 1_2 and / or transistor 312_2 can be P-channel The transistor 311_2 is connected to the transistor 301_2 when the potential of the gate of the transistor 301_2 is approximately equal to V1. When the potential of the gate of the transistor 301_2 is increased, the diode The transistor 312_2 can function as a gate in response to the potential of the node n2. Therefore, by controlling the conduction state between the wiring 117 and the transistor 301_2, the voltage V1 to the gate of the transistor 301_2. It is possible to function as a switch.

[0248] The operation of the circuit 310_2 shown in FIG. 23A will be described. In this case, the potential of the node n2 becomes higher than the threshold voltage of the transistor 312_2. The transistor 312_2 is turned on. By making the channel width of the transistor 301 larger than that of the transistor 311_2, The potential of the gate of transistor 301_2 is approximately V1. The potential is the potential of the wiring 117 (V1) and the threshold voltage of the transistor 301_2 (Vth301 The value is smaller than the sum of period A2, period B2, period C1, period C2, and period D. In periods D1, D2, E1, and E2, the potential of node n2 is approximately V1. Therefore, the transistor 312_2 is turned off. The potential of the transistor 311_2 is changed from the potential of the wiring 113 (V2) to the threshold voltage (Vth 311_2), the value is (V2-Vth311_2).

[0249] The channel width of the transistor 312_2 is It is preferably 2 times or more, and more preferably 4 times or more. Preferably, the ratio is 8 times or more, but is not limited to this.

[0250] Note that the gate and the first terminal of the transistor 311_2 may be connected to various wirings. For example, the gate and the first terminal of the transistor 311_2 may be connected to the wiring 112 or It can be connected to the wiring 118. However, it is not limited to this.

[0251] The first terminal of the transistor 312_2 can be connected to various wirings. For example, the first terminal of the transistor 312_2 may be connected to the wiring 115_1. It is possible, but not limited to this.

[0252] As shown in FIG. 23B, the circuit 310_2 includes a transistor 311_2 and a transistor In addition to the transistor 312_2, a transistor 313_2 and a transistor 314_2 are provided. The first terminal of the transistor 313_2 is connected to the wiring 113. The second terminal of the transistor 313_2 is connected to the gate of the transistor 301_2. The gate of the transistor 313_2 is connected to the second terminal of the transistor 311_2 and the The transistor 311_2 and the transistor 312_3 are connected to the second terminal of the transistor 311_3. The transistor 31 is an N-channel type. However, it is not limited to this. 1_2 and / or transistor 312_2 can be P-channel. The transistor 313_2 supplies the voltage supplied to the wiring 113 to the transistor 301_2. It has the function of controlling the timing of supplying power to the bootstrap transistor or switch. The transistor 314_2 can function as a Therefore, by controlling the conduction state between the wiring 117 and the transistor 301_2, the voltage V1 to the gate of the transistor 301_2. It is possible to function as a switch.

[0253] The first terminal of the transistor 313_2 can be connected to various wirings. For example, the first terminal of the transistor 313_2 is connected to the wiring 112 or the wiring 118. However, it is not limited to this.

[0254] The first terminal of the transistor 314_2 can be connected to various wirings. For example, the first wiring of the transistor 314_2 may be connected to the wiring 115_1. It is possible, but not limited to this.

[0255] As shown in FIG. 23C, a transistor 313_2 is connected between the gate and the second terminal thereof. , a capacitive element 315_2 can be connected.

[0256] As shown in FIG. 23D, the circuit 300 includes a transistor 316_2. A first terminal of the transistor 316_2 is connected to the wiring 117. The second terminal of the transistor 316_2 is connected to the gate of the transistor 301_2. The gate of the transistor 316_2 is connected to the wiring 114. However, the transistor 316_2 is not limited to a P-channel type. The transistor 316_2 can be a channel type. By controlling the conduction state between 117 and the gate of transistor 301_2, The voltage V1 is supplied to the transistor 301_2.

[0257] As in FIG. 23(D), the first terminal is connected to the wiring 117 in FIGS. 23(B) to 23(C). The second terminal is connected to the gate of the transistor 301_2, and the gate is connected to the wiring 11. 4. A transistor 316_2 connected to the output of ...

[0258] Next, FIG. 24A shows an example of a circuit 320. The circuit 320 includes a transistor 321 and a A first terminal of the transistor 321 is connected to the wiring 113. The second terminal of the transistor 321 is connected to the gate of the transistor 302. The gate of the transistor 321 is connected to the wiring 113. The first terminal of the transistor 322 is The second terminal of the transistor 322 is connected to the wiring 117. The gate of the transistor 322 is connected to the wiring 111. 21 and transistor 322 are N-channel type. and the transistor 321 and / or the transistor 322 are P-channel. The transistor 321 is connected to the transistor 302 when the potential of the gate of the transistor 302 is approximately equal to the potential of the gate of the transistor 302. When the potential of the gate of the transistor 302 becomes V1, the potential of the gate of the transistor 302 is increased. The transistor 322 can function as a transistor in response to the potential of the wiring 111. Therefore, by controlling the conduction state between the wiring 117 and the transistor 302, the voltage V1 to the gate of the transistor 302. It is possible to function as such.

[0259] The operation of the circuit 320 shown in FIG. 24A will be described. In the period B2, the potential of the wiring 111 becomes higher than the threshold voltage of the transistor 322. Therefore, the transistor 322 is turned on. By making the channel width of the transistor 321 larger than that of the transistor 302, The potential of the gate of the transistor 302 is approximately V1. than the sum of the potential of the line 117 (V1) and the threshold voltage of the transistor 302 (Vth302). The value becomes small. Period A1, Period A2, Period C1, Period C2, Period D1, Period D2, Period In the periods E1 and E2, the potential of the wiring 111 is approximately V1. Therefore, the potential of the gate of the transistor 302 is equal to the potential of the wiring 113. The value (V2-Vt h321).

[0260] The channel width of the transistor 322 is at least twice as large as that of the transistor 321. It is more preferable that the ratio is 4 times or more. Preferably, the ratio is 8 times or more, but is not limited to this.

[0261] The gate and the first terminal of the transistor 321 can be connected to various wirings. For example, the gate and the first terminal of the transistor 321 are connected to the wiring 112 or the wiring 11 8, but is not limited to this.

[0262] The first terminal of the transistor 322 can be connected to various wirings. For example, a first wiring of the transistor 322 can be connected to the wiring 112. However, this is not limited to this.

[0263] As shown in FIG. 24B, the circuit 320 includes a transistor 321 and a transistor In addition to transistor 322, it is possible to have transistor 323 and transistor 324. A first terminal of the transistor 323 is connected to the wiring 113, and a second terminal of the transistor 323 is connected to the wiring 113. The terminal is connected to the gate of the transistor 302, and the gate of the transistor 323 is connected to the The second terminal of the transistor 321 is connected to the second terminal of the transistor 322. The first terminal of the transistor 324 is connected to the second terminal of the transistor 323. The second terminal of the transistor 324 is connected to the wiring 117, and the gate of the transistor 324 is connected to the wiring 111. The transistor 323 and the transistor 324 are N-channel transistors. However, the transistor 323 and / or the transistor 324 may be used without being limited to this. The transistor 323 can be a P-channel transistor. The timing at which the voltage to be applied to the transistor 302 is controlled is also controlled. It can function as a trap transistor or a switch. Transistor 3 24 indicates a potential difference between the wiring 117 and the gate of the transistor 302 depending on the potential of the wiring 111. By controlling the state, the timing of supplying voltage V1 to the gate of transistor 302 is determined. It has the function of controlling the switching and can function as a switch.

[0264] The first terminal of the transistor 323 can be connected to various wirings. For example, the first wiring of the transistor 323 may be connected to the wiring 112 and the wiring 118. It is possible, but not limited to this.

[0265] The first terminal of the transistor 324 can be connected to various wirings. For example, the first terminal of the transistor 324 can be connected to the wiring 118 .

[0266] As shown in FIG. 24C, in addition to the configuration shown in FIG. 24B, a transistor 323 A capacitive element 325 can be connected between the gate and the second terminal.

[0267] Note that as shown in FIG. 24D, the circuit 320 may include a transistor 326. The first terminal of the transistor 326 is connected to the wiring 117. The second terminal of the transistor 6 is connected to the gate of the transistor 302 and the second terminal of the transistor 326. is connected to the wiring 114. The transistor 326 is an N-channel transistor. However, without limitation, transistor 326 can be a P-channel type. The transistor 326 connects the wiring 117 and the gate of the transistor 302 in response to the signal SP. By controlling the conduction state between the transistor 302 and the voltage V1, It has the function of controlling the timing of

[0268] As in FIG. 24(D), in FIGS. 24(B) to 24(C), the first terminal is connected to the wiring 117. The first terminal is connected to the gate of the transistor 302, and the second terminal is connected to the wiring 114. A new connected transistor 326 can be added.

[0269] Next, FIG. 25A illustrates an example of a circuit 330. The circuit 330 includes a transistor 331. , transistor 332, and transistor 333. The first terminal of transistor 331 is , the second terminal of the transistor 331 is connected to the wiring 113, and the second terminal of the transistor 301_1 is connected to the wiring 113. The gate of the transistor 301_1 is connected to the gate of the transistor 301_2, and the gate of the transistor 302. The gate of the transistor 331 is connected to the wiring 113. The first terminal of the transistor 332 is connected to the wiring 117, and the second terminal of the transistor 331 The gate of the transistor 332 is connected to the second terminal of the transistor 333, and the gate of the transistor 332 is connected to the node n1. A first terminal of the transistor 333 is connected to the wiring 117, and a second terminal of the transistor 333 is connected to the wiring 117. , the second terminal of the transistor 331, and the gate of the transistor 333 is connected to the node n 2. The transistors 331, 332, and 333 are connected to , and N-channel type. However, this is not limited to this. The transistor 332 and the transistor 333 can be P-channel.

[0270] The operation of the circuit 330 shown in FIG. 25A will be described. In the periods A2, B1, and B2, the potential of the node n1 or the potential of the node n2 is Since the threshold voltage of the transistor 332 or the transistor 333 is higher than that of the transistor 332 or the transistor 333, At this time, the transistor 332 or the transistor 333 is turned on. The channel width of the transistor 333 is made larger than the channel width of the transistor 331. The gate of the transistor 301_1, the gate of the transistor 301_2, and the The potential of the gate of the transistor 302 becomes approximately V1. In the periods D2, E1, and E2, the potential of the node n1 and the potential of the node n2 becomes approximately V1, so transistors 332 and 333 are turned off. Therefore, the gate of the transistor 301_1, the gate of the transistor 301_2, and the The potential of the gate of the transistor 302 is changed from the potential (V2) of the wiring 113 to the potential of the transistor 331 The value (V2-Vth331+Vx) is greater than the value obtained by subtracting the threshold voltage (Vth331) from the value (V2-Vth331+Vx). In this case, Vx is greater than 0.

[0271] Note that the channel width of the transistor 332 or the channel width of the transistor 333 is It is preferable that the width is at least twice the channel width of the transistor 331. More preferably, it is at least four times the channel width of the transistor 331. It is more preferable that the ratio is 8 times or more. However, This is not limited to this.

[0272] The gate and the first terminal of the transistor 331 can be connected to various wirings. For example, the gate and the first terminal of the transistor 331 are connected to the wiring 112 or the wiring 11 8, but is not limited to this.

[0273] Note that the gates of the transistors 332 and 333 are connected to various wirings. For example, the gate of the transistor 332 can be connected to the wiring 114. The gate of the transistor 333 can be connected to the wiring 111. , but is not limited to this.

[0274] The first terminal of the transistor 332 and the first terminal of the transistor 333 are connected to separate circuits. For example, the first terminal of the transistor 332 can be connected to the wiring 11. 5_2, and a first terminal of the transistor 333 is connected to the wiring 115_1. However, the present invention is not limited to the above.

[0275] As shown in FIG. 25B, the circuit 330 includes a transistor 331, a transistor 332, and a 32 and transistor 333, as well as transistor 334, transistor 335, and The first terminal of the transistor 334 may be connected to the line 113, and the second terminal of the transistor 334 is connected to the gate of the transistor 301_1. , the gate of the transistor 301_2 and the gate of the transistor 302 are connected to the transistor The gate of the transistor 334 is connected to the second terminal of the transistor 331. A first terminal of the transistor 335 is connected to the wiring 117, and a second terminal of the transistor 335 is connected to the wiring 117. The gate of transistor 335 is connected to the second terminal of transistor 334, and the gate of transistor 335 is connected to node n1. The first terminal of the transistor 336 is connected to the wiring 117. The second terminal of the transistor 334 is connected to the second terminal of the transistor 336. The transistor 334, the transistor 335, and the transistor The transistor 336 is of an N-channel type. However, it is not limited to this. The transistor 334, the transistor 335, and the transistor 336 are P-channel type. It is possible.

[0276] Note that a capacitor may be connected between the gate and the second terminal of the transistor 334. is.

[0277] The first terminal of the transistor 334 can be connected to various wirings. For example, the first terminal of the transistor 334 may be connected to the wiring 112 or the wiring 118. It is possible, but not limited to this.

[0278] Note that the gates of the transistors 335 and 336 are connected to various wirings. For example, the gate of the transistor 335 can be connected to the wiring 114. The gate of the transistor 336 can be connected to the wiring 111. However, it is not limited to this.

[0279] The first terminal of the transistor 335 and the first terminal of the transistor 336 are connected to separate circuits. For example, the first terminal of the transistor 335 can be connected to the line 11. 5_2, and the first terminal of the transistor 336 is connected to the wiring 115_1. However, the present invention is not limited to the above.

[0280] Here, an example of a semiconductor device in which the contents described in the first to third embodiments are appropriately combined is shown in FIG. 41. However, the present invention is not limited to this, and other embodiments described in the first to third embodiments may also be used. The semiconductor device can be configured in various ways by combining the components.

[0281] The semiconductor device of FIG. 41 includes a circuit 100 and a circuit 10. The circuit 10 includes a circuit 200 and a The semiconductor device of FIG. 41 includes a circuit 300, and the circuit 300 includes a circuit 330. The circuit 100 has the configuration shown in FIG. 4A, and the circuit 200 has the configuration shown in FIG. The circuit 300 has the configuration shown in FIG. 19C. The circuit 330 has the configuration shown in FIG. As a result, the configuration shown in FIG. 25(B) is used.

[0282] Furthermore, the operation of the semiconductor device shown in Fig. 41 was verified. The verification results are shown in Fig. 42. 42 is a diagram showing the verification results of the semiconductor device of this embodiment. The test was carried out using an E simulator. As a comparative example, the transistor of the semiconductor device shown in FIG. Transistor 101_2, transistor 201_2, transistor 203_1, transistor 20 3_2, transistor 301_2, transistor 303_2, transistor 333, and The operation of a semiconductor device having a circuit configuration without the transistor 336 was also verified. ,The verification was performed with Vdd=30V, Vss=0V, clock frequency=25kHz (1 cycle=20 μsec), mobility of each transistor = 1 cm 2 / VS, threshold voltage of each transistor = 5 The test was performed with V and output capacitance set to 50 pF.

[0283] FIG. 42A is a timing chart showing the verification results for the semiconductor device of the comparative example. As shown in 42(A), in the semiconductor device of the comparative example, the node n The transistor 101_1 is turned on in response to the potential of the line 1, and the wiring 112 and the wiring 111 are connected to each other. The transistor 101_1 is turned on, and the signal CK1 is transmitted from the wiring 112 to the transistor 101_2. The signal is supplied to the wiring 111 via the starter 101_1.

[0284] FIG. 42(B) is a timing chart of the verification results for the semiconductor device shown in FIG. 41. As shown in FIG. 42B, in the semiconductor device shown in FIG. 41, in the period T1, the node n1 The transistor 101_1 is turned on in accordance with the potential of the The signal CK1 is transmitted from the wiring 112 to the transistor 101_1. is supplied to the wiring 111 through the capacitor 101_1, and in the period T2, The transistor 101_1 is turned on, and the wiring 112 and the wiring 111 are connected to the transistor 101_2. 1_1, the signal CK1 is transmitted from the wiring 112 to the transistor 101_1. 42, the semiconductor device of this embodiment is In this case, by turning on different transistors in each period, each transistor It can be seen that the number of times that the device is turned on and the duration of time that the device is turned on can be reduced.

[0285] (Fourth embodiment) In this embodiment, an example of a shift register will be described. The system can include the semiconductor device according to the first to third embodiments. The soft resistor may refer to a semiconductor device or a gate driver. The contents described in the first to third embodiments will not be described here. The contents described in the third embodiment can be appropriately combined with the contents described in this embodiment. .

[0286] First, an example of a shift register will be described with reference to FIG. 0 has a plurality of flip-flops called flip-flops 501_1 to 501_N. .

[0287] The flip-flops 501_1 to 501_N are the same as those in the first to third embodiments, respectively. 26 corresponds to the semiconductor device described in the section 1. In the example of FIG. 1_N, the semiconductor device of FIG. 4A is used. The flip-flops 501_1 to 501_N are not limited to this, and may be other types, for example, The semiconductor devices or circuits described in the first to third embodiments can be used.

[0288] Next, the connection relationship of the shift register will be described. 1_1 to 511_N, wiring 512, wiring 513, wiring 514, wiring 515_1 to 515_ 2, the wiring 516, the wiring 517, and the wiring 518. In 501_i (i is any one of 2 to N), the wiring 111, the wiring 112, the wiring 113 , the wiring 114, the wiring 115_1, the wiring 115_2, the wiring 116, and the wiring 117 are respectively , wiring 511_i, wiring 512, wiring 514, wiring 511_i-1, wiring 515_1, wiring The line 515_2, the wiring 511_i+1, and the wiring 516 are connected. In many cases, the connection destination of the wiring 112 is different between the flip-flop and the flip-flops in the even stages. For example, in the flip-flop in the i-th stage, when the wiring 112 is connected to the wiring 512, In this case, the flip-flop in the (i+1)th stage or the flip-flop in the (i-1)th stage The line 112 is connected to the wiring 513 .

[0289] In the flip-flop 501_1, when the wiring 114 is connected to the wiring 517, In the flip-flop 501_N, the wiring 116 is connected to the wiring 518. In many cases, however, it is not limited to this.

[0290] Next, an example of a signal or voltage input to or output from each wiring will be described. For example, signals GOUT_1 to GOUT_N are output from the inputs 1 to 511_N, respectively. The signals GOUT_1 to GOUT_N are output from the flip-flops 501_1 to 501_N, respectively. The signals GOUT_1 to GOUT_N are output signals of the signals OU Corresponding to T, output signal, selection signal, transfer signal, start signal, reset signal, gate signal The wiring 512 can function as a signal GCK1 or a scanning signal. The signal GCK1 corresponds to the signal CK1 and functions as a clock signal. It is possible to input a signal GCK2 to the wiring 513, for example. Signal GCK2 corresponds to signal CK2 and can function as an inverted clock signal. For example, a voltage V2 is supplied to the wiring 514. As an example, signals SEL1 to SEL2 are input to the inputs 515_1 to 515_2, respectively. For example, a voltage V1 is supplied to the wiring 516. As an example, assume that a signal GSP is input. The signal GSP corresponds to the signal SP, and The wiring 518 may function as a clock signal or a vertical synchronization signal. The signal GRE corresponds to the signal RE and is a reset signal. However, this is not a limitation, and these wirings can be used for: It is also possible to input various other signals, various voltages, or various currents.

[0291] The wirings 511_1 to 511_N function as signal lines, gate signal lines, or scanning lines. The wiring 512 and the wiring 513 can be used as a signal line or a clock signal line. The wiring 514 can function as a power supply line. The wirings 515_1 to 515_2 can function as signal lines. The wiring 517 can function as a power supply line or a ground line. The wiring 518 can function as a signal line. However, this is not limited to this, and these wirings can function as various other types of wiring. is possible.

[0292] In addition, the wiring 512, the wiring 513, the wiring 514, the wiring 515_1 to 515_2, and the wiring 516 The wiring 517 and the wiring 518 are used to input a signal or a voltage from the circuit 520. The circuit 520 supplies a signal or voltage to the shift register to It has the function of controlling the external register and functions as a control circuit or controller. is possible.

[0293] Note that the circuit 520 includes, for example, a circuit 521 and a circuit 522. The circuit 521 generates power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, and a reference voltage. The circuit 52 has a function of supplying a power to the power supply circuit or a regulator. 2 is a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a It has the function of generating various signals such as video signals and functions as a timing generator. However, the present invention is not limited to this, and the circuit 520 may be implemented by the circuit 521 and the circuit 522. In addition to the circuit 22, various circuits or elements may be included. For example, the circuit 52 0 is an oscillator, a level shifter circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, AD conversion circuit, operational amplifier, shift register, look-up table, coil, transistor The circuit may include a resistor, a capacitive element, a resistive element, and / or a frequency divider.

[0294] Next, the operation of the shift register of FIG. 26 will be described with reference to FIG. 27. FIG. 27 is an example of a timing chart for explaining the operation of a shift register. Signal GSP, Signal GRE, Signal GCK1, Signal GCK2, Signal SEL1, Signal SEL2, Signal GOUT_1, Signal GOUT_i-1, Signal GOUT_i, Signal GOUT_i+1, and a signal GOUT_N are shown. The explanation of the operations common to those of the first embodiment will be omitted.

[0295] The operation of the flip-flop 501_i in the k-th frame (k is a natural number) will be described. First, the signal GOUT_i-1 goes to H level. Then, the flip-flop 501_ i starts operation in period A1, and the signal GOUT_i becomes L level. Then, the flip-flop 501_GCK1 and the signal GCK2 are inverted. i starts operation in period B1, and the signal GOUT_i becomes H level. _i is input to the flip-flop 501_i-1 as a reset signal, and The start signal is input to the flip-flop 501_i+1. The flip-flop 501_i-1 starts its operation in the period C1, and the flip-flop 501_i+1 The operation in the period A1 starts. After that, the signals GCK1 and GCK2 are inverted again. Then, the flip-flop 501_i+1 starts its operation in the period B1, and the signal The signal GOUT_i+1 goes to H level. Therefore, the flip-flop 501_i is reset during the period Since the operation in C1 starts, the signal GOUT_i becomes L level. Until the signal GOUT_i-1 becomes H level, the flip-flop 501_i keeps the signal GC Every time the signals K1 and GCK2 are inverted, the operation in the period D1 and the operation in the period E1 are Repeat this process.

[0296] The operation of the flip-flop 501_i in the (k+1)th frame will be described. The signal GOUT_i-1 becomes H level. Then, the flip-flop 501_i is in a state A2 starts, and the signal GOUT_i goes to the L level. , and the signal GCK2 is inverted. Then, the flip-flop 501_i The signal GOUT_i becomes H level. The reset signal is input to the flip-flop 501_i-1 and the +1 as a start signal. The flip-flop 501_i+1 starts its operation in the period C2, and the flip-flop 501_i+1 starts its operation in the period A2. After that, the signals GCK1 and GCK2 are inverted again. The flip-flop 501_i+1 starts its operation in the period B1, and the signal GOUT_i+1 The signal GOUT_i+1 is a reset signal to the flip-flop 501_i. Therefore, the operation of the flip-flop 501_i in the period C2 is Then, the signal GOUT_i-1 goes low again. becomes H level, the flip-flop 501_i receives the signals GCK1 and GCK Every time 2 is inverted, the operation in period D2 and the operation in period E2 are repeated.

[0297] In addition, in the flip-flop 501_1, instead of the output signal of the previous stage flip-flop, The signal GSP is input from the circuit 520 through the wiring 517. When the flip-flop 501_1 becomes H level, the flip-flop 501_1 stops the operation in the period A1 or the period A2. Start.

[0298] In addition, in the flip-flop 501_N, instead of the output signal of the next stage flip-flop, The signal GRE is input from the circuit 520 through the wiring 518. When the flip-flop 501_N becomes H level, the operation in the period C1 or the period C2 is Start.

[0299] As described above, the shift register of this embodiment is made of the semiconductor By using the device, it is possible to obtain the same advantages as the semiconductor device.

[0300] It is possible to make the relationship between the signals GCK1 and GCK2 unbalanced. For example, As shown in the timing chart of FIG. 28(A), in the signals GCK1 and GCK2, This makes it possible to make the period during which the signal is at the H level shorter than the period during which the signal is at the L level. By doing so, even if delay or distortion occurs in the signals GOUT_1 to GOUT_N, It is possible to prevent the period during which these signals are at H level. When the shift register is used in a display device, it prevents multiple rows from being selected at the same time. However, the present invention is not limited to this, and the signal GCK1 and / or the signal GCK2 may be used. In this case, the period during which the signal is at the H level can be longer than the period during which the signal is at the L level.

[0301] It is possible to input multiphase clock signals to the shift register. For example, see Figure 2. As shown in the timing chart of 8(B), a clock signal with M phases (M is a natural number greater than or equal to 3) is In this case, in the signals GOUT_1 to GOUT_N, The period when the signal is at the H level in a given stage overlaps with the period when the signal is at the H level in the preceding and following stages. Therefore, when this embodiment is used in a display device, a plurality of rows This allows the video signals to be precharged to the pixels in other rows. It becomes possible to use it as a voltage.

[0302] In FIG. 28(B), it is preferable that M≦8. More preferably, it is preferable that M≦6. It is more preferable that M≦4. When the register is used in a scanning line driving circuit of a display device, if M is too large, multiple This is because several kinds of video signals are written to the pixel. This is because the period during which the signal is input becomes longer, which may result in a decrease in display quality.

[0303] As in FIG. 28(B), the timing chart in FIG. 28(A) also includes a multi-phase clock. A lock signal can be used.

[0304] Note that the wiring 518 and other wirings (for example, wiring 512, wiring 513, wiring 515_1, wiring 515_2, wiring 516, or wiring 517) are configured as one common wiring, and wiring 518 In this case, the wiring 116 in the flip-flop 501_N can be omitted. is the wiring 512, the wiring 513, the wiring 515_1, the wiring 515_2, the wiring 516, or the wiring 5 It is preferable that the wiring 518 is connected to the wiring 517. In addition, the wiring 518 may be omitted by using other configurations. In this case, in the flip-flop 501_N, the transistors 303_1 to 303_2 and the transistor 304 may be omitted.

[0305] It is possible to divide the output signal as shown in Figure 29. In the example of Figure 29, The flip-flops 501_1 to 501_N are each made of the semiconductor device shown in FIG. 10(E). Then, in the flip-flop 501_i (i is any one of 2 to N), Wiring 111, wiring 112, wiring 113, wiring 114, wiring 115_1, wiring 115_2, The wiring 116 and the wiring 117 are respectively connected to the wiring 511_i, the wiring 512, the wiring 514, and the wiring 511_i. 518_i-1, wiring 515_1, wiring 515_2, wiring 511_i+1, wiring 516 By doing so, pixel or gate signals are connected to the wirings 511_1 to 511_N. Even when a load such as a power line is connected, the transfer There is no distortion or delay in the signal. Therefore, the influence of the delay of the shift register is eliminated. However, the present invention is not limited to this, and the wiring 114 can be reduced by the wiring 511_i-1 Alternatively, the wiring 116 can be connected to the wiring 517_i+1. It is possible.

[0306] (Embodiment 5) In this embodiment, an example of a display device will be described.

[0307] First, an example of a system block of a liquid crystal display device will be described with reference to FIG. The liquid crystal display device includes a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_2, a circuit 5363_3, a circuit 5363_4, a circuit 5363_5, a circuit 5363_6, a circuit 5363_7, a circuit 5363_8, a circuit 5363_9, a circuit 5363_10, a circuit 5 2, a pixel portion 5364 having a pixel, a circuit 5365, and a lighting device 5366. In the portion 5364, a plurality of wirings 5371 are arranged extending from the circuit 5362, and the plurality of wirings 5372 is arranged extending from the circuit 5363_1 and the circuit 5363_2. In the intersecting regions of the plurality of wirings 5371 and the plurality of wirings 5372, there are provided liquid crystal elements and the like. Pixels 5367 each having a display element are arranged in a matrix.

[0308] In response to a video signal 5360, a circuit 5361 outputs a signal to a circuit 5362, a circuit 5363_1, a circuit 5363_2, a circuit 5363_3, a circuit 5363_4, a circuit 5363_5, a circuit 5363_6, a circuit 5363_7, a circuit 5363_8, a circuit 5363_9, a circuit 536 5363_2 and the circuit 5365, and has a function of supplying a signal, a voltage, a current, or the like to the Controller, control circuit, timing generator, power supply circuit, regulator, etc. In this embodiment, as an example, the circuit 5361 can function as a circuit 5362, the start signal for the signal line driver circuit (SSP), the clock signal for the signal line driver circuit (SCK), inverted clock signal for signal line driver circuit (SCKB), data for video signal (D ATA), and a latch signal (LAT). Then, a start signal for the scanning line driving circuit (G SP), clock signal for the scanning line driving circuit (GCK), and clock signal for the inverted scanning line driving circuit Alternatively, the circuit 5361 may supply a buffer signal (GCKB) to the circuit 5365. However, it is not limited to this, and the circuit 5 361 also transmits various signals, various voltages, or various currents to a circuit 5362, a circuit 5363_1, circuit 5363_2, and circuit 5365.

[0309] The circuit 5362 receives signals (e.g., SSP, SCK, SCKB) supplied from the circuit 5361. , DATA, LAT) to output video signals to multiple wirings 5371. The circuit 5363_1 and the circuit 536_2 can function as a signal line driver circuit. 3_2 runs in response to the signals (GSP, GCK, GCKB) supplied from the circuit 5361. It has a function of outputting scanning signals to a plurality of wirings 5372 and functions as a scanning line driver circuit. The circuit 5365 performs the following in response to the signal (BLC) supplied from the circuit 5361: By controlling the amount of power supplied to the lighting device 5366 or the time, the lighting device It has the function of controlling the brightness (or average brightness) of 5366 and can function as a power supply circuit. It is possible.

[0310] When video signals are input to the multiple wirings 5371, the multiple wirings 5371 The wiring can function as a line, a video signal line, a source signal line, or the like. When a scanning signal is input to 5372, the plurality of wirings 5372 are signal lines, scanning lines, or gate lines. It can function as a port signal line, etc. However, it is not limited to this.

[0311] The same signal is input to the circuit 5363_1 and the circuit 5363_2. When the scan signal is input from the circuit 5363_1, the scan signal is output to the plurality of wirings 5372. The scanning signals output from the line 5363_2 to the plurality of wirings 5372 are output at approximately the same timing. Therefore, the circuits 5363_1 and 5363_2 are driven Therefore, the display device can be made larger. Alternatively, the circuit 5363_1 and the circuit 5363_2 may be Since the channel width of the transistor can be reduced, a display device with a narrow frame can be manufactured. However, the present invention is not limited to this, and the circuit 5361 may be connected to the circuit 5363_1. It is possible to provide separate signals to the paths 5363_1 and 5363_2.

[0312] It is possible to omit either the circuit 5363_1 or the circuit 5363_2. do.

[0313] In addition, in the pixel portion 5364, wiring such as a capacitance line, a power supply line, and a scanning line can be newly arranged. The circuit 5361 can output a signal or a voltage to these wirings. Alternatively, a circuit similar to the circuit 5363_1 or the circuit 5363_2 may be newly added. This newly added circuit can transmit signals such as scanning signals to the newly added wiring. It is possible to output

[0314] The pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in FIG. 30(B), the display element can emit light, so that the circuit 5 365 and the lighting device 5366 can be omitted. In order to supply power, a plurality of wirings 5373 that can function as power supply lines are provided in the pixel portion 53 64. The circuit 5361 supplies a power supply voltage (also called a voltage ANO) The wiring 5373 can be connected to each color element of the pixel. It can be connected to all pixels in common.

[0315] Note that in FIG. 30B, as an example, the circuit 5361 includes a circuit 5363_1 and a circuit 536 3_2. The circuit 5361 is a circuit for a scanning line driver circuit. Start signal (GSP1), clock signal for scanning line driving circuit (GCK1), and inverse scanning A signal such as a clock signal (GCKB1) for the line driving circuit is supplied to the circuit 5363_1. The circuit 5361 outputs a start signal (GSP2) for the scanning line driving circuit, Clock signal (GCK2), clock signal for inverted scanning line driver circuit (GCKB2), etc. In this case, the circuit 5363_1 supplies the signal to the circuit 5363_2. 72, and the circuit 5363_2 scans only the odd-numbered wirings among the plurality of wirings 5372. That is, only the wirings in the even rows can be scanned. Since the driving frequency of the circuit 5363_2 can be reduced, power consumption can be reduced. Alternatively, it is possible to increase the area in which one stage of flip-flops can be laid out. Therefore, the display device can be made high-definition. However, the present invention is not limited to this. As in FIG. 30A, the circuit 5361 can be It is possible to output the same signal to the circuit 5363_1 and the circuit 5363_2.

[0316] 30(B), the circuit 5361 in FIG. 30(A) is the same as the circuit 5363 in FIG. It is possible to provide separate signals to the circuit 5363_1 and the circuit 5363_2.

[0317] The above is a description of an example of the system blocks of the display device.

[0318] Next, an example of the configuration of the display device will be described with reference to FIGS. 31(A), (B), (C), (D), and ( Please refer to E) for further explanation.

[0319] In FIG. 31A, a circuit (for example, a circuit 5364) having a function of outputting a signal to the pixel portion 5364 is shown. 362, a circuit 5363_1, and a circuit 5363_2 are formed on the same substrate as the pixel portion 5364. The circuit 5361 is formed on a substrate different from the pixel portion 5364. This reduces the number of external components, thereby reducing costs. Since the number of signals or voltages input to the board 5380 is reduced, the connections between the board 5380 and external components are reduced. This reduces the number of connections, thereby improving reliability and yield. Cut.

[0320] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is a TAB (Ta Flexible PCB (Flexible Printed Circuit) Alternatively, the substrate may be implemented as a The COG (Chip on Glass) method is used to mount the pixel part 5364 on the same substrate 5380. It is possible to implement it in

[0321] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is formed on a single crystal semiconductor. Therefore, it is possible to form a transistor using the substrate. The circuit can set the drive frequency over a wide range. For example, by increasing the drive frequency, This allows the number of pixels arranged in the pixel portion 5364 to be increased (by increasing the resolution). By reducing the drive voltage, power consumption can be reduced. The circuit formed on the substrate can increase the driving voltage, and therefore can be used as a display element. In addition, the circuit formed on the substrate can be , the variation in the output signal can be reduced.

[0322] A signal, voltage, or current is input from an external circuit via an input terminal 5381. This is often the case.

[0323] In FIG. 31B, the driving frequencies of the circuit 5363_1 and the circuit 5363_2 are 1 or the driving frequency of the circuit 5362, and the transistor formed in the pixel portion Transistors formed in the same process as the transistors are used for the circuits 5363_1 and 5363_2. Therefore, the circuit 5363_1 and the circuit 5363_2 can be connected to the pixel portion 5364. The circuit 5361 and the circuit 5362 are formed on the same substrate 5380. 364. In this way, the low-mobility transistor This allows the circuit formed on the plate 5380 to be configured. The semiconductor layer is made of an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. Therefore, it is possible to increase the size of the display device, reduce the number of steps, reduce costs, or It is possible to improve yield, etc.

[0324] As shown in FIG. 31C, a part of the circuit 5362 (circuit 5362a) is connected to the pixel section 53 64, and the remaining part of the circuit 5362 (circuit 5362b) is formed on the same substrate 5380. The circuit 5362a can be formed on a substrate separate from the element portion 5364. Circuits that can be constructed using low-power transistors (e.g., shift registers, select The circuit 5362b has high mobility and It is preferable to configure a circuit (for example, a semiconductor device) using transistors with small variations in characteristics. (including soft registers, latch circuits, buffer circuits, DA conversion circuits, AD conversion circuits, etc.) By doing this, the semiconductor layer of the transistor and For example, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor is used. This makes it possible to further reduce the number of external parts.

[0325] In FIG. 31(D), a circuit (for example, a circuit 5364) having a function of outputting a signal to the pixel portion 5364 is shown. 362, circuit 5363_1, and circuit 5363_2, etc.), and controlling these circuits A circuit having a function (for example, a circuit 5361) is formed on a substrate different from that of the pixel portion 5364. This makes it possible to form the pixel section and its peripheral circuits on separate substrates. Therefore, the yield can be improved.

[0326] As in FIG. 31(D), in FIGS. 31(A) to 31(C), the circuit 5363_1 and The circuit 5363_2 can be formed on a substrate different from that of the pixel portion 5364.

[0327] In FIG. 31(E), a part of the circuit 5361 (circuit 5361a) is on the same substrate as the pixel portion 5364. 5380, and the remaining circuit 5361 (circuit 5361b) is formed separately from the pixel portion 5364. The circuit 5361a is formed on a substrate. The circuit 5361a is formed by a transistor with low mobility. They often have circuits (e.g., switches, selectors, level shifters, etc.) that can The circuit 5361b is constructed using transistors with high mobility and small variations. It is preferable to construct a circuit (e.g., a shift register, a timing generator, an oscillator, etc.) These often have a built-in power supply, a regulator, or an analog buffer.

[0328] 31(A) to (D), the circuit 5361a and the pixel section 5364 are mounted on the same substrate. The circuit 5361b can be formed on a substrate different from that of the pixel portion 5364.

[0329] Here, the circuits 5363_1 and 5363_2 are the circuits according to the first to fourth embodiments. In this case, the semiconductor device or shift register of the circuit 5363 can be used. 1, the circuit 5363_2 and the pixel portion are formed on the same substrate, All transistors can be N-channel or P-channel. Therefore, the number of processes can be reduced, the yield can be improved, the reliability can be improved, or the cost can be reduced. In particular, when all the transistors are N-channel type, The semiconductor layer of the transistor is made of an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide. Therefore, it is possible to increase the size of the display device, reduce the cost, or It is possible to improve yield, etc.

[0330] Alternatively, the semiconductor device or shift register according to the first to fourth embodiments may include a transistor Therefore, the layout area can be reduced. This allows for a smaller frame, or a smaller layout area. Therefore, the resolution can be increased.

[0331] Alternatively, the semiconductor device or shift register according to the first to fourth embodiments may reduce parasitic capacitance. Therefore, the power consumption can be reduced. The flow capacity can be reduced, or the size of the external circuit or the The size of the display device can be reduced.

[0332] The semiconductor layer may be made of an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. The transistors used in this case may experience degradation in characteristics such as an increase in threshold voltage or a decrease in mobility. However, the semiconductor devices or shift registers of the first to fourth embodiments are This can suppress the deterioration of transistor characteristics, thereby extending the life of the display device. Cut.

[0333] As a part of the circuit 5362, the semiconductor device of the first to fourth embodiments or the shift For example, the circuit 5362a can be implemented by using a register similar to that in the first to third embodiments. The semiconductor device of the fourth aspect may have a shift register.

[0334] (Sixth embodiment) In this embodiment, an example of a signal line driver circuit will be described. It can be referred to as a conductor device or a signal generating circuit.

[0335] An example of a signal line driver circuit will be described with reference to FIG. The circuit includes a plurality of circuits 602_1 to 602_N, a circuit 600, and a circuit 601. The circuits 602_1 to 602_N are respectively connected to transistors 603_1 to 603_k. (k is a natural number of 2 or more) 603_k is an N-channel type, but is not limited to this. The transistors 603_1 to 603_k can be P-channel transistors, or CMOS transistors. It is possible to switch

[0336] The connection relationship of the signal line driver circuit will be described using the circuit 602_1 as an example. The first terminals of the transistors 603_1 to 603_k are connected to the wiring 605_1. The second terminals of the transistors 6_1 to 603_k are connected to the wirings S1 to Sk, respectively. The gates of 603_1 to 603_k are connected to wirings 604_1 to 604_k, respectively. For example, a first terminal of the transistor 603_1 is connected to a wiring 605_1. A second terminal of the transistor 603_1 is connected to the wiring S1. It is connected to the line 604_1.

[0337] The circuit 600 transmits signals to circuits 602_1 to 602_k via wirings 604_1 to 604_k. N, and can function as a shift register, decoder, etc. This signal is often a digital signal and can function as a selection signal. The wirings 604_1 to 604_k can function as signal lines. be.

[0338] The circuit 601 has a function of outputting signals to circuits 602_1 to 602_N, and is a video signal generator. For example, the circuit 601 can function as a At the same time, a signal is supplied to the circuit 602_1 via the wiring 605_2. The signal is often an analog signal and functions as a video signal. The wirings 605_1 to 605_N can function as signal lines. It is possible to do this.

[0339] The circuits 602_1 to 602_N select to which wiring the output signal of the circuit 601 is to be output. For example, the circuit 602 has a function of selecting a _1 indicates which of the wirings S1 to Sk the signal output from the circuit 601 to the wiring 605_1 is connected to. It has the function to select whether to output to

[0340] The transistors 603_1 to 603_N are connected to the wiring 6 in response to the output signal of the circuit 600. 05_1 and the wiring S1 to Sk, and functions as a switch. do.

[0341] Next, the operation of the signal line driver circuit of FIG. 32(A) will be explained with reference to the timing chart of FIG. 32(B). 32B shows a signal 614_1 input to a wiring 604_1. , a signal 614_2 input to the wiring 604_2, a signal 614_k input to the wiring 604_k, _k, a signal 615_1 input to the wiring 605_1, and a signal 615_2 input to the wiring 605_2. An example of No. 615_2 is shown below.

[0342] One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is the period during which pixels belonging to a certain row are selected and a video signal is written to the pixel. This refers to the period during which it is possible to

[0343] One gate selection period is divided into a period T0 and periods T1 to Tk. is a period for simultaneously applying a precharge voltage to pixels belonging to a selected row. The periods T1 to Tk can function as precharge periods. This is the period for writing video signals to pixels belonging to the selected row, and functions as a write period. It is possible to do this.

[0344] For convenience, the operation of the signal line driver circuit will be described using the operation of the circuit 602_1 as an example.

[0345] First, in a period T0, the circuit 600 applies an H-level signal to the wirings 604_1 to 604_k. Then, the transistors 603_1 to 603_k are turned on, and the wiring 605 At this time, the circuit 601 is in a conductive state between the wiring 605_1 and the wirings S1 to Sk. Since the precharge voltage Vp is supplied to the transistor 6 The signals are output to the wirings S1 to Sk via the signals 03_1 to 603_k. The charge voltage Vp is written to the pixels belonging to the selected row, so that the The corresponding pixels are precharged.

[0346] Next, in the period T1, the circuit 600 outputs an H-level signal to the wiring 604_1. Then, the transistor 603_1 is turned on, and the wiring 605_1 and the wiring S1 are brought into a conductive state. Then, the wiring 605_1 and the wirings S2 to Sk are in a non-conductive state. If the circuit 601 outputs a signal Data (S1) to the wiring 605_1, the signal D The ata (S1) is output to the wiring S1 through the transistor 603_1. The signal Data(S1) is supplied to the pixels in the selected row among the pixels connected to the wiring S1. It is written in simple terms.

[0347] Next, in a period T2, the circuit 600 outputs an H-level signal to the wiring 604_2. Then, the transistor 603_2 is turned on, and the wiring 605_2 and the wiring S2 are brought into a conductive state. Then, the wiring 605_1 and the wiring S1 are brought into a non-conductive state, and the wiring 605_1 and The wirings S3 to Sk remain in a non-conductive state. At this time, the circuit 601 outputs the signal Data( S2) is output to the wiring 605_1, the signal Data (S2) is In this way, the signal Data (S1) is output to the wiring S2 via the data input terminal 603_2. Of the pixels connected to line S1, those belonging to the selected row are written.

[0348] After that, until the period Tk, the circuit 600 outputs a high-level signal to the wirings 604_1 to 604_k. Since the signals are output in sequence, the signals are output in the same manner as in the periods T1 and T2, from the period T3 to the period Tk. 00 outputs H-level signals to the wirings 604_3 to 604_k in order. Since the resistors 603_3 to 603_k are turned on in order, the signal output from the circuit 601 is In this way, the signals are sequentially output to the wirings S3 to Sk. It becomes possible to write.

[0349] An example of the signal line driver circuit has been described above. Since the circuit has a function as a connector, the number of signals or the number of wirings can be reduced. Alternatively, before writing a video signal to the pixel (period T0), a voltage for precharging is set to Since the video signal is written to the pixel, the time required to write the video signal can be shortened. It is possible to increase the size of the display device and to increase the resolution of the display device. However, this is not limited to this. , it is possible to omit period T0 and not precharge the pixels.

[0350] If k is too large, the time it takes to write to the pixel becomes too short, so the time it takes to write to the pixel of the video signal becomes too short. Writing may not finish in time, so it is preferable that k≦6. More preferably, k≦3. Further preferably, k=2. It's nice.

[0351] In particular, if the color components of a pixel are divided into n, it is possible to set k=n. For example, If the color components of a pixel are divided into three, red (R), green (G), and blue (B), then k=3. In this case, one gate selection period is made up of period T0, period T1, period T2, and period T3. The period T1, period T2, and period T3 are divided into three periods T1, T2, and T3. It is possible to write video signals to the green (G) and blue (B) pixels. However, the order of the periods T1, T2, and T3 can be set arbitrarily. is.

[0352] In particular, a pixel has n (n is a natural number) sub-pixels (hereinafter also referred to as sub-pixels or sub-pixels). For example, if a pixel is divided into two sub-pixels, then k=n. In this case, one gate selection period is the period T In the period T1, one of the two sub-pixels In the period T1, a video signal is written to the other of the two sub-pixels. It is possible to do this.

[0353] The driving frequencies of the circuit 600 and the circuits 602_1 to 602_N are higher than those of the circuit 601. Therefore, the circuit 600 and the circuits 602_1 to 602_N are In this way, the substrate on which the pixel section is formed and the external circuit can be formed on the same substrate. This reduces the number of connections, which can improve yield and reliability. Furthermore, as shown in Figures 31(A) to 31(E), the scanning line driver circuit is also based on the same substrate as the pixel section. By forming it on a plate, the number of connections to external circuits can be further reduced.

[0354] The circuit 600 may be a semiconductor device or a shift register according to any one of the first to fourth embodiments. In this case, the polarities of all the transistors in the circuit 600 can be changed to It can be made into either an N-channel type or a P-channel type. Therefore, the number of processes can be reduced. This can improve yield or reduce costs.

[0355] It should be noted that not only the circuit 600 but also all the transistors included in the circuits 602_1 to 602_N The polarity of the transistor can be either N-channel or P-channel. 00, and when the circuits 602_1 to 602_N are formed on the same substrate as the pixel portion, the number of steps is This can reduce the number of transistors, improve the yield, or reduce the cost. By making the polarity of the transistor N-channel, the semiconductor layer of the transistor can be made of, for example, An amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. .

[0356] (Embodiment 7) In this embodiment, a pixel configuration and pixel operation applicable to a liquid crystal display device will be described. explain.

[0357] 33A shows an example of a pixel. The pixel 3020 includes a transistor 3021, a liquid crystal element The first terminal of the transistor 3021 is The second terminal of the transistor 3021 is connected to a wiring 3031, and the second terminal of the transistor 3021 is connected to a part of the liquid crystal element 3022. one electrode of the capacitor 3023 and the gate of the transistor 3021. The other electrode of the liquid crystal element 3022 is connected to the electrode 3034. The other electrode of the capacitor 3023 is connected to a wiring 3033 .

[0358] For example, a video signal can be input to the wiring 3031. For example, a scan signal, a selection signal, or a gate signal can be input to the input terminal 2. For example, a constant voltage can be supplied to the wiring 3033. For example, a constant voltage may be supplied to the 034. The precharge voltage is supplied to the wiring 3031, and the It is possible to shorten the writing time. Alternatively, a signal can be input to the wiring 3033. By this, it is possible to control the voltage applied to the liquid crystal element 3022. By inputting a signal to electrode 3034, frame inversion driving can be realized. be.

[0359] The wiring 3031 can function as a signal line, a video signal line, or a source signal line. The wiring 3032 can function as a signal line, a scanning line, or a gate signal line. The wiring 3033 can function as a power supply line or a capacitance line. The electrode 3034 can function as a common electrode or a counter electrode. When a voltage is supplied to the wiring 3031 and the wiring 3032, these wirings are not limited to the above. 3033 can function as a power supply line. The wiring 3033 can function as a signal line.

[0360] The transistor 3021 controls electrical continuity between the wiring 3031 and one electrode of the liquid crystal element 3022. By controlling the timing of writing a video signal to the pixel, The capacitor element 3023 can function as a switch. The potential difference between the electrode and the wiring 3033 is maintained, and the voltage applied to the liquid crystal element 3022 is The capacitor has a function of keeping the capacitance constant, and functions as a storage capacitor. However, the invention is not limited to this.

[0361] FIG. 33(B) is a timing chart for explaining the operation of the pixel of FIG. 33(A). 33B shows an example of a signal 3042_j (j is a natural number), a signal 3042_j+1 , signal 3041_i, signal 3041_i+1, and voltage 3043. (B) shows the kth (k is a natural number) frame and the k+1th frame. 42_j, ​​signal 3042_j+1, signal 3041_i, signal 3041_i+1, and voltage 3043 indicates a signal input to the j-th line wiring 3032, and 3044 indicates a signal input to the j+1-th line wiring 3032. a signal input to the wiring 3031 in the i-th column, a signal input to the wiring 3031 in the (i+1)-th column 3033.

[0362] The operation of the pixel 3020 in the jth row and the ith column will be described. When this occurs, the transistor 3021 is turned on. Since the signal 3041_j is connected to one electrode of the transistor 3022, The voltage is input to one electrode of the liquid crystal element 3022 via a capacitor 3023. At this time, the potential difference between the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033 is maintained. Therefore, the liquid crystal element 302 remains in the H level until the signal 3042_j becomes H level again. The voltage applied to the liquid crystal element 3022 is constant. It expresses gradation.

[0363] In FIG. 33(B), positive and negative signals are alternately arranged for each row selection period. This shows an example of a case where a signal is input to a line 3031. A positive signal is a signal whose potential is equal to or greater than a reference value (for example, A negative signal is a signal whose potential is higher than the reference value. (for example, the potential of the electrode 3034). The signal input to the wiring 3031 can have the same polarity during one frame period. do.

[0364] In addition, in FIG. 33(B), the polarity of the signal 3041_i and the polarity of the signal 3041_i+1 are different. However, the present invention is not limited to this example, and the polarity and The polarity of the signal 3041_i+1 can be the same.

[0365] 33B shows a period in which the signal 3042_j is at H level and a period in which the signal 3042_j is at H level. This is an example of a case where the period when +1 is at H level does not overlap. However, this is not limited to this. As shown in FIG. 33(C), there is a period in which the signal 3042_j is at H level and a period in which the signal 30 42_j+1 is at H level. In this case, the period when the wiring 303 It is preferable that signals of the same polarity are supplied to all the inputs during one frame. By using the signal 3041_j written to the pixel in the jth row, the pixel in the j+1th row is This allows the time required to write a video signal to the pixel to be shortened. Therefore, the display device can be made high-definition. Alternatively, the wiring 3031 may be connected to the same polarity in one frame period. Since the signal is input, power consumption can be reduced.

[0366] It should be noted that the pixel configuration of FIG. 34(A) and the timing chart of FIG. 33(C) can be combined. In this way, dot inversion driving can be realized. The pixel 3020(i, j) is connected to the wiring 3031_i. j+1) is connected to the wiring 3031_i+1. In this way, the i-th row is connected to the wiring 3031_i and the wiring 3031_i+1 alternately. The pixels belonging to the eye are written with positive and negative polarity signals alternately, row by row. However, the present invention is not limited to this, and the dot inversion driving can be realized. The pixels are arranged in a plurality of rows (for example, two or three rows) alternately with the wiring 3031_i and the wiring 3031 _i+1.

[0367] It should be noted that a sub-pixel structure can be used as the pixel configuration. 34(A) and 34(B) show the configuration when a pixel is divided into two sub-pixels. B) uses 1S+2G (for example, one signal line and two scan lines per subpixel) Figure 34(C) shows a sub-pixel structure called 2S+1G (e.g., 1 sub-pixel). A sub-pixel structure called a sub-pixel (using two signal lines and one scan line per pixel) The sub-pixel 3020A and the sub-pixel 3020B correspond to the pixel 3020. The transistor 3021A and the transistor 3021B correspond to the transistor 3021. The liquid crystal element 3022A and the liquid crystal element 3022B correspond to the liquid crystal element 3022. The wiring 3031A and the capacitor 3023B correspond to the capacitor 3023. The wiring 3031A and the wiring 3031B correspond to the wiring 3031. The wiring 3032A and the wiring 3032B correspond to the wiring 3031. Corresponding to wiring 3032.

[0368] Here, the pixel of this embodiment, the semiconductor device of the first to sixth embodiments, and the shift register By combining it with a display, a signal line driver circuit, or a For example, when a subpixel structure is used as a pixel, the display device can be driven Therefore, the number of gate signal lines or source lines increases. The number of signal lines increases. As a result, the number of connections between the substrate on which the pixel unit is formed and the external circuit However, even if the number of gate signal lines increases, As shown in FIG. 1, the scanning line driver circuit can be formed on the same substrate as the pixel portion. This allows the sub-pixels to be connected without significantly increasing the number of connections between the substrate on which the pixel part is formed and the external circuit. Alternatively, even if the number of source signal lines increases, the embodiment By using the signal line driver circuit of 6, the number of source signal lines can be reduced. Therefore, the number of connections between the substrate on which the pixel part is formed and the external circuit can be reduced significantly. A pixel having a sub-pixel structure can be used.

[0369] Alternatively, when a signal is input to a capacitance line, the number of connections between the substrate on which the pixel unit is formed and the external circuit is Therefore, the semiconductor of the first to fifth embodiments is used for the capacitance line. A physical device or a shift register can be used to provide the signal. The semiconductor device or shift register of the first to fifth embodiments may be formed on the same substrate as the pixel section. Therefore, the number of connections between the substrate on which the pixel section is formed and the external circuit can be greatly reduced. A signal can be input to the capacitance line without increasing the capacitance.

[0370] Alternatively, when AC driving is used, the time required to write a video signal to a pixel becomes shorter. As a result, there may not be enough time to write the video signal to the pixels. In addition, when using pixels with a subpixel structure, the time required to write a video signal to the pixel is shortened. As a result, there may be insufficient time to write the video signal to the pixels. Therefore, it is possible to write a video signal to the pixel by using the signal line driver circuit of the sixth embodiment. In this case, a precharge voltage is applied to the pixel before writing the video signal to the pixel. Therefore, the video signal can be written to the pixel in a short time. ), the period in which one row is selected overlaps the period in which another row is selected. Therefore, it is possible to use a video signal of another row as a precharge voltage.

[0371] (Embodiment 8) In this embodiment, an example of a display device will be described with reference to FIGS. 35(A), 35(B), and 35(C). Here, a liquid crystal display device will be described as an example.

[0372] FIG. 35A is an example of a top view of a display device. A pixel portion 5393 is formed. An example of the driver circuit 5392 is a scanning line driver circuit. For example, in the case of a liquid crystal display device, the pixel portion 5393 includes a pixel. The pixel has a voltage applied to the liquid crystal element set in accordance with the output signal of the driver circuit 5392. can be.

[0373] FIG. 35(B) shows an example of the cross section AB of FIG. 35(A). 5400, a conductive layer 5401 formed on the substrate 5400, and An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. and a semiconductor layer 5403b formed on the semiconductor layer 5403a. a conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402; an insulating layer 5405 having an opening formed on the edge layer 5402 and on the conductive layer 5404; a conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405; an insulating layer 5408 disposed on the layer 5405 and on the conductive layer 5406; a liquid crystal layer 5407 formed on the insulating layer 5408; 5 shows a conductive layer 5409 formed over the conductive layer 5409 and a substrate 5410 formed over the conductive layer 5409 .

[0374] The conductive layer 5401 can function as a gate electrode. The conductive layer 5404 can function as a gate insulating film. The insulating layer 5405 can function as an electrode, an electrode of a capacitor, or the like. The conductive layer 5406 can function as a wiring, a pixel electrode, or a planarization film. The insulating layer 5408 can function as a polarizer or a reflector. The conductive layer 5409 can function as a counter electrode or a common electrode. It is possible.

[0375] Here, a parasitic capacitance may occur between the driver circuit 5392 and the conductive layer 5409. As a result, the output signal of the driver circuit 5392 or the potential of each node may be rounded or delayed. However, as shown in Figure 35(B), An insulating layer 5408 that can function as a sealant is formed on the driver circuit 5392. By forming the conductive layer 5409, the parasitic capacitance generated between the driving circuit 5392 and the conductive layer 5409 can be reduced. This is because the dielectric constant of the sealing material is often lower than that of the liquid crystal layer. Therefore, the output signal of the driver circuit 5392 or the potential of each node may be rounded. Alternatively, the delay can be reduced. Alternatively, the power consumption of the driver circuit 5392 can be reduced. can.

[0376] As shown in FIG. 35C, a film that functions as a sealant is provided on a part of the driver circuit 5392. In this case, an insulating layer 5408 can be formed. The parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 can be reduced. Therefore, it is possible to reduce the distortion or delay of the output signal of the driver circuit 5392 or the potential of each node. However, it is not limited to this, and a film that functions as a sealant can be provided on the driver circuit 5392. It is possible that the insulating layer 5408 is not formed.

[0377] The display element is not limited to a liquid crystal element, and may be any of various display elements such as an EL element or an electrophoretic element. It is possible to use a display element.

[0378] In the above, an example of the cross-sectional structure of the display device has been described in the present embodiment. and the semiconductor device or shift register according to any one of the first to fourth embodiments. For example, the semiconductor layer of the transistor can be formed of an amorphous semiconductor, a microcrystalline semiconductor, When an organic semiconductor or an oxide semiconductor is used, the channel width of the transistor becomes large. However, if the parasitic capacitance of the drive circuit can be reduced as in this embodiment, The channel width of the transistor can be reduced, which contributes to reducing the layout area. Therefore, the frame of the display device can be narrowed. It can be made thinner.

[0379] (Embodiment 9) In this embodiment, examples of the structure of a transistor are shown in FIGS. ) will be referred to for explanation.

[0380] FIG. 36(A) is a diagram showing an example of the structure of a display device, and also shows a top gate type transistor. 36(A) is a diagram showing an example of the structure of a display device. Also, an example of a structure of a bottom-gate transistor or an example of a structure of a display device is shown. FIG. 36(C) shows one example of the structure of a transistor manufactured using a semiconductor substrate. FIG.

[0381] An example of the transistor in FIG. 36(A) is formed on a substrate 5260 with an insulating layer 5261 sandwiched therebetween. and regions 5262a, 5262b, 5262c, 5262d, and 526 A semiconductor layer 5262 having 2e and an insulating layer 52 formed to cover the semiconductor layer 5262 63, a conductive layer 5264 formed on the semiconductor layer 5262 and the insulating layer 5263, and an insulating an insulating layer 5265 having an opening formed on the layer 5263 and the conductive layer 5264; and a conductive layer 5266 formed on the layer 5265 and in the opening of the insulating layer 5265.

[0382] An example of a transistor in FIG. 36B is a transistor including a conductive layer 5301 formed over a substrate 5300 and a 5302 formed to cover the conductive layer 5301; A semiconductor layer 5303a formed on the semiconductor layer 5302 and a A semiconductor layer 5303b and a conductive layer formed on the semiconductor layer 5303b and on the insulating layer 5302. a conductive layer 5304, and a conductive layer 5305 formed on the insulating layer 5302 and the conductive layer 5304 and having an opening. an insulating layer 5305 formed on the insulating layer 5305 and in the opening of the insulating layer 5305; layer 5306.

[0383] An example of the transistor in FIG. 36C is a semiconductor substrate having a region 5353 and a region 5355. a plate 5352, an insulating layer 5356 formed on the semiconductor substrate 5352, and a semiconductor substrate 53 An insulating layer 5354 is formed on the insulating layer 5356, and a conductive layer 535 is formed on the insulating layer 5356. 7, and an insulating layer 5354, an insulating layer 5356, and a conductive layer 5357 are formed on the insulating layer 5354, the insulating layer 5356, and the conductive layer 5357, and an opening is formed. and an insulating layer 5358 having a conductive film formed on the insulating layer 5358 and in the opening of the insulating layer 5358. The region 5350 and the region 5351 each have a conductive layer 5359. A zygote is created.

[0384] Note that when a display device is configured using the transistor of this embodiment, for example, 6(A), a conductive layer 5266 and an insulating layer 5265 are formed on the conductive layer 5266, and an opening an insulating layer 5267 having a first insulating layer 5268 and a second insulating layer 5269 formed on the insulating layer 5267 and in the opening of the insulating layer 5267; a conductive layer 5268 having an opening formed on the insulating layer 5267 and the conductive layer 5268; and an insulating layer 5269 having a conductive film formed on the insulating layer 5269 and in the opening of the insulating layer 5269. A light-emitting layer 5270 and a conductive layer 52 formed on the insulating layer 5269 and on the light-emitting layer 5270. 71 and can be formed.

[0385] 36(B), a conductive layer 5306 is disposed over the insulating layer 5305. and a conductive layer 5308 formed on the liquid crystal layer 5307. It is possible.

[0386] The insulating layer 5261 can function as a base film. The insulating layer 5263, the insulating layer 5302, and the insulating layer 5303 function as an isolation layer (for example, a field oxide film). The insulating layer 5356 can function as a gate insulating film. The insulating layer 5301 and the conductive layer 5357 can function as gate electrodes. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 are interlayer films or flat films. The conductive layer 5266, the conductive layer 5304, and the conductive layer 5305 can function as a conductive film. 359 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The conductive layer 5268 and the conductive layer 5306 can be used as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a partition wall. The conductive layer 5271 and the conductive layer 5308 can function as a counter electrode, a common electrode, or the like. It is possible to do this.

[0387] Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, a semiconductor substrate ( For example, a single crystal substrate (e.g., a silicon substrate), a SOI substrate, a plastic Metal substrate, stainless steel substrate, substrate with stainless steel foil, tongue Tungsten substrates, tungsten foil substrates, flexible substrates, glass substrates, etc. Examples of suitable glass include barium borosilicate glass and aluminoborosilicate glass. Examples of flexible substrates include polyethylene terephthalate (PET), polyethylene naphtha Plastics such as polyethersulfone (PEN) and polyethersulfone (PES), or There are also flexible synthetic resins such as acrylic. propylene, polyester, vinyl, polyvinyl fluoride, polyvinyl chloride, etc.), fibrous materials Including paper, base film (polyester, polyamide, polyimide, inorganic vapor deposition film, Paper, etc.

[0388] The semiconductor substrate 5352 is, for example, a single-crystal Si substrate having n-type or p-type conductivity. The region 5353 is, for example, a semiconductor substrate 5352 having impurities. For example, if the semiconductor substrate 5352 is a p-type When the region 5353 has a conductivity type of n-type, the region 5353 functions as an n-well. On the other hand, if the semiconductor substrate 5352 has n-type conductivity, the region 5353 has p-type conductivity. The region 5355 has a conductivity type and functions as a p-well. It is a region doped in the plate 5352 and functions as a source region or a drain region. In the semiconductor substrate 5352, an LDD region can be formed.

[0389] Examples of the insulating layer 5261 include silicon oxide (SiOx), silicon nitride (SiNx), and oxynitride. Silicon nitride (SiOxNy) (x>y>0), silicon nitride oxide (SiNxOy) (x>y>0) The insulating layer 5261 may be a film containing oxygen or nitrogen, such as a film containing oxygen or nitrogen, or a laminate structure of these. In one example of a two-layer structure, a silicon nitride film is provided as the first insulating layer, A silicon oxide film can be provided as the second insulating layer. The insulating layer 5261 has a three-layer structure. For example, a silicon oxide film is provided as the first insulating layer, and a silicon dioxide film is provided as the second insulating layer. It is possible to provide a silicon nitride film as an insulating layer and a silicon oxide film as a third insulating layer. do.

[0390] An example of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b is a non-single layer. Crystalline semiconductors (e.g., amorphous silicon, polycrystalline silicon, microcrystalline silicon) semiconductors, compound semiconductors or oxide semiconductors (e.g., ZnO, InG aZnO, SiGe, GaAs, IZO, ITO, SnO, AZTO, organic semiconductors, or Carbon nanotubes, etc.

[0391] For example, the region 5262a is an intrinsic semiconductor layer 5262 to which no impurities are added. However, when impurities are added to the region 5262a, the region 5262a functions as a channel region. The impurity added to the region 5262a can be added to the region 5262b, the region 5262c, and the region 5262d. 2c, region 5262d, or region 5262e. It is preferable that the region 5262b and the region 5262d are not included in the region 5262c or the region 5262e. This region is doped with impurities at a lower concentration than the LDD region. The area 5262b and the area 5262d can be omitted. The region 5262e is a region where impurities are added to the semiconductor layer 5262 at a high concentration. The gate electrode functions as a drain region.

[0392] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. It has n-type conductivity.

[0393] When an oxide semiconductor or a compound semiconductor is used for the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0394] An example of the insulating layer 5263, the insulating layer 5302, and the insulating layer 5356 is silicon oxide (Si Ox), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y>0), nitriding acid a film containing oxygen or nitrogen, such as silicon carbide (SiNxOy) (x>y>0), or There are also laminated structures.

[0395] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301, A conductive layer 5304, a conductive layer 5306, a conductive layer 5308, a conductive layer 5357, and a conductive layer 535 The conductive film 9 can have a single layer structure or a multilayer structure. Examples of these include aluminum (Al), tantalum (Ta), titanium (Ti), and molybdenum (Mo). Mo, Tungsten (W), Neodymium (Nd), Chromium (Cr), Nickel (Ni ), platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon (C), scandium (Sc), zinc (Zn), gallium (Ga), indium (In) tin (Sn), zirconium (Zr), and cerium (Ce) A single film of one element selected from the group, or a compound containing one or more elements selected from the group, etc. The simple films or compounds include phosphorus (P), boron (B), arsenic (As), and and / or oxygen (O). Examples of such compounds include the aforementioned Alloys containing one or more elements selected from multiple elements (e.g., ITO, IZO, Indium tin oxide with silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO ), Cadmium Tin Oxide (CTO), Aluminum Neodymium (Al-Nd), Aluminum Tungsten (Al-W), aluminum zirconium (Al-Zr), aluminum titanium Titanium (Al-Ti), Aluminum Cerium (Al-Ce), Magnesium Silver (Mg-A g), Molybdenum-niobium (Mo-Nb), Molybdenum-tungsten (Mo-W), Molyb alloy materials such as tantalum (Mo-Ta), and one or more of the elements mentioned above. or compounds of nitrogen with multiple elements (e.g., titanium nitride, tantalum nitride, molybdenum nitride, etc.) nitride film, or a combination of one or more elements selected from the above elements Compounds with silicon (e.g., tungsten silicide, titanium silicide, nickel silicide) Silicide films such as aluminum silicon, molybdenum silicon, etc. Other examples include carbon nanotubes, organic nanotubes, inorganic nanotubes, and gold nanotubes. Nanotube materials include metal nanotubes.

[0396] Insulating layer 5265, insulating layer 5267, insulating layer 5269, insulating layer 5305, and insulating layer 535 An example of the insulating layer 8 is a single-layer insulating layer or a laminated structure of these layers. Examples include silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride ( Oxygen such as SiOxNy (x>y>0) and silicon nitride oxide (SiNxOy) (x>y>0) or a film containing nitrogen, a film containing carbon such as DLC (diamond-like carbon), or , siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzo Examples include organic materials such as cyclobutene and acrylic.

[0397] An example of the light-emitting layer 5270 is an organic EL element or an inorganic EL element. An example of the element is a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material; an electron transport layer made of an electron transport material; A single layer structure of an electron injection layer, or a layer in which a plurality of materials among these materials are mixed, or These include laminated structures.

[0398] An example of the liquid crystal layer 5307, an example of a liquid crystal material applicable to the liquid crystal layer 5307, or the liquid crystal layer 530 Examples of liquid crystal modes applicable to liquid crystal elements including 7 include nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystals, discotic liquid crystals, thermotropic liquid crystals, lyotropic liquid crystals Cliotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), Ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma addressed liquid crystal (P ALC), banana type LCD, TN (Twisted Nematic) mode, STN (S Super Twisted Nematic mode, IPS (In-Plane-Switched) mode Fringe Field Switching (FFS) mode mode, MVA (Multi-domain Vertical Alignment) mode code, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Sym metric aligned Micro-cell) mode, OCB (Optica) l Compensated Birefringence mode, ECB (Electronic Control Board) Electrically Controlled Birefringence mode, FL C (Ferroelectric Liquid Crystal) mode, AFLC ( AntiFerroelectric Liquid Crystal) mode, PDL C (Polymer Dispersed Liquid Crystal) mode, There are various modes, such as Stormhost mode and Blue Phase mode.

[0399] Note that an insulating layer functioning as an alignment film is provided over the insulating layer 5305 and the conductive layer 5306. It is possible to form an insulating layer or the like that functions as a protrusion.

[0400] Note that a color filter, a black matrix, or a protrusion may be formed on the conductive layer 5308. An insulating layer or the like that functions as an alignment film can be formed under the conductive layer 5308. It is possible to form an insulating layer that acts as a barrier.

[0401] The transistor of this embodiment can be applied to the first to eighth embodiments. In particular, in FIG. 36(B), the semiconductor layer is made of an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or the like. When a semiconductor or an oxide semiconductor is used, the transistor may deteriorate. Therefore, the transistor of this embodiment can be used in a semiconductor device, a shift register, or a display device. However, if the semiconductor devices of the first to eighth embodiments are used, their lifespans will be shortened. In semiconductor devices, shift registers, or display devices, deterioration of transistors can be suppressed. Therefore, the transistor of this embodiment can be used in combination with the semiconductors of the first to eighth embodiments. By applying it to devices, shift registers, or display devices, the life of these devices can be extended. It is possible.

[0402] (Embodiment 10) In this embodiment, an example of a manufacturing process of a transistor and a capacitor will be described. A manufacturing process in the case where an oxide semiconductor is used for the layer will be described.

[0403] 37(A) to 37(C), an example of a manufacturing process of a transistor and a capacitor will be described. 37A to 37C show a transistor 5441 and a capacitor 5442. The transistor 5441 is an example of an inverted staggered thin film transistor. a wiring is provided over the oxide semiconductor layer with a source electrode or a drain electrode interposed therebetween; This is an example of a transistor.

[0404] First, a first conductive layer is formed on the entire surface of the substrate 5420 by sputtering. A resist mask formed by a photolithography process using a first photomask is used. Then, the first conductive layer is selectively etched to form a conductive layer 5421 and a conductive layer 5422. The conductive layer 5421 can function as a gate electrode, and the conductive layer 542 2 can function as one electrode of a capacitor element. The conductive layers 5421 and 5422 are used as wirings, gate electrodes, or electrodes of a capacitor. After this, the resist mask is removed.

[0405] Next, an insulating layer 5423 is formed on the entire surface by plasma CVD or sputtering. The insulating layer 5423 can function as a gate insulating layer, and the conductive layer 5421, The insulating layer 5423 is formed to cover the conductive layer 5422. It is often ~250 nm.

[0406] Next, a resist mask formed by a photolithography process using a second photomask 5423 to selectively etch the insulating layer 5423 to form a contact that reaches the conductive layer 5421. A hole 5424 is formed. After this, the resist mask is removed. However, the present invention is not limited to this. Therefore, the contact hole 5424 can be omitted. After the formation, a contact hole 5424 can be formed. The cross-sectional view corresponds to FIG.

[0407] Next, an oxide semiconductor layer is formed on the entire surface by sputtering. The oxide semiconductor layer is formed by sputtering, and a buffer layer (e.g., For example + The oxide semiconductor layer can be formed with a thickness of 5 nm to 2 00nm in most cases.

[0408] Next, a resist mask formed by a photolithography process using a third photomask The oxide semiconductor layer is selectively etched using the resist mask. do.

[0409] Next, a second conductive layer is formed on the entire surface by sputtering. The second conductive layer is selectively formed using a resist mask formed by a photolithography process. The conductive layer 5429, the conductive layer 5430, and the conductive layer 5431 are formed by etching the conductive layer 5429, the conductive layer 5430, and the conductive layer 5431. The conductive layer 5429 is connected to the conductive layer 5421 through a contact hole 5424. The conductive layer 5429 and the conductive layer 5430 function as a source electrode and a drain electrode. The conductive layer 5431 can function as the other electrode of the capacitor. However, the conductive layer 5429, the conductive layer 5430, and the conductive layer 54 31 is a part that functions as a wiring, a source or drain electrode, or an electrode of a capacitor element. It is possible to include

[0410] If heat treatment (for example, at 200°C to 600°C) is to be performed after this, Therefore, the second conductive layer is preferably made of Al and a heat-resistant material. Highly thermally conductive materials (e.g., Ti, Ta, W, Mo, Cr, Nd, Sc, Zr, Ce) Elements such as these, alloys combining these elements, or nitrides containing these elements However, it is not limited to this, and the second conductive material is also preferable. By forming the second conductive layer into a laminated structure, it is possible to provide the second conductive layer with high heat resistance. For example, it is possible to provide a highly heat-resistant conductive material such as Ti or Mo above and below Al. It is Noh.

[0411] When etching the second conductive layer, a part of the oxide semiconductor layer is also etched. By this etching, an oxide semiconductor layer 5425 overlapping with the conductive layer 5421 is formed. the oxide semiconductor layer 5425 in a portion where the second conductive layer is not formed or the oxide semiconductor layer 5425 in a portion where the second conductive layer is not formed The oxide semiconductor layer 5425 is often thinned by being etched. Therefore, the oxide semiconductor layer 5425 may not be etched. On the nitride semiconductor layer 5425 + In the case where a layer is formed, the oxide semiconductor layer 5425 is After this, the resist mask is removed. At this stage, the transistor 5441 and the capacitor 5442 are completed. The plan view corresponds to Figure 37(B).

[0412] Next, a heat treatment is performed at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere. This thermal treatment causes rearrangement at the atomic level in the oxide semiconductor layer 5425. This heating (including photo-annealing) releases the strain that inhibits carrier movement. The timing of the treatment is not limited, and various timings can be used after the formation of the oxide semiconductor layer. This can be done in a group.

[0413] Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 may have a single-layer structure. For example, the insulating layer 5432 may be an organic insulating layer. When using the above, a composition that is a material for the organic insulating layer is applied, and the composition is then heated under an air atmosphere or a nitrogen atmosphere. Then, a heat treatment is performed at 200 to 600°C to form an organic insulating layer. By forming an organic insulating layer in contact with the semiconductor layer 5425, a highly reliable thin film transistor can be obtained. When an organic insulating layer is used as the insulating layer 5432, A silicon nitride film or a silicon oxide film can be provided under the insulating layer.

[0414] In addition, in FIG. 37(C), a mode in which the insulating layer 5432 is formed using a non-photosensitive resin is shown. For illustration, in the cross section of the region where the contact hole is to be formed, the end of the insulating layer 5432 is However, when the insulating layer 5432 is formed using a photosensitive resin, the contact In the cross section of the region where the cut hole is formed, the end of the insulating layer 5432 can be curved. As a result, the coverage of the third conductive layer or pixel electrode to be formed later is improved.

[0415] Instead of applying the composition, dipping, spray application, or ink application may be used depending on the material. Ink jet method, printing method, doctor knife, roll coater, curtain coater, or An ifcoater or the like can be used.

[0416] Note that the composition of the material for the organic insulating layer was not subjected to heat treatment after the oxide semiconductor layer was formed. The heat treatment can also serve as heat treatment for the oxide semiconductor layer 5425.

[0417] The thickness of the insulating layer 5432 is 200 nm to 5 μm, preferably 300 nm to 1 μm. It is possible to do this.

[0418] Next, a third conductive layer is formed on the entire surface. Next, a photolithography process is performed using a fifth photomask. The third conductive layer is selectively etched using the resist mask formed by the etching process. A conductive layer 5433 and a conductive layer 5434 are formed. A cross-sectional view of the process up to this stage is shown in FIG. The conductive layer 5433 and the conductive layer 5434 correspond to a wiring, a pixel electrode, a reflective electrode, a transparent electrode, and the like. The conductive layer 5434 can function as a photo-transistor or an electrode of a capacitor. Since the conductive layer 5422 is connected to the conductive layer 5422, the conductive layer 5422 can function as an electrode of the capacitor 5442. However, the present invention is not limited to this, and the conductive layer formed using the first conductive layer and the second conductive layer may be used. For example, the conductive layer may have a function of connecting to the conductive layer formed by using the conductive layer. By connecting the layer 5433 and the conductive layer 5434, the conductive layer 5422 and the conductive layer 543 0 can be connected via the third conductive layer (conductive layer 5433 and conductive layer 5434). becomes.

[0419] Note that the capacitor 5442 is formed by the conductive layer 5422 and the conductive layer 5434. Since the structure is such that 1 is sandwiched, the capacitance value of the capacitor 5442 can be increased. However, the present invention is not limited to this, and one of the conductive layer 5422 and the conductive layer 5434 may be omitted. It is Noh.

[0420] After the resist mask is removed by wet etching, the substrate is etched in air or nitrogen atmosphere. It is possible to carry out a heat treatment at 200 to 600°C under the above temperature.

[0421] Through the above steps, the transistor 5441 and the capacitor 5442 can be manufactured. .

[0422] As shown in FIG. 37D, an insulating layer 5435 is formed over the oxide semiconductor layer 5425. The insulating layer 5435 can be used to prevent oxidation when the second conductive layer is patterned. It has the function of preventing the nitride semiconductor layer 5425 from being scraped off, and functions as a stop film. Therefore, the thickness of the oxide semiconductor layer 5425 can be reduced, Reduction of drive voltage, reduction of off-current, improvement of on / off ratio of drain current, improvement of S value, etc. Note that the insulating layer 5435 is formed by continuously forming the oxide semiconductor layer and the insulating layer. The pattern is then formed on the entire surface, and then a pattern is formed by a photolithography process using a photomask. The insulating layer is selectively patterned using a resist mask to form a Thereafter, a second conductive layer is formed on the entire surface, and an oxide semiconductor layer is formed simultaneously with the second conductive layer. That is, the oxide semiconductor layer and the second In this case, an oxide film must be formed under the second conductive layer. In this way, the insulating layer 543 is formed without increasing the number of steps. In such a manufacturing process, an oxide semiconductor layer is formed under the second conductive layer. However, the present invention is not limited to this, and the oxide semiconductor layer may be patterned. After the wiring, an insulating layer is formed on the entire surface, and the insulating layer is patterned to form an insulating film. A layer 5435 can be formed.

[0423] In FIG. 37D, the capacitor 5442 includes a conductive layer 5422 and a conductive layer 5431. The insulating layer 5423 and the oxide semiconductor layer 5436 are sandwiched between the insulating layer 5423 and the oxide semiconductor layer 5436. The oxide semiconductor layer 5436 can be omitted. 5431 is connected via a conductive layer 5437 formed by patterning the third conductive layer. Such a structure can be used, for example, in the pixels of a liquid crystal display device. For example, the transistor 5441 functions as a switching transistor and The element 5442 can function as a storage capacitor. The conductive layer 5422, the conductive layer 5429, and the conductive layer 5437 are gate lines, capacitance lines, and source lines, respectively. , can function as a pixel electrode. However, it is not limited to this. 37(D), the conductive layer 5430 and the conductive layer 5431 are connected to the third The connection can be made through a conductive layer.

[0424] As shown in FIG. 37(E), after the second conductive layer is patterned, the oxide semiconductor layer 5425. By doing so, the second conductive layer can be patterned. In this case, the oxide semiconductor layer 5425 is not formed. Therefore, the oxide semiconductor layer 5425 can be thin. Therefore, it is possible to reduce the driving voltage of the transistor, reduce the off-current, and improve the on-off ratio of the drain current. The oxide semiconductor layer 5425 can be formed by After the conductive layer is patterned, an oxide semiconductor layer 5425 is formed on the entire surface. Selective resist mask formed by photolithography process using a photomask The oxide semiconductor layer 5425 can be formed by patterning the oxide semiconductor layer 5425 in a predetermined manner.

[0425] In FIG. 37E, the capacitor 5442 is formed by connecting the conductive layer 5422 and the third conductive layer. The insulating layer 5423 and the insulating layer 5432 are formed by the conductive layer 5439 formed by turning. The conductive layer 5422 and the conductive layer 5430 are sandwiched between the third conductive layer. The connection is made via a conductive layer 5438 formed by patterning. 9 is connected to a conductive layer 5440 formed by patterning the second conductive layer. 37(E), in FIGS. 37(C) and (D), the conductive layer 5430 and the conductive layer 54 22 can be connected via a conductive layer 5438.

[0426] The thickness of the oxide semiconductor layer (or channel layer) is determined by the thickness of the depletion layer when the transistor is off. By making the thickness of the gate electrode less than this, it is possible to create a fully depleted state. In order to achieve this, the off-state current of the oxide semiconductor layer 5425 can be reduced. The film thickness is preferably 20 nm or less, and more preferably 10 nm or less. It is especially preferable that the thickness is 6 nm or less.

[0427] In addition, the reduction of the transistor operating voltage, the reduction of the off-current, and the improvement of the on-off ratio of the drain current are also important. In order to improve the S value, the thickness of the oxide semiconductor layer is set to be equal to the thickness of the layers constituting the transistor. For example, the oxide semiconductor layer is preferably thinner than the insulating layer 5423. The thickness of the oxide semiconductor layer is preferably thinner than that of the insulating layer 5423. It is preferably 1 / 2 or less, and more preferably 1 / 5 or less. More preferably, it is 1 / 10 or less. However, it is not limited to this. In order to improve reliability, the oxide semiconductor layer may be thicker than the insulating layer 5423. In particular, when the oxide semiconductor layer is removed as shown in FIG. Since the thickness of the conductor layer is preferably thick, the thickness of the oxide semiconductor layer is set to be thicker than that of the insulating layer 5423. It is possible to make the thickness of the film thicker.

[0428] In order to increase the dielectric strength of the transistor, the thickness of the insulating layer 5423 is set to be equal to or larger than that of the first conductive layer. It is preferable that the thickness of the insulating layer 5423 is thicker than that of the first conductive layer. It is preferable that the thickness is 5 / 4 or more of the layer, and more preferably 4 / 3 or more. However, the present invention is not limited to this, and the insulating layer 54 may be used to increase the mobility of the transistor. The thickness of 23 can be thinner than that of the first conductive layer.

[0429] The substrate, insulating layer, conductive layer, and semiconductor layer of this embodiment may be the same as those of other embodiments. Materials described or similar to those described herein can be used.

[0430] The transistor of this embodiment may be used in the semiconductor device of the first to eighth embodiments, the shift register, or the like. By using it in a computer or a display device, the display area can be enlarged. The part can be made highly detailed.

[0431] (Embodiment 11) In this embodiment, a layout diagram (hereinafter also referred to as a top view) of a shift register will be described. In this embodiment, as an example, the layer of the shift register described in the fourth embodiment is The contents explained in this embodiment are the same as those in the fourth embodiment. In addition to the shift registers described above, the semiconductor devices and shift registers according to the first to seventh embodiments are also The layout diagram of this embodiment is It should be noted that this is just an example and is not limiting.

[0432] The layout diagram of this embodiment will be described with reference to FIG. 38. FIG. 38 shows an example of a layout diagram. The layout diagram of FIG. 5(A) is shown as an example. The hatching pattern shown on the right side of FIG. indicates the hatching patterns of the components of the symbols attached to each hatching pattern. This shows that.

[0433] The transistor or wiring shown in FIG. 38 includes a conductive layer 701, a semiconductor layer 702, a conductive layer 703, and a 703, a conductive layer 704, and a contact hole 705. Without limitation, it is possible to form another conductive layer, an insulating film, or another contact hole. For example, a contact hole for connecting the conductive layer 701 and the conductive layer 703 may be added. It is possible to do this.

[0434] The conductive layer 701 can include a portion that functions as a gate electrode or a wiring. The conductor layer 702 may include a portion that functions as a semiconductor layer of a transistor. The conductive layer 703 may include a portion functioning as a wiring, a source electrode, or a drain electrode. The conductive layer 704 functions as a light-transmitting electrode, a pixel electrode, or a wiring. The contact hole 705 can include a conductive layer 701 and a conductive layer 704. or a function of connecting the conductive layer 703 and the conductive layer 704 .

[0435] In this embodiment, the transistor 101_1, the transistor 101_2, the transistor 2 01_1 and / or the transistor 202_2, which functions as a second terminal. The area where the conductive layer 703 overlaps with the conductive layer 701 is the conductive layer having the function of the first terminal. It is preferable that the area is smaller than the area where the layer 703 and the conductive layer 701 overlap. Therefore, the concentration of the electric field on the second terminal can be suppressed, and the deterioration of the transistor or However, the second terminal is not limited to this and may be any other terminal. The area where the conductive layer 703 having all the functions and the conductive layer 701 overlap is The area of ​​the conductive layer 703 having the function and the conductive layer 701 can be larger than the overlap area. .

[0436] Note that a semiconductor layer 702 is formed in a portion where the conductive layer 701 and the conductive layer 703 overlap each other. By doing so, the parasitic capacitance between the conductive layer 701 and the conductive layer 703 can be reduced. For the same reason, the conductive layer A semiconductor layer 702 can be formed in the area where the conductive layer 704 overlaps with the conductive layer 703. .

[0437] The conductive layer 704 is formed on a part of the conductive layer 701. It is possible to connect with the conductive layer 704 through the hole 705. Alternatively, the conductive layer 703 may be formed on a part of the conductive layer 701. and a conductive layer 704 are formed, and the conductive layer 701 is connected to the The conductive layer 703 is connected to the conductive layer 704 through another contact hole 705. It is possible to connect with the conductive layer 704. By doing so, the wiring resistance can be reduced. It is possible.

[0438] The conductive layer 704 is formed on a part of the conductive layer 703. It is possible to connect with the conductive layer 704 through the hole 705. This can reduce the wiring resistance.

[0439] Note that the conductive layer 701 or the conductive layer 703 is formed under a part of the conductive layer 704, and the conductive layer 704 is connected to the conductive layer 701 or the conductive layer 703 through a contact hole 705. By doing so, the wiring resistance can be reduced. .

[0440] As already mentioned, the parasitic capacitance between the gate and the first terminal of the transistor 101_1 The parasitic capacitance between the gate and the second terminal of the transistor 101_1 is set to be larger than the amount of As shown in FIG. 38, a transistor 101_1 serving as a first terminal thereof can be provided. The width of the conductive layer 703 that can be connected to the second terminal of the transistor 101_1 is indicated as a width 731. The width of the conductive layer 703 that can function as a This allows the width of transistor 101 to be greater than the width 732. The parasitic capacitance between the gate of the transistor 101_1 and the second terminal is larger than the parasitic capacitance between the gate of the transistor 101_1 and the first terminal. It is possible to increase the parasitic capacitance between the terminals, but this is not limitative.

[0441] As already mentioned, the parasitic capacitance between the gate and the first terminal of the transistor 101_2 The parasitic capacitance between the gate and the second terminal of the transistor 101_2 is set to be larger than the amount of As shown in FIG. 38, a transistor 101_2 serving as a first terminal thereof can be provided. The width of the conductive layer 703 that can be connected to the second terminal of the transistor 101_2 is indicated as width 741. The width of the conductive layer 703 that can function as a This allows the width of transistor 101 to be greater than the width 742. The parasitic capacitance between the gate of the transistor 101_2 and the second terminal is larger than the parasitic capacitance between the gate of the transistor 101_3 and the first terminal. It is possible to increase the parasitic capacitance between the terminals, but this is not limitative.

[0442] (Embodiment 12) In this embodiment, an example of an electronic device will be described.

[0443] 39(A) to 39(H) and 40(A) to 40(D) ​​are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, an LED Lamp 5004, operation key 5005 (operation switch for controlling the operation of the display device, or power switch), connection terminal 5006, sensor 5007 (force, displacement, position, velocity, acceleration , angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, The function of measuring current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared 5008, etc.

[0444] FIG. 39(A) shows a mobile computer, which includes, in addition to the above, a switch 5009, It may have an infrared port 5010, etc. FIG. 39(B) shows a portable device equipped with a recording medium. A type of image reproducing device (for example, a DVD reproducing device), which, in addition to the above, also has a second display 39(C) shows a GOG In addition to the above, the display includes a second display unit 5002, a support unit 5012, The game machine may have earphones 5013, etc. Figure 39(D) shows a portable game machine. In addition to the above, it can have a recording medium reading unit 5011, etc. In addition to the components described above, the projector includes a light source 5033, a projection lens 5034, etc. FIG. 39(F) shows a portable gaming machine, which, in addition to the above, has a second display unit 39(G) shows a television receiver. In addition to the components described above, the image sensor may also include a tuner, an image processor, etc. 39(H) is a portable television receiver, which, in addition to the above, is capable of transmitting and receiving signals. 40(A) is a display, and the above-mentioned In addition to the above, it may have a support stand 5018, etc. Figure 40(B) shows a camera. In addition to the above, an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 40(C) is a computer, and In addition, there are a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 40(D) ​​shows a mobile phone, which can have the above-mentioned 2, an antenna 5014, a 1-segment partial reception service tuner for mobile phones and mobile terminals It may have a lens, etc.

[0445] The electronic devices shown in FIGS. 39(A) to 39(H) and 40(A) to 40(D) ​​are various For example, various information (still images, videos, text images, etc.) Function to display on the display, touch panel function, calendar, date or time, etc. Functions, functions to control processing by various software (programs), wireless communication functions, The ability to connect to various computer networks using wireless communication functions, The function of transmitting or receiving various data using the program or The data can be read out and displayed on the display unit. In electronic devices with displays, one display is used primarily to display image information, and another is used The function of displaying text information mainly on one display unit, or displaying images that take parallax into account on multiple displays. By displaying a stereoscopic image, the device can have the function of displaying a stereoscopic image. In electronic devices with an image unit, there are functions for taking still images, taking videos, and The function to automatically or manually correct the captured image, and to store the captured image on a recording medium (external or built-in to the camera). ) and displaying the captured image on the display unit. The electronic devices shown in FIGS. 39(A) to 39(H) and 40(A) to 40(D) ​​are The functions that can be performed are not limited to these, and various other functions can be performed.

[0446] The electronic device described in this embodiment has a display unit for displaying some information. The electronic device of this embodiment and the semiconductor device of any one of the first to ninth embodiments are characterized in that: By combining it with a device, a shift register, or a display device, the reliability and yield can be improved. This allows for improved resolution, cost reduction, larger display area, and higher resolution display area. .

[0447] Next, application examples of the semiconductor device will be described.

[0448] FIG. 40(E) shows an example in which a semiconductor device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. 025, etc. The semiconductor device is a wall-mounted type that is integrated with the building, and the installation space is limited. It can be installed without requiring a large space.

[0449] FIG. 40(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027 as a unit. The display panel 5026 becomes viewable.

[0450] In this embodiment, a wall and a unit bath are used as examples of buildings. The manner in which the semiconductor device is installed is not limited to this, and the semiconductor device can be installed in various buildings.

[0451] Next, an example in which the semiconductor device is integrated with a moving object will be described.

[0452] FIG. 40G is a diagram showing an example in which the semiconductor device is provided in an automobile. 5028 is attached to the body 5029 of the automobile, and is The information entered can be displayed on demand. It may be possible.

[0453] FIG. 40(H) is a diagram showing an example in which a semiconductor device is integrated with a passenger airplane. FIG. 40(H) shows a passenger plane with a display panel 5031 on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 50. 30 and the hinge part 5032 are attached together, and the extension and contraction of the hinge part 5032 This allows passengers to view the display panel 5031. The display panel 5031 is operated by passengers. It has the function of displaying information by

[0454] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorails, etc.), It can be installed on a variety of things, including buildings, railways, ships, etc. [Explanation of symbols]

[0455] 10 circuits 11_1 switch 11_2 Switch 11 Switch 21 Routes 100 circuits 101 Transistor 101p transistor 101a diode 102 transistor 102p transistor 111 Wiring 112 Wiring 111A wiring 112A wiring 112B wiring 114A wiring 114B wiring 117A wiring 117B wiring 117C wiring 117D Wiring 117E wiring 117F wiring 117G wiring 117H Wiring 117I wiring 117J wiring 117K wiring 301a diode 301p transistor 3020 pixels 3021 Transistor 3022 Liquid crystal element 3023 Capacitor element 302a diode 302p transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 118 Wiring 120 circuits 121 Capacitor element 122 transistors 200 circuits 201 Transistor 202 Transistor 203 Transistor 211 Wiring 300 circuits 301 Transistor 302 Transistor 303 Transistor 303a diode 303p transistor 304 Transistor 304a diode 304p transistor 310 circuits 311 Transistor 312 Transistor 313 Transistor 314 Transistor 315 Capacitor 316 Transistor 320 circuits 321 Transistor 322 transistor 323 Transistor 324 transistors 325 Capacitor 326 Transistor 330 circuits 331 Transistor 332 transistors 333 Transistor 334 Transistor 335 Transistor 336 Transistor 342 transistors 344 transistors 500 Shift Registers 501 Flip-Flop 511 Wiring 512 Wiring 513 Wiring 514 Wiring 515 Wiring 516 Wiring 517 Wiring 518 Wiring 520 circuits 521 circuits 522 circuits 600 circuits 601 circuits 602 circuits 603 Transistor 604 Wiring 605 Wiring 614 signal 615 Signal 701 Conductive layer 702 Semiconductor layer 703 Conductive layer 704 Conductive layer 705 Contact Hole 731 width 732 width 741 width 742 width 3031 Wiring 3032 Wiring 3033 Wiring 3034 Electrode 3041 Signal 3042 signal 3043 Voltage 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 pointing device 5021 Reader / Writer 5022 Housing 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit bath 5028 Display Panel 5029 Car Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection lens 5260 board 5261 Insulation layer 5262 Semiconductor layer 5263 Insulation layer 5264 Conductive layer 5265 Insulation layer 5266 Conductive layer 5267 Insulation layer 5268 Conductive layer 5269 Insulation layer 5270 luminous layer 5271 Conductive layer 5273 Insulation layer 5300 board 5301 Conductive layer 5302 Insulation layer 5304 Conductive layer 5305 Insulation layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulation layer 5355 area 5356 Insulation layer 5357 Conductive layer 5358 Insulation layer 5359 Conductive layer 5360 video signal 5361 Circuit 5362 Circuit 5363 Circuit 5364 Pixel section 5365 Circuit 5366 Lighting equipment 5367 pixels 5371 Wiring 5372 Wiring 5373 Wiring 5380 PCB 5381 input terminal 5391 Circuit Board 5392 drive circuit 5393 Pixel section 5400 board 5401 Conductive layer 5402 Insulation layer 5404 Conductive layer 5405 Insulation layer 5406 Conductive layer 5407 Liquid crystal layer 5408 Insulation layer 5409 Conductive layer 5410 PCB 5420 PCB 5421 Conductive layer 5422 Conductive layer 5423 Insulation layer 5424 Contact Hole 5425 Oxide semiconductor layer 5429 Conductive layer 5430 Conductive layer 5431 Conductive layer 5432 Insulation layer 5433 Conductive layer 5434 Conductive layer 5435 Insulation layer 5436 Oxide semiconductor layer 5437 Conductive layer 5438 Conductive layer 5439 Conductive layer 5440 Conductive layer 5441 Transistor 5442 Capacitor element 3020A subpixel 3020B subpixel 3021A Transistor 3021B Transistor 3022A Liquid Crystal Element 3022B Liquid crystal element 3023A Capacitive Element 3023B Capacitive Element 3031A Wiring 3031B wiring 3032A Wiring 3032B wiring 5262a area 5262b area 5262c area 5262d area 5262e area 5303a Semiconductor layer 5303b Semiconductor layer 5361a circuit 5361b circuit 5362a circuit 5362b circuit 5403a Semiconductor layer 5403b Semiconductor layer

Claims

[Claim 1] forming a first conductive layer functioning as a gate electrode of a transistor and a second conductive layer functioning as a first electrode of a capacitor over a substrate; forming a first insulating layer having a region disposed above the first conductive layer and having a region disposed above the second conductive layer; forming a contact hole in the first insulating layer that reaches the first conductive layer; forming an oxide semiconductor layer having a region overlapping with the first conductive layer via the first insulating layer in which the contact hole is formed, above the first insulating layer; forming a third conductive layer having a region disposed above the first insulating layer and a region disposed above the oxide semiconductor layer; and etching the third conductive layer to form a fourth conductive layer having a function as a second electrode of the capacitor, a fifth conductive layer having a function as a source electrode of the transistor, and a sixth conductive layer having a function as a drain electrode of the transistor. A method for manufacturing a semiconductor device.

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