Semiconductor device

Abstract

An object is to suppress deterioration in characteristics of a transistor in a driver circuit.SOLUTION: The semiconductor device includes a circuit 200, a transistor 101 _ 1, and a transistor 101 _ 2, on / off of the transistor 101 _ 1 and the transistor 101 _ 2 is controlled by selective input of a signal from the circuit 200 to a gate, and the wiring 112 and the wiring 111 are brought into a conduction state or a non-conduction state by on / off of the transistor 101 _ 1 or the transistor 101 _ 2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Semiconductor device, display device, liquid crystal display device, light-emitting device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device having a driver circuit formed on the same substrate as a pixel portion, The present invention relates to a display device, a liquid crystal display device, a light emitting device, or a driving method thereof. electronic equipment having the display device, the liquid crystal display device, or the light-emitting device . [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single-crystal semiconductors are used to form a pixel portion. The technology of configuring drive circuits such as gate drivers on the board is expected to significantly reduce costs and improve reliability. Development is underway actively to contribute significantly to the

[0003] A transistor made of a non-single-crystal semiconductor has a fluctuation in threshold voltage or a decrease in mobility. As this transistor degradation progresses, the drive circuit becomes difficult to operate, Therefore, there is a problem that the image cannot be displayed. Patent Document 1 describes a function of maintaining the output signal of a flip-flop at a low level, or A transistor that has the function of lowering a signal to a low level (hereinafter referred to as a pull-down transistor) These documents disclose shift registers that can suppress the deterioration of the Two pull-down transistors are used. , the output terminal of the flip-flop and the wiring that supplies Vss (also called negative power supply voltage) Then, one pull-down transistor and the other pull-down transistor are connected The power supply and the power supply are turned on alternately (also called the on state). The time that the pull-down transistor is on is shortened, so the characteristics of the pull-down transistor Deterioration can be suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-50502 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-24350 [Non-patent literature]

[0005] [Non-Patent Document 1] Yong Ho Jang, et al., “Integrated Gate Driver Circuit Using a-Si TFT with Dual Pull-down Structure”, Proceedings of The 11th International Display Workshops 2004, pp.333-336 Summary of the Invention [Problem to be solved by the invention]

[0006] In the configuration of the conventional technology, a transistor (hereinafter referred to as The voltage at the gate of the pull-up transistor is the positive supply voltage or the clock signal. This can cause the high level voltage of the pull-up transistor to be higher than the A large voltage may be applied to the gate of the pull-up transistor. A large voltage may be applied to the transistor being used, or the transistor may be degraded. Even if the transistor is increased in size, the channel width of the transistor may be increased so that the shift register can operate. Alternatively, when the channel width of the transistor is increased, the gate of the transistor and It may be easy for a short circuit to occur between the source and drain of the transistor. As the channel width increases, the parasitic capacitance of each transistor that makes up the shift register increases. This may happen.

[0007] An object of one embodiment of the present invention is to suppress deterioration of transistor characteristics. One embodiment of the present invention aims to reduce the channel width of a transistor. The object is to suppress the deterioration of the characteristics of a transistor or to reduce the channel width. An object of one embodiment of the present invention is to increase the amplitude of an output signal. Another object of the present invention is to increase the on-time of a transistor included in a pixel. An object of one embodiment of the present invention is to improve insufficient writing to pixels. Another object of the present invention is to shorten the fall time of an output signal. The object is to shorten the rise time of the output signal. It is an object of the present invention to prevent a video signal from being written to a pixel belonging to another row. Another object of the present invention is to reduce variations in the fall time of the output signal of the drive circuit. The objective of the present invention is to make the influence of feedthrough on each pixel constant. Another object of one embodiment of the present invention is to reduce the layout area. Another object of one embodiment of the present invention is to narrow the frame of a display device. Another object of one embodiment of the present invention is to provide a display device with high resolution. Another object of one embodiment of the present invention is to increase the yield. Another object of the present invention is to reduce the distortion of an output signal. Another object of one embodiment of the present invention is to reduce a delay in an output signal. Another object of one embodiment of the present invention is to reduce power consumption. Another object of the present invention is to reduce the current capability of an external circuit. The objective is to reduce the size of an external circuit or the size of a display device having the external circuit. The description of these issues does not preclude the existence of other issues. It is understood that one embodiment of the invention does not necessarily solve all of these problems. [Means for solving the problem]

[0008] One embodiment of the present invention is a liquid crystal display device including a driver circuit that receives a first signal and outputs a second signal; a pixel in which a voltage to be applied to a liquid crystal element is set in accordance with a second signal; The operating circuit has a gate, a source, and a drain, and the gate and one of the source and drain A first transistor and a second transistor to which a first signal is input, a gate, a source, and a drain. the gate is connected to the other of the source and drain of the first transistor; The second signal is electrically connected to the first terminal and is turned on or off to set the voltage state of the second signal. a third transistor having a gate, a source, and a drain, the gate of which is connected to the third transistor; The other of the two transistors is electrically connected to the source and drain of the other of the two transistors, and is turned on or off. a fourth transistor for controlling whether to set the voltage state of the second signal by switching the fourth transistor; a gate, a source, and a drain, one of the source and the drain being a fourth transistor; The fourth transistor is electrically connected to the gate and is turned on or off to turn off the fourth transistor. a fifth transistor that controls whether the second transistor is turned on or off; a fifth transistor that has a gate, a source, and a drain, and One of the source and drain of the third transistor is electrically connected to the gate of the third transistor, and is turned on or off. A sixth transistor that controls whether the third transistor is turned off by being turned off. and a liquid crystal display device having the same.

[0009] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. a pixel to which a voltage corresponding to the pixel voltage is set, and the driving circuit has a gate, a source, and a drain. a first transistor to which a first input signal is input to the gate and one of the source and drain; a first transistor and a second transistor, each having a gate, a source, and a drain, the gate being connected to the first The other of the source and drain of the transistor is electrically connected to turn it on or off. a third transistor for controlling whether to set the voltage state of the output signal by a gate; a gate connected to the other of the source and drain of the second transistor; and turns on or off to set the voltage state of the output signal. a fourth transistor having a gate, a source, and a drain, the gate of which is connected to the third transistor; The second input signal is input, and one of the source and drain is connected to the gate of the fourth transistor. A first voltage is applied to the other of the source and drain, and the transistor is turned on or off. a fifth transistor that controls whether the fourth transistor is turned off by turning on the fifth transistor; The transistor has a gate, a source, and a drain, and a third input signal is input to the gate, and the source and One of the drains is electrically connected to the gate of the third transistor, and the source and drain The other of the two is applied with a second voltage, which turns on or off to turn on the third transistor. and a sixth transistor that controls whether the first transistor is turned on or off.

[0010] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. a pixel to which a voltage corresponding to the pixel voltage is set, and the driving circuit has a gate, a source, and a drain. a first transistor to which a first input signal is input to the gate and one of the source and drain; a first transistor and a second transistor, each having a gate, a source, and a drain, the gate being connected to the first The other of the source and drain of the transistor is electrically connected to turn it on or off. a third transistor for controlling whether to set the voltage state of the output signal by a gate; a gate connected to the other of the source and drain of the second transistor; and turns on or off to set the voltage state of the output signal. a fourth transistor having a gate, a source, and a drain, the gate of which is connected to the third transistor; The second input signal is input, and one of the source and drain is connected to the gate of the fourth transistor. A third input signal is input to the other of the source and drain, and the transistor is turned on or off. a fifth transistor that controls whether the fourth transistor is turned off by being turned on; a gate, a source, and a drain, and a third input signal is input to the gate, and a and one of the source and drain is electrically connected to the gate of the third transistor, A second input signal is input to the other input, and the third transistor is turned on or off. and a sixth transistor that controls whether the first transistor is turned off. .

[0011] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. a pixel to which a voltage corresponding to the pixel voltage is set, and the driving circuit has a gate, a source, and a drain. a first transistor to which a first input signal is input to the gate and one of the source and drain; a first transistor and a second transistor, each having a gate, a source, and a drain, the gate being connected to the first The other of the source and drain of the transistor is electrically connected to turn it on or off. a third transistor for controlling whether to set the voltage state of the output signal by a gate; a gate connected to the other of the source and drain of the second transistor; and turns on or off to set the voltage state of the output signal. a fourth transistor having a gate, a source, and a drain, the gate of which is connected to the first The source and drain of the second transistor are electrically connected to the other of the two transistors. One of the terminals is electrically connected to the gate of the fourth transistor, and the other terminal is electrically connected to the source and drain of the fourth transistor. A third input signal is input and turns on or off to turn off the fourth transistor. a fifth transistor that controls whether or not the gate is turned on; and a fifth transistor that has a gate, a source, and a drain, The gate is electrically connected to the other of the source and drain of the first transistor, and the source and One of the drains is electrically connected to the gate of the third transistor, and the source and drain The second input signal is input to the other of the two transistors, and the third transistor is turned on or off. and a sixth transistor that controls whether the first transistor is turned off.

[0012] In one embodiment of the present invention, the channel width of the third transistor is It can also be configured to be equal to the channel width of the capacitor.

[0013] In one embodiment of the present invention, the channel width of the first transistor is The channel width of the second transistor is smaller than the channel width of the fourth transistor. It is also possible to configure the channel width to be smaller than that of the first embodiment.

[0014] One embodiment of the present invention is a liquid crystal display device including a driver circuit that receives a first signal and outputs a second signal; a pixel in which a voltage to be applied to a liquid crystal element is set in accordance with a second signal; The operating circuit has a gate, a source, and a drain, and the gate and one of the source and drain A first transistor and a second transistor to which a first signal is input, a gate, a source, and a drain. the gate is connected to the other of the source and drain of the first transistor; The second signal is electrically connected to the first terminal and is turned on or off to set the voltage state of the second signal. a third transistor having a gate, a source, and a drain, the gate of which is connected to the third transistor; The other of the two transistors is electrically connected to the source and drain of the other of the two transistors, and is turned on or off. a fourth transistor for controlling whether to set the voltage state of the second signal by switching the positive a positive electrode and a negative electrode, one of which is electrically connected to the gate of the fourth transistor; The fourth transistor is turned off by being turned on or off. a first diode for controlling the third transistor, the first diode having a positive terminal and a negative terminal, one of the positive terminal and the negative terminal being connected to the third transistor; The third transistor is electrically connected to the gate of the transistor and is turned on or off to A second diode that controls whether the transistor is turned off. be.

[0015] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. a pixel to which a voltage corresponding to the pixel voltage is set, and the driving circuit has a gate, a source, and a drain. a first transistor to which a first input signal is input to the gate and one of the source and drain; a first transistor and a second transistor, each having a gate, a source, and a drain, the gate being connected to the first The other of the source and drain of the transistor is electrically connected to turn it on or off. a third transistor for controlling whether to set the voltage state of the output signal by a gate; a gate connected to the other of the source and drain of the second transistor; and turns on or off to set the voltage state of the output signal. a fourth transistor having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being connected to the fourth transistor; A second input signal is input to the other of the positive and negative terminals of the transistor. and whether the fourth transistor is turned off by being in a conducting or non-conducting state. a first diode for controlling the third transistor, and a positive and negative terminals of the first diode; The third input signal is input to the other of the positive and negative terminals of the transistor. By being in a conducting or non-conducting state, the third transistor is controlled to be turned off or not. and a second diode that controls the first diode.

[0016] One embodiment of the present invention is a liquid crystal display device including a driver circuit that receives a first signal and outputs a second signal; a pixel in which a voltage to be applied to a liquid crystal element is set in accordance with a second signal; The operating circuit has a gate, a source, and a drain, and the gate and one of the source and drain A first transistor and a second transistor to which a first signal is input, and a positive and a negative One of the positive and negative electrodes is electrically connected to the other of the source and drain of the first transistor. and sets the voltage state of the second signal by being electrically connected to the first terminal and being in a conducting or non-conducting state. a first diode that controls whether or not the first diode is turned on; a first diode that controls whether or not the first diode is turned on; The other of the source and drain of the second transistor is electrically connected to the a second diode that controls whether to set the voltage state of the second signal by being in a a gate, a source, and a drain, one of the source and the drain being connected to a second diode; The second diode is electrically connected to one of the positive and negative electrodes of the first diode and is turned on or off. a third transistor for controlling whether the diode is in a non-conductive state; and a drain, one of the source and the drain being connected to one of the positive and negative electrodes of the first diode. The first diode is electrically connected to the first side and is turned on or off to make the first diode non-conductive. and a fourth transistor that controls whether or not the light is turned on.

[0017] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. a pixel to which a voltage corresponding to the pixel voltage is set, and the driving circuit has a gate, a source, and a drain. a first transistor to which a first input signal is input to the gate and one of the source and drain; a first transistor and a second transistor, and a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being connected to the first transistor; The transistor is electrically connected to the other of the source and drain of the transistor, and is in a conductive or non-conductive state. a first diode that controls whether or not to set the voltage state of the output signal by switching the first diode; and a negative electrode, one of the positive electrode and the negative electrode being connected to the other of the source and drain of the second transistor. The voltage state of the output signal is set by being electrically connected to the a second diode that controls whether or not the gate is turned on; a gate, a source, and a drain; A second input signal is input to the output terminal, and one of the source and drain is connected to the positive electrode of the second diode. and a negative electrode, and a first voltage is applied to the other of the source and drain. , which controls whether the second diode is in a non-conducting state by being turned on or off. a third transistor having a gate, a source, and a drain, the gate of which is connected to a third input signal; is input, and one of the source and drain is electrically connected to one of the positive and negative electrodes of the first diode. and a second voltage is applied to the other of the source and drain to turn it on or off. a fourth transistor that controls whether or not the first diode is made non-conductive by the The liquid crystal display device has:

[0018] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. a pixel to which a voltage corresponding to the pixel voltage is set, and the driving circuit has a gate, a source, and a drain. a first transistor to which a first input signal is input to the gate and one of the source and drain; a first transistor and a second transistor, and a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being connected to the first transistor; The transistor is electrically connected to the other of the source and drain of the transistor, and is in a conductive or non-conductive state. a first diode that controls whether or not to set the voltage state of the output signal by switching the first diode; and a negative electrode, one of the positive electrode and the negative electrode being connected to the other of the source and drain of the second transistor. The voltage state of the output signal is set by being electrically connected to the a second diode that controls whether or not the gate is turned on; a gate, a source, and a drain; A second input signal is input to the output terminal, and one of the source and drain is connected to the positive electrode of the second diode. and a negative electrode, and a third input signal is input to the other of the source and drain. By being turned on or off, it controls whether the second diode is in a non-conducting state. a third transistor having a gate, a source, and a drain, the gate of which is connected to a third input; A signal is input, and one of the source and drain is connected to one of the positive and negative terminals of the first diode. The transistors are electrically connected to each other, and a second input signal is input to the other of the source and drain to turn on or off. a fourth transistor that controls whether the first diode is turned off or not; and a liquid crystal display device having the same.

[0019] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. a pixel to which a voltage corresponding to the pixel voltage is set, and the driving circuit has a gate, a source, and a drain. a first transistor to which a first input signal is input to the gate and one of the source and drain; a first transistor and a second transistor, and a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being connected to the first transistor; The transistor is electrically connected to the other of the source and drain of the transistor, and is in a conductive or non-conductive state. a first diode that controls whether or not to set the voltage state of the output signal by switching the first diode; and a negative electrode, one of the positive electrode and the negative electrode being connected to the other of the source and drain of the second transistor. The voltage state of the output signal is set by being electrically connected to the a second diode that controls whether or not the gate is turned on; a gate, a source, and a drain; The gate is electrically connected to the other of the source and drain of the second transistor, and the source and drain One of the drains is electrically connected to one of the positive and negative electrodes of the second diode, and the source and A third input signal is input to the other of the drains, and the second drain is turned on or off. a third transistor for controlling whether the diode is in a non-conductive state; and a drain, the gate of which is electrically connected to the other of the source and drain of the first transistor. and one of the source and drain is electrically connected to one of the positive and negative electrodes of the first diode. A second input signal is input to the other of the source and drain, and the transistor is turned on or off. a fourth transistor that controls whether the first diode is made non-conductive by becoming and a liquid crystal display device having the same.

[0020] One embodiment of the present invention is a liquid crystal display device including a driver circuit that receives a first signal and outputs a second signal; a pixel in which a voltage to be applied to a liquid crystal element is set in accordance with a second signal; The operating circuit has a gate, a source, and a drain, and the gate and one of the source and drain A first transistor and a second transistor to which a first signal is input, and a positive and a negative One of the positive and negative electrodes is electrically connected to the other of the source and drain of the first transistor. and sets the voltage state of the second signal by being electrically connected to the first terminal and being in a conducting or non-conducting state. a first diode that controls whether or not the first diode is turned on; a first diode that controls whether or not the first diode is turned on; The other of the source and drain of the second transistor is electrically connected to the a second diode that controls whether to set the voltage state of the second signal by being in a a first diode, a positive electrode, and a negative electrode, one of the positive electrode and the negative electrode being connected to one of the positive electrode and the negative electrode of the second diode; The second diode is electrically connected to the first diode and is turned on or off to turn off the second diode. a third diode for controlling whether or not the third diode is in a conductive state; and a third diode having a positive electrode and a negative electrode. One of the electrodes is electrically connected to one of the positive and negative electrodes of the first diode, and is in a conductive or non-conductive state. a fourth diode that controls whether or not the first diode is made non-conductive by being made conductive; and a diode.

[0021] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. a pixel to which a voltage corresponding to the pixel voltage is set, and the driving circuit has a gate, a source, and a drain. a first transistor to which a first input signal is input to the gate and one of the source and drain; a first transistor and a second transistor, and a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being connected to the first transistor; The transistor is electrically connected to the other of the source and drain of the transistor, and is in a conductive or non-conductive state. a first diode that controls whether or not to set the voltage state of the output signal by switching the first diode; and a negative electrode, one of the positive electrode and the negative electrode being connected to the other of the source and drain of the second transistor. The voltage state of the output signal is set by being electrically connected to the a second diode that controls whether or not the voltage is set to a positive or negative terminal; is electrically connected to one of the positive and negative electrodes of the second diode, and the other of the positive and negative electrodes is connected to the first diode. When the second input signal is input, the second diode is turned on or off. a third diode that controls whether or not the third diode is in a non-conductive state; and a third diode having a positive electrode and a negative electrode, One of the negative electrodes is electrically connected to one of the positive and negative electrodes of the first diode, and the positive and negative electrodes A third input signal is input to the other of the first and second diodes, and the first and second diodes are turned on or off. a fourth diode for controlling whether or not the first diode is in a non-conducting state. It is a location.

[0022] One aspect of the present invention is a liquid crystal display device including any one of the above-described liquid crystal display devices and a device for controlling the operation of the liquid crystal display device. and an operation switch for controlling the operation of the electronic device.

[0023] The switch may take various forms. For this purpose, an electrical switch or a mechanical switch can be used. The switch is not limited to a specific type as long as it can control the current.

[0024] An example of a switch is a transistor (e.g., a bipolar transistor, a MOS transistor, etc.). transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, -Diode, MIM (Metal Insulator Metal) diode, M IS (Metal Insulator Semiconductor) diode, These include transistors with diode connections, or logic circuits that combine these. An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. The switch has a mechanically movable electrode, and the movement of the electrode causes The transistor operates by controlling conduction and non-conduction.

[0025] As a switch, both N-channel and P-channel transistors are used. Alternatively, a CMOS type switch may be used.

[0026] Note that a display element, a display device which is a device having a display element, a light-emitting element, and a device having a light-emitting element are also included. A light-emitting device, which is a device that emits light, can take various forms or have various elements. An example of a display element, a display device, a light-emitting element, or a light-emitting device is an EL (electroluminescence) luminescence) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LED (white LED, red LED, green LED, blue LED, etc.), transistor (current transistors that emit light in response to light), electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices , Grating Light Valve (GLV), Digital Micromirror Device (DMD) , carbon nanotubes, etc., due to electromagnetic effects, contrast, brightness, reflectivity, Some display devices have a display medium with a variable transmittance. Display devices using EL elements include displays and piezoelectric ceramic displays. An example of such a display device is an EL display. For example, a field emission display (FED) or an SED type flat panel display Ray (SED: Surface-conduction Electron-emitting An example of a display device using a liquid crystal element is a liquid crystal display. Display (transmissive LCD display, semi-transmissive LCD display, reflective LCD display) LCDs include OLEDs (e.g., LCDs with a 1000 x 1000 pixel resolution ... An example of a display device using an electrophoretic element is electronic paper.

[0027] An example of a liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The element can be constructed by a pair of electrodes and a liquid crystal layer. The optical modulation effect of liquid crystals is determined by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field or diagonal electric field). Specifically, a liquid crystal element is a nematic liquid crystal element. tic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal Pycnic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDL C), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma address liquid Examples of liquid crystal driving methods include PALC (Panel-Aligned Liquid Crystal), banana-shaped liquid crystal, etc. TN (Twisted Nematic) mode, STN (Super Twist ed Nematic mode, IPS (In-Plane-Switching) mode Mode, FFS (Fringe Field Switching) mode, MVA (Multiple ti-domain Vertical Alignment) mode, PVA(Pat terned Vertical Alignment) mode, ASV (Advanced ed Super View) mode, ASM (Axially Symmetric aligned micro-cell mode, OCB (Optically Com Pensated Birefringence mode, ECB (Electric FLC (Fer Controlled Birefringence) mode Electric Liquid Crystal (AFLC) mode, Electroelectric Liquid Crystal (PDLC) mode, ymer Dispersed Liquid Crystal) mode, guest host Mode, Blue Phase Mode, etc. However, they are not limited to these. In addition, various liquid crystal elements and driving methods thereof can be used.

[0028] Note that transistors with various structures can be used as the transistors. There is no limitation on the type of transistor used. An example of a transistor is an amorphous silicon transistor. , polycrystalline silicon, microcrystalline (microcrystalline, nanocrystalline, semi-amorphous and Thin film transistors (also called TFTs) with non-single crystal semiconductor films, typically silicon ) can be used.

[0029] Examples of transistors include ZnO, a-InGaZnO, SiGe, and GaAs. , IZO (indium zinc oxide), ITO (indium tin oxide), SnO, TiO, Transistors containing compound semiconductors or oxide semiconductors such as AlZnSnO(AZTO) Alternatively, thin film transistors made of these compound semiconductors or oxide semiconductors may be used. It is possible.

[0030] An example of a transistor is a transistor formed by an ink-jet method or a printing method. A transistor or the like can be used.

[0031] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. A resistor or the like can be used.

[0032] Note that as the transistor, transistors with various other structures can also be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A transistor or the like can be used.

[0033] An example of a transistor is a multi-gate transistor having two or more gate electrodes. A register can be used.

[0034] An example of a transistor is a structure in which gate electrodes are arranged above and below a channel. The transistors can be applied.

[0035] An example of a transistor is a transistor having a structure in which a gate electrode is disposed above a channel region. structure in which the gate electrode is located below the channel region, normal stagger structure, inverted stagger structure , a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in parallel. A transistor having a structure in which channel regions are connected in series can be used.

[0036] An example of a transistor is a transistor having a source electrode or a gate electrode in the channel region (or a part thereof). A transistor having an overlapping drain electrode structure can be used.

[0037] As an example of the transistor, a structure in which an LDD region is provided can be applied.

[0038] Note that a transistor can be formed using various substrates. Examples of the substrate include, but are not limited to, a semiconductor substrate, a single crystal substrate (e.g., For example, silicon substrate, SOI substrate, glass substrate, quartz substrate, plastic substrate, metal substrate , stainless steel substrate, substrate with stainless steel foil, tungsten substrate Plates, tungsten foil substrates, flexible substrates, laminated films, fibrous materials Examples of glass substrates include barium borate and glass-based paper. Examples of suitable glass include boron oxide glass, aluminoborosilicate glass, and soda-lime glass. Examples of boards include polyethylene terephthalate (PET) and polyethylene naphthalate. (PEN), polyethersulfone (PES), or acrylic Examples of laminated films include polypropylene and other flexible synthetic resins. Examples of the substrate include propylene, polyester, vinyl, polyvinyl fluoride, and polyvinyl chloride. Examples of films include polyester, polyamide, polyimide, inorganic vapor deposition film, In particular, semiconductor substrates, single crystal substrates, SOI substrates, etc. are used for By manufacturing transistors, there is little variation in characteristics, size, or shape, and the This allows the manufacture of transistors with high current capacity and small size. When a circuit is constructed using a resistor, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit. can be done.

[0039] Note that a transistor is formed using a certain substrate and then transferred to another substrate. However, the transistor may be disposed on another substrate. As the substrate, in addition to the substrate on which the above-mentioned transistor can be formed, a paper substrate, a cellophane substrate, etc. substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, Polyurethane, polyester) or recycled fiber (acetate, cupra, rayon, recycled These substrates include raw polyester, leather substrates, and rubber substrates. This allows for the formation of transistors with good characteristics and low power consumption. This allows for the manufacture of devices that are less likely to break, more heat resistant, lighter in weight, or thinner.

[0040] All of the circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate, a plastic substrate, a single crystal substrate, an SOI substrate, etc. This reduces the number of components, thereby reducing costs, and the number of connections to circuit components. This can improve reliability.

[0041] It is possible that not all of the circuits required to realize a given function are formed on the same substrate. In other words, part of the circuitry required to achieve a given function is formed on a certain substrate. Another part of the circuitry required to achieve a given function is formed on a different substrate. For example, some of the circuits required to realize a specific function can be made of glass. Another part of the circuitry required to realize a given function is formed on the single crystal substrate. (or SOI substrate). The single crystal substrate (also called IC chip) on which another part of the circuit required for the semiconductor device is formed is called COG ( By using the IC chip on glass, the IC is connected to the glass substrate. It is possible to place the chip on the board. Alternatively, the IC chip can be mounted on the board using TAB (Tape Auto) technology. omated Bonding), COF(Chip On Film), SMT(Su Surface Mount Technology, or a printed circuit board, etc. In this way, part of the circuit is formed on the same substrate as the pixel section. This reduces the number of components and reduces costs, and the number of connections to the circuit components. This reduces the power consumption and improves reliability. In many cases, circuits with high drive frequencies consume a lot of power. So, such a circuit is formed on a substrate (for example, a single crystal substrate) separate from the pixel section, and By using this IC chip, it is possible to prevent an increase in power consumption. do.

[0042] The transistor has at least three terminals including a gate, a drain, and a source. It is also possible to use a device having a channel between the drain and source regions. The transistor has a channel region and allows current to flow through the drain region, the channel region, and the source region. Here, the source and drain are the same in structure or operation of the transistor. It is difficult to determine which is the source and which is the drain, as this varies depending on the conditions. Therefore, the region that functions as the source and the region that functions as the drain are In some cases, the source and drain are not called the same. One of the two is referred to as a first terminal, a first electrode, or a first region, and the other of the source and drain is referred to as a first electrode, a first region, or a first region. It may be referred to as the second terminal, the second electrode, or the second region. It may also be referred to as the third electrode.

[0043] The transistor has at least three terminals including a base, an emitter, and a collector. In this case, the element may be, for example, an element having one of an emitter and a collector. The first terminal, the first electrode, or the first region is referred to as the emitter or the collector. The second terminal, second electrode, or second region may be used as a transistor. When a bipolar transistor is used, the term "gate" can be replaced with "base." It is possible.

[0044] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are functionally connected, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) , wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, a predetermined connection relationship, For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be modified to include the connection relationships shown in the drawings or text. This also includes matters other than those in charge.

[0045] An example of an electrical connection between A and B is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more resistors (e.g., diodes) can be connected between A and B.

[0046] An example of a functional connection between A and B is a connection that allows the functional connection between A and B. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), voltage level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the voltage level of signals, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between A and B. For example, even if another circuit is inserted between A and B, the signal output from A is transmitted to B, A and B are said to be functionally connected.

[0047] When it is explicitly stated that A and B are electrically connected, it means that A and B are electrically connected. When A and B are electrically connected (i.e., when another element or circuit is placed between A and B) A and B are functionally connected (i.e., there is no connection between A and B) When A and B are connected directly, the two are functionally connected via another circuit. (i.e., when A and B are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it is not simply The same applies if the document is explicitly stated as being connected to the

[0048] Note that it is not explicitly stated that B is formed on A, or that B is formed on A. In the case of the above, it is not limited to B being formed on A in direct contact with it. This also includes cases where A and B are not in agreement, i.e., where another object is present between A and B. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0049] Therefore, for example, it is not possible to explicitly state that layer B is formed on top of layer A (or on top of layer A). When described, it means that layer B is formed directly on layer A, and layer A is formed on layer B. Another layer (such as layer C or layer D) is formed directly on top of it, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be formed as follows: It may be a single layer or multiple layers.

[0050] Furthermore, the same applies to cases where it is explicitly stated that B is formed above A. It is not limited to B being directly on A, and there is another object between A and B. For example, if layer B is formed above layer A, In this case, there are two cases: when layer B is formed directly on top of layer A, and when layer B is formed directly on top of layer A. Another layer (such as layer C or layer D) is formed on top of it, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be used as single layers. It may be a multi-layer structure.

[0051] In addition, B is formed on A, B is formed on A, or B is formed above A. When explicitly stating that "B" is formed, this also includes the case where B is formed diagonally above. .

[0052] The same applies to the case where B is below A, or B is below A.

[0053] In addition, it is preferable that anything explicitly stated as singular be in the singular. However, it is not limited to this, and plurals are also possible. It is preferable that the items described in the table be plural. However, this is not limited to this. It is also possible for the term to be singular.

[0054] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0055] The diagrams are merely diagrams showing ideal examples, and are not limited to the shapes or values ​​shown in the diagrams. For example, variations in shape due to manufacturing technology, variations in shape due to errors, and noise Variations in signals, voltages, or currents due to timing differences, or variations in signals, voltages, Alternatively, it is possible to include variations in current.

[0056] Note that technical terms may be used to describe specific embodiments or examples. However, one aspect of the present invention is not to be construed as being limited by technical terms. .

[0057] In addition, undefined terms (including scientific and technical terms such as technical terms or academic terms) are generally It can be used as a meaning equivalent to the general meaning understood by a person of ordinary skill in the art. The terms defined herein shall be construed in a manner consistent with the background of the relevant art. is preferred.

[0058] It should be noted that the terms first, second, third, etc., refer to various elements, members, regions, layers, and sections as distinct from one another. Therefore, the words "first," "second," "third," etc. are used to distinguish between elements, parts, etc. It is not intended to limit the number of materials, regions, layers, areas, etc. It is possible to replace "second" or "third" etc.

[0059] In addition, "up," "upward," "down," "downward," "sideways," "right," "left," Spatial arrangement such as "diagonally," "in the back," "in front," "inside," "outside," or "inside" The location phrases should be used to easily illustrate the relationship of one element or feature to another. However, it is not limited to this and is often used to indicate the spatial arrangement of these. The phrase "above A" can include other directions in addition to the direction shown in the drawing. For example, When explicitly indicated as B, B is not limited to being above A. can be flipped or rotated 180 degrees, so it can include B being below A. In this way, the word "upon" can be used to refer to the direction of "up" as well as the direction of "down." The devices shown may include, but are not limited to, various orientations. Since it is possible to rotate the word "on" in addition to the directions "on" and "under" "Sideways", "Right", "Left", "Diagonally", "Back", "Front", "Inside", "Outside" It is possible to include other directions such as "into" or "into"; It is possible to interpret this as:

[0060] One embodiment of the present invention is a gate having a function of receiving a first signal and outputting a second signal. A first signal is input to the gate and one of the source and drain. a first transistor and a second transistor, and a gate, a source, and a drain a gate electrically connected to the other of the source and drain of the first transistor; a third signal that controls whether to set the voltage state of the second signal by being turned on or off; a second transistor having a gate, a source, and a drain, the gate of which is connected to a second transistor; The second signal is electrically connected to the other of the source and drain and is turned on or off. a fourth transistor for controlling whether to set the voltage state of the signal; a drain, one of the source and the drain being electrically connected to the gate of the fourth transistor; The fourth transistor is connected to the first transistor, and is turned on or off to control whether the fourth transistor is turned off or not. a fifth transistor having a gate, a source, and a drain, One of the terminals is electrically connected to the gate of the third transistor, which is turned on or off. a sixth transistor that controls whether the third transistor is turned off. is. [Effects of the Invention]

[0061] According to one embodiment of the present invention, deterioration of the characteristics of a transistor can be suppressed. One aspect is that the channel width of the transistor can be reduced. The present invention can suppress the deterioration of the transistor characteristics or reduce the channel width. According to one aspect of the present invention, the amplitude of a signal can be increased. In addition, one embodiment of the present invention can be realized by using a pixel. Alternatively, one embodiment of the present invention can improve the insufficient writing to the element. Alternatively, one aspect of the present invention is to shorten the rise time of a signal. Or you can shorten the video to pixels belonging to one row and vice versa. It is possible to prevent the signal from being written. This can reduce the feedthrough effect on the pixel. Alternatively, crosstalk can be reduced. The layout area can be reduced. Alternatively, one embodiment of the present invention can provide a display device with high resolution. Alternatively, one embodiment of the present invention can increase the yield. In one aspect, the cost can be reduced. Alternatively, in one aspect of the present invention, the signal distortion can be reduced. Alternatively, one aspect of the present invention can reduce signal delay. Alternatively, one embodiment of the present invention can reduce power consumption. In this way, the current capacity of the external circuit can be reduced. The size of the circuit or the size of a display device having such external circuitry can be reduced. [Brief explanation of the drawings]

[0062] [Figure 1] 1 is an example of a circuit diagram of a semiconductor device according to a first embodiment. [Figure 2]4 is an example of a timing chart for explaining the operation of the semiconductor device in the first embodiment. [Figure 3] FIG. 2 is an example of a schematic diagram for explaining the operation of the semiconductor device in the first embodiment. [Figure 4] FIG. 2 is an example of a schematic diagram for explaining the operation of the semiconductor device in the first embodiment. [Figure 5] 4 is an example of a timing chart for explaining the operation of the semiconductor device in the first embodiment. [Figure 6] 1 is an example of a circuit diagram of a semiconductor device according to a first embodiment. [Figure 7] 4 is an example of a timing chart for explaining the operation of the semiconductor device in the first embodiment. [Figure 8] FIG. 2 is an example of a schematic diagram for explaining the operation of the semiconductor device in the first embodiment. [Figure 9] FIG. 2 is an example of a schematic diagram for explaining the operation of the semiconductor device in the first embodiment. [Figure 10] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 11] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment. [Figure 12] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment. [Figure 13] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment. [Figure 14] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment. [Figure 16] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment. [Figure 17] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment. [Figure 18] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 19]FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 20] 10A and 10B are an example of a circuit diagram of a semiconductor device according to a second embodiment and an example of a timing chart for explaining the operation thereof. [Figure 21] 10A and 10B are an example of a circuit diagram of a semiconductor device according to a third embodiment and an example of a timing chart for explaining the operation thereof. [Figure 22] FIG. 11 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the third embodiment. [Figure 23] FIG. 11 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the third embodiment. [Figure 24] FIG. 11 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the third embodiment. [Figure 25] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 26] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 27] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 28] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 29] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 30] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 31] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a fourth embodiment. [Figure 32] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the fourth embodiment. [Figure 33] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the fourth embodiment. [Figure 34] FIG. 10 is an example of a schematic diagram for explaining the operation of the semiconductor device according to the fourth embodiment. [Figure 35] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a fourth embodiment. [Figure 36] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a fourth embodiment. [Figure 37]13A and 13B are an example of a block diagram of a display device according to Embodiment 5 and an example of a circuit diagram of a pixel. [Figure 38] FIG. 13 is an example of a circuit diagram of a shift register according to the fifth embodiment. [Figure 39] 13 is an example of a timing chart illustrating the operation of the shift register according to the fifth embodiment. [Figure 40] FIG. 20 is an example of a cross-sectional view of a semiconductor device according to an eighth embodiment. [Figure 41] 13A and 13B are an example of a block diagram and an example of a cross-sectional view of a display device according to a ninth embodiment. [Figure 42] 13A to 13C are examples of diagrams illustrating a manufacturing process of a semiconductor device in Embodiment 10. [Figure 43] FIG. 22 is an example of a top view of a semiconductor device according to an eleventh embodiment. [Figure 44] 12A to 12C are diagrams illustrating examples of electronic devices according to Embodiment 12. [Figure 45] 12A to 12C are diagrams illustrating examples of electronic devices according to Embodiment 12. [Figure 46] 13A and 13B are an example of a circuit diagram of a source driver according to a sixth embodiment, an example of a timing chart for explaining the operation thereof, and an example of a block diagram of a display device. [Figure 47] FIG. 20 is an example of a circuit diagram of a protection circuit according to a seventh embodiment. [Figure 48] FIG. 22 is an example of a circuit diagram of a semiconductor device provided with a protection circuit according to a seventh embodiment. [Figure 49] 10 is a timing chart showing the verification results of the semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0063] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms and in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. It should not be construed as being limited to the description of the form. Therefore, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the same parts are denoted by the same reference numerals in different drawings. A detailed description of some parts or parts having similar functions will be omitted.

[0064] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the above, and / or one or more other implementations The content (or part of the content) described in the form of etc. can be done.

[0065] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0066] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, , and many more diagrams can be constructed.

[0067] In addition, in a drawing or a sentence described in a certain embodiment, a part thereof may be extracted. Therefore, the drawings and drawings that illustrate certain parts of the invention may be omitted. If a part of a drawing or text is included in the invention, the part of the drawing or text may also be included in the invention. It is disclosed as an embodiment and may constitute an embodiment of the invention. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (Capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, substrates, modules, devices, solids, liquids, gases, operating methods, manufacturing methods, etc. are described singly or in plural in the attached drawings (cross-sectional views, plan views, circuit diagrams, block diagrams, flowcharts, process diagrams, perspective views , elevation views, layout diagrams, timing charts, structural diagrams, schematic diagrams, graphs, tables, optical path diagrams, vector diagrams, state diagrams, waveform diagrams, photographs, chemical formulas, etc.) or in the text, and a part thereof can be extracted to form an aspect of the invention. As an example, from a circuit diagram composed of P (P is an integer) circuit elements (transistors, capacitive elements, etc.), M (M is an integer and M < P) circuit elements (transistors, capacitive elements, etc.) can be extracted to form an aspect of the invention. Another example is that from a cross-sectional view composed of P layers, M layers can be extracted to form an aspect of the invention. Another example is that from a flowchart composed of P elements, M elements can be extracted to form an aspect of the invention. Another example is that from a cross-sectional view composed of P layers, M layers can be extracted to form an aspect of the invention. Another example is that from a flowchart composed of P elements, M elements can be extracted to form an aspect of the invention. It is possible to form an aspect of the invention.

[0068] (Embodiment 1) An example of this embodiment is a first transistor in which a first terminal is electrically connected to a first wiring and a second terminal is electrically connected to a second wiring, a second transistor in which a first terminal is electrically connected to the first wiring and a second terminal is electrically connected to the second wiring, and a first circuit electrically connected to the gate of the first transistor and electrically connected to the gate of the second transistor. The first circuit causes the first signal to be in a second voltage state and the second signal to be in a first voltage state, and when this occurs, the gate of the first transistor is in a certain state, and the gate of the second transistor A function of increasing the voltage and a function of increasing the voltage when the first signal is at the second voltage state and the third signal is at the first voltage state. and a function of increasing the voltage of the gate of the second transistor when the voltage state is This is what is done.

[0069] An example of a semiconductor device according to this embodiment will be described. as a shift register, gate driver, or source driver. Note that the semiconductor device of this embodiment mode is referred to as a driver circuit or a circuit. It is possible.

[0070] First, a circuit configuration of a semiconductor device of this embodiment mode will be described with reference to FIG. The semiconductor device in FIG. 1A includes a circuit 100 and a circuit 200. The semiconductor device has a plurality of transistors 101_1 to 101_2.

[0071] It is assumed that the transistors 101_1 and 101_2 are N-channel type. In a transistor with a gate-source potential difference (Vgs), the threshold voltage (Vth ) is exceeded. However, this is not limited to this, and the transistor 10 1_1 and / or transistor 101_2 can be P-channel In a P-channel transistor, the potential difference between the gate and source (Vgs) is equal to the threshold voltage ( Vth), it will turn on.

[0072] Next, the connection relationship of the semiconductor device in FIG. The first terminal of the transistor 101_1 is connected to the wiring 112, and the second terminal of the transistor 101_1 is connected to the wiring 113. A first terminal of the transistor 101_2 is connected to a wiring 112. A second terminal of the transistor 101_2 is connected to the wiring 111. 13, wiring 114, wiring 115, wiring 116_1 to 116_2, wiring 117, wiring 118 , the gate of the transistor 101_1, the gate of the transistor 101_2, and the wiring 111 However, the present invention is not limited to this. For example, the circuit 200 may be configured as follows: , and can be connected to various other wirings or various nodes. 00 does not need to be connected to all of the above-mentioned wirings, but may be connected to any of the above-mentioned wirings. It is possible that this has not been done.

[0073] The connection point between the gate of the transistor 101_1 and the circuit 200 is denoted as a node n1. The connection point between the gate of the transistor 101_2 and the circuit 200 is denoted as a node n2.

[0074] In many cases, the wiring 111 is arranged to extend to the pixel portion. The transistors included in the pixel (for example, selection transistors or switching transistors) ) is often connected to the gate of the semiconductor device. However, this is not limited to this. For example, In this case, the wiring 111 is connected to another stage (for example, the next stage). As another example, the wiring 111 can be connected to the wiring 115 of the semiconductor device. , can be connected to the wiring 117 of a semiconductor device in another stage (for example, the previous stage).

[0075] Next, signals or voltages input to or output from each wiring will be described.

[0076] As an example, a signal OUT is output from the wiring 111. For example, the signal O may be a signal having a first voltage state and a second voltage state. UT is often a digital signal having high and low levels, Therefore, the wiring 111 can function as a signal line or an output signal. In particular, the wiring 111 can function as an output signal line. When the signal OUT is arranged in an extended manner, it functions as a gate signal, a scanning signal, or a selection signal. Therefore, the wiring 111 can function as a gate signal line (hereinafter referred to as a gate line). For example, in the case of a liquid crystal display device, In this case, the wiring 111 is connected to a pixel having a liquid crystal element, and the liquid crystal element is turned on or off depending on the voltage of the wiring 111. However, the present invention is not limited to this. For example, For example, if a plurality of semiconductor devices are connected in series, the wiring 111 may be connected to another stage ( For example, when connected to the wiring 115 of the semiconductor device in the next stage, the signal OUT is a signal for transfer. As another example, the wiring 11 may function as a start signal. When the signal OUT is connected to the wiring 117 of a semiconductor device in another stage (for example, the previous stage), the signal OUT , can function as a reset signal.

[0077] As an example, a signal CK1 is input to the wiring 112. The signal CK1 is, for example, For example, the signal CK may be a signal having a first voltage state and a second voltage state. 1 is often a digital signal that alternates between high and low levels. Therefore, the wiring 112 can function as a signal line. , can function as a clock line, clock signal line, or clock supply line. However, the present invention is not limited to this. For example, the wiring 112 may be connected to a voltage V1 or a voltage V2. Therefore, the wiring 112 functions as a power supply line. It is possible to have

[0078] As an example, a signal CK2 is input to the wiring 113. The signal CK2 is, for example, For example, the signal CK may be a signal having a first voltage state and a second voltage state. 2 is often a digital signal that alternates between high and low levels. , can function as an inverted clock signal. It is an inverted signal of CK1 or a signal that is approximately 180° out of phase with signal CK1. Therefore, the wiring 113 may be a signal line, an inverted clock line, an inverted clock signal line, or It is possible for the line to function as an inverted clock supply line. However, this is not limited to this. For example, the wiring 113 may be supplied with a voltage such as a voltage V1 or a voltage V2. Therefore, the wiring 113 can function as a power supply line.

[0079] As an example, a voltage V2 is supplied to the wiring 114. The voltage V2 is a high level It is often approximately equal to the signal of the power supply voltage, reference voltage, or positive power supply voltage. Therefore, the wiring 114 can function as a power supply line. However, the present invention is not limited to this. For example, the signal C A signal such as signal K1 or signal CK2 can be input to the wiring 114. , and can function as a signal line.

[0080] As an example, a signal SP is input to the wiring 115. The signal SP is, for example, It can be a signal having one voltage state and a second voltage state. For example, the signal SP can be It is often a digital signal and can function as a start signal. Therefore, the wiring 115 can function as a signal line. For example, if a plurality of semiconductor devices are connected in series, the wiring When 115 is connected to the wiring 111 of a semiconductor device in another stage (for example, the previous stage), the signal SP is , can function as a transfer signal, a gate signal, or a scanning signal. The wiring 115 may function as an output signal line, a gate signal line, or a scanning line. It is Noh.

[0081] For example, a signal SEL1 is input to the wiring 116_1. may be, for example, a signal having a first voltage state and a second voltage state. The signal SEL1 changes between a high level and a low level every certain period (for example, every frame period). It is often a digital signal that alternates between two states, and is used as a control signal, clock signal, or clock Therefore, the wiring 116_1 can function as a signal lock control signal. It is possible for the line to function as a signal line, control line, or clock line. For example, the signal SEL1 may be generated every few frames, every time the power is turned on, or every time the power is turned on. The dam can alternate between high and low levels.

[0082] As an example, the signal SEL2 is input to the wiring 116_2. may be, for example, a signal having a first voltage state and a second voltage state. The signal SEL2 changes between a high level and a low level every certain period (for example, every frame period). In many cases, the signal SEL2 is a digital signal that alternates between two states. It is often an inverted signal of EL1 or a signal that is 180° out of phase with signal SEL1. It can function as a control signal, an inverted clock signal, or an inverted clock control signal. Therefore, it can function as a signal line, control line, or inverted clock line. For example, when the signal SEL1 is at either a high level or a low level, the signal SE L2 can also be set to the other of high level and low level. For example, the signal SEL2 may be generated every few frames, every time the power is turned on, or every time the power is turned on. The dam can alternate between high and low levels.

[0083] For example, a signal RE is input to the wiring 117. The signal RE is, for example, It can be a signal having one voltage state and a second voltage state. For example, the signal RE can be It is often a digital signal and can function as a reset signal. Therefore, the wiring 117 can function as a signal line. For example, if a plurality of semiconductor devices are connected in series, the wiring When the signal RE can function as a transfer signal, a gate signal, or a scanning signal. The wiring 117 may function as an output signal line, a gate signal line, or a scanning line. It is possible.

[0084] As an example, a voltage V1 is supplied to the wiring 118. The voltage V1 is a low level. It is often roughly equal to the signal in the Therefore, the wiring 118 can function as a power supply line, Alternatively, it may have a function as a ground. However, it is not limited to this. For example, the signal CK1, the signal CK2, the signal SEL1, or the signal SEL2 is input to the wiring 118. Therefore, the wiring 118 can function as a signal line. In this case, it is possible to apply a reverse bias to the transistor. This can suppress the deterioration of the transistor.

[0085] These wirings can have various other functions, and all of the above functions can be You don't need to have everything.

[0086] The term "generally" refers to errors due to noise, process variations, and the manufacturing process of the element. This includes various errors such as errors due to variations in process and / or measurement errors.

[0087] Generally, voltage refers to the potential difference between two points, and potential refers to the The electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a point In an electronic circuit, the potential at a certain point is referred to as a reference. Since the difference between the potential (for example, ground potential) and the voltage at a certain point is often expressed as the voltage at that point, So, when we say voltage at a certain point, unless otherwise specified, we mean the potential at a certain point and the reference This indicates the potential difference between the potential at which

[0088] As an example, the voltage of the first state, i.e., the low-level signal, is V1, and the voltage of the second state is V2. The voltage of the high-level signal is V2. And, V2>V1. Therefore, When the voltage V1 is written as "voltage V1", the voltage V1 is a value that is approximately equal to the low level of the signal. On the other hand, when the voltage V2 is written, the voltage V2 is the high level of the signal. The values ​​are assumed to be approximately equal, but are not limited to this. For example, The voltage of the signal can be lower than V1 or higher than V1. Alternatively, the voltage of the high level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, a high level signal or a high level voltage may be generated. Even when written as voltage, the voltage may be lower than V2 or higher than V2. Depending on the circuit configuration, it may be described as a low-level signal or a low-level voltage. In this case, the voltage may be lower than V1 or higher than V1.

[0089] It should be noted that the signal CK1 and / or the signal CK2 can be balanced or unbalanced. Balanced means that only a few pulses in one cycle are at a high level. The non-equilibrium state means that the period when the signal is at a high level is roughly equal to the period when the signal is at a low level. This means that the period during which the signal is at a high level is different from the period during which the signal is at a low level. It is assumed to be outside the range of cases where they are approximately equal.

[0090] When the signals CK1 and CK2 are unbalanced, the signal CK2 is the inverse of the signal CK1. In this case, the period when the signal CK1 is at a high level and the period when the signal CK The period when 2 is at a high level and the length of 2 can be roughly equal. Not limited to.

[0091] Next, the functions of each circuit or each transistor will be described.

[0092] For example, the circuit 100 may be configured to: , has a function of controlling electrical continuity between the wiring 112 and the wiring 111. Alternatively, the circuit 100 The voltage control circuit 114 has a function of controlling the timing at which the voltage of the wiring 112 is supplied to the wiring 111. For example, A signal or voltage (for example, a voltage V2 or a signal CK1) is supplied to the wiring 112. In this case, the circuit 100 supplies a signal or voltage supplied to the wiring 112 to the wiring 111. Alternatively, the circuit 100 may have a function of controlling the timing of the high-level signal (e.g., For example, it has a function of controlling the timing of supplying a signal CK1 to the wiring 111. The circuit 100 has a function of controlling the timing at which the voltage of the wiring 111 is increased. The circuit 100 supplies a low-level signal (for example, the signal CK1) to the wiring 111. Alternatively, the circuit 100 may have a function of controlling the timing of decreasing the voltage of the wiring 111. The circuit 100 has a function of controlling the timing of the start or maintenance of the The voltage of node n1 and / or the voltage of node n2 are increased by the bootstrap operation. As described above, the circuit 100 has a function of controlling the timing of the control circuit, the buffer, and the like. It is possible for the device to have functions such as a power supply circuit or a switch. However, this is not limited to this. It should be noted that the circuit 100 does not need to have all of the above functions.

[0093] The circuit 200, for example, receives input signals or voltages (signal CK2, signal SP, signal RE , the voltage of node n1, the voltage of node n2, and / or the signal OUT, etc. The voltage of the node n1, the voltage of the node n2, and / or the voltage of the wiring 111. Alternatively, the circuit 200 may apply a high-level signal to the node n1 and / or the node n2. Alternatively, the circuit 200 may have a function of controlling the timing of supplying the voltage V2. A function of controlling the timing of increasing the voltage of node n1 and / or the voltage of node n2. Alternatively, the circuit 200 may provide a low level at the node n1 and / or the node n2. The circuit 200 has a function of controlling the timing of supplying the signal or voltage V1. is the timing or duration for decreasing the voltage of the node n1 and / or the voltage of the node n2. Alternatively, the circuit 200 may have a function of controlling the timing at which the nodes n1 and / or n2 are turned on. Alternatively, the node n2 has a function of controlling the timing at which a signal or voltage is not supplied. Alternatively, the circuit 200 may determine the timing at which the node n1 and / or the node n2 are floating. Alternatively, the circuit 200 may transmit a low-level signal to the wiring 111. Alternatively, the circuit 200 may have a function of controlling the timing of supplying the voltage V1. It has the function of controlling the timing of decreasing or maintaining the voltage on line 111. As described above, the circuit 200 can function as a control circuit. However, the circuit 200 is not limited to this. It is not necessary for the circuit 200 to have all of the above functions. .

[0094] For example, the transistor 101_1 is connected to the wiring 112 in response to the voltage of the node n1. The transistor 101_1 has a function of controlling the electrical continuity between the wiring 111 and the transistor 101_2. The timing at which the voltage of the wiring 112 is supplied to the wiring 111 is controlled. When a signal or voltage (for example, voltage V2 or signal CK1) is supplied to 112, The transistor 101_1 transmits a signal or a voltage supplied to the wiring 112 to the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the timing of supplying the high The function of controlling the timing at which a signal of a certain level (for example, signal CK1) is supplied to the wiring 111 is Alternatively, the transistor 101_1 may be configured to increase the voltage of the wiring 111 at a timing Alternatively, the transistor 101_1 has a function of controlling a low-level signal (for example, For example, it has a function of controlling the timing of supplying a signal (CK1) to the wiring 111. The transistor 101_1 determines the timing to decrease or maintain the voltage of the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the bootstrap operation. Alternatively, the transistor 101_1 has a function of boosting the voltage of the node n1. The transistor 101_1 has a function of increasing the voltage by a strap operation. This function controls whether to set the voltage state of the signal OUT by turning it on or off. As described above, the transistor 101_1 can be used as a buffer, a switch, or the like. However, it is not limited to this. 101_1 does not need to have all of the above functions.

[0095] For example, the transistor 101_2 is connected to the wiring 112 in response to the voltage of the node n2. The transistor 101_2 has a function of controlling electrical continuity between the wiring 111 and the transistor 101_2. The timing at which the voltage of the wiring 112 is supplied to the wiring 111 is controlled. When a signal or voltage (for example, voltage V2 or signal CK1) is supplied to 112, The transistor 101_2 transmits a signal or a voltage supplied to the wiring 112 to the wiring 111. Alternatively, the transistor 101_2 has a function of controlling the timing of supplying the high The function of controlling the timing at which a signal of a certain level (for example, signal CK1) is supplied to the wiring 111 is Alternatively, the transistor 101_2 may be configured to increase the voltage of the wiring 111 at a timing Alternatively, the transistor 101_2 has a function of controlling a low-level signal (for example, For example, it has a function of controlling the timing of supplying a signal (CK1) to the wiring 111. The transistor 101_2 determines the timing to decrease or maintain the voltage of the wiring 111. Alternatively, the transistor 101_2 has a function of controlling the bootstrap operation. Alternatively, the transistor 101_2 has a function of boosting the voltage of the node n2. The transistor 101_2 has a function of increasing the voltage by a strap operation. This function controls whether to set the voltage state of the signal OUT by turning it on or off. As described above, the transistor 101_2 can be used as a buffer, a switch, or the like. However, it is not limited to this. 101_2 does not need to have all of the above functions.

[0096] Next, an example of the operation of the semiconductor device in FIG. 1A will be described with reference to a timing chart in FIG. The timing chart of FIG. 2 shows the signals SEL1, SEL2, and CK 1, signal CK2, signal SP, signal RE, voltage of node n1 (Va1), voltage of node n2 (Va2), and signal OUT. Note that the operation of the semiconductor device of FIG. 1A is the same as that of the timing diagram of FIG. It is not limited to timing charts and can be controlled by various timings. .

[0097] The timing chart in FIG. 2 shows a plurality of periods (hereinafter, a period is also called a frame period). Each period has a plurality of sub-periods (hereinafter, a sub-period is referred to as one gate selection period). For example, the timing chart in FIG. 2 includes a period T1 and a period T2. The period T1 includes a period A1, a period B1, a period C1, a period D1, and a period The period T2 has a plurality of sub-periods, namely, period E1, period A2, period B2, period C2, period However, the present invention is not limited to this. For example, For example, the timing chart of FIG. 2 may have a period other than the period T1 and the period T2. It is possible to omit either the period T1 or the period T2. T1 can have various periods other than the periods A1 to E1, and the periods A1 to E Alternatively, the period T2 may include the periods A2 to E2 as well as the periods A1 to E3. It is possible to have various periods, and it is also possible to omit any of the periods A2 to E2. It is possible.

[0098] As an example, the periods T1 and T2 are alternately arranged. However, the order of the periods T1 and T2 is not limited to this, and the periods T1 and T2 can be arranged in various orders.

[0099] As an example, in the period T1, the period A1, the period B1, and the period C1 are arranged in this order. Then, until the end of period T1 (or the beginning of period T2), periods D1 and E 1 and 2 are alternately arranged. However, this is not limited to this. For example, Period D1 and / or period E1 are placed in the period from the beginning to the beginning of period A1. It is possible to do this.

[0100] As an example, in the period T2, the period A2, the period B2, and the period C2 are arranged in this order. Then, until the end of period T2 (or the beginning of period T1), periods D2 and E 2 are alternately arranged. However, this is not limited to this. For example, Period D2 and / or Period E2 are placed in the period from the beginning to the beginning of Period A2. It is possible to do this.

[0101] First, the operation during the period T1 will be described. During the period T1, the signal SEL1 is at a high level. As a result, the signal SEL2 goes low.

[0102] During the period A1, as shown in FIG. 3(A), the signal SP becomes high level. Path 200 supplies a high level signal or voltage V2 to node n1. Meanwhile, the circuit 200 is not driving a low level signal or voltage V1. Therefore, the voltage at node n2 decreases to approximately V1. Or, it is maintained at approximately V1. As a result, the transistor 101_2 is turned off. After that, the voltage of node n1 continues to rise, and eventually the voltage of node n1 becomes V1+Vth1 01_1 (Vth101_1: threshold voltage of transistor 101_1) + Vx At this time, Vx is greater than 0. Then, transistor 101_1 turns on. Therefore, the wiring 112 and the wiring 111 are brought into electrical continuity through the transistor 101_1. Therefore, the low-level signal CK1 is transmitted from the wiring 112 through the transistor 101_1. As a result, the signal OUT goes low. The voltage at node n1 continues to rise. Eventually, the circuit 200 turns off the supply of a signal or voltage to node n1. This stops the connection between the circuit 200 and the node n1. As a result, the node n1 , it becomes floating state, and the voltage of node n1 is maintained at the value of V1 + Vth101_1 + Vx. However, the present invention is not limited to this. For example, in the period A1, the circuit 200 It is possible to continue supplying the voltage th101_1+Vx to the node n1.

[0103] Note that during the period A1, the circuit 200 applies a low-level signal or a voltage V1 to the wiring 111. It is possible to supply a signal or voltage to the wiring 111, or it is possible not to supply a signal or voltage to the wiring 111. be.

[0104] Next, during a period B1, the signal SP goes low as shown in FIG. Then, the circuit 200 does not supply a signal or voltage to the node n1. Since node n1 is left floating, the voltage at node n1 is V1 + Vth101_1 This means that transistor 101_1 remains on, and the The line 112 and the wiring 111 remain in a conductive state via the transistor 101_1. Therefore, the circuit 200 supplies a low level signal or voltage V1 to the node n2. The voltage of node n2 remains at approximately V1. As a result, transistor 101_2 is turned on. At this time, the signal CK1 rises from low level to high level. The high-level signal CK1 is input from the wiring 112 to the wiring 11 through the transistor 101_1. 1, the voltage of the wiring 111 starts to rise. Then, the node n1 is in a floating state. Therefore, the voltage of the node n1 is the voltage between the gate and the second terminal of the transistor 101_1. Due to the parasitic capacitance between the two, the voltage rises to the value of V2 + Vth101_1 + Vx. This is a ground strap operation. In this way, the voltage of the wiring 111 can rise to V2. In this way, the signal OUT becomes high level.

[0105] Note that during the period B1, the circuit 200 does not supply a signal, a voltage, or the like to the wiring 111. However, the circuit 200 may be configured to generate a high-level signal or voltage V 2 can be supplied to the wiring 111.

[0106] Next, during a period C1, the signal RE goes high as shown in FIG. Then, the circuit 200 applies a low level signal or voltage V1 to the node n1, the node n2, and / or is supplied to the wiring 111. Therefore, the voltage of the node n1, the voltage of the node n2, and / or As a result, the voltage of the wiring 111 becomes approximately V1. Since the transistor 101_2 is turned off, the wiring 112 and the wiring 111 are not electrically connected to each other. Then, the signal OUT goes low.

[0107] In the period C1, the signal CK1 becomes higher than the timing at which the voltage of the node n1 decreases. In other words, the timing when the transistor 101_1 becomes low may be earlier. Before turning off, the signal CK1 may become low level. When CK1 is supplied from the wiring 112 to the wiring 111 via the transistor 101_1, In such a case, the channel width of the transistor 101_1 is, for example, When a signal OUP has a channel width larger than that of other transistors, Therefore, in the period C1, the fall time of the circuit 200 When a low-level signal or voltage V1 is supplied to the wiring 111 from the wiring 112, When a low-level signal is supplied to the wiring 111 via the transistor 101_1, A low-level signal or voltage V1 is supplied from 200 to the wiring 111, and a low-level signal or voltage V2 is supplied from the wiring 112. A low-level signal may be supplied to the wiring 111 via the transistor 101_1. do.

[0108] Next, in the periods D1 and E1, as shown in FIG. 3D, the circuit 200 A signal or voltage V1 of a certain level is supplied to the node n1, the node n2, and / or the wiring 111. Then, the voltage of the node n1, the voltage of the node n2, and / or the voltage of the wiring 111 are as follows: Therefore, the transistor 101_1 and the transistor 101 Since the signal _2 remains off, the wiring 112 and the wiring 111 remain in a non-conductive state. Therefore, the signal OUT remains at a low level.

[0109] In one of the periods D1 and E1, the circuit 200 outputs a low-level signal or supplying a voltage V1 to the node n1, the node n2, and / or the wiring 111, and In the circuit 200, a signal or a voltage is applied to the node n1, the node n2, and / or the wiring 11. It is possible not to supply 1.

[0110] Next, the operation during the period T2 will be described. During the period T2, the signal SEL1 is at a low level. As a result, the signal SEL2 goes high.

[0111] During the period A2, as shown in FIG. 4(A), the signal SP becomes high level. Path 200 supplies a low level signal or voltage V1 to node n1. The voltage at 1 is reduced to approximately V1, or is maintained at approximately V1. As a result, the transistor 101_1 is turned off. A signal or voltage V2 is applied to node n2, so the voltage at node n2 begins to rise. After that, the voltage of node n2 continues to rise, and eventually the voltage of node n2 becomes V1+Vth1 01_2 (Vth101_2: threshold voltage of transistor 101_2) + Vx Then, the transistor 101_2 is turned on, and the wiring 112 and the wiring 111 are connected to each other. Therefore, the signal CK1 at a low level is The signal is supplied from the line 112 to the wiring 111 via the transistor 101_2. OUT becomes low level. After that, the voltage of node n2 rises further. Path 200 stops supplying a signal or voltage to node n2, so that circuit 200 and node n2 As a result, node n2 is in a floating state, and the voltage of node n2 is , V1 + Vth101_2 + Vx. However, it is not limited to this. For example, For example, the circuit 200 continues to supply a voltage of V1+Vth101_2+Vx to the node n2. It is possible to do this.

[0112] Note that during the period A2, the circuit 200 applies a low-level signal or a voltage V1 to the wiring 111. It is possible to supply a signal or voltage to the wiring 111, or it is possible not to supply a signal or voltage to the wiring 111. be.

[0113] Next, during a period B2, the signal SP goes low as shown in FIG. Then, the circuit 200 supplies a low-level signal or voltage V1 to the node n1. The voltage of node n1 remains at approximately V1. As a result, transistor 101_1 is turned on. On the other hand, the circuit 200 does not supply a signal or voltage to the node n2. Therefore, node n2 remains floating, and the voltage at node n2 is V The value remains at 1+Vth101_2+Vx. In other words, transistor 101_2 is on. Therefore, the wiring 112 and the wiring 111 are electrically connected to each other through the transistor 101_2. At this time, the signal CK1 rises from low level to high level. The high-level signal CK1 is input from the wiring 112 to the wiring 11 through the transistor 101_2. 1, the voltage of the wiring 111 starts to rise. Then, the node n2 is in a floating state. Therefore, the voltage of the node n2 is the voltage between the gate and the second terminal of the transistor 101_2. Due to the parasitic capacitance between the two, the voltage rises to the value of V2 + Vth101_2 + Vx. This is a ground strap operation. In this way, the voltage of the wiring 111 can rise to V2. In this way, the signal OUT becomes high level.

[0114] Note that during the period B2, the circuit 200 does not supply a signal, a voltage, or the like to the wiring 111. However, the circuit 200 may be configured to generate a high-level signal or voltage V 2 can be supplied to the wiring 111.

[0115] Next, during a period C2, the signal RE goes high as shown in FIG. Then, the circuit 200 applies a low level signal or voltage V1 to the node n1, the node n2, and / or is supplied to the wiring 111. Therefore, the voltage of the node n1, the voltage of the node n2, and / or As a result, the voltage of the wiring 111 becomes V1. Since the starter 101_2 is turned off, the wiring 112 and the wiring 111 are in a non-conductive state. As a result, the signal OUT goes low.

[0116] In the period C2, the signal CK1 becomes higher than the timing at which the voltage of the node n1 decreases. In other words, the timing when the transistor 101_2 becomes low may be earlier. Before turning off, the signal CK1 may become low level. When CK1 is supplied from the wiring 112 to the wiring 111 via the transistor 101_1, In such a case, the channel width of the transistor 101_1 is, for example, When a signal OUP has a channel width larger than that of other transistors, Therefore, in the period C2, the fall time of the circuit 200 When a low-level signal or voltage V1 is supplied to the wiring 111 from the wiring 112, When a low-level signal is supplied to the wiring 111 via the transistor 101_1, A low level signal or voltage V1 is supplied from 200 to the wiring 111, and A low-level signal may be supplied to the wiring 111 via the transistor 101_1. do.

[0117] Next, in the period D2 and the period E2, as shown in FIG. 4(D), the circuit 200 A signal or voltage V1 of a certain level is supplied to the node n1, the node n2, and / or the wiring 111. Then, the voltage of the node n1, the voltage of the node n2, and / or the voltage of the wiring 111 are as follows: Therefore, the transistor 101_1 and the transistor 101 Since the signal _2 remains off, the wiring 112 and the wiring 111 remain in a non-conductive state. Therefore, the signal OUT remains at a low level.

[0118] During one of the periods D2 and E2, the circuit 200 outputs a low-level signal or supplying a voltage V1 to the node n1, the node n2, and / or the wiring 111, and In the circuit 200, a signal or a voltage is applied to the node n1, the node n2, and / or the wiring 11. It is possible not to supply 1.

[0119] As described above, in the period T1, the transistor 101_2 is turned off, and in the period T2, Therefore, the transistor 101_1 can be turned off. The number of times 01_1 to 101_2 are turned on, the number of times that transistors 101_1 to 101_2 are turned on The number of times Vgs is applied and / or the number of times the transistors 101_1 to 101_2 are turned on Therefore, the time required for the transistors 101_1 to 101_2 to be turned on can be reduced. This can suppress the deterioration of the characteristics.

[0120] Alternatively, various benefits can be obtained by suppressing the deterioration of transistor characteristics. For example, when the wiring 111 is connected to a pixel, the video signal held by the pixel is It may be affected by the waveform of the signal OUT. For example, if the high level voltage of the signal OUT If the voltage does not rise to V2, the transistor (e.g., the select transistor or switch transistor) of the pixel The time that the switching transistor is on is shortened. This may cause insufficient writing of the signal OUT, resulting in a decrease in display quality. If the fall time and rise time become longer, the pixels belonging to the selected row will have different This can cause the video signal to be written to the pixels in the row, resulting in a poor display quality. Or, if the fall time of the signal OUT varies, the pixel The effect of feedthrough on the video signal can vary. This results in display irregularities caused by talking, etc.

[0121] However, the semiconductor device of this embodiment can suppress the deterioration of the transistor characteristics. Therefore, the high level voltage of the signal OUT can be increased to V2. This allows the transistor in the pixel to be turned on for a longer period of time. This allows for sufficient time for the video signal to be written, improving the display quality. Alternatively, the fall time and rise time of the signal OUT can be shortened. Therefore, the video signal for the pixels in another row is written to the pixels in the selected row. As a result, the display quality can be improved. Alternatively, the variation in the fall time of the signal OUT can be suppressed, so that the pixel is maintained. This reduces the variation in the effect of feedthrough on the video signal being held. Display unevenness can be suppressed.

[0122] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors is set to N-channel or Therefore, compared to CMOS circuits, the number of processes is reduced. It is possible to reduce the number of defects, improve the yield, improve the reliability, or reduce the cost. If all transistors are N-channel, including the elemental part, the semiconductor layer of the transistor a non-single-crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor However, transistors using these semiconductors tend to deteriorate. However, the semiconductor device of this embodiment is designed to suppress the deterioration of the transistor. It is possible.

[0123] Alternatively, since it can suppress the deterioration of the transistor, if the transistor deteriorates, Therefore, it is not necessary to increase the channel width of the transistor. This allows the channel width of the star to be reduced.

[0124] In the period T1, the transistor 101_1 is turned on (period A1 and period The period B1) is called the first period or the first sub-period, during which the transistor 101_1 is turned off. Calling the periods (period C1, period D1, and period E1) second periods or second sub-periods Similarly, in the period T2, the period when the transistor 101_2 is turned on ( The period A2 and the period B2 are called the third period or the third sub-period, and the transistor 101 The periods during which _2 is off (periods C2, D2, and E2) are called the fourth period or the fourth subperiod. This can be called a sub-period.

[0125] It should be noted that the periods (periods A1 and B1) during which the transistor 101_1 is turned on are This is often shorter than the period (period C1 to E1) during which the resistor 101_1 is turned off. During the periods (periods A2 and B2) when the transistor 101_2 is turned on, This is often shorter than the period when 101_2 is off (period C2 to E2). The period during which the transistor 101_1 is on and the period during which the transistor 101_2 is on are as follows: In many cases, they are roughly equal in length, but this is not the only option.

[0126] In the period T1, the period B1 functions as a selection period, and the periods A1 and C 1, period D1, and period E1 can function as non-selection periods. In the period T2, the period B2 functions as a selection period, and the periods A2 and C2 , period D2, and period E2 can function as non-selection periods.

[0127] In addition, Period A1 and Period A2 function as a set period or a start period. The period B1 and the period B2 can function as a selection period. Alternatively, the periods C1 and C2 may function as reset periods. be.

[0128] Note that the period T1 and the period T2 can function as a frame period. It is preferable that the frame frequency is approximately 60 Hz (or 50 Hz). However, this is not limiting. For example, the frame frequency can be increased to more than 60 Hz. Therefore, blurring of moving images or afterimages can be improved. However, if the frame frequency is high, If it is too high, the drive frequency will become high, which will increase the power consumption. To suppress the increase, the frame frequency should be 60Hz (or 50Hz) or higher, or 360Hz. It is preferable that the frequency is 60Hz (or 50Hz) or less, and more preferably 240Hz or more. More preferably, it is 60Hz (or 50Hz) or more and 120Hz or less. On the other hand, it is preferable to set the frame frequency to 60 Hz or less. By making the external circuit configuration lower than the Therefore, one aspect of the present invention can be applied to mobile devices such as mobile phones. However, if the frame frequency is too low, the pixel The storage capacitance becomes large, and the aperture ratio of the pixel decreases. To achieve this, the frame frequency must be between 15Hz and 60Hz (or 50Hz). More preferably, it is 30 Hz or more and 60 Hz or less (or 50 Hz or less). preferable.

[0129] The periods A1 to E1 and the periods A2 to E2 are sub-periods or one gate selection period. It is possible to have the following functions.

[0130] Note that a period or sub-period can be referred to as a step, a process, or an operation. For example, a first period may refer to a first step, a first process, or a first action. It can be rephrased as "creation."

[0131] The time from the start time of period T1 to the start time of period A1 is the start time of period T2. It is preferable that the time from the start of period A1 to the start of period A2 is approximately equal to the time from the start of period A1 to the start of period A2. Not limited.

[0132] It should be noted that the signals CK1 and CK2 can be unbalanced. For example, if the period during which the signal is at high level is shorter than the period during which the signal is at low level in one cycle, The timing chart shows the period when the signal is at high level and the period when the signal is at low level. By this, in the period C1 or the period C2, the low-level signal CK1 is applied to the wiring 1. 11, the fall time of the signal OUT can be shortened. In particular, when the wiring 111 is formed extending to the pixel portion, an incorrect video signal to the pixel may be transmitted. However, this is not limited to this. For example, That is, the period during which the signal is at a high level can be longer than the period during which the signal is at a low level.

[0133] It is possible to use a multiphase clock signal in a semiconductor device. The device can use an n-phase clock signal (n is a natural number). A clock signal is a set of n clock signals whose periods are shifted by 1 / n period. 5(B) shows an example of the timing when a three-phase clock signal is used in a semiconductor device. Charts include, but are not limited to:

[0134] The larger n is, the lower the clock frequency becomes, which can reduce power consumption. However, if n is too large, the number of signals increases, which increases the layout area. Therefore, it is preferable that n<8. It is preferable that n<6. It is further preferable that n=4, or Preferably, n=3, but is not limited to this.

[0135] The transistor 101_1 and the transistor 101_2 may be turned on at the same time. In this case, for example, the circuit 200 applies high-level A bell signal or voltage V2 can be supplied.

[0136] The channel width of the transistor 101_1 and the channel width of the transistor 101_2 are It is preferable that the transistor sizes are roughly equal. By doing so, the current supply capacity can be made roughly equal. Therefore, the degree of deterioration of the selected transistors can be made roughly equal. Even if the output voltage is switched, the waveform of the signal OUT can be made roughly the same. For this reason, the channel length of the transistor 101_1 and the channel length of the transistor 101_2 It is preferable that the values ​​are approximately equal to each other, but this is not a limitation.

[0137] When referring to the channel width of a transistor, it is expressed as W / L (W is the channel width) of the transistor. This can be rephrased as the ratio of the width of the channel to the channel length.

[0138] The transistors 101_1 and 101_2 are connected to large circuits such as gate signal lines. Since the transistor 101_1 drives a large load, the channel width of the transistor 101_1 and the For example, the channel width of the transistor 101_1 is preferably large. The channel width of the transistor 101_1 and the channel width of the transistor 101_2 are 1000 μm to 30000 μm. It is more preferable that the thickness is 2000 μm to 20000 μm. More preferably, it is 3000 μm to 8000 μm, or 10000 μm to 18000 μm. It is preferable that the thickness is 1 μm, but it is not limited to this.

[0139] In the configuration described in FIG. 1A, as shown in FIG. 1B, the circuit 100 It has multiple transistors 101_1 to 101_N (N is a natural number greater than or equal to 2). The first terminals of the transistors 101_1 to 101_N are connected to the wiring 11. 2. The second terminals of the transistors 101_1 to 101_N are connected to the wiring 111. The gates of the transistors 101_1 to 101_N are connected to the circuit 200. The connection points between the gates of the transistors 101_1 to 101_N and the circuit 200 are respectively , nodes n1 to nN, but are not limited to this.

[0140] Note that a large N reduces the number of times the transistor is turned on or Therefore, the larger N, the more transistors However, if N is too large, the number of transistors increases. Therefore, it is preferable that N is 6 or less. More preferably, N is 4 or less. Even more preferably, N=2 or N= Preferably it is 3.

[0141] In the configuration described in FIGS. 1(A) to 1(B), as shown in FIG. 1(C), The first terminal of the transistor 101_1 and the first terminal of the transistor 101_2 are connected to different wires. In the example of FIG. 1C, the wiring 112 is made up of wirings 112A to 112B. A first terminal of the transistor 101_1 is divided into a plurality of wirings, each of which is designated as a wiring B. The first terminal of the transistor 101_1 is connected to the wiring 112A, and the second terminal of the transistor 101_2 is connected to the wiring 112B. The wirings 112A and 112B can have the same function as the wiring 112. Therefore, signals such as the signal CK1 can be input to the wirings 112A and 112B. However, the present invention is not limited to this. For example, the wiring 112A and the wiring 112B may be provided with separate wirings. It is possible to provide separate voltages or separate signals.

[0142] In the configurations described in FIGS. 1(A) to 1(C), as shown in FIG. 1(D), A capacitor element 102_1 is connected between the gate and the second terminal of the transistor 101_1. A capacitance element 102_2 can be connected between the gate of 101_2 and the second terminal. By doing so, during the bootstrap operation, the voltage of the node n1 or the node Therefore, the voltage of the transistor 101_1 and the transistor 101_2 is easily increased. Since the Vgs of 01_2 can be increased, the channel width of these transistors can be Alternatively, the fall time or rise time of the signal OUT can be reduced. However, the present invention is not limited to this. For example, the capacitance element may be a MIS It is possible to use capacitance.

[0143] The material of one electrode of each of the capacitors 102_1 and 102_2 is the same as that of the transistor 101_1. It is preferable that the gate electrodes 102_1 to 102_2 are made of the same material as the gate electrodes 102_1 to 102_2. The material of the other electrode of the transistor 101_1 to 101_2 is the source or drain of the transistor 101_1 to 101_2. It is preferable that the material is the same as that of the semiconductor device. By doing so, the layout area can be reduced. Alternatively, the capacitance value can be increased. However, this is not limitative. stomach.

[0144] The capacitance value of the capacitor 102_1 and the capacitance value of the capacitor 102_2 are approximately equal. Alternatively, it is preferable that the area where one electrode and the other electrode of the capacitor 102_1 overlap and the area where one electrode and the other electrode of the capacitor 102_2 overlap are approximately equal. By doing so, the transistor 101_1 and the transistor 10 Even if the transistors 101_1 and 1_2 are switched to each other, the Vgs of the transistor 101_1 and the Vgs of the transistor 1 Since it is possible to roughly equalize the Vgs of 01_2, the waveform of the signal OUT can be roughly However, it is not limited to this.

[0145] In the configurations described in FIGS. 1(A) to 1(D), as shown in FIG. 1(E), The positive terminal of the capacitor 101_1 is connected to the node n1, and the positive terminal of the capacitor 101_2 is connected to the node n2. The negative electrode (hereinafter also referred to as the negative electrode) of the diode 101a_1 is connected to the wiring 111. , the transistor 101_2 is connected at one terminal to the node n2 and at the other terminal to the wiring 1 11 can be replaced with the diode 101a_2 connected to the For example, in the configuration described in Fig. 1(A) to (D), By connecting the first terminal of the transistor 101_1 to the node n1, It is possible to configure the transistor 101_1 as a diode. By connecting the first terminal of the transistor 101_2 to the node n2, the transistor It is possible to configure the starter 101_2 as a diode-connected one.

[0146] In the configuration described in FIGS. 1A to 1F, as shown in FIG. 6A, the signal OUT For example, if multiple semiconductor devices are connected in series, it is possible to generate a signal for transfer. In this case, the transfer signal is not input to the gate signal line, but to the next In many cases, the signal is input as a start signal to the semiconductor device at the next stage, so the delay or The delay or distortion is often small compared to the signal OUT. Since the semiconductor device can be driven using a signal with a small Alternatively, the delay in charging the node n1 or the node n2 can be reduced. This allows for faster switching, which in turn allows for a wider operating range. Not determined.

[0147] For this reason, as shown in FIG. 6A, the semiconductor device of this embodiment has a circuit 150. The circuit 150 includes a plurality of transistors 151_1 to 151_2. The transistors 151_1 and 151_2 are the same as the transistors 101_ It is preferable that the polarity is the same as that of 1 to 101_2, and that the electrodes are of the N-channel type. However, the present invention is not limited to this, and the transistors 151_1 to 151_2 may be of a P-channel type. It is possible to do this.

[0148] A first terminal of the transistor 151_1 is connected to the wiring 112. A second terminal of the transistor 151_1 is connected to a wiring 119, and a gate of the transistor 151_1 is connected to a node A first terminal of the transistor 151_2 is connected to the wiring 112. The second terminal of the transistor 151_2 is connected to the wiring 119. The gate of is connected to node n2.

[0149] For example, if a plurality of semiconductor devices are connected in series, the wiring 119 may be connected to another stage ( For example, it is often connected to the wiring 115 of the semiconductor device in the next stage. 1 can be formed by extending to the pixel portion. The gate of a transistor (e.g., a switching transistor or a selection transistor) is often connected to the However, the present invention is not limited to this. For example, the wiring 119 may be arranged so as to extend to the pixel portion. Alternatively, the wiring 119 may be connected to the gate of a transistor included in the pixel. Alternatively, the wiring 119 may be connected to a semiconductor of another stage (for example, a previous stage). It can be connected to the wiring 117 of the body device.

[0150] As an example, a signal SOUT is output from the wiring 119. The signal SOUT is , is often a digital signal having high and low levels, Therefore, the wiring 119 can function as a signal line or an output line. For example, when a plurality of semiconductor devices are connected in series, In this case, the wiring 119 is connected to the wiring of a semiconductor device in another stage (for example, the next stage). Since it is often connected to 115, the signal SOUT is a transfer signal or a start signal. However, the present invention is not limited to this. For example, the wiring 1 When the wiring 119 is arranged to extend to the pixel portion, or when the wiring 119 is arranged to connect the gate of the transistor of the pixel, When connected to the GND, the signal SOUT functions as a gate signal, a scan signal, or a selection signal. Therefore, the wiring 119 can be used as a gate signal line or a scan line. As another example, the wiring 119 may have a function of connecting the wiring 119 to another stage (for example, the previous stage). When connected to the wiring 117 of the semiconductor device, the signal SOUT functions as a reset signal. It is possible to have:

[0151] For example, the circuit 150 may be configured to: The circuit 150 has a function of controlling electrical continuity between the wiring 112 and the wiring 119. The voltage control circuit 114 has a function of controlling the timing at which the voltage of the wiring 112 is supplied to the wiring 119. For example, A signal or voltage (for example, a voltage V2 or a signal CK1) is supplied to the wiring 112. In this case, the circuit 150 supplies a signal or voltage supplied to the wiring 112 to the wiring 119. Alternatively, the circuit 150 may output a high-level signal (e.g., For example, it has a function of controlling the timing of supplying a signal CK1 to the wiring 119. The circuit 150 has a function of controlling the timing at which the voltage of the wiring 119 is increased. The circuit 150 determines the timing at which a low-level signal (for example, the signal CK1) is supplied to the wiring 119. Alternatively, the circuit 150 may have a function of controlling the timing to decrease the voltage of the wiring 119. The circuit 150 has a function of controlling the timing of the start or maintenance of the The voltage of node n1 and / or the voltage of node n2 are increased by the bootstrap operation. As described above, the circuit 150 has a function of controlling the timing of the control circuit, the buffer, and the like. It is possible for the device to have functions such as a power supply circuit or a switch. However, this is not limited to this. It should be noted that the circuit 150 does not need to have all of the above functions.

[0152] For example, the transistor 151_1 is connected to the wiring 112 in response to the voltage of the node n1. The transistor 151_1 has a function of controlling the conduction state between the wiring 119 and the transistor 151_2. The timing at which the voltage of the wiring 112 is supplied to the wiring 119 is controlled. When a signal or voltage (for example, voltage V2 or signal CK1) is supplied to 112, The transistor 151_1 transmits a signal or a voltage supplied to the wiring 112 to the wiring 119. Alternatively, the transistor 151_1 has a function of controlling the timing of supplying the high The function of controlling the timing at which a signal of a certain level (for example, signal CK1) is supplied to the wiring 119 is Alternatively, the transistor 151_1 may be configured to increase the voltage of the wiring 119. Alternatively, the transistor 151_1 has a function of controlling a low-level signal (for example, For example, it has a function of controlling the timing of supplying a signal CK1 to the wiring 119. The transistor 151_1 determines the timing to decrease or maintain the voltage of the wiring 119. Alternatively, the transistor 151_1 has a function of controlling the bootstrap operation. Alternatively, the transistor 151_1 has a function of boosting the voltage of the node n1. As described above, the transistor 151 has a function of increasing the voltage by strapping. 1 can have a function as a buffer or a switch. It should be noted that the transistor 151_1 does not necessarily have all of the above functions. There is no.

[0153] For example, the transistor 151_2 is connected to the wiring 112 in response to the voltage of the node n2. The transistor 151_2 has a function of controlling the electrical continuity between the wiring 119 and the transistor 151_3. The timing at which the voltage of the wiring 112 is supplied to the wiring 119 is controlled. When a signal or voltage (for example, voltage V2 or signal CK1) is supplied to 112, The transistor 151_2 transmits a signal or a voltage supplied to the wiring 112 to the wiring 119. Alternatively, the transistor 151_2 has a function of controlling the timing of supplying the high The function of controlling the timing at which a signal of a certain level (for example, signal CK1) is supplied to the wiring 119 is Alternatively, the transistor 151_2 may be configured to increase the voltage of the wiring 119. Alternatively, the transistor 151_2 has a function of controlling a low-level signal (for example, For example, it has a function of controlling the timing of supplying a signal CK1 to the wiring 119. The transistor 151_2 determines the timing to decrease or maintain the voltage of the wiring 119. Alternatively, the transistor 151_2 has a function of controlling the bootstrap operation. Alternatively, the transistor 151_2 has a function of boosting the voltage of the node n2. As described above, the transistor 151 has a function of increasing the voltage by strapping. 2 can have a function as a buffer or a switch. It should be noted that the transistor 151_2 does not necessarily have all of the above functions. There is no.

[0154] The timing chart of FIG. 7, the schematic diagrams of the semiconductor device of FIGS. 8(A) to 8(D), and FIG. 9(A) As shown in the schematic diagrams of the semiconductor device in (D), the transistors 151_1 and 151_2 are It often operates at roughly the same timing as transistors 101_1 and 101_2. For example, in the period A1 to B1, when the transistor 101_1 is turned on, the transistor Then, in the period C1 to E1, the transistor 101_ When the transistor 151_1 is turned off, the transistor 151_1 is also turned off. When the transistor 101_2 is turned on, the transistor 151_2 is also turned on. After that, in a period C2 to E2, when the transistor 101_2 is turned off, the transistor Therefore, the signal SOUT has a time approximately equal to the signal OUT. In many cases, the signal switches between high and low levels depending on the timing. However, this is not limited to this. stomach.

[0155] The channel width of the transistor 151_1 and the channel width of the transistor 151_2 are It is preferable that the transistor sizes are roughly equal. By doing so, the current supply capacity can be made roughly equal. Therefore, the degree of deterioration of the selected transistors can be made roughly equal. Even if the voltage is switched, the waveform of the signal SOUT can be made roughly the same. For this reason, the channel length of the transistor 151_1 and the channel length of the transistor 151_2 are The lengths are preferably approximately equal, but are not limited to this.

[0156] The signal SOUT is used as a transfer signal, and the signal OUT is used as a gate signal and a scanning signal. When used as a select signal, the load on the wiring 119 is smaller than the load on the wiring 111. Therefore, the channel width of the transistor 151_1 is often smaller than that of the transistor 1 It is preferable that the channel width of the transistor 151_2 is smaller than that of the transistor 151_1. The channel width is preferably smaller than that of the transistor 101_2. However, it is not limited to this.

[0157] The channel length of the transistor 151_1 is the same as that of the transistor 101_1. It is preferable that the channel lengths of the transistors 151_2 and 151_3 are approximately equal. It is preferable that the channel length of the first transistor 101_1 is approximately equal to that of the second transistor 101_2. However, this is not a limitation. It will not be done.

[0158] The channel width of the transistor 151_1 and the channel width of the transistor 151_2 are The thickness is preferably 100 μm to 5000 μm. More preferably, it is 300 μm to 2 000 μm, and more preferably 500 μm to 1000 μm. However, the present invention is not limited to this.

[0159] In the configuration described in FIG. 6(A), as shown in FIG. 6(B), similarly to FIG. 1(B), The circuit 150 includes a plurality of transistors 151_1 to 151_N (N is a natural number of 2 or more). It is possible to have a number of transistors. The first terminal of the transistors 151_1 to 151_N is connected to the wiring 112. The gates of the transistors 151_1 to 151_N are connected to the wiring 119. , and is connected to one of the nodes n1 to nN, but is not limited to this.

[0160] In the configuration described in FIGS. 6(A) to 6(B), as shown in FIG. 6(C), Similarly, the first terminal of the transistor 151_1 and the first terminal of the transistor 151_2 In the example shown in FIG. 6C, the wiring 112 is , is divided into a plurality of wirings 112C to 112D. A first terminal of the transistor 151_1 is connected to the wiring 112C, and a first terminal of the transistor 151_2 is connected to the wiring 112C. , and is connected to the wiring 112D, but is not limited to this.

[0161] In the configuration described in FIGS. 6(A) to 6(C), as shown in FIG. 6(D), Similarly, a capacitor 152_1 is provided between the gate and the second terminal of the transistor 151_1. and a capacitor 152_2 is connected between the gate and the second terminal of the transistor 151_2. However, it is not limited to this.

[0162] The capacitance value of the capacitor 152_1 and the capacitance value of the capacitor 152_2 are approximately equal. Alternatively, it is preferable that the area where one electrode and the other electrode of the capacitor 152_1 overlap and the area where one electrode and the other electrode of the capacitor 152_2 overlap are approximately equal. By doing so, the transistor 151_1 and the transistor 15 Even if the transistors 151_1 and 1_2 are switched to each other, the Vgs of the transistor 151_1 and the Vgs of the transistor 1 Since it is possible to make the Vgs of 51_2 approximately equal to the Vgs of 51_3, the waveform of the signal SOUT can be made large. The thickness can be equal to, but is not limited to, the thickness.

[0163] In the configuration described in FIGS. 6(A) to 6(D), as shown in FIG. 6(E), Similarly, the transistor 151_1 is connected at one terminal to the node n1 and at the other terminal can be replaced with the diode 151a_1 connected to the wiring 119. The transistor 151_2 is connected at one terminal to the node n2 and at the other terminal to the wiring 119 can be replaced with the diode 151a_2 connected to the For example, in the configuration described in Fig. 6(A) to (D), 1F, the first terminal of the transistor 151_1 is connected to the node n1. By connecting the transistor 151_1 to the diode, the transistor 151_1 is configured as a diode. Similarly, the first terminal of the transistor 151_2 is connected to the node n2. By doing so, it is possible to configure the transistor 151_2 as a diode. be.

[0164] In the configurations described in FIGS. 6(A) to 6(F), as shown in FIG. 6(G), The second terminal of the transistor 151_1 and the second terminal of the transistor 151_2 are connected to different wires. In the example of FIG. 6(G), the wiring 119 can be connected to wirings 119A to 119C. 9B. The second terminal of the transistor 151_1 is The second terminal of the transistor 151_2 is connected to the wiring 119A, and the second terminal of the transistor 151_3 is connected to the wiring 119B. However, this is not limited to this.

[0165] (Embodiment 2) In one example of this embodiment, the first terminal is electrically connected to the first wiring, and the second terminal is a first transistor electrically connected to the second wiring; a first terminal electrically connected to the first wiring; a second transistor having a first terminal electrically connected to the first wiring and a second terminal electrically connected to the second wiring; , electrically connected to the gate of the first transistor and to the gate of the second transistor; a first circuit electrically connected to the gate of the first transistor; a second wiring electrically connected to the gate of the second transistor; a second circuit electrically connected to the gate of the first transistor and a third circuit electrically connected to the port and electrically connected to the second wiring, The first circuit is configured to operate when the first signal is at a first voltage state and the second signal is at a second voltage state. a function of increasing the voltage of the gate of the first transistor when the first signal is and the third signal is in a second voltage state, the second circuit has a function of increasing the voltage of the gate of the first transistor; When either the gate of the first transistor, the gate of the second transistor, or the second wiring is in a first voltage state, , the gate of the first transistor, the gate of the second transistor, or the second wiring The third circuit has a function of outputting a signal or voltage of the first voltage state to the In the second voltage state, the gate of the first transistor and the gate of the second transistor are connected to each other. The device has a function of outputting a signal or voltage in a first voltage state to either of the first and second wirings. do.

[0166] In one example of this embodiment, the first terminal is electrically connected to the first wiring, and the second terminal is a first transistor electrically connected to the second wiring; a first terminal electrically connected to the first wiring; a second transistor having a first terminal electrically connected to the first wiring and a second terminal electrically connected to the second wiring; The first terminal is electrically connected to the third wiring, and the second terminal is connected to the gate of the first transistor. a third transistor electrically connected to the first wiring and having a gate electrically connected to a third wiring; a first terminal electrically connected to the third wiring and a second terminal electrically connected to the second transistor; a fourth transistor electrically connected to the gate, the gate of which is electrically connected to the third wiring; a first terminal electrically connected to the fourth wiring and a second terminal electrically connected to the second transistor; a fifth transistor electrically connected to the gate of the first transistor and the gate of the fifth transistor electrically connected to the fifth wiring; a first terminal electrically connected to the fourth wiring and a second terminal electrically connected to the first transistor; a sixth wiring electrically connected to the gate of the transistor, the gate of which is electrically connected to the sixth wiring; and a transistor.

[0167] An example of the semiconductor device of this embodiment will be described. This can be used in the circuit 200 described in the first embodiment. The content described in this embodiment is the same as that described in the first embodiment. The content can be combined as appropriate.

[0168] First, an example of the circuit 200 will be described with reference to Fig. 10. In the example of Fig. 10, the circuit 200 includes a circuit 300, a circuit 400, and a circuit 500. The circuit 300 is , circuit 400 shows a portion of circuit 200, and circuit 500 shows a portion of circuit 200. Some or all of the circuits in the circuit 300, the circuit 400, and the circuit 500 may be the same as the circuit 300. , circuit 400 and circuit 500 can share the same.

[0169] The circuit 300 includes, for example, a wiring 115, a wiring 116_1, a wiring 116_2, and a wiring 118. , the node n1, and the node n2. The wiring 113, the wiring 114, the wiring 118, the node n1, and the node n2 are connected. 500 is, for example, a wiring 111, a wiring 117, a wiring 118, a node n1, and a node n2. However, this is not limiting. For example, the circuit 300, the circuit 400, and The circuit 500 may be connected to various other wirings or various nodes depending on its configuration. It is possible.

[0170] Note that the circuit 300, the circuit 400, and the circuit 500 are connected to all of the above-mentioned wirings. It is not necessary to connect any of the above-mentioned wirings. The path 300 can be connected to the wiring 113 and / or the wiring 114. For example, the circuit 300 may not be connected to the wiring 118. Therefore, the circuit 400 may be disconnected from either the wiring 113 or the wiring 114. As another example, the circuit 500 may not be connected to the wiring 111. However, it is not limited to this.

[0171] The circuit 300, for example, receives input signals (e.g., signals SP, SEL1, and / or or signal SEL2), the voltage of node n1 and / or the voltage of node n2 Alternatively, the circuit 300 may have a function of controlling the node n1 and / or the node n2. It has a function to control the timing of supplying a high-level signal or voltage V2. Alternatively, the circuit 300 may include a timing circuit for increasing the voltage at the node n1 and / or the voltage at the node n2. Alternatively, the circuit 300 may have a function of controlling the timing of the node n1 and / or The function of controlling the timing of supplying a low-level signal or voltage V1 to node n2 is Alternatively, the circuit 300 may reduce the voltage at the node n1 and / or the voltage at the node n2. It has a function to control the timing to decrease or maintain the voltage. 00 is a timing when no signal or voltage is supplied to the node n1 and / or the node n2. Alternatively, the circuit 300 may have a function of controlling the node n1 and / or the node n2 is set to a floating state. , and has a function as a control circuit. However, it is not limited to this. It is not necessary to have all of the above functions.

[0172] The circuit 400 may, for example, receive an input signal or a supplied voltage (e.g., signal CK2, The line 114, the wiring 118, the signal OUT, the voltage at node n1, the voltage at node n2, and / or Depending on the voltage of the node n1, the voltage of the node n2, and / or The circuit 400 has a function of controlling the voltage of the wiring 111. Alternatively, the circuit 400 n2 and / or the timing of supplying a low-level signal or voltage V1 to the wiring 111 Alternatively, the circuit 400 has a function of controlling the voltage of the node n1, the voltage of the node n2, and / or controlling the timing of decreasing or maintaining the voltage of the wiring 111. Alternatively, the circuit 400 may provide a signal to the node n1 and / or the node n2. The circuit 400 has a function of controlling the timing at which a signal or voltage is not supplied. , and has a function of controlling the timing of putting the node n1 and / or the node n2 into a floating state. As described above, the circuit 400 has a function as a control circuit. It should be noted that the circuit 400 does not necessarily have all of the above functions.

[0173] For example, the circuit 500 may be configured to control the wiring 11 in response to an input signal (such as a signal RE). 8 and node n1, the conduction state between the wiring 118 and node n2, and / or the conduction state between the wiring The circuit 500 has a function of controlling electrical continuity between the wiring 118 and the wiring 111. The timing at which the voltage of 118 is supplied to the node n1, the node n2, and / or the wiring 111 For example, a signal or voltage (for example, a signal CK 2, or voltage V1, the circuit 500 generates a signal on the wiring 118. Or, the timing of supplying a voltage or the like to the node n1, the node n2, and / or the wiring 111 Alternatively, the circuit 500 may have a function of controlling the node n1, the node n2, and / or has a function of controlling the timing of supplying a low-level signal or voltage V1 to the wiring 111. Alternatively, the circuit 500 may include the voltage at the node n1, the voltage at the node n2, and / or The voltage of the wiring 111 is controlled by the timing of decreasing or maintaining the voltage. As described above, the circuit 500 has a function as a control circuit, a switch, or the like. However, the circuit 500 is not limited to this. It is not necessary for the circuit 500 to have all of the above functions. do not have.

[0174] Note that the circuit 300, the circuit 400, and the circuit 500 often represent parts of the circuit 200. Therefore, the circuit 200 may perform some or all of the functions of the circuits 300, 400, and 500. Alternatively, the circuit 300, the circuit 400, and the Circuits 500 may each have some or all of the functionality of circuit 200. However, it is not limited to this.

[0175] Next, an example of the operation of the semiconductor device of FIG. The operation has much in common with the operation of the semiconductor device in Figure 1, so the timing chart in Figure 2 The semiconductor device of FIG. 10 is not limited to the timing chart of FIG. It can be controlled by various timings.

[0176] First, the operation during the period T1 will be described. During the period T1, the signal SEL1 is at a high level. As a result, the signal SEL2 goes low.

[0177] During the period A1, the signal SP goes high as shown in FIG. The circuit 300 supplies a voltage V2 or a high-level signal to the node n1. 00 supplies a low level signal or voltage V1 to node n2. As described above, when the voltage of node n1 becomes V1+Vth101_1 or higher, the circuit The circuit 300 stops supplying a signal or voltage to the node n1. n1. However, this is not limiting. For example, the circuit 300 may be configured such that V1 It is possible to continue supplying a voltage equal to or higher than +Vth101_1 to the node n1.

[0178] Note that in the period A1, the circuit 400 does not supply a signal or a voltage to the node n1. In addition, the circuit 400 supplies a low-level signal or voltage V1 to the nodes n2 and / or n3. Alternatively, it is possible to supply the wiring 111 or not to supply the wiring 111.

[0179] Note that during the period A1, the circuit 500 outputs a signal or a voltage to the node n1, the node n2, And / or, in many cases, the wiring 111 is not supplied with the current.

[0180] Next, in the period B1, as shown in FIG. 11B, the circuit 300 outputs a signal, a voltage, or the like. Therefore, the circuit 300 and the node n1 are in a non-conductive state. Meanwhile, the circuit 300 provides a low level signal or voltage V1 to the node n2. Provide.

[0181] Note that during the period B1, the circuit 400 supplies a signal or a voltage to the node n1 and the wiring 11. In most cases, the circuit 400 does not supply a low level signal or voltage V1 to the node. It is possible to supply the signal to node n2, or not to supply it.

[0182] Note that during the period B1, the circuit 500 outputs a signal or a voltage to the node n1, the node n2, And / or, in many cases, the wiring 111 is not supplied with the current.

[0183] Next, during a period C1, the signal RE goes high as shown in FIG. Then, the circuit 500 applies a low level signal or voltage V1 to the nodes n1, n2, and / or n3. Alternatively, it is supplied to the wiring 111 .

[0184] Note that during the period C1, the circuit 300 applies a low-level signal or voltage V1 to the node n1, And / or it may or may not be supplied to node n2.

[0185] Note that during the period C1, the circuit 400 applies a low-level signal or voltage V1 to the node n1, It is possible to supply the current to the node n2 and / or the wiring 111, or not to supply the current. It is possible.

[0186] Next, in the period D1 and the period E1, as shown in FIG. 12A, the circuit 400 A high-level signal or voltage V1 is supplied to the node n1, the node n2, and / or the wiring 111. However, this is not limiting. For example, in one of the periods D1 and E1, Thus, the circuit 400 supplies a voltage V1 or a low level signal to the node n1, the node n2, and / or is supplied to the wiring 111, and in the other period, the circuit 400 supplies a voltage or signal to the node n It is possible that the current is not supplied to the node n1, the node n2, and / or the wiring 111.

[0187] Note that during the periods D1 and E1, the circuit 300 outputs a low-level signal or a low-level voltage V1 to node n1 and / or node n2, or not to supply is possible.

[0188] Note that during the periods D1 and E1, the circuit 500 outputs a signal or a voltage to the node n1 , the node n2 and / or the wiring 111 are not supplied in many cases.

[0189] Next, the operation during the period T2 will be described. During the period T2, the signal SEL1 is at a low level. As a result, the signal SEL2 goes high.

[0190] During the period A2, the signal SP goes high as shown in FIG. The circuit 300 supplies a low-level signal or voltage V1 to the node n1. 00 supplies a voltage V2 or a high-level signal to node n2. As described above, when the voltage of node n2 becomes V1+Vth101_2 or higher, The circuit 300 stops supplying a signal or voltage to the node n2. n2 is in a non-conductive state. However, this is not limited to this. For example, the circuit 300 It is possible to continue supplying a voltage equal to or higher than +Vth101_2 to the node n2.

[0191] Note that in the period A2, the circuit 400 does not supply a signal or a voltage to the node n2. In addition, the circuit 400 supplies a low-level signal or voltage V1 to the nodes n1 and / or n2. Alternatively, it is possible to supply the wiring 111 or not to supply the wiring 111.

[0192] Note that during the period A2, the circuit 500 outputs a signal or a voltage to the node n1, the node n2, And / or, in many cases, the wiring 111 is not supplied with the current.

[0193] Next, in a period B2, as shown in FIG. 12C, the circuit 300 outputs a low-level signal Alternatively, the circuit 300 may supply a signal or voltage to the node n1. Therefore, the circuit 300 and the node n2 remain in a non-conductive state. becomes.

[0194] Note that during the period B2, the circuit 400 supplies a signal or a voltage to the node n2 and the wiring 11. In most cases, the circuit 400 does not supply a low level signal or voltage V1 to the node. It is possible to supply the signal to node n1 or not.

[0195] Note that during the period B2, the circuit 500 outputs a signal or a voltage to the node n1, the node n2, And / or, in many cases, the wiring 111 is not supplied with the current.

[0196] Next, during a period C2, the signal RE goes high, as shown in FIG. Then, the circuit 500 applies a low level signal or voltage V1 to the nodes n1, n2, and / or n3. Alternatively, it is supplied to the wiring 111 .

[0197] Note that during the period C2, the circuit 300 applies a low-level signal or voltage V1 to the node n1, And / or it may or may not be supplied to node n2.

[0198] Note that during the period C2, the circuit 400 applies a low-level signal or voltage V1 to the node n1, It is possible to supply the current to the node n2 and / or the wiring 111, or not to supply the current. It is possible.

[0199] Next, in the period D2 and the period E2, as shown in FIG. 13B, the circuit 400 A high-level signal or voltage V1 is supplied to the node n1, the node n2, and / or the wiring 111. However, this is not limiting. For example, in one of the periods D2 and E2, Thus, the circuit 400 supplies a voltage V1 or a low level signal to the node n1, the node n2, and / or is supplied to the wiring 111, and in the other period, the circuit 400 supplies a voltage or signal to the node n It is possible that the current is not supplied to the node n1, the node n2, and / or the wiring 111.

[0200] Note that during the periods D2 and E2, the circuit 300 outputs a low-level signal or a low-level voltage V1 to node n1 and / or node n2, or not to supply is possible.

[0201] Note that during the periods D2 and E2, the circuit 500 outputs a signal or a voltage to the node n1 , the node n2 and / or the wiring 111 are not supplied in many cases.

[0202] Next, a specific example of the circuit 300 will be described with reference to FIG. A plurality of transistors 301_1 to 301_2 and a transistor 30 The transistors 301_1 to 302_2 are 1_2, and transistors 302_1 to 302_2 are transistors 101_1 to 101_2. It is preferable that the polarity is the same as that of _2, and that it is an N-channel type. Without being limited thereto, the transistors 301_1 to 301_2 and the transistors 302_1 to 302_3 2_2 can be of the P-channel type.

[0203] A first terminal of the transistor 301_1 is connected to the wiring 115. A second terminal of the transistor 301_1 is connected to a node n1. A gate of the transistor 301_1 is connected to a wiring 1. A first terminal of the transistor 301_2 is connected to the wiring 115. The second terminal of the transistor 301_2 is connected to the node n2. The gate of the transistor 302_1 is connected to the wiring 115. The first terminal of the transistor 302_1 is connected to the wiring 115. The second terminal of the transistor 302_1 is connected to the node n2. The gate of the transistor 302_1 is connected to the wiring 116_1. A first terminal of the transistor 302_2 is connected to the wiring 118, and a second terminal of the transistor 302_2 is connected to the The gate of the transistor 302_2 is connected to the wiring 116_2.

[0204] For example, the transistor 301_1 controls electrical continuity between the wiring 115 and the node n1. Alternatively, the transistor 301_1 may apply the voltage of the wiring 115 to the node n1. For example, the wiring 115 has a function of supplying a signal or a voltage (e.g., When a signal SP or a voltage V2 is supplied, the transistor 301_1 is connected to the wiring 11. 5 to the node n1. Alternatively, the transistor 301_1 may be turned on when a high-level signal (e.g., signal SP) or a voltage V 2 to the node n1. Alternatively, the transistor 3 01_1 has a function of controlling the timing of increasing the voltage of the node n1. The timing at which a signal or voltage is not supplied to the node n1 is controlled. The transistor 301_1 has a function of controlling the timing at which the node n1 is brought into a floating state. As described above, the transistor 301_1 has functions as a switch, a rectifier, a diode, and the like. or functions as a diode-connected transistor. The transistor 301_1 turns off the transistor 101_1 by turning on or off. The transistor 301_1 has a function of controlling whether or not the transistor 301_1 is turned on or off. By this, it is possible to control whether the diode 101a_1 (shown in FIG. 1(E)) is made non-conductive. However, the transistor 301_1 has a function of controlling the It is not necessary to have all of the above functions.

[0205] The transistor 301_2 controls electrical continuity between the wiring 115 and the node n2, for example. Alternatively, the transistor 301_2 may apply the voltage of the wiring 115 to the node n2. For example, the wiring 115 has a function of supplying a signal or a voltage (e.g., When a signal SP or a voltage V2 is supplied, the transistor 301_2 is connected to the wiring 11. 5 to the node n2. Alternatively, the transistor 301_2 may be turned on when a high-level signal (e.g., signal SP) or a voltage V 2 to node n2. Alternatively, transistor 3 01_2 has a function of controlling the timing of increasing the voltage of the node n2. The timing at which a signal or voltage is not supplied to the node n2 is controlled. The transistor 301_2 has a function of controlling the timing at which the node n2 is brought into a floating state. As described above, the transistor 301_2 has functions as a switch, a rectifier, a diode, and the like. or functions as a diode-connected transistor. The transistor 301_2 turns off the transistor 101_2 by turning on or off. The transistor 301_2 has a function of controlling whether or not the transistor 301_2 is turned on or off. By this, it is possible to control whether the diode 101a_2 (shown in FIG. 1(E)) is made non-conductive. However, the transistor 301_2 has a function of controlling the It is not necessary to have all of the above functions.

[0206] For example, the transistor 302_1 controls electrical continuity between the wiring 118 and the node n2. Alternatively, the transistor 302_1 may apply the voltage of the wiring 118 to the node n2. For example, the wiring 118 has a function of controlling the timing of supplying a signal or a voltage (e.g., When a signal SEL2 or a voltage V1 is supplied, the transistor 302_1 is connected to the wiring 118 to the node n2. Alternatively, the transistor 302_1 may apply a low-level signal or voltage V1 to the node n2. Alternatively, the transistor 302_1 has a function of controlling the timing of supplying the It has the function of controlling the timing to decrease or maintain the voltage of node n2. Alternatively, the transistor 302_1 controls whether the transistor 101_2 is turned off. That is, the timing at which the transistor 101_2 is turned off is controlled. As described above, the transistor 302_1 functions as a switch. It should be noted that the transistor 302_1 does not need to have all of the above functions.

[0207] The transistor 302_2 controls electrical continuity between the wiring 118 and the node n1, for example. Alternatively, the transistor 302_2 may apply the voltage of the wiring 118 to the node n1. For example, the wiring 118 has a function of controlling the timing of supplying a signal or a voltage (e.g., When a signal SEL1, a voltage V1, etc. is supplied, the transistor 302_2 118 to the node n1. Alternatively, the transistor 302_2 applies a low-level signal or voltage V1 to the node n1. Alternatively, the transistor 302_2 has a function of controlling the timing of supplying the It has the function of controlling the timing to decrease or maintain the voltage of node n1. Alternatively, the transistor 302_2 controls whether the transistor 101_1 is turned off. That is, the timing at which the transistor 101_1 is turned off is controlled. As described above, the transistor 302_2 functions as a switch. It should be noted that the transistor 302_2 does not need to have all of the above functions.

[0208] Next, an example of the operation of the semiconductor device in FIG. The operation of the semiconductor device is similar to that of the semiconductor device shown in FIG. The semiconductor device of FIG. 14A is the same as that of FIG. It is not limited to the timing chart and can be controlled by various timings. do.

[0209] During the period A1, the signal SP goes to a high level as shown in FIG. The transistor 301_1 and the transistor 301_2 are turned on, so that the wiring 115 and Electrical continuity is established between the node n1 and the wiring 115, and electrical continuity is established between the wiring 115 and the node n2. The high-level signal SP is supplied from the wiring 115 to the node n1 via the transistor 301_1. At this time, the signal SEL2 goes low. Since the node n1 is turned off, the wiring 118 and the node n1 are not electrically connected to each other. The voltage at node n1 begins to rise. Eventually, the voltage at node n1 rises to the gate of transistor 301_1. The voltage of the output terminal (for example, the high-level voltage (V2) of the signal SP) of the transistor 301_1 The threshold voltage (Vth301_1) of the transistor 1 rises to a value (V2-Vth301_1) obtained by subtracting the threshold voltage (Vth301_1) from the threshold voltage (Vth301_1). Then, the transistor 301_1 is turned off, and therefore, the wiring 115 and the node n1 are not electrically connected. On the other hand, the high-level signal SP is supplied from the wiring 115 to the transistor 301_2. At this time, the signal SEL1 becomes high level. Since the transistor 302_1 is turned on, electrical continuity is established between the wiring 118 and the node n2. Therefore, the voltage V1 is applied from the wiring 118 to the node n2 through the transistor 302_1. As a result, the voltage at node n2 is supplied to transistor 301_2 and transistor 301_3. Therefore, the channel width of the transistor 302_1 is determined by the resistance ratio of the transistor 302_2. By making the channel width of the transistor 301_2 larger than that of the transistor 301_1, the voltage of the node n2 is reduced. It is possible to set it to a small value (for example, V1).

[0210] During the period B1 to the period E1, as shown in FIGS. 15(B) to 15(C) and FIG. 16(A), The signal SP goes low. Then, the transistor 301_1 and the transistor 301 Since the node n1 is turned off, the wiring 115 and the node n2 are not electrically connected. At this time, the signal SEL1 goes high, and the signal SE L2 goes low, and the transistor 302_1 turns on. 302_2 is turned off, the wiring 118 and the node n2 are brought into a conductive state, and the wiring 118 Therefore, the voltage V1 is applied from the wiring 118 to the transistor It is supplied to node n2 via 302_1.

[0211] During the period A2, the signal SP becomes high level as shown in FIG. The transistor 301_1 and the transistor 301_2 are turned on, so that the wiring 115 and The node n1 is electrically connected, and the wiring 115 is electrically connected to the node n2. The signal SP of the line is supplied to the node n1 from the wiring 115 through the transistor 301_1. At this time, the signal SEL2 becomes high level. Then, the transistor 302_2 is turned on. Therefore, the wiring 118 and the node n1 are in a conductive state. 118 to the node n1 via the transistor 302_2. The voltage of n1 is determined by the resistance ratio between the transistor 301_1 and the transistor 302_2. Therefore, the channel width of the transistor 302_2 is set to the channel width of the transistor 301_1. By making it larger than the width, the voltage at node n1 can be set to a low value (e.g., V1). On the other hand, a high-level signal SP is transmitted from the wiring 115 to the transistor 301_ 2 to node n2. At this time, the signal SEL1 goes low. Then, the transistor 302_1 is turned off, and therefore, there is no electrical continuity between the wiring 118 and the node n2. Therefore, the voltage at node n2 starts to rise. From the voltage of the gate of the transistor 301_2 (for example, the high-level voltage (V2) of the signal SP) The value obtained by subtracting the threshold voltage (Vth301_2) of the transistor 301_2 (V2-Vth30 1_2), the transistor 301_2 is turned off, and the wiring 115 and node n2 are in a non-conductive state.

[0212] During the period B2 to the period E2, as shown in FIG. 16(C) and FIGS. 17(A) to 17(C), The signal SP goes low. Then, the transistor 301_1 and the transistor 301 Since the node n1 is turned off, the wiring 115 and the node n2 are not electrically connected. At this time, the signal SEL1 goes low and the signal SE L2 goes high, and the transistor 302_1 turns off. 302_2 is turned on, the wiring 118 and the node n2 are in a non-conductive state, and the wiring 11 8 and node n1 are electrically connected. Therefore, the voltage V1 is applied from the wiring 118 to the transistor 302_2 to the node n1.

[0213] As described above, one of the signals SEL1 and SEL2 is set to a high level. By keeping one of the voltages at node n1 and node n2 at a low value (for example, V1), Therefore, which of the transistors 101_1 and 101_2 is turned on? However, the present invention is not limited to this. For example, both the signal SEL1 and the signal SEL2 are selected. In this case, the voltage of node n1 and the voltage of node n2 can be set to a low level. Therefore, both the transistor 101_1 and the transistor Since both the wiring 112 and the wiring 111 are turned on, the wiring 112 and the wiring 111 are turned on. The signal O is turned on through the transistor 101_1 and the transistor 101_2 in parallel. The fall time or rise time of the UT can be shortened.

[0214] The channel width of the transistor 301_1 and the channel width of the transistor 301_2 are It is preferable that the transistor sizes are roughly equal. By doing so, the current supply capacity can be made roughly equal. Therefore, the voltage at node n1 and the voltage at node n2 can be made to be approximately equal. Since the voltage of the input n1 and the voltage of the output n2 can be made roughly equal, the waveform of the signal OUT can be made roughly equal. For the same reason, the channel length of the transistor 301_1 and It is preferable that the channel length of the transistor 301_1 is approximately equal to that of the transistor 301_2. This is not limited to:

[0215] The channel width of the transistor 301_1 and the channel width of the transistor 301_2 are The thickness is preferably 500 μm to 3000 μm. More preferably, it is 800 μm to 2 It is preferably 500 μm, and more preferably 1000 μm to 2000 μm. However, the present invention is not limited to this.

[0216] The channel width of the transistor 302_1 and the channel width of the transistor 302_2 are It is preferable that the transistor sizes are roughly equal. By doing so, the current supply capacity can be made roughly equal. Therefore, the voltage at node n1 and the voltage at node n2 can be made to be approximately equal. Since the voltage of the input n1 and the voltage of the output n2 can be made roughly equal, the waveform of the signal OUT can be made roughly equal. For the same reason, the channel length of the transistor 302_1 and It is preferable that the channel length of the transistor 302_1 is approximately equal to that of the transistor 302_2. This is not limited to:

[0217] The channel width of the transistor 302_1 is smaller than that of the transistor 301_2. Thus, in the period A2, the voltage of the node n1 is set to a low value ( Preferably, the channel of the transistor 302_1 can be set to V1. The width is preferably about 10 times or less the channel width of the transistor 301_2. More preferably, it is 7 times or less, and even more preferably, it is 3 times or less. However, the present invention is not limited to this.

[0218] The channel width of the transistor 302_2 is smaller than that of the transistor 301_1. Thus, during the period A1, the voltage of the node n2 is set to a low value ( Preferably, the channel of the transistor 302_2 can be set to V1. The width is preferably about 10 times or less the channel width of the transistor 301_1. More preferably, it is 7 times or less, and even more preferably, it is 3 times or less. However, the present invention is not limited to this.

[0219] The channel width of the transistor 301_1 and the channel width of the transistor 301_2 are The thickness is preferably 600 μm to 3500 μm, more preferably 1000 μm to It is preferably 3000 μm, and more preferably 1500 μm to 2500 μm. However, it is not limited to this.

[0220] In the configuration described in FIG. 14(A), as shown in FIG. 14(B), transistor 3 The first terminal of the transistor 302_1 and the first terminal of the transistor 302_2 are connected to different wirings. In an example of FIG. 14B, the wiring 118 is made up of wirings 118A to 118B. The first terminal of the transistor 302_1 is divided into a plurality of wirings. A first terminal of the transistor 302_2 is connected to the wiring 118B, and a first terminal of the transistor 302_3 is connected to the wiring 118A. However, the wirings 118A to 118B are not limited to this. Therefore, the wirings 118A to 118B can receive signals such as CK1. However, it is not limited to this. For example, the wiring 11 It is possible to supply different voltages or different signals to 8A to 118B.

[0221] In the configuration described in FIGS. 14(A) and 14(B), as shown in FIG. 14(C), One terminal of the resistor 302_1 is connected to the node n2, and the other terminal is connected to the wiring 116_1. Similarly, the transistor One terminal of the stator 302_2 is connected to the node n1, and the other terminal is connected to the wiring 116_2. For example, the diode 302a_2 can be replaced with the diode 302a_3. 02a_1 turns off the transistor 101_2 by being in a conductive state or a non-conductive state. Alternatively, the diode 302a_2 has a function of controlling whether to turn on or off. The function of controlling whether or not to turn off the transistor 101_1 by turning it on is Alternatively, the diode 302a_1 may be in a conductive state or a non-conductive state. The MOSFET 101a_2 (shown in FIG. 1(E)) has a function of controlling whether to make the MOSFET 101a_2 non-conductive. Alternatively, the diode 302a_2 may be in a conductive state or a non-conductive state. The control circuit 101 has a function of controlling whether or not the node 101a_1 (shown in FIG. 1(E)) is in a non-conducting state. However, the present invention is not limited to this. For example, in the configuration described in FIGS. 14(A) to 14(B), As shown in FIG. 14D, the first terminal of the transistor 302_1 is connected to the wiring 116_1. The gate of the transistor 302_1 is connected to the node n2, and the gate of the transistor 302_2 is connected to the node n3. The transistor 302_1 can be configured as a diode. A first terminal of the transistor 302_2 is connected to the wiring 116_2. The gate of transistor 302_2 is connected to node n1, thereby forming a diode. It is possible to have a hard-wired configuration.

[0222] In the configuration described in FIGS. 14(A) to 14(D), as shown in FIG. 14(E), The first terminal of the resistor 302_1 can be connected to the wiring 116_2. , the first terminal of the transistor 302_2 can be connected to the wiring 116_1. By doing so, during the period when the transistor 302_1 is turned off, A high level signal can be supplied to the terminal. During the period when 2 is off, a high-level signal can be supplied to the first terminal. Therefore, a reverse bias can be applied to the transistor. However, the present invention is not limited to this.

[0223] In the configuration described in FIGS. 14(A) to 14(E), as shown in FIG. 18(A), The first terminal of the transistor 301_1 and the first terminal of the transistor 301_2 are connected to separate wires. In the example of FIG. 18A, the wiring 115 can be connected to the wiring 115A. It is possible to divide the wiring into multiple wirings of 115B or less. In this case, as an example, 115A is connected to one of the wiring 119A and the wiring 119B shown in FIG. 6(G), and 15B can be connected to the other of the wiring 119A and the wiring 119B. However, the wirings 115A to 115B are not limited to this. Therefore, signals such as the signal SP can be input to the wirings 115A and 115B. However, the present invention is not limited to this. For example, the wirings 115A to 115 B can be supplied with a separate voltage or a separate signal.

[0224] In the configurations described in Figs. 14(A) to 14(E) and Fig. 18(A), As shown, the gate of transistor 301_1 and the gate of transistor 301_2 are , can be connected to the wiring 114. However, this is not limitative. For example, The gate of the transistor 301_1 and the gate of the transistor 301_2 are connected to the wiring 113. As another example, the gate of the transistor 301_1 and the gate of the transistor 301_2 can be connected to each other. When the gate of the transistor 301_2 is connected to the wiring 115, The first terminal of the transistor 301_1 and the first terminal of the transistor 301_2 are connected to the wiring 113 or the wiring 114. 14.

[0225] In the configurations described in FIGS. 14(A) to 14(E) and 18(A) to 18(B), As shown in (C) and (D), the circuit 300 includes transistors 303_1 and 303_2. It is possible to have a plurality of transistors such as transistors 303_1 to 303_2. It is preferable that the polarity of the N-channel transistors 301_1 to 301_2 is the same as that of the N-channel transistors 301_1 to 301_2. However, the present invention is not limited to this, and the transistors 303_1 to 303_2 can be of the P-channel type.

[0226] A first terminal of the transistor 303_1 is connected to a second terminal of the transistor 301_1. The second terminal of the transistor 303_1 is connected to the node n1. The gate of transistor 3_1 is connected to the second terminal of transistor 301_1. A first terminal of the transistor 303_2 is connected to a second terminal of the transistor 301_2. The second terminal of the transistor 303_2 is connected to the node n2. is connected to the second terminal of the transistor 301_2, but is not limited to this.

[0227] For example, the transistor 303_1 controls the timing at which the node n1 is brought into a floating state. Alternatively, the transistor 303_1 has a function of preventing charge leakage from the node n1. Alternatively, the transistor 303_1 has a function of preventing the voltage of the node n1 from decreasing. Alternatively, the transistor 303_1 may be a rectifying element, a diode, or The transistor functions as a diode-connected transistor. It is not necessary for the transistor 303_1 to have all of the above functions. stomach.

[0228] For example, the transistor 303_2 controls the timing at which the node n2 is brought into a floating state. Alternatively, the transistor 303_2 has a function of preventing charge leakage from the node n2. Alternatively, the transistor 303_2 has a function of preventing the voltage of the node n2 from decreasing. As described above, the transistor 303_2 has a function of preventing a rectification element, a diode, It functions as a diode-connected transistor, etc. The transistor 303_2 is not limited to this. There's no need.

[0229] In the configurations described in FIGS. 14(A) to 14(E) and 18(A) to 18(D), As shown in (E) to (F), the second terminal of the transistor 302_1 is connected to the transistor 302_2. The second terminal of transistor 301_2 may be connected to the first terminal of transistor 303_2. Alternatively, the second terminal of the transistor 302_2 is connected to the first terminal of the transistor 301_1. The second terminal of the transistor 303_1 may be connected to the first terminal of the transistor 303_2. However, it is not limited to this.

[0230] In the configurations described in FIGS. 14(A) to 14(E) and 18(A) to 18(F), As shown in (A) and (B), the gate of the transistor 303_1 is connected to the wiring 115. Alternatively, the gate of the transistor 303_2 can be connected to the wiring 115. However, the present invention is not limited to this. For example, the transistor 303 The gate of transistor 303_1 and the gate of transistor 303_2 can be connected to separate wirings. As another example, the gate of the transistor 303_1 and the gate of the transistor 303_2 The transistor 303 can be connected to the wiring 114. The gate of the transistor 303_1 is connected to the wiring 116_1, and the gate of the transistor 303_2 is connected to the wiring 116_2. 16_2.

[0231] In addition, the points described in FIGS. 14(A) to (E), 18(A) to (F), and 19(A) to (B) In this configuration, as shown in FIGS. 19(C) to 19(D), the transistor 303_1 is a transistor It can be connected to the first terminal side of the transistor 301_1. The transistor 303_2 may be connected to the first terminal side of the transistor 301_2. In the example of FIGS. 19C and 19D, the first terminal of the transistor 303_1 is connected to the wiring 11. 5, and the second terminal of the transistor 303_1 is connected to the first terminal of the transistor 301_1. The gate of the transistor 301_1 is connected to the wiring 115. A first terminal of the transistor 303_2 is connected to the wiring 115. The second terminal is connected to the first terminal of the transistor 301_2, and the second terminal is connected to the first terminal of the transistor 301_ The gate of 2 is connected to the wiring 115. However, the present invention is not limited to this.

[0232] 14(A) to (E), 18(A) to (F), and 19(A) to (D). In this configuration, as shown in FIG. 19(E), the transistor 303_1 is connected to the resistor element 304 Alternatively, the transistor 303_2 can be replaced with the resistor element 304. The resistor element 304_1 and the resistor element 304_2 can be replaced with In addition to transistors or diodes, electrodes having light-transmitting properties (for example, pixel electrodes, Materials such as ITO and IZO can be used, but are not limited to these.

[0233] In addition, the points described in FIGS. 14(A) to (E), 18(A) to (F), and 19(A) to (E) In this configuration, as shown in FIG. 19(F), a transistor in a diode-connected configuration is can be replaced with diodes. Diodes 301d_1 to 301d_2 The diode 303d has the same function as the transistors 301_1 and 301_2. 1 to 303d_2 have the same functions as the transistors 303_1 to 303_2. For example, a diode-connected transistor may be used as a rectifier. In this case, the circuit can be replaced with a circuit having at least one It is preferable to have a diode or a transistor in a diode-connected configuration. This is not limited to this.

[0234] For example, when a transistor is used as a diode, if the transistor is a P-channel In this case, as an example, as shown in FIG. 17(C), In the transistors 301p_1 to 301p_2 and the transistors 303p_1 to 303p_2 In many cases, the gate and the second terminal are connected. 1p_2 has the same function as the transistors 301_1 to 301_2 and is a P-channel type. The transistors 303p_1 and 303p_2 are the transistors 303_1 It has the same function as 303_2 and is a P-channel type. However, this is not limited to this. It will not be done.

[0235] 14(A) to (E), 18(A) to (F), 17(C), and 19(A) In the configuration described in (D) to (D), as shown in FIG. 20(A), a P-channel transistor is used. It is possible to use a channel type transistor. _2 has the same function as the transistors 101_1 to 101_2 and is a P-channel type. The transistors 302p_1 and 302p_2 are connected to the transistors 302_1 and 302_2. It has the same function as the P-channel type. When the polarity of the transistor is P-channel, the voltage V1 is supplied to the wiring 113 and the voltage V2 is supplied to the wiring 118. The voltage V2 is supplied, and the signals CK1, CK2, SP, SEL1, and SEL2 are , signal RE, the voltage at node n1, the voltage at node n2, and signal OUT are the same as those in the timing diagram of FIG. Note that the chart is reversed compared to the previous chart.

[0236] (Embodiment 3) In this embodiment, an example of a semiconductor device will be described. It can be used in the circuit 400 described in the second embodiment. The contents described in the second embodiment will be omitted. The present invention can be combined with the contents described in the first and second embodiments as appropriate.

[0237] First, an example of the circuit 400 will be described with reference to FIG. In the example, the circuit 400 includes a circuit 600 and a plurality of transistors 401_1 to 401_2. The transistor 401_1 includes a transistor 402. The transistor 401_2 and the transistor 402 are the same as the transistors 101_1 to 101_2. It is preferable that the polarity is N-channel type, but it is not limited to this. , the transistor 401_1, the transistor 401_2, and the transistor 402 are P-channel transistors. It should be noted that the circuit 400 uses all of these transistors. It is not necessary to have these transistors, and some of these transistors can be omitted.

[0238] A first terminal of the transistor 401_1 is connected to the wiring 118. A second terminal of the transistor 401_1 is connected to the node n1. A first terminal of the transistor 401_2 is connected to the node n2. The second terminal of the transistor 401_2 is connected to the wiring 118, and the second terminal of the transistor 401_2 is connected to the node n2. A first terminal of the transistor 402 is connected to the wiring 118. The second terminal is connected to the wiring 111. The circuit 600 includes the wiring 111, the wiring 114, and the wiring 118, node n1, node n2, the gate of transistor 401_1, transistor 40 1_2 and / or the gate of transistor 402. For example, the circuit 600 may have various other wiring or various other Alternatively, the circuit 600 may be connected to any of the above-mentioned wirings. It does not need to be connected to any of the above wirings and can be unconnected to any of the above wirings. do.

[0239] The connection point between the gate of the transistor 401_1 and the circuit 600 is denoted as a node m1. The connection point between the gate of the transistor 401_2 and the circuit 600 is indicated as a node m2. The connection point between the gate of the register 402 and the circuit 600 is indicated as node k.

[0240] Note that the transistor 401_1 controls electrical continuity between the wiring 118 and the node n1, for example. Alternatively, the transistor 401_1 has a function of controlling the voltage of the wiring 118 to the node For example, the wiring 118 has a function of controlling the timing at which a signal or voltage is supplied to the wiring 118. When a voltage (e.g., signal CK2 or voltage V1) is supplied, the transistor 401_1 The timing at which a signal or a voltage supplied to the wiring 118 is supplied to the node n1 is controlled. Alternatively, the transistor 401_1 has a function of controlling a low-level signal or a voltage V 1 to the node n1. Alternatively, the transistor 4 01_1 has the function of controlling the timing of decreasing or maintaining the voltage of node n1 As described above, the transistor 401_1 can function as a switch. However, the present invention is not limited to this. The transistor 401_1 has the above functions. You don't need to have everything.

[0241] Note that the transistor 401_2, for example, Alternatively, the transistor 401_2 has a function of controlling the voltage of the wiring 118 to the node For example, the wiring 118 has a function of controlling the timing at which a signal or voltage is supplied to the wiring 118. When a voltage V1 or a signal CK2 is supplied, the transistor 401_2 The timing at which a signal or a voltage supplied to the wiring 118 is supplied to the node n2 is controlled. Alternatively, the transistor 401_2 has a function of controlling a low-level signal or a voltage V 1 to node n2. Alternatively, transistor 4 01_2 has the function of controlling the timing of decreasing or maintaining the voltage of node n2 As described above, the transistor 401_2 can function as a switch. However, the transistor 401_2 is not limited to this. You don't need to have everything.

[0242] Note that the transistor 402 controls electrical continuity between the wiring 118 and the wiring 111, for example. Alternatively, the transistor 402 may supply the voltage of the wiring 118 to the wiring 111. For example, the wiring 118 has a function of controlling the timing of supplying a signal or voltage (e.g., When a signal CK2 or a voltage V1 is supplied, the transistor 402 is connected to the line 11. 8 to the wiring 111. Alternatively, the transistor 402 may apply a low-level signal or a voltage V1 to the wiring 111. Alternatively, the transistor 402 may be connected to the wiring 11. The function of the transistor is to control the timing at which the voltage of the transistor 1 is reduced or maintained. The transistor 402 can function as a switch. It should be noted that the transistor 402 does not necessarily have all of the above functions.

[0243] For example, the circuit 600 may be configured to detect the voltage of the node n1, the voltage of the node n2, and / or the voltage of the wiring 1. Depending on the voltage of node m1, the voltage of node m2, and / or the voltage of node k, Alternatively, the circuit 600 may have a function of controlling the voltage at the node m1, the node m2, and / or applies a high-level signal, a low-level signal, a voltage V1, or a voltage V2 to node k. Alternatively, the circuit 600 may control the timing of supplying the voltage of the node m1. , the timing to increase or decrease the voltage of node m2 and / or the voltage of node k. It has the function of controlling the timing or maintaining the timing, but is not limited to this. It should be noted that the circuit 600 does not necessarily have all of the above functions.

[0244] Next, an example of the operation of the semiconductor device of FIG. 21A will be described with reference to the timing chart of FIG. 21B. The timing chart of FIG. 21B shows the timing of signals SEL1 and SEL2. SEL2, signal CK1, signal CK2, signal SP, signal RE, voltage of node n1 (Va1) , the voltage of node n2 (Va2), the voltage of node m1 (Vb1), the voltage of node m2 (Vb 2), the voltage (Vc) at node k, and the signal OUT. The semiconductor device is not limited to the timing chart of FIG. 21(B), and may be operated at various timings. It can be controlled by

[0245] During the period A1, as shown in FIG. 22A, the circuit 300 outputs a high-level signal or voltage Since V2 is supplied to node n1, the voltage of node n1 rises to V1+Vth101_1 +Vx, where Vx is a value greater than 0. The circuit 300 is a low-level signal or supplies voltage V1 to node n2, the voltage at node n2 decreases. Since the signal CK1 is supplied to the wiring 111, the voltage of the wiring 111 decreases. As an example, these voltages (the voltage of node n1, the voltage of node n2, and the voltage of the wiring 111 A low level signal or voltage V1 is supplied to node m1 according to the voltage of A low level signal or voltage V2 is applied to node m2, and a high level signal or voltage V2 is applied to node k Therefore, the transistor 401_1 is turned off, and the wiring 118 and the node n The transistor 401_2 is turned on, so that the wiring 118 and the node Therefore, the voltage V1 is applied from the wiring 118 to the transistor 401_ 2 to the node n2. Since the transistor 402 is turned on, the Therefore, the voltage V1 is applied from the wiring 118 to the transistor 4 02 to the wiring 111. However, this is not limiting. For example, 0 provides a low level signal or voltage V1 to node m2 and / or node k. Therefore, the transistor 401_2 can be turned off, and the wiring 118 and node n2 can be in a non-conductive state. 2 can be turned off, so that the wiring 118 and the wiring 111 can be in a non-conductive state. It is possible.

[0246] During the period B1, as shown in FIG. 22(B), the node The voltage of n1 rises to V2+Vth101_1+Vx. A signal or voltage V1 is applied to node n2, so that the voltage at node n2 is low (e.g., V1 ) is maintained. In addition, since a high level signal CK1 is supplied to the wiring 111, The voltage at node n1 rises. The circuit 600 detects these voltages (the voltage at node n1, the voltage at node n2) A low level signal or voltage V1 is applied to node m according to the voltage of the line 111. 1, a high level signal or voltage V2 is supplied to node m2, and a low level signal or voltage V3 is supplied to node m3. supplies voltage V1 to node k. Therefore, transistor 401_1 is turned off, and The wiring 118 and the node n1 are brought out of conduction. Therefore, the wiring 118 and the node n2 are in a conductive state. The voltage is supplied to the node n2 through the transistor 401_2. The transistor 402 is turned off. Therefore, the wiring 118 and the wiring 111 are not electrically connected to each other. However, this is not limiting. For example, the circuit 600 may provide a low level signal or voltage V1 to node m2. Therefore, the transistor 401_2 can be turned off, and the wiring 11 8 and node n2 can be in a non-conductive state.

[0247] During the period C1 to E1, as shown in FIG. 22(C) and FIG. 23(A), the nodes n1, A low-level signal or voltage V1 is supplied to the node n2 and the wiring 111. The voltage of node n1, the voltage of node n2, and the voltage of wire 111 decrease or become low (for example, The circuit 600 is, as an example, maintained at these voltages (the voltage at node n1, A high-level signal or voltage V2 A high level signal or voltage V2 is applied to node m2, and a high level The signal or voltage V2 of the transistor 401_1 is supplied to the node k. Therefore, the wiring 118 and the node n1 are in a conductive state. 8 to the node n1 via the transistor 401_1. 2 is turned on, the wiring 118 and the node n2 are in a conductive state. , is supplied to the node n2 from the wiring 118 through the transistor 401_2. Since the capacitor 402 is turned on, the wiring 118 and the wiring 111 are in a conductive state. V1 is supplied from the wiring 118 to the wiring 111 through the transistor 402. For example, the circuit 600 may apply a low level signal or voltage V1 to node m 1, node m2, and / or node k. Since the starter 401_1 can be turned off, the wiring 118 and the node n1 are in a non-conductive state. Alternatively, the transistor 401_2 can be turned off. Therefore, the wiring 118 and the node n2 can be brought into a non-conductive state. Since the switch 402 can be turned off, the wiring 118 and the wiring 111 are not electrically connected. It is possible to do this.

[0248] During one of the periods E1 and D1, the circuit 600 outputs a high-level signal or supplies voltage V2 to node m1, node m2, and / or node k, and in the other period In this case, the circuit 600 applies a low level signal or voltage V1 to nodes m1, m2, and / or m3. Alternatively, it can be supplied to node k. Since the time or number of times the transistor is turned on is reduced, deterioration of the transistor can be suppressed. can.

[0249] During the period A2, as shown in FIG. 23B, the circuit 300 outputs a low-level signal or voltage By supplying V1 to node n1, the voltage at node n1 decreases. Since the signal or voltage V2 of the FET is applied to node n2, the voltage of node n2 rises and V1+ Vth101_2+Vx, where Vx is greater than 0. Since the signal CK1 of the line 60 is supplied to the line 111, the voltage of the line 111 decreases. 0 is, for example, the voltages of these voltages (the voltage of node n1, the voltage of node n2, and the voltage of the wiring 11 1), a high level signal or voltage V2 is supplied to node m1, and a low level A low level signal or voltage V1 is applied to node m2, and a high level signal or voltage V2 is applied to node m3. Therefore, the transistor 401_1 is turned on, and the wiring 118 and the node k are connected to each other. n1 is electrically connected to the wiring 118. Therefore, the voltage V1 is supplied to the transistor 401_1 The transistor 401_2 is turned off, and the potential of the wiring 11 is supplied to the node n1 through the The transistor 402 is turned on, and therefore the wiring 11 8 and the wiring 111 are in a conductive state. Therefore, the voltage V1 is applied from the wiring 118 to the transistor The signal is supplied to the wiring 111 via the circuit 402. However, this is not limiting. For example, 00 provides a low level signal or voltage V1 to node m1 and / or node k. Therefore, the transistor 401_1 can be turned off, and the The line 118 and the node n1 can be in a non-conductive state. Since the 02 can be turned off, the wiring 118 and the wiring 111 are not electrically connected. is possible.

[0250] During the period B2, as shown in FIG. 23C, the circuit 300 outputs a low-level signal or voltage Since V1 is supplied to node n1, the voltage at node n1 is maintained at a low value (e.g., V1). The voltage of node n2 rises due to the bootstrap operation, and becomes V2+Vth101_ 2+Vx. In addition, since a high-level signal CK1 is supplied to the wiring 111, The voltage at node n1 rises. The circuit 600, as an example, The voltage of the node n2 and the voltage of the wiring 111) 2 to node m1, a low level signal or voltage V1 to node m2, and a low level signal or voltage V3 to node m3. The bell signal or voltage V1 is supplied to the node k, so that the transistor 401_1 is turned on. Therefore, the wiring 118 and the node n1 are in a conductive state. 18 to the node n1 via the transistor 401_1. Since the transistor _2 is turned off, there is no electrical continuity between the wiring 118 and the node n2. Since the signal 02 is turned off, the wiring 118 and the wiring 111 are not electrically connected. For example, the circuit 600 may provide a low level signal or voltage V1 to node m1. Therefore, the transistor 401_1 can be turned off. Therefore, the wiring 118 and the node n1 can be brought into a non-conductive state.

[0251] During the period C2 to E2, as shown in FIG. 24(A) and FIG. 24(B), the nodes n1, A low-level signal or voltage V1 is supplied to the node n2 and the wiring 111. The voltage of node n1, the voltage of node n2, and the voltage of wire 111 decrease or become low (for example, The circuit 600 is, as an example, maintained at these voltages (the voltage at node n1, A high-level signal or voltage V2 A high level signal or voltage V2 is applied to node m2, and a high level The signal or voltage V2 of the transistor 401_1 is supplied to the node k. Therefore, the wiring 118 and the node n1 are in a conductive state. 8 to the node n1 via the transistor 401_1. 2 is turned on, the wiring 118 and the node n2 are in a conductive state. , is supplied to the node n2 from the wiring 118 through the transistor 401_2. Since the capacitor 402 is turned on, the wiring 118 and the wiring 111 are in a conductive state. V1 is supplied from the wiring 118 to the wiring 111 through the transistor 402. For example, the circuit 600 may apply a low level signal or voltage V1 to node m 1, node m2, and / or node k. Since the starter 401_1 can be turned off, the wiring 118 and the node n1 are in a non-conductive state. Alternatively, the transistor 401_2 can be turned off. Therefore, the wiring 118 and the node n2 can be brought into a non-conductive state. Since the switch 402 can be turned off, the wiring 118 and the wiring 111 are not electrically connected. It is possible to do this.

[0252] During one of the periods E2 and D2, the circuit 600 outputs a high-level signal or supplies voltage V2 to node m1, node m2, and / or node k, and in the other period In this case, the circuit 600 applies a low level signal or voltage V1 to nodes m1, m2, and / or m3. Alternatively, it can be supplied to node k. This will turn the transistor on. Since the time or number of times that the transistor is turned on is reduced, deterioration of the transistor can be suppressed.

[0253] The channel width of the transistor 401_1 and the channel width of the transistor 401_2 are It is preferable that they are approximately equal. The change in voltage of the node n2 during the period T1 can be made approximately equal to the change in voltage of the node n2 during the period T2. By doing so, the waveform of the signal OUT can be made roughly the same. The channel length of the transistor 401_1 and the channel length of the transistor 401_2 are approximately equal. However, it is not limited to this.

[0254] The channel width of the transistor 401_1 and the channel width of the transistor 401_2 are The thickness is preferably 100 μm to 4000 μm, and more preferably 500 μm to 30 It is more preferable that the thickness is 1000 μm to 2000 μm. However, the present invention is not limited to this.

[0255] The channel width of the transistor 402 is preferably 500 μm to 5000 μm. It is more preferable that the thickness is 1000 μm to 3000 μm. Preferably, the thickness is 2000 μm to 3000 μm. However, the thickness is not limited to this. stomach.

[0256] In the configuration described in FIG. 21(A), as shown in FIG. 25(A), The transistors can be connected in parallel. They can be turned on in order or randomly. This shows the configuration when the transistors are connected in parallel. In this case, the two transistors are , repeating on and off for each gate selection period or for each half cycle of the clock signal. The transistor 401_1, the transistor 401_2, and the transistor 401_3 are connected in series. 02, transistors 411_1 to 411_2, and The first terminal of the transistor 411_1 is connected to the wiring 118. The second terminal of the transistor 411_1 is connected to the node n1, and the third terminal of the transistor 411_2 is connected to the node n2. The gate of the transistor 411_1 is connected to the circuit 600. The first terminal of the transistor 411_2 is connected to the The second terminal of the transistor 411_2 is connected to the wiring 118, and the second terminal of the transistor 411_2 is connected to the node n2. The gate of the transistor 411_2 is connected to the circuit 600. The first terminal of the transistor 411 is connected to the wiring 118, and the second terminal of the transistor 412 is connected to the wiring 111. The gate of the transistor 412 is connected to the circuit 600. For example, any of the transistors 411_1 to 411_2 and the transistor 412 It is possible to add only one.

[0257] In FIG. 25A, the transistor 401_1, the transistor 411_1, the transistor By omitting the transistors 401_2 and 411_2, the circuit 400 may include only the circuit 600, the transistor 402, and the transistor 412. 25A, the transistor 401_1 and the transistor 411 By omitting transistors 401, 402, and 412, the circuit 40 0 includes only the circuit 600, the transistor 401_2, and the transistor 411_2. Alternatively, in FIG. 25A, the transistor 401_2, By omitting transistor 411_2, transistor 402, and transistor 412, The circuit 400 includes the circuit 600, the transistor 401_1, and the transistor 411_1. However, it is not limited to this.

[0258] In FIG. 25A, the channel width of the transistor 401_1 is The channel width of the transistor 401_2 is preferably approximately equal to that of the transistor 11_1. The channel width is preferably approximately equal to that of the transistor 411_2. The channel width of transistor 402 is approximately equal to the channel width of transistor 412. Therefore, for example, the channel width of the transistor 411_1 is The channel width of the transistor 411_2 is preferably 100 μm to 4000 μm. It is more preferable that the thickness is 500 μm to 3000 μm. Preferably, the thickness is 1000 μm to 2000 μm. The width of the hole is preferably 500 μm to 5000 μm, and more preferably 1000 μm. It is preferable that the thickness is 2000 μm to 3000 μm. Preferably, m is used, but is not limited to this.

[0259] In the configurations described in FIG. 21(A) and FIG. 25(A), as shown in FIG. 25(B), A first terminal of the transistor 411_1 is connected to the wiring 115_1. The gate of the transistor 411_1 can be connected to the wiring 113. A first terminal of the transistor 411_2 is connected to the wiring 115_2. The gate of the transistor 412 can be connected to the wiring 113. The transistor can be connected to the wiring 113. 411_1 to 411_2 and a circuit for controlling the conduction state of the transistor 412 are omitted. However, the present invention is not limited to this. For example, the transistor 401_1 may be omitted. the second terminal of the transistor 401_2, the second terminal of the transistor 402, and / or The second terminal can be connected to the wiring 113. A reverse bias can be applied to the transistor, which suppresses the deterioration of the transistor's characteristics. It is possible.

[0260] In the configurations described in FIG. 21(A) and FIG. 25(A) to (B), As shown, the gates of the transistors 401_1 to 401_2 and the gate of the transistor 402 The gates of the transistors 401_1 to 401_40 can be connected to each other. The gates of the transistors 1_2 and 402 are connected to the circuit 600. In this case, the circuit 600 performs the following in the periods A1 to B1 and A2 to B2: A low level signal or voltage V1 can be applied to node j. Meanwhile, circuit 6 00 indicates a high-level signal or voltage V2 during periods C1 to E1 and C2 to E2. can be supplied to node j. Therefore, transistor 401_1, transistor The transistor 401_2 and the transistor 402 are in the period A1 to B1 and the period A2 to B2. It can be turned off during periods C1 to E1 and on during periods C2 to E2. Thus, the transistor 401_1, the transistor 401_2, and the transistor 401_3 are connected to the The circuit for controlling the conduction state of O2 can be shared, simplifying the circuit scale. However, the present invention is not limited to this. For example, the circuit 600 may be configured to In either the period E1 or the period D2, or in either the period D2 or the period E2, a low-level signal or voltage is applied. Alternatively, the circuit 600 may supply a voltage V1 to the node j during the period C1 to E1. During one of the periods C2 to E2, a low-level signal or voltage V1 is supplied to the node j. By doing so, it is possible to make the transistor select a gate voltage for each gate selection period. Since it is possible to repeat on and off every frame, the characteristics of the transistor As another example, as shown in FIG. The gate of 402 is the gate of the transistor 401_1 and the gate of the transistor 401_2. It is possible to connect only one of the two.

[0261] In the configurations described in FIG. 21(A), FIG. 25(A) to (B), and FIG. 26(A) to (B), 26(C), the first terminal of the transistor 401_1, the The first terminal of the transistor 401_2 and the first terminal of the transistor 402 are connected to different wirings. In FIG. 26(A), as an example, the wiring 118 includes wirings 118C to 118F. The circuit 600 is connected to the wiring 118C. The first terminal of the transistor 401_1 is connected to the wiring 118D. A first terminal of the transistor 401_2 is connected to the wiring 118E, and a first terminal of the transistor 402 is connected to the wiring 118F. , and is connected to the wiring 118F. However, this is not limiting. 8F can have the same function as the wiring 118. Therefore, the wirings 118C to 118F can have the same function as the wiring 118. Voltages such as voltage V1 can be input to 18F. However, this is not limited to this. For example, different voltages or different signals may be supplied to the wirings 118C to 118F. is possible.

[0262] In the configurations described in FIG. 21(A), FIGS. 25(A) to 25(B), and FIGS. 26(A) to 26(C), As shown in FIG. 27A, the transistor 401_1 is connected to one terminal (hereinafter referred to as the positive terminal) of the The other terminal (hereinafter also referred to as the negative terminal) is connected to node m1. It is possible to replace the diode 401a_1 connected to the transistor The positive terminal of the capacitor 401_2 is connected to the node n2, and the positive terminal of the capacitor 401_2 is connected to the node n3. The negative pole of the diode 401a_2 is connected to the node m2. Alternatively, one terminal (hereinafter also referred to as a positive terminal) of the transistor 402 may be connected to a ) is connected to the wiring 111, and the other terminal (hereinafter also referred to as the negative electrode) is connected to the node k. However, it is not limited to this. For example, For example, in the configurations described in FIG. 21(A), FIG. 25(A) to (B), and FIG. 26(A) to (C), As shown in FIG. 27B, the first terminal of the transistor 401_1 is connected to the node m1. The second terminal of the transistor 401_1 is connected to the node n1, and the second terminal of the transistor 401_1 is connected to the node n1. The transistor 401_1 can be configured in a diode-connected configuration. A first terminal of the transistor 401_2 is connected to the node m2, and The second terminal of the transistor 401_2 is connected to the node n2, thereby The first terminal of the transistor 402 is connected to the node k, and the second terminal of the transistor 402 is connected to the wiring 111. , transistor 402 can be configured in a diode-connected configuration.

[0263] Next, a specific example of the circuit 600 will be described with reference to FIG. The circuit 601_1 to 601_2 and the circuit 602 are included. The circuit 602 has a function as a NOT circuit or an inverter, for example. The input terminal of the circuit 601_1 is connected to the node n1. The output terminal of the circuit 601_2 is connected to the node m1. The input terminal of the circuit 601_2 is connected to the node n2. The output terminal of the circuit 601_2 is connected to the node m2. The input terminal of the circuit 602 is , is connected to the wiring 111, and the output terminal of the circuit 602 is connected to the node k.

[0264] Another example of the circuit 600 will be described with reference to FIG. 28B. 03. For example, the circuit 603 has a function as a two-input NOR circuit. One input terminal of the circuit 603 is connected to the node n1, and the other input terminal of the circuit 603 is connected to the node n2. The input terminal of the circuit 603 is connected to the node n2, and the output terminal of the circuit 603 is connected to the node j. do.

[0265] Another example of the circuit 600 will be described with reference to FIG. 28C. The circuit 611_1 to 611_2 and the circuit 612. The circuit 612 is, for example, a logic circuit that combines a two-input AND circuit and a NOT circuit. One input terminal of the circuit 611_1 is connected to the wiring 113. The other input terminal of the circuit 611_1 is connected to the node n1, and the other input terminal of the circuit 611_ An output terminal of the circuit 611_2 is connected to the node m1. 13, and the other input terminal of the circuit 611_2 is connected to the node n2. An output terminal of the circuit 612 is connected to the node m2. The other input terminal of the circuit 612 is connected to the wiring 111. The output terminal is connected to node k.

[0266] Another example of the circuit 600 will be described with reference to FIG. 28(D). The circuit 613 is a logic circuit that combines a three-input AND circuit and a NOT circuit. The first input terminal of the circuit 613 is connected to the wiring 113. The second input terminal of the circuit 613 is connected to the node n1, and the third input terminal of the circuit 613 is connected to the node n2. The input terminal of the circuit 611 is connected to the node n2, and the output terminal of the circuit 612 is connected to the node j. .

[0267] Another example of the circuit 600 will be described with reference to FIG. 21_1 to 621_2 and a circuit 622. As an example, the circuit 622 can function as a two-input NOR circuit. One input terminal of the circuit 621_1 is connected to the wiring 113, and the other input terminal of the circuit 621_1 is connected to the wiring 113. The input terminal of the circuit 621_1 is connected to a node n1, and the output terminal of the circuit 621_2 is connected to a node m1. One input terminal of the circuit 621_2 is connected to the wiring 113, and the other input terminal of the circuit 621_2 is connected to the wiring 113. The input terminal of the circuit 621_2 is connected to the node n2, and the output terminal of the circuit 621_3 is connected to the node m2. One input terminal of the circuit 622 is connected to the wiring 113, and the other input terminal of the circuit 622 is connected to the wiring 113. The input terminal of the circuit 622 is connected to the wiring 111, and the output terminal of the circuit 622 is connected to the node k.

[0268] Another example of the circuit 600 will be described with reference to FIG. The circuit 623 can function as a three-input NOR circuit. The first input terminal of the circuit 623 is connected to the wiring 113, and the second input terminal of the circuit 623 is connected to the wiring 113. The third input terminal of the circuit 623 is connected to the node n1, and the third input terminal of the circuit 623 is connected to the node n2. The output terminal of the circuit 623 is connected to the node j.

[0269] Another example of the circuit 600 will be described with reference to FIG. The circuit 614 is a logic circuit that combines a two-input AND circuit and a NOT circuit. The first input terminal of the circuit 614 is connected to the wiring 113. , the second input terminal of the circuit 614 is connected to the wiring 111, and the output terminal of the circuit 614 is connected to the wiring 112. The child is connected to node j.

[0270] Another example of the circuit 600 will be described with reference to FIG. The circuit 624 can function as a two-input NOR circuit. The first input terminal of the circuit 624 is connected to the wiring 113, and the second input terminal of the circuit 624 is connected to the wiring 113. The output terminal of the circuit 624 is connected to the wiring 111, and the output terminal of the circuit 624 is connected to the node j.

[0271] Next, circuits 601_1 to 601_2, circuit 602, and circuit 603 shown in FIGS. 3, circuit 611_1~611_2, circuit 612, circuit 613, circuit 621_1~621_ 2. An example of the circuit 622 and the circuit 623 is shown in FIGS. 29(A) to 29(F) and FIG. 30( The following description will be made with reference to A) to D). However, the circuits 601_1 to 601_2, the circuit 602, Circuit 603, circuit 611_1~611_2, circuit 612, circuit 613, circuit 621_1~ Various other configurations can be used for the circuits 621_2, 622, and 623. It is Noh.

[0272] In the circuit of FIG. 29(A), the first terminal is connected to the wiring 114, and the second terminal is connected to the output terminal 69. a transistor 631 having a first terminal connected to a wiring 114 and a gate connected to a wiring 115; The first terminal is connected to the line 118, the second terminal is connected to the output terminal 691, and the gate is connected to the input terminal 692. 29A includes a circuit 601_1, a circuit It is possible to apply this to the circuit 601_2 and / or the circuit 602. The terminal 691 can be connected to a node m1, a node m2, a node k, or the like. Alternatively, the input terminal 692 is connected to the node n1, the node n2, the wiring 111, or the like. It is possible to do this.

[0273] In the circuit of FIG. 29B, the first terminal is connected to the wiring 114, and the second terminal is connected to the transistor a transistor 631 whose gate is connected to the wiring 114; The first terminal is connected to the wiring 118, and the second terminal is connected to the gate of the transistor 633. , a transistor 632 whose gate is connected to an input terminal 692, and a first terminal of a transistor 632 whose second terminal is connected to a wiring 114 and a transistor 633 having a first terminal connected to the output terminal 691; The first terminal is connected to the wiring 118, the second terminal is connected to the output terminal 691, and the gate is connected to the input terminal 29B includes a transistor 634 connected to the circuit 601. It is possible to apply the same to the circuit 601, the circuit 601, the circuit 602, and / or the circuit 602. Therefore, the output terminal 691 may be connected to a node m1, a node m2, a node k, or the like. Alternatively, the input terminal 692 may be connected to the node n1, the node n2, the wiring 111, etc. It is possible to connect with.

[0274] In the circuit of FIG. 29(C), the first terminal is connected to the wiring 114, and the second terminal is connected to the output terminal 69. 1 and a transistor 641 having a gate connected to a wiring 114; The first terminal is connected to the line 118, the second terminal is connected to the output terminal 691, and the gate is connected to the input terminal 692. a transistor 642 having a first terminal connected to the wiring 118 and a second terminal connected to the a transistor 643 connected to an output terminal 691 and having a gate connected to an input terminal 693; The circuit in FIG. 29C includes a circuit 603, a circuit 621_1, a circuit 621_2, and a circuit 622, or circuit 624. Therefore, the output terminal 691 is It is possible to be connected to node j, node m1, node m2, or node k, and so on. Alternatively, the input terminals 692 and 693 may be connected to the node n1, the node n2, the wiring 111, or the wiring 112. 13, etc.

[0275] In the circuit of FIG. 29(D), the first terminal is connected to the wiring 114 and the second terminal is connected to the transistor a transistor 641 whose gate is connected to the wiring 114; One terminal is connected to the wiring 118, and the second terminal is connected to the gate of the transistor 644. a transistor 642 whose gate is connected to an input terminal 692 and whose first terminal is connected to a wiring 118; and a second terminal connected to the gate of transistor 644, the gate of which is connected to input terminal 6 93, a transistor 643 having a first terminal connected to the wiring 114 and a second terminal connected to the wiring 114; A transistor 644 having a first terminal connected to the output terminal 691 and a second terminal connected to the wiring 118 The second terminal is connected to the output terminal 691, and the gate is connected to the input terminal 692. The transistor 645 has a first terminal connected to the wiring 118 and a second terminal connected to the output terminal 691. and a transistor 646 whose gate is connected to an input terminal 693. The circuit of 9(D) is the circuit 603, the circuit 621_1, the circuit 621_2, the circuit 622, or the circuit Therefore, the output terminal 691 is connected to the node j, the node The input terminal may be connected to a node m1, a node m2, or a node k. The children 692 to 693 are connected to the node n1, the node n2, the wiring 111, or the wiring 113. It is possible to do this.

[0276] In the circuit of FIG. 29(E), the first terminal is connected to the wiring 114, and the second terminal is connected to the output terminal 69. 1 and a transistor 641 having a gate connected to a wiring 114; The first terminal is connected to the line 118, the second terminal is connected to the output terminal 691, and the gate is connected to the input terminal 692. a transistor 642 having a first terminal connected to the wiring 118 and a second terminal connected to the a transistor 643 connected to an output terminal 691 and having a gate connected to an input terminal 693; , a first terminal is connected to the wiring 118, a second terminal is connected to the output terminal 691, and a gate and a transistor 647 connected to an input terminal 694. The circuit of FIG. Therefore, the output terminal 691 is connected to the node j, etc. Alternatively, the input terminals 692 to 694 can be connected to the node n1, It is possible to connect the node n2, the wiring 113, or the like.

[0277] In the circuit of FIG. 29(F), the first terminal is connected to the wiring 114, and the second terminal is connected to the transistor a transistor 641 whose gate is connected to the wiring 114; One terminal is connected to the wiring 118, and the second terminal is connected to the gate of the transistor 644. a transistor 642 whose gate is connected to an input terminal 692 and whose first terminal is connected to a wiring 118; and a second terminal connected to the gate of transistor 644, the gate of which is connected to input terminal 6 93, a transistor 643 having a first terminal connected to the wiring 118 and a second terminal connected to the wiring 118; The transistor 644 has its terminal connected to the gate of the transistor 644 and its gate connected to the input terminal 694. A first terminal of the transistor 647 is connected to the wiring 114, and a second terminal of the transistor 647 is connected to the output terminal 691. The transistor 644 has a first terminal connected to the wiring 118 and a second terminal connected to the output a transistor 645 connected to the output terminal 691 and having its gate connected to the input terminal 692; The first terminal is connected to the wiring 118, the second terminal is connected to the output terminal 691, and the gate is A transistor 646 connected to an input terminal 693 and a transistor 646 having a first terminal connected to a wiring 118 , a transistor whose second terminal is connected to the output terminal 691 and whose gate is connected to the input terminal 694. The circuit in FIG. 29(F) can be applied to the circuit 623, etc. Therefore, the output terminal 691 can be connected to a node j, etc. The input terminals 692 to 694 are connected to the node n1, the node n2, the wiring 113, etc. It is possible to do this.

[0278] The circuit of FIG. 30(A) has a first terminal connected to the input terminal 692 and a second terminal connected to the transistor. A transistor 65 is connected to the gate of the transistor 653 and the gate of the transistor 65 is connected to an input terminal 692. 1, a first terminal of which is connected to the wiring 118, and a second terminal of which is connected to the gate of the transistor 653. a transistor 652 having a first terminal connected to an input terminal 693; a transistor 653 having a first terminal connected to the input terminal 692 and a second terminal connected to the output terminal 691; The first terminal is connected to the wiring 118, the second terminal is connected to the output terminal 691, and the gate The circuit in FIG. 30(A) has a transistor 654 connected to an input terminal 693. , circuit 611_1, circuit 611_2, circuit 612, and / or circuit 614, etc. Therefore, the output terminal 691 can be connected to the node m1, the node m2, or the node m3. k, etc. Alternatively, the input terminal 692 may be connected to the wiring 113, etc. Alternatively, the input terminals 693 and 694 may be connected to the nodes n1 and n 2, or wiring 111, etc.

[0279] The circuit of FIG. 30(B) has a first terminal connected to the input terminal 692 and a second terminal connected to the transistor. A transistor 65 is connected to the gate of the transistor 653 and the gate of the transistor 65 is connected to an input terminal 692. 1, a first terminal of which is connected to the wiring 118, and a second terminal of which is connected to the gate of the transistor 653. a transistor 652 having a first terminal connected to an input terminal 693; a transistor 653 having a first terminal connected to the input terminal 692 and a second terminal connected to the output terminal 691; The first terminal is connected to the wiring 118, the second terminal is connected to the output terminal 691, and the gate A transistor 654 having a first terminal connected to an input terminal 693 and a second terminal connected to a wiring 118 The second terminal is connected to the gate of the transistor 653, and the gate is connected to the input terminal 694. The transistor 655 has a first terminal connected to the wiring 118 and a second terminal connected to the output terminal. a transistor 656 whose gate is connected to an input terminal 691 and whose gate is connected to an input terminal 694; The circuit in FIG. 30B can be applied to the circuit 613 and the like. The output terminal 691 can be connected to a node j, etc. 2 can be connected to the wiring 113, etc. Alternatively, the input terminals 693 to 694 can be connected to node n1, or node n2, and so on.

[0280] In the circuit of FIG. 30C, the first terminal is connected to the wiring 118, and the second terminal is connected to the output terminal 69. 1 and a transistor 661 whose gate is connected to an input terminal 693; The capacitor element 662 has one electrode connected to the input terminal 692 and the other electrode connected to the output terminal 691. The circuit in FIG. 30C includes a circuit 611_1, a circuit 611_2, a circuit 612, and and / or the circuit 614. Therefore, the output terminal 691 is It is possible to connect to node m1, node m2, node k, or node j. Alternatively, the input terminal 692 can be connected to the wiring 113 or the like. The terminal 693 can be connected to the node n1, the node n2, the wiring 111, or the like. be.

[0281] In the circuit of FIG. 30(D), the first terminal is connected to the wiring 118, and the second terminal is connected to the output terminal 69. 1 and a transistor 661 whose gate is connected to an input terminal 693; The capacitor element 662 has one electrode connected to the input terminal 692 and the other electrode connected to the output terminal 691. The first terminal is connected to the wiring 118, the second terminal is connected to the output terminal 691, and the gate The circuit in FIG. 30(D) has a transistor 663 connected to an input terminal 694. Therefore, the output terminal 691 can be applied to the node j, Alternatively, the input terminal 692 may be connected to the wiring 113 or the like. Alternatively, the input terminals 693 to 694 may be connected to the node n1 or the node n 2, etc.

[0282] The circuit configuration is not limited to those shown in FIGS. 29(A) to 29(F) and 30(A) to 30(D). For example, in the configurations described in FIGS. 29(A) to 29(F) and 30(A) to 30(D), As shown in Fig. 0(E), each terminal of the transistor is connected to a separate wire or a separate terminal. In the example of FIG. 30(E), the first terminal of the transistor 651 is connected to a The first terminal of the transistor 653 is connected to the wiring 681, and the second terminal of the transistor 654 is connected to the wiring 682. The first terminal of the transistor 652 is connected to the wiring 683, and the first terminal of the transistor 654 is connected to the wiring 683. The terminal is connected to the wiring 684. However, the present invention is not limited to this.

[0283] As another example, in the configurations described in FIGS. 29(A) to 29(F) and 30(A) to 30(E), As shown in FIG. 30(F), instead of a diode-connected transistor, a resistor It is possible to use other elements such as resistors or diodes. In this example, an element 631A is used instead of the transistor 631. The terminal of element 631A is connected to wiring 114, and the other terminal of element 631A is connected to output terminal 691. The element 631A is an element having a resistance component (for example, a resistor element or a diode). It has the function of

[0284] As another example, in the configurations described in FIGS. 29(A) to 29(F) and 30(A) to 30(F), As shown in FIG. 30(G), a transistor or an MIS capacitor is used as a capacitance element. In an example of FIG. 30G, a transistor 662 is used as the capacitor 662. The first and second terminals of the transistor 662A are connected to the output terminal 691. and the gate of transistor 662A is connected to input terminal 692.

[0285] (Fourth embodiment) In this embodiment, an example of a semiconductor device will be described. It can be used in the circuit 500 described in the second embodiment. The contents described in the third embodiment will be omitted. The present invention can be combined with the contents described in the first to third embodiments as appropriate.

[0286] First, an example of the circuit 500 will be described with reference to FIG. In the example, the circuit 500 includes a transistor 501_1, a transistor 501_2, and a transistor The transistor 501_1, the transistor 501_2, and the transistor 502 are connected to each other. The resistor 502 preferably has the same polarity as the transistors 101_1 and 101_2. , and N-channel type. However, this is not limited thereto. , transistor 501_2, and transistor 502 can be P-channel It should be noted that the circuit 500 does not need to include all of these transistors. It is possible to omit some of the transistors.

[0287] A first terminal of the transistor 501_1 is connected to the wiring 118. A second terminal of the transistor 501_1 is connected to a node n1. A gate of the transistor 501_1 is connected to a wiring 1. A first terminal of the transistor 501_2 is connected to the wiring 118. The second terminal of the transistor 501_2 is connected to the node n2. The gate of the transistor 502 is connected to a wiring 117. The first terminal of the transistor 502 is connected to a wiring 118. a second terminal of the transistor 502 connected to the wiring 111; The gate of 502 is connected to the wiring 117 .

[0288] The transistor 501_1 controls electrical continuity between the wiring 118 and the node n1, for example. Alternatively, the transistor 501_1 may apply the voltage of the wiring 118 to the node n1. For example, the wiring 118 has a function of controlling the timing of supplying a signal or voltage ( When a voltage such as a signal CK2 or a voltage V1 is supplied, the transistor 501_1 A function for controlling the timing of supplying a signal or voltage supplied to the line 118 to the node n1. Alternatively, the transistor 501_1 may be configured to apply a low-level signal or voltage V1 to the node. The transistor 501_1 has a function of controlling the timing of supplying the voltage to the node n1. is a function of controlling the timing at which the voltage of node n1 is decreased or maintained. As described above, the transistor 501_1 has a function as a switch. However, the present invention is not limited to this. It is not necessary to have all of the functions of the above.

[0289] The transistor 501_2 controls electrical continuity between the wiring 118 and the node n2, for example. Alternatively, the transistor 501_2 may apply the voltage of the wiring 118 to the node n2. For example, the wiring 118 has a function of controlling the timing of supplying a signal or voltage ( When a voltage such as a signal CK2 or a voltage V1 is supplied, the transistor 501_2 Controlling the timing at which a signal or voltage supplied to the line 118 is supplied to the node n2 Alternatively, the transistor 501_2 may be configured to output a low-level signal or a voltage V1. The transistor 501 has a function of controlling the timing of supplying the voltage to the node n2. 2 is a function for controlling the timing of decreasing or maintaining the voltage of node n2. As described above, the transistor 501_2 has a function as a switch. However, the transistor 501_2 is not limited to this. It is not necessary to have all of the above functions.

[0290] The transistor 502 has a function of controlling electrical continuity between the wiring 118 and the wiring 111, for example. Alternatively, the transistor 502 may supply the voltage of the wiring 118 to the wiring 111. For example, a signal or voltage (for example, a signal) is applied to the wiring 118. When a voltage (such as a signal CK2 or a voltage V1) is supplied to the line 118, the transistor 502 The signal or voltage to be supplied to the wiring 111 is controlled by the Alternatively, the transistor 502 supplies a low-level signal or a voltage V1 to the wiring 111. Alternatively, the transistor 502 has a function of controlling the timing of the voltage drop of the wiring 111. It has the function of controlling the timing of reducing or maintaining the pressure. Thus, the transistor 502 can function as a switch. However, the transistor 502 does not necessarily have all of the above functions. There is no.

[0291] Next, an example of the operation of the semiconductor device in FIG. The operation of the semiconductor device is similar to that of the semiconductor device shown in FIG. The semiconductor device of FIG. 31A is the same as that of FIG. It is not limited to the timing chart and can be controlled by various timings. do.

[0292] In the periods A1 to B1, D1 to E1, A2 to B2, and C2 to E2, FIG. 3 As shown in Figures 2(A) to (B), 33(A) to (C), and 34(B), the signal RE is , becomes low level. Then, the transistors 501_1 to 501_2 and the transistor 502 will be turned off.

[0293] In the periods C1 and C2, as shown in FIG. 32(C) and FIG. 34(A), the signal RE goes high. Then, the transistor 501_1 turns on, and the wiring 1 18 and the node n1 are electrically connected via the transistor 501_1. V1 is supplied to the node n1 from the wiring 118 through the transistor 501_1. The transistor 501_2 is turned on, so that the wiring 118 and the node n2 are connected to each other through the transistor 501_2. Therefore, the voltage V1 is supplied from the wiring 118 to the transistor 50. The transistor 502 is turned on, and the potential is supplied to the node n2 via the wiring 1_2. 11 and the wiring 118 are electrically connected via the transistor 502. Therefore, the voltage V1 is supplied from the wiring 118 to the wiring 111 through the transistor 502.

[0294] The channel width of the transistor 501_1 and the channel width of the transistor 501_2 are It is preferable that they are approximately equal. The change in voltage of the node n2 during the period T1 can be made approximately equal to the change in voltage of the node n2 during the period T2. By doing so, the waveform of the signal OUT can be made roughly the same. The channel length of the transistor 501_1 and the channel length of the transistor 501_2 are approximately equal. However, it is not limited to this.

[0295] The channel width of the transistor 501_1 and the channel width of the transistor 501_2 are , which is preferably smaller than the channel width of the transistor 502. The time during which the voltage of the node n1 decreases in period C1 and the time during which the voltage of the node n2 decreases in period C2 are Therefore, the low level signal CK1 can shorten the period during which the transistor 1 Since the signal OUT Alternatively, in the period C1 and the period C2, the fall time of the voltage The voltage V1 is supplied to the wiring 111 via the transistor 502, so that the rising edge of the signal OUT The fall time can be shortened.

[0296] The channel width of the transistor 501_1 and the channel width of the transistor 501_2 are It is preferably 100 μm to 3000 μm. More preferably, it is 300 μm to 20 It is more preferable that the thickness is 300 μm to 1000 μm. However, the present invention is not limited to this.

[0297] The channel width of the transistor 502 is preferably 500 μm to 5000 μm. It is more preferable that the thickness is 1000 μm to 30000 μm. Preferably, the thickness is 2000 μm to 3000 μm. However, it is not limited to this. do not have.

[0298] In the configuration described in FIG. 31(A), as shown in FIG. 31(B), transistor 5 a first terminal of the transistor 501_1, a first terminal of the transistor 501_2, and a first terminal of the transistor 502 The first terminals of the first and second terminals can be connected to separate wirings. The wiring 118 is divided into a plurality of wirings 118G to 118I. The first terminal of the transistor 501_1 is connected to the wiring 118G, and the third terminal of the transistor 501_2 is connected to the wiring 118G. The first terminal of the transistor 501 is connected to the wiring 118H, and the second terminal of the transistor 502 is connected to the wiring 118I. However, the wirings 118G to 118I are not limited to this. Therefore, the wirings 118G to 118I can have the same function as the wirings 118G to 118I. It is possible to input a voltage such as 1 and it can function as a signal line. However, the present invention is not limited to this. For example, the wirings 118G to 118I may carry separate signals or separate It is possible to supply a voltage of

[0299] In the configuration described in FIGS. 31(A) to 31(B), as shown in FIG. 31(C), The resistor 501_1 is connected at one terminal to the node n1 and at the other terminal to the wiring 118. Alternatively, the transistor 501_2, one terminal of which is connected to the node n2 and the other terminal of which is connected to the wiring 118. Alternatively, the transistor 502 may be replaced with a diode 501a_2. The diode is connected to the wiring 111 at one terminal and to the wiring 118 at the other terminal. However, this is not limiting. For example, in FIG. In the configuration described in 1(A) to 1(B), as shown in FIG. 31(D), the transistor 50 The gate terminal of the transistor 501_1 is connected to the node n1, Similarly, the transistor 501_2 can be configured as a diode. The gate terminal is connected to the node n2, so that the transistor 501_2 is a diode. Similarly, the gate terminal of transistor 502 can be By connecting to the wiring 111, the transistor 502 is diode-connected. It is possible to do this.

[0300] Here, one example of a semiconductor device in which the contents described in the first to fourth embodiments are combined is shown. Examples are shown in Figs. 35 and 36. However, the present invention is not limited to these examples, and other examples may be used in the first to fifth embodiments. The semiconductor device can be configured in various ways by combining the contents described in the fourth embodiment. be.

[0301] In the semiconductor device of FIG. 35, the configuration described with reference to FIG. 1A is used as the circuit 100. The circuit 300 has the configuration shown in FIG. 18(B). The circuit 400 has the configuration shown in FIG. The circuit 500 has the configuration shown in FIG. The circuit 600 has the configuration shown in FIG. The configuration described in Fig. 29(D) is used, but is not limited to this.

[0302] In the semiconductor device of FIG. 36, the configuration described with reference to FIG. 1A is used as the circuit 100. The circuit 300 has the configuration shown in FIG. 14(B). The circuit 400 has the configuration shown in FIG. The circuit 500 has the configuration shown in FIG. The circuit 600 has the configuration shown in FIG. 28(H). The circuit 624 has the following configuration: The configuration described in Fig. 30(A) is used, but is not limited to this.

[0303] As an example, the operation of the semiconductor device shown in FIG. 35 will be described. This will be explained using a timing chart.

[0304] During the period A1, the signal SP is at a high level. Therefore, the transistor 301_1 is turned on. Since the transistor 301_2 is turned on, the wiring 114 and the node n1 are brought into electrical continuity. Since the signal SEL1 is turned on, the wiring 114 and the node n2 are electrically connected. The transistor 302_1 then goes high, and the signal SEL2 goes low. is turned on and the transistor 302_2 is turned off, so that the wiring 118 and the node n2 As a result, the voltage at node n1 rises and the voltage at node n2 drops to a low value (e.g. Then, the transistor 101_1 is turned on, and the transistor Since 101_2 is turned off, the wiring 112 and the wiring 111 are brought into a conductive state. In circuit 600, transistor 642 and transistor 645 are turned on, Therefore, the wiring 118 and the transistor 646 are turned off. The gate of 644 is electrically connected, and the wiring 118 is electrically connected to the node j. As a result, the voltage at the gate of transistor 644 is at a low value (e.g., V1). Since the resistor 644 is turned off, the wiring 114 and the node j are not electrically connected. The voltage at node j is low (for example, V1), so that transistor 401_1, transistor At this time, the signal RE is at a low level. Then, the transistors 501_1 to 501_2 and the transistor 502 are turned off. Therefore, the wiring 118 and the node n1 are not electrically connected to each other. 2 is in a conductive state, and the wiring 118 and the wiring 111 are in a non-conductive state.

[0305] During the period B1, the signal SP goes low, and the transistor 301_1 is turned on. Therefore, the wiring 114 and the node n1 are not electrically connected to each other. is turned off, so that the wiring 114 and the node n2 are not electrically connected to each other. L1 remains at a high level, and the signal SEL2 remains at a low level. Transistor 302_1 remains on and transistor 302_2 remains off. Therefore, the wiring 118 and the node n2 remain in a conductive state. As a result, the voltage of the node n1 is The voltage at node n2 rises due to the bootstrap operation and remains at a low value (e.g., V1). Then, the transistor 101_1 remains on and the transistor 101_2 remains off, so that the wiring 112 and the wiring 111 remain in a conductive state. In the circuit 600, as in the period A1, the transistors 642 and 645 remains on, and transistor 643 and transistor 646 remain off. Thus, transistor 644 remains off and the voltage at node j remains low (e.g., V1 ) remains. Then, the transistor 401_1, the transistor 401_2, and the transistor The transistor 402 remains off. At this time, the signal RE remains at a low level. When this happens, the transistors 501_1 to 501_2 and the transistor 502 remain off. Therefore, the wiring 118 and the node n1 remain in a non-conducting state, and the wiring 118 and the node n 2 remains in a conductive state, and wiring 118 and wiring 111 remain in a non-conductive state.

[0306] During the period C1, the signal SP remains at a low level. Since the transistor 114 and the transistor 301_2 remain off, the wiring 114 and the node n1 are not connected to each other. The conductive state remains, and the wiring 114 and the node n2 remain in a non-conductive state. Therefore, the signal SEL1 remains at a high level and the signal SEL2 remains at a low level. When this occurs, transistor 302_1 remains on and transistor 302_2 remains off. Therefore, the wiring 118 and the node n2 remain in a conductive state. Then, the transistors 501_1 to 501_2 and the transistor 5 Since node n1 is turned on, the wiring 118 and node n2 are electrically connected. The node n2 is electrically connected, and the wiring 118 is electrically connected to the wiring 111. The voltage of node n1, the voltage of node n2, and the voltage of the wiring 111 decrease. The transistor 101_1 and the transistor 101_2 are turned off, so that the wiring 112 and the wiring 11 At this time, in the circuit 600, the transistor 642, the transistor The transistor 643, the transistor 645, and the transistor 646 are turned off. Voltage V2 is supplied to the gate of transistor 644 via transistor 641, so that The voltage at the gate of transistor 644 rises, so transistor 644 turns on. Therefore, the wiring 114 and the node j are electrically connected. The voltage at the gate rises, and transistor 401_1, transistor 401_2, and transistor 401_3 are turned on. Register 402 is turned on.

[0307] During periods D1 and E1, the signal SP remains at a low level. Since the transistor 301_1 and the transistor 301_2 remain off, the wiring 114 and the The wiring 114 and the node n2 remain in a non-conductive state. At this time, the signal SEL1 remains at a high level, and the signal SEL2 remains at a low level. Then, the transistor 302_1 remains on, and the transistor 302 Since node n_2 remains off, the wiring 118 and node n2 remain electrically connected. In this case, in the circuit 600, the transistor 642, the transistor 643, and the transistor 6 45 and transistor 646 remain off, so the voltage at node j remains high. Therefore, the transistor 401_1, the transistor 401_2, and the transistor 40 2 is turned on, the wiring 118 and the node n1 are in a conductive state, and the wiring 118 and the node n2 is electrically connected, and the wiring 118 and the wiring 111 are electrically connected. The voltages of node n1, node n2, and wiring 111 are maintained at a low value (for example, V1). Then, the transistors 101_1 and 101_2 are turned off, and the wiring 11 2 and the wiring 111 are in a non-conductive state.

[0308] During the period A2, the signal SP is at a high level. Therefore, the transistor 301_1 is turned on. Since the transistor 301_2 is turned on, the wiring 114 and the node n1 are brought into electrical continuity. Since the signal SEL1 is turned on, the wiring 114 and the node n2 are electrically connected. The signal SEL2 goes to a low level, and the signal SEL3 goes to a high level. is turned off and the transistor 302_2 is turned on, so that the wiring 118 and the node n1 As a result, the voltage at node n1 is maintained at a low value (for example, V1), and The voltage of node n2 rises. Then, transistor 101_1 turns off and transistor Since 101_2 is turned on, the wiring 112 and the wiring 111 are brought into a conductive state. In circuit 600, transistor 642 and transistor 645 are turned off, and transistor Therefore, the wiring 118 and the transistor 646 are turned on. The gate of 644 is electrically connected, and the wiring 118 is electrically connected to the node j. As a result, the voltage at the gate of transistor 644 is at a low value (e.g., V1). Since the resistor 644 is turned off, the wiring 114 and the node j are not electrically connected. The voltage at the gate of these transistors is low (for example, V1), so the transistors 401_1, the transistor 401_2, and the transistor 402 are turned off. Then, the signal RE goes low. The transistor 502 is turned off. Therefore, the wiring 118 and the node n1 are electrically connected. The line 118 and the node n2 are in a non-conductive state, and the line 118 and the line 111 are in a non-conductive state. become.

[0309] During a period B2, the signal SP goes low, and the transistor 301_1 is turned on. Therefore, the wiring 114 and the node n1 are not electrically connected to each other. is turned off, so that the wiring 114 and the node n2 are not electrically connected to each other. L1 remains at a low level, and the signal SEL2 remains at a high level. Transistor 302_1 remains off and transistor 302_2 remains on. Therefore, the wiring 118 and the node n1 remain in a conductive state. As a result, the voltage of the node n1 is The voltage at node n2 remains low (for example, below V1) and is bootstrapped. Then, transistor 101_1 remains off and transistor 10 Since 1_2 remains on, the wiring 112 and the wiring 111 remain in a conductive state. At this time, in the circuit 600, as in the period A1, the transistor 642 and the transistor 645 remains off, and transistor 643 and transistor 646 remain on. Therefore, the transistor 644 remains off, and the transistor 401_1, the transistor The voltage of the gate of the transistor 401_2 and the transistor 402 is set to a low value (for example, V1). Then, the transistor 401_1, the transistor 401_2, and the transistor The starter 402 remains off. At this time, the signal RE remains at a low level. Therefore, the transistors 501_1 to 501_2 and the transistor 502 remain off. Therefore, the wiring 118 and the node n1 remain in a conductive state, and the wiring 118 and the node n2 remain in a conductive state. The wiring 118 and the wiring 111 remain in a non-conductive state.

[0310] During the period C2, the signal SP remains at a low level. Since the transistor 114 and the transistor 301_2 remain off, the wiring 114 and the node n1 are not connected to each other. The conductive state remains, and the wiring 114 and the node n2 remain in a non-conductive state. Therefore, the signal SEL1 remains at a low level and the signal SEL2 remains at a high level. When this occurs, transistor 302_1 remains off and transistor 302_2 remains on. Therefore, the wiring 118 and the node n1 remain in a conductive state. Then, the transistors 501_1 to 501_2 and the transistor 5 Since node n1 is turned on, the wiring 118 and node n2 are electrically connected. The node n2 is electrically connected, and the wiring 118 is electrically connected to the wiring 111. The voltage of node n1, the voltage of node n2, and the voltage of the wiring 111 decrease. The transistor 101_1 and the transistor 101_2 are turned off, so that the wiring 112 and the wiring 11 At this time, in the circuit 600, the transistor 642, the transistor The transistor 643, the transistor 645, and the transistor 646 are turned off. Voltage V2 is supplied to the gate of transistor 644 via transistor 641, so that The voltage at the gate of transistor 644 rises, so transistor 644 turns on. Therefore, the wiring 114 and the node j are brought into electrical continuity. The voltages at the gates of the transistors 401_2 and 402 rise, The transistor 401_1, the transistor 401_2, and the transistor 402 are turned on.

[0311] During periods D2 and E2, the signal SP remains at a low level. Since the transistor 301_1 and the transistor 301_2 remain off, the wiring 114 and the The wiring 114 and the node n2 remain in a non-conductive state. At this time, the signal SEL1 remains at a low level, and the signal SEL2 becomes a high level. Then, the transistor 302_1 remains off, and the transistor 302 Since the node n1 remains on, the wiring 118 and the node n1 remain in a conductive state. In this case, in the circuit 600, the transistor 642, the transistor 643, and the transistor 6 45 and transistor 646 remain off, so the voltage at node j remains high. Therefore, the transistor 401_1, the transistor 401_2, and the transistor 40 2 is turned on, the wiring 118 and the node n1 are in a conductive state, and the wiring 118 and the node n2 is electrically connected, and the wiring 118 and the wiring 111 are electrically connected. The voltages of node n1, node n2, and wiring 111 are maintained at a low value (for example, V1). Then, the transistors 101_1 and 101_2 are turned off, and the wiring 11 2 and the wiring 111 are in a non-conductive state.

[0312] Furthermore, the operation of the semiconductor device shown in Fig. 35 was verified. The verification results are shown in Fig. 49. FIG. 49 is a diagram showing the results of verification of the semiconductor device of this embodiment. The test was carried out using a SPICE simulator. As a comparative example, the semiconductor device shown in FIG. The transistor 101_2, the transistor 301_2, the transistor 302_1, Transistor 302_2, transistor 401_2, transistor 501_2, transistor 6 43, the operation of a semiconductor device having a circuit configuration without transistor 646 was also verified. In addition, the verification was performed under the following conditions: high power supply voltage (also called Vdd) = 30V, Vss = 0V, clock frequency Frequency = 25 kHz (1 period = 40 μsec), mobility of each transistor = 1 cm 2 / Vs, The threshold voltage of each transistor was set to 5 V and the output capacitance was set to 50 pF.

[0313] FIG. 49(A) is a timing chart showing the verification results for the semiconductor device of the comparative example. As shown in 49(A), in the semiconductor device of the comparative example, one step is performed in both the period T1 and the period T2. The voltage of node n1 changes in accordance with the signal SP, which is a start pulse. The transistor 101_1 is turned on, and the wiring 112 and the wiring 111 are connected to the transistor 101_1, the signal CK1 is transmitted from the wiring 112 to the transistor 101_ 1 to the wiring 111.

[0314] FIG. 49(B) is a timing chart of the verification results for the semiconductor device shown in FIG. As shown in FIG. 49B, in the semiconductor device shown in FIG. 35, in the period T1, Therefore, the voltage of the node n1 changes, and the transistor 101_1 changes according to the voltage of the node n1. The wiring 112 and the wiring 111 are electrically connected via the transistor 101_1. The signal CK1 is supplied from the wiring 112 to the wiring 111 via the transistor 101_1. During the period T2, the voltage of the node n2 changes in accordance with the signal SP, and The transistor 101_2 is turned on, and the wiring 112 and the wiring 111 are connected to the transistor 101_2, the signal CK1 is transmitted from the wiring 112 to the transistor 101_ 49, the semiconductor device of this embodiment In the device, a different transistor is turned on in each period, and each transistor It can be seen that the number of times and the duration for which the motor is turned on can be reduced.

[0315] (Embodiment 5) In this embodiment, an example of a display device, an example of a shift register included in the display device, and a display An example of a pixel included in the device will be described. The semiconductor device according to the fourth aspect can be used. It is possible to refer to the device or the gate driver. The contents described in the first to fourth embodiments will not be explained here. The contents can be appropriately combined with the contents described in this embodiment.

[0316] First, an example of a display device will be described with reference to FIGS. 37(A) to 37(D). , a circuit 1001, a circuit 1002, a circuit 1003_1, a pixel portion 1004, and a terminal 1005 In the pixel portion 1004, a plurality of wirings are arranged extending from the circuit 1003_1. The plurality of wirings may function as gate signal lines or scanning lines. Alternatively, a plurality of wirings may be extended from the circuit 1002 to the pixel portion 1004. The plurality of wirings can function as video signal lines or data lines. A plurality of wirings extending from the circuit 1003_1 and the circuit 10 A plurality of pixels are arranged corresponding to a plurality of wirings extending from 02. However, the present invention is not limited to this. For example, various other wirings may be arranged in the pixel section 1004. The wiring can be used as a gate signal line, a data line, a power supply line, a capacitance line, or the like. It is possible to have the following functions.

[0317] The circuit 1001 supplies a signal, a voltage, a current, etc. to the circuit 1002 and the circuit 1003_1. Alternatively, the circuit 1001 has a function of supplying a signal to the circuit 1002 and the circuit 1003_1. In this way, the circuit 1001 has a function of controlling the controller, the control circuit, the timer, and the like. It can function as a timing generator, power supply circuit, regulator, etc. However, it is not limited to this.

[0318] The circuit 1002 has a function of supplying a video signal to the pixel portion 1004. The pixel portion 1004 has a function of controlling the luminance or transmittance of the pixel. In this way, the circuit 1002 may be used as a driver circuit, a source driver, a signal line driver circuit, or the like. It has all the functions, but is not limited to these.

[0319] The circuit 1003_1 has a function of supplying a scanning signal or a gate signal to the pixel portion 1004. Alternatively, the circuit 1003_1 has a function of selecting a pixel included in the pixel portion 1004. In this way, the circuit 1003_1 functions as a driver circuit, a gate driver, or a scanning line driver circuit. However, it is not limited to this.

[0320] As shown in FIG. 37A, the circuit 1001 and the circuit 1002 are The substrate 1006 is formed on a substrate (for example, a semiconductor substrate or an SOI substrate) other than the substrate 1006. Alternatively, the circuit 1003_1 may be formed on the same substrate 100 as the pixel portion 1004. The driving frequency of the circuit 1003_1 can be formed in the circuit 1001 or In many cases, the circuit is slower than the circuit 1002. Use of crystalline semiconductors, amorphous semiconductors, microcrystalline semiconductors, oxide semiconductors, organic semiconductors, etc. As a result, the display device can be made larger. However, it is not limited to this.

[0321] In the configuration described in FIG. 37(A), as shown in FIG. 37(B), the display device The circuit 1003_2 may have the same functions as the circuit 1003_1. For example, the circuit 1003_1 and the circuit 1003_2 have the same functions. This allows the signal to be supplied to the pixel portion 1004 at a low power consumption. This allows the display device to be made larger. For example, the circuit 1003_1 selects pixels in odd-numbered stages, and the circuit 1003_2 selects pixels in even-numbered stages. By doing so, the driving frequency can be reduced. This allows for a reduction in power consumption. Also, it is possible to achieve a layout per stage. Since the area of ​​the display can be increased, the display device can have high definition.

[0322] In the configuration described in FIGS. 37(A) to 37(B), as shown in FIG. 37(C), 1002 can be formed on the same substrate 1006 as the pixel portion 1004. Not limited to.

[0323] In the configuration described in FIGS. 37(A) to 37(C), as shown in FIG. 37(D), A part of 002 (for example, a circuit 1002a) is formed on the same substrate 1006 as the pixel portion 1004, Another part of the circuit 1002 (for example, the circuit 1002b) is formed on a substrate separate from the pixel portion 1004. In this case, the circuit 1002a may include a switch, a shift register, , and / or a circuit such as a selector that has a relatively low driving frequency can be used. However, this is not limited to this.

[0324] Next, an example of a pixel included in the pixel portion 1004 will be described with reference to FIG. The pixel 3020 includes a transistor 3021, a liquid crystal element 3022, and a capacitor 3023. A first terminal of the transistor 3021 is connected to a wiring 3031. The second terminal of the liquid crystal element 3021 is connected to one electrode of the liquid crystal element 3022 and one electrode of the capacitor element 3023. The gate of the transistor 3021 is connected to a wiring 3032. The other electrode of the capacitor 3022 is connected to an electrode 3034, and the other electrode of the capacitor 3023 is connected to an electrode 3034. It is connected to wiring 3033.

[0325] The wiring 3031 is, for example, a wiring from the circuit 1002 described in FIGS. 37(A) to (D) to a video A signal is input to the wiring 3031. Therefore, the wiring 3031 is a signal line, a video signal line, or a source signal line. The wiring 3032 can have a function as a 〜(D) from the circuit 1003_1 and / or the circuit 1003_2, the scanning signal, selection A signal or a gate signal is input to the wiring 3032. The wiring 3033 and the electrode 3034 can have a function as a port signal line. As an example, a constant voltage is supplied from a circuit 1001 described in FIGS. 37(A) to 37(D). Therefore, the wiring 3033 functions as a power supply line or a capacitor line. Alternatively, the electrode 3034 may function as a common electrode or a counter electrode. However, the present invention is not limited to this. For example, the wiring 3031 may be A charge voltage can be applied to the electrode 3034. In many cases, the voltage is approximately equal to the voltage applied to the signal line 3033. In this way, the voltage applied to the liquid crystal element 3022 can be controlled. This makes it possible to reduce the amplitude of the video signal and realize inversion driving. As another example, a signal can be input to electrode 3034. Frame inversion driving can be realized.

[0326] The transistor 3021 is electrically connected to the wiring 3031 and one electrode of the liquid crystal element 3022. Or, it has a function to control the timing of writing a video signal to the pixel. In this way, the transistor 3021 functions as a switch. The capacitor 3023 is connected to the voltage of one electrode of the liquid crystal element 3022 and the voltage of the wiring 3033. Alternatively, the voltage applied to the liquid crystal element 3022 can be kept constant. In this way, the capacitor 3023 functions as a storage capacitor. However, it is not limited to this.

[0327] Next, an example of a shift register will be described with reference to FIG. may be included in the circuit 1002, the circuit 1003_1, and / or the circuit 1003_2. It is possible.

[0328] The shift register 1100 includes a plurality of flip-flops 1101_1 to 1101_N. In the example of FIG. 38, flip-flops 1101_1 to 1101_1 are included. 1_N, the semiconductor device shown in FIG. 1(A) is used. However, it is not limited to this. As the flip-flops 1101_1 to 1101_N, for example, the flip-flops 1101_1 to 1101_N may be any of those described in the first to fifth embodiments. The semiconductor device or circuit described in Embodiment Mode 4 can be used.

[0329] The shift register 1100 includes wirings 1111_1 to 1111_N, wiring 1112, and wiring 1113. 13, wiring 1114, wiring 1115, wiring 1116_1, wiring 1116_2, wiring 111 7 and the wiring 1118. Then, the flip-flop 1101_i (i is 2 In any one of the above, the wiring 111, the wiring 112, the wiring 113, the wiring 114, the wiring 115, wiring 116_1, wiring 116_2, wiring 117, and wiring 118 are wirings. Line 1111_i, wiring 1112, wiring 1113, wiring 1114, wiring 1111_i-1, It is connected to the wiring 1116_1, wiring 1116_2, wiring 1111_i+1, and wiring 1118. However, the odd-numbered flip-flops and the even-numbered flip-flops are connected by wiring 11. 2 and the wiring 113 are often connected to the opposite ends. In this case, the wiring 115 is often connected to the wiring 1115. In the group 1101_N, the wiring 117 is often connected to the wiring 1117. , but is not limited to this.

[0330] For example, signals GOUT_1 to GOUT_N are output from the wirings 1111_1 to 1111_N, respectively. The signals GOUT_1 to GOUT_N are each a flip-flop. It is the output signal of the LSIs 1101_1 to 1101_N and has the same function as the signal OUT. Therefore, the wirings 1111_1 to 1111_N have the same function as the wiring 111. For example, a signal GCK1 is input to the wiring 1112, and a signal GCK2 is input to the wiring 1113. As an example, the signal GCK2 is input. 2 has the same function as the signal CK1 or the signal CK2. The line 1113 can have the same function as the line 112 or the line 113. For example, a voltage V2 is supplied to the wiring 1114. The wiring 1115 can have the same function as the wiring 114. For example, The signal GSP is input. The signal GSP has the same function as the signal SP. Therefore, the wiring 1115 can have the same function as the wiring 115. For example, a signal SEL1 is input to the wiring 1116_1, and for example, , the signal SEL2 is input. The wiring 1116_2 can have the same function as the wiring 116_2. For example, the signal GRE is input to the wiring 1117. The signal GRE has the same function as the signal RE. Therefore, the wiring 1117 is The wiring 1118 can have the same function as the wiring 117. For example, the wiring 1118 The voltage V1 is supplied to the wiring 1118. However, it is not limited to this, and various other wirings can be used. It is possible to input a signal, a different voltage, or a different current.

[0331] Next, the operation of the shift register in Figure 38 will be explained with reference to the timing chart in Figure 39. The timing chart of FIG. 39 shows, as an example, the signals GCK1 and GCK2. , signal GSP, signal GRE, signal SEL1, signal SEL2, signal GOUT_1~GOUT Indicates _N.

[0332] The flip-flop 1101_i (i is a natural number greater than or equal to 2) in the k-th frame (k is a natural number greater than or equal to 2) First, in the k-th frame, the signal SEL1 is high. Therefore, the signal OUT_i-1 becomes high level, and the signal SEL2 becomes low level. When the bell is reached, the flip-flop 1101_i starts its operation in the period A1. After that, when the signals GCK1 and GCK2 are inverted, the flip-flop 1101_i Therefore, the signal OUT_i becomes high level. The signal OUT_i is input to the flip-flop 1101_i+1. The process 1101_i+1 starts operation in the period A1. Then, the signals GCK1 and When the signal GCK2 is inverted again, the flip-flop 1101_i+1 outputs the Therefore, the signal OUT_i+1 becomes high level. Since 1 is input to flip-flop 1101_i, flip-flop 1101_i starts the operation in the period C1. Therefore, the signal GOUT_i becomes low level. After that, flip-flop 1 remains in the high level until signal SOUT1_i-1 goes high again. 101_i repeats the operation in the period D1 and the operation in the period E1. After that, the signal SEL1 goes low and the signal SEL2 goes high. The flip-flop 1101_i repeats the operation in the period D1 and the operation in the period E1. vinegar.

[0333] The operation of the flip-flop 1101_i in the (k+1)th frame will be described. In the k+1th frame, the signal SEL1 becomes low level and the signal SEL2 becomes high level. Therefore, when the signal OUT_i-1 goes high, the flip-flop 1101 _i starts operation in period A2. After that, the signals GCK1 and GCK2 When the signal is inverted, the flip-flop 1101_i starts operating in the period B2. As a result, the signal OUT_i goes high. 1_i+1, the flip-flop 1101_i+1 is After that, when the signals GCK1 and GCK2 are inverted again, the flip The flop 1101_i+1 starts operation in the period B2. i+1 goes high. The signal OUT_i-1 goes high to the input of the flip-flop 1101_i. As a result, the flip-flop 1101_i starts operating in the period C2. Then, the signal GOUT_i becomes low level. Until the high level is reached, the flip-flop 1101_i operates in accordance with the operation and expectation in the period D2. The operation in the period E2 is repeated. Alternatively, the signal SEL1 then becomes high level, Until the signal SEL2 becomes low level, the flip-flop 1101_i is in a state of being ... The operation in period E1 and the operation in period E2 are repeated.

[0334] In addition, in the flip-flop 1101_1, instead of the output signal of the previous stage flip-flop, Instead, the signal GSP is input via the wiring 1115. 1_1 indicates that when the signal GSP goes high, the operation in period A1 or the operation in period A2 is started. The operation begins.

[0335] In addition, in the flip-flop 1101_N, instead of the output signal of the next stage flip-flop, Therefore, the signal GRE is input via the wiring 1117. When this happens, the flip-flop 1101_N operates in the period C1 or in the period C2. The operation to remove the

[0336] (Sixth embodiment) In this embodiment, an example of a signal line driver circuit will be described. It can be referred to as a conductor device or a signal generating circuit.

[0337] An example of a signal line driver circuit will be described with reference to FIG. The circuit 2002 includes circuits 2002_1 to 2002_2. The circuit 2002_1 to 2002_N each include a transistor. The transistor 20 has a plurality of transistors 2003_1 to 2003_k. 03_1 to 2003_k are N-channel type, but are not limited to this. The transistors 2003_1 to 2003_k can be P-channel type. , and it is possible to use a CMOS type switch.

[0338] The connection relationship of the signal line driver circuit will be described using the circuit 2002_1 as an example. The first terminals of the terminals 2003_1 to 2003_k are connected to the wirings 2004_1 to 2004_k, respectively. The second terminals of the transistors 2003_1 to 2003_k are connected to the wiring S The gates of the transistors 2003_1 to 2003_k are connected to the wiring 20 Connected to 05_1.

[0339] The circuit 2001 outputs high-level signals to the wirings 2005_1 to 2005_N in order. Or, it has a function of selecting the circuits 2002_1 to 2002_N in order. In this way, the circuit 2001 functions as a shift register. The circuit 2001 is not limited to the wiring 2005_1 to 2005_N. Alternatively, the circuits 2002_1 to 2002_N can be configured to output various signals. In this way, the circuit 2001 functions as a decoder. It is possible to have a function.

[0340] The circuit 2002_1 controls the conduction state between the wirings 2004_1 to 2004_k and the wirings S1 to Sk. Alternatively, the circuit 2002_1 has a function of controlling the wirings 2004_1 to 2004_k. The circuit 2002_1 has a function of supplying the voltage to the wirings S1 to Sk. However, it is not limited to this. The circuits 2002_2 to 2002_N can have the same function as the circuit 2002_1. be.

[0341] The transistors 2003_1 to 2003_N are connected to the wirings 2004_1 to 2004_k, respectively. The transistor 2003 has a function of controlling electrical continuity with the wirings S1 to Sk. 1 to 2003_N respectively transmit the voltages of the wirings 2004_1 to 2004_k to the wirings S1 to Sk. For example, the transistor 2003_1 is connected to the wiring 2004_1. The transistor 2003_1 has a function of controlling the conduction state between the wiring S1 and the transistor 2003_2. The transistor 20 has a function of supplying the voltage of the transistor 2004_1 to the wiring S1. Each of 03_1 to 2003_N can function as a switch. However, it is not limited to this.

[0342] In many cases, signals are input to the wirings 2004_1 to 2004_k. The signal is often an analog signal corresponding to image information or an image signal. The analog signal corresponding to the image signal can function as a video signal. Therefore, the wirings 2004_1 to 2004_k can function as signal lines. However, the present invention is not limited to this. For example, depending on the pixel configuration, the wiring 2004_1 to 2 The signal input to 004_k can be a digital signal or an analog voltage. It can be an analog current.

[0343] Next, the operation of the signal line driver circuit of FIG. 46(A) will be explained with reference to the timing chart of FIG. 46(B). In FIG. 46(B), signals 2015_1 to 2015_N and signals An example of signals 2014_1 to 2014_k is shown below. Signals 2015_1 to 2015_N are respectively The signals 2014_1 to 2014_k are examples of output signals of the circuit 2001. 2004_1 to 2004_k. The operation period corresponds to one gate selection period in the display device. The period is divided into a period T0 and periods T1 to TN. This is the period during which a precharge voltage is simultaneously applied to the pixels belonging to the same pixel. Each of the periods T1 to TN belongs to a selected row. This is the period for writing video signals to the pixels to be recorded, and functions as a writing period. It is possible.

[0344] First, in a period T0, the circuit 2001 applies high-level Then, for example, in the circuit 2002_1, the transistor 20 03_1~2003_k will be turned on, so wiring 2004_1~2004_k and wiring S At this time, the wirings 2004_1 to 2004_k are connected to each other. Therefore, the precharge voltage Vp is supplied to the transistor 2003. The signals are output to the wirings S1 to Sk via the precharge signals _1 to 2003_k. The voltage Vp is written to the pixels in the selected row. The pixel is precharged.

[0345] During the period T1 to the period TN, the circuit 2001 transmits a high-level signal to the wirings 2005_1 to 2005_2. For example, in the period T1, the circuit 2001 outputs a high level Then, the signal of the line 2005_1 is output to the wiring 2005_2. _k is turned on, so that the wiring 2004_1 to 2004_k and the wiring S1 to Sk are in a conductive state. At this time, the wiring 2004_1 to 2004_k are connected to Data(S1) to Data(S2). a(Sk) is input. Data(S1) to Data(Sk) are the transistors Among the pixels belonging to the selected row via 2003_1 to 2003_k, the pixels in the 1st to kth columns In this way, during the periods T1 to TN, the pixels belonging to the selected row are written. First, the video signal is written in k columns in order.

[0346] As described above, the video signal is written to the pixels in multiple columns. Therefore, the number of connections to external circuits can be reduced. This allows for improved yield, improved reliability, reduced component count, and / or reduced costs. Alternatively, the video signal can be written to the pixels in multiple columns at a time. This allows the write time to be extended, preventing insufficient writing of video signals. Therefore, the display quality can be improved.

[0347] By increasing k, the number of connections to external circuits can be reduced. If k is too large, the time required to write to the pixel becomes short. Therefore, it is preferable that k≦6. It is preferable that k≦3. It is further preferable that k=2. However, the present invention is not limited to this.

[0348] In particular, when the number of color elements of a pixel is n (n is a natural number), k=n or k=n×d (d is a natural number). For example, if the color components of a pixel are red (R), green (G), and blue (B), When the number of divisions is three, it is preferable that k=3 or k=3×d. For example, a pixel may have m (m is a natural number) sub-pixels (hereinafter referred to as sub-pixels or When the pixel is divided into subpixels, it is preferable that k=m or k=m×d. For example, if a pixel is divided into two sub-pixels, then k=2 is preferred, or When the number of color elements of a pixel is n, it is preferable that k=m×n or k=m×n×d. However, it is not limited to this.

[0349] As shown in FIG. 46(C), the driving frequency of the circuit 2001 and the driving frequency of the circuit 2002 are Since the frequency is often slow, the circuit 2001 and the circuit 2002 are connected to the pixel portion 2007. In this way, the substrate on which the pixel portion is formed and the substrate on which the external circuit is formed can be formed on the same substrate. The number of connections to the circuit can be reduced, improving yield, reliability, and reducing the number of parts. In particular, the signal line driver circuit 2006 and the pixel portion 2 By forming it on the same substrate as 007, the number of connections to external circuits can be further reduced. However, the present invention is not limited to this. For example, as shown in FIG. 46(D), The circuit 2001 is formed on a substrate different from that of the pixel portion 2007, and the circuit 2002 is formed on the same substrate as that of the pixel portion 2007. In this case, the substrate on which the pixel part is formed and the external circuit This reduces the number of connections, improving yield, reliability, reducing the number of parts, Alternatively, it is possible to reduce costs. Since there is less circuitry, the frame can be made smaller.

[0350] The circuit 2001 may be a semiconductor device or a shift circuit described in any one of the first to fifth embodiments. This allows the use of a resistor to suppress the deterioration of the transistor. Since the voltage drop can be controlled, the life of the signal line driver circuit can be extended.

[0351] (Embodiment 7) In this embodiment, an example of a protection circuit will be described.

[0352] First, an example of a protection circuit will be described with reference to FIG. , a semiconductor device (for example, a transistor, a capacitor, a circuit, etc.) connected to the wiring 3011, It is provided to prevent damage to the circuitry due to ESD (electrostatic discharge). The circuit 3000 includes a transistor 3001 and a transistor 3002. The transistor 3001 and the transistor 3002 are often N-channel types. However, it is not limited to this and may be a P-channel type.

[0353] A first terminal of the transistor 3001 is connected to a wiring 3012. The second terminal of the transistor 3001 is connected to a wiring 3011. A first terminal of the transistor 3002 is connected to a wiring 3013. A second terminal of the transistor 3002 is connected to a wiring 3011. The gate is connected to a wiring 3013 .

[0354] The wiring 3011 is connected to, for example, a signal (for example, a scanning signal, a video signal, a clock signal, Start signal, reset signal, or select signal), or voltage (negative power supply voltage, ground A voltage, a positive power supply voltage, etc.) can be supplied to the wiring 3012. A positive power supply voltage (Vdd) is supplied to the wiring 3013. The power supply voltage (Vss) or ground voltage is supplied. However, this is not limited to this. It will not be done.

[0355] If the voltage of the wiring 3011 is between Vss and Vdd, the transistor 3001 and the The transistor 3002 is turned off. is supplied to the semiconductor device connected to the wiring 3011. However, the influence of static electricity, etc. Thus, a voltage higher than the power supply voltage or a voltage lower than the power supply voltage is supplied to the wiring 3011. In addition, a voltage higher than this power supply voltage or a voltage lower than this power supply voltage may be used. This may destroy the semiconductor device connected to the wiring 3011. In order to prevent electrostatic breakdown of semiconductor devices, a voltage higher than the power supply voltage is applied to the wiring 3011. When the potential is supplied, the transistor 3001 is turned on. Then, the charge on the wiring 3011 is The voltage of the wiring 3011 is reduced because the voltage of the wiring 3012 is transferred via the transistor 3001. On the other hand, when a voltage lower than the power supply voltage is supplied to the wiring 3011, the transistor Then, the charge in the wiring 3011 is transferred to the transistor 3002. The voltage of the wire 3011 rises. Electrostatic damage to semiconductor devices connected to the semiconductor device 1 can be prevented.

[0356] In the configuration shown in FIG. 47(A), as shown in FIG. 47(B), transistor 3 002 can be omitted. Alternatively, in the configuration described in FIG. 47(A), As shown in FIG. 7(C), the transistor 3001 can be omitted. This is not limited to:

[0357] In the configuration described in FIGS. 47(A) to 47(C), as shown in FIG. 47(D), the wiring 3 A transistor can be connected in series between the gate electrode 3011 and the wiring 3012. In this case, a transistor can be connected in series between the wiring 3011 and the wiring 3013. A first terminal of the transistor 3003 is connected to a wiring 3012. The second terminal of transistor 3003 is connected to the first terminal of transistor 3001, and the second terminal of transistor 3003 is connected to the first terminal of transistor 3002. The gate of transistor 3003 is connected to the first terminal of transistor 3001. A first terminal of the transistor 3004 is connected to a wiring 3013, and a second terminal of the transistor 3004 is connected to a wiring 3014. The first terminal of the transistor 3002 is connected to the gate of the transistor 3004. 3013. However, this is not limiting. For example, as shown in FIG. The gate of the transistor 3001 and the gate of the transistor 3003 are connected to each other. Alternatively, the gate of the transistor 3002 and the gate of the transistor 3004 may be connected in series. can be connected to.

[0358] In the configuration described in FIGS. 47(A) to 47(E), as shown in FIG. 47(F), the wiring 3 A transistor can be connected in parallel between the transistor 011 and the wiring 3012. Alternatively, a transistor can be connected in parallel between the wiring 3011 and the wiring 3013. A first terminal of the transistor 3003 is connected to a wiring 3012. The second terminal of the transistor 3003 is connected to the wiring 3011. The first terminal of the transistor 3004 is connected to a wiring 3011. The second terminal of the transistor 3004 is connected to a wiring 3013. The second terminal of the transistor 3004 is connected to the wiring 3011. The gate of 004 ​​is connected to the wiring 3013 .

[0359] In the configurations described in Figures 47(A) to 47(F), as shown in Figure 47(G), Between the gate and the first terminal of the transistor 3001, a capacitance element 3005 and a resistance element 3006 are provided. Alternatively, the gate and the first terminal of the transistor 3002 may be connected in parallel. A capacitance element 3007 and a resistance element 3008 can be connected in parallel between the This prevents the protection circuit 3000 itself from being damaged or deteriorated. For example, when a voltage higher than the power supply voltage is supplied to the wiring 3011, the transistor 30 Therefore, the Vgs of the wiring 3001 becomes large, and the transistor 3001 turns on. However, the voltage between the gate and the second terminal of transistor 3001 is Since a large voltage is applied, the transistor 3001 may be destroyed or deteriorated. To prevent this, the voltage at the gate of transistor 3001 is increased to To achieve this, a capacitance element 3005 is used. When transistor 3001 is turned on, the first terminal of transistor 3001 is momentarily Then, the capacitance of the capacitor 3005 increases. The gate voltage rises. This reduces the Vgs of the transistor 3001. This can prevent the transistor 3001 from being damaged or deteriorated. Similarly, when a voltage lower than the power supply voltage is supplied to the wiring 3011, the transistor The voltage at the first terminal of the capacitor 3002 is instantaneously decreased. The coupling reduces the voltage at the gate of transistor 3002. Since the Vgs of the transistor 3002 can be reduced, the breakdown or deterioration of the transistor 3002 can be prevented. This can suppress the degradation.

[0360] The protection circuits shown in Figures 47(A) to 47(G) can be used in a variety of places. FIG. 48A shows an example of a configuration in which a protection circuit is provided on a gate signal line. In this case, the wiring 3012 and the wiring 3013 are connected to the gate driver 3100. This allows the number of power supplies and As an example, Figure 48(B) shows a case where an external FPC or other This shows a configuration in which a protection circuit is provided at a terminal to which a signal or voltage is supplied from a wiring. The line 3012 and the wiring 3013 can be connected to any of the external terminals. For example, the wire 3012 is connected to the terminal 3101a, and the wire 3013 is connected to the terminal 3101b. In this case, in the protection circuit provided at the terminal 3101a, Similarly, the protection circuit provided at the terminal 3101b can be omitted. In this case, the transistor 3002 can be omitted. The number of transistors can be reduced, which reduces the layout area. .

[0361] (Embodiment 8) In this embodiment, examples of the structure of a transistor are shown in FIGS. ) will be referred to for explanation.

[0362] FIG. 40A shows an example of a structure of a top-gate transistor or a structure of a display device. FIG. 40B shows an example of a structure of a bottom-gate transistor. 40(C) is a diagram showing an example of the structure of a display device manufactured using a semiconductor substrate. 1A and 1B are diagrams illustrating an example of a structure of a transistor.

[0363] An example of a transistor in FIG. 40(A) is a transistor including an insulating layer 5261 formed over a substrate 5260 and a , formed on the insulating layer 5261, and regions 5262a, 5262b, 5262c, A semiconductor layer 5262 having regions 5262d and 5262e, and a semiconductor layer 5262 covering the semiconductor layer 5262 The insulating layer 5263 is formed as follows: a conductive layer 5264 formed on the insulating layer 5263 and the conductive layer 5264 and having an opening; and a conductive layer 5265 formed on the insulating layer 5265 and in the opening of the insulating layer 5265. and an electrically conductive layer 5266.

[0364] An example of the transistor in FIG. 40B includes a substrate 5300 and a A conductive layer 5301, an insulating layer 5302 formed to cover the conductive layer 5301, and the conductive layer 5302 301 and a semiconductor layer 5303a formed on the insulating layer 5302, and a semiconductor layer 5303b formed on the insulating layer 5302; A conductive layer 5304 is formed on the insulating layer 5302 and a conductive layer 5304 is formed on the insulating layer 5302. an insulating layer 5305 having an opening; and a conductive layer 5306 formed on the insulating film 5304.

[0365] An example of the transistor in FIG. 40C is a semiconductor substrate having a region 5353 and a region 5355. a plate 5352, an insulating layer 5356 formed on the semiconductor substrate 5352, and a semiconductor substrate 53 An insulating layer 5354 is formed on the insulating layer 5356, and a conductive layer 535 is formed on the insulating layer 5356. 7, and an insulating layer 5354, an insulating layer 5356, and a conductive layer 5357 are formed on the insulating layer 5354, the insulating layer 5356, and the conductive layer 5357, and an opening is formed. and an insulating layer 5358 having a conductive film formed on the insulating layer 5358 and in the opening of the insulating layer 5358. The region 5350 and the region 5351 each have a conductive layer 5359. A zygote is created.

[0366] Note that when a display device is configured using the transistor of this embodiment, for example, As shown in FIG. 1(A), an opening 5266 is formed on the conductive layer 5266 and on the insulating layer 5265. an insulating layer 5267 having a first insulating layer 5268 and a second insulating layer 5269 formed on the insulating layer 5267 and in the opening of the insulating layer 5267; a conductive layer 5268 having an opening formed on the insulating layer 5267 and the conductive layer 5268; and an insulating layer 5269 having a conductive film formed on the insulating layer 5269 and in the opening of the insulating layer 5269. A light-emitting layer 5270 and a conductive layer 52 formed on the insulating layer 5269 and on the light-emitting layer 5270. 71 and can be formed.

[0367] 40(B), a conductive layer 5306 is disposed on the insulating layer 5305. and a conductive layer 5308 formed on the liquid crystal layer 5307. It is possible.

[0368] The insulating layer 5261 can function as a base film. The insulating layer 5263, the insulating layer 5302, and the insulating layer 5303 function as an isolation layer (for example, a field oxide film). The insulating layer 5356 can function as a gate insulating film. The insulating layer 5301 and the conductive layer 5357 can function as gate electrodes. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 are interlayer films or flat films. The conductive layer 5266, the conductive layer 5304, and the conductive layer 5305 can function as a conductive film. 359 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The conductive layer 5268 and the conductive layer 5306 can be used as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a partition wall. The conductive layer 5271 and the conductive layer 5308 can function as a counter electrode, a common electrode, or the like. It is possible to do this.

[0369] Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, a semiconductor substrate ( For example, silicon substrates, SOI substrates, plastic substrates, metal substrates, stainless steel substrates, Substrate with stainless steel foil, tungsten substrate, tungsten foil Examples of glass substrates include barium borosilicate glass substrates. Examples of flexible substrates include glass and aluminoborosilicate glass. Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone Plastics such as polyethersulfone (PES) or flexible synthetic resins such as acrylic Other examples include laminated films (polypropylene, polyester, vinyl, poly vinyl fluoride, vinyl chloride, etc.), paper containing fibrous materials, base film (polyester , polyamide, polyimide, inorganic vapor deposition film, paper, etc.

[0370] The semiconductor substrate 5352 is, for example, a single-crystal Si substrate having n-type or p-type conductivity. The region 5353 is, for example, a semiconductor substrate 5352 having impurities. For example, if the semiconductor substrate 5352 is a p-type When the region 5353 has a conductivity type of n-type, the region 5353 functions as an n-well. On the other hand, if the semiconductor substrate 5352 has n-type conductivity, the region 5353 has p-type conductivity. The region 5355 has a conductivity type and functions as a p-well. It is a region doped in the plate 5352 and functions as a source region or a drain region. In the semiconductor substrate 5352, an LDD region can be formed.

[0371] Examples of the insulating layer 5261 include silicon oxide (SiOx), silicon nitride (SiNx), and oxynitride. Silicon nitride (SiOxNy) (x>y>0), silicon nitride oxide (SiNxOy) (x>y>0) The insulating layer 5261 may be a film containing oxygen or nitrogen, such as a film containing oxygen or nitrogen, or a laminate structure of these. In one example of a two-layer structure, a silicon nitride film is provided as the first insulating layer, A silicon oxide film can be provided as the second insulating layer. The insulating layer 5261 has a three-layer structure. For example, a silicon oxide film is provided as the first insulating layer, and a silicon dioxide film is provided as the second insulating layer. It is possible to provide a silicon nitride film as an insulating layer and a silicon oxide film as a third insulating layer. do.

[0372] An example of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b is a non-single layer. Crystalline semiconductors (e.g., amorphous silicon, polycrystalline silicon, microcrystalline silicon) semiconductors, single crystal semiconductors, oxide semiconductors (e.g., ZnO, InGaZnO, IZO, I TO, SnO, TiO, AZTO), compound semiconductors (e.g. SiGe, GaAs), Examples include organic semiconductors and carbon nanotubes.

[0373] For example, the region 5262a is an intrinsic semiconductor layer 5262 to which no impurities are added. However, when impurities are added to the region 5262a, the region 5262a functions as a channel region. The impurity added to the region 5262a can be added to the region 5262b, the region 5262c, and the region 5262d. 2c, region 5262d, or region 5262e. It is preferable that the region 5262b and the region 5262d are not included in the region 5262c or the region 5262e. It is a region where impurities are added at a lower concentration than that of the LDD (Lightly Doped Diode). However, the area 5262b and the area 5262 The region 5262c and the region 5262e are regions containing highly concentrated impurities. The material is added to the semiconductor layer 5262 and functions as a source region or a drain region. do.

[0374] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. It has n-type conductivity.

[0375] When an oxide semiconductor or a compound semiconductor is used for the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0376] An example of the insulating layer 5263, the insulating layer 5302, and the insulating layer 5356 is silicon oxide (Si Ox), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y>0), nitriding acid a film containing oxygen or nitrogen, such as silicon carbide (SiNxOy) (x>y>0), or There are also laminated structures.

[0377] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301, A conductive layer 5304, a conductive layer 5306, a conductive layer 5308, a conductive layer 5357, and a conductive layer 535 The conductive film 9 can have a single layer structure or a multilayer structure and is formed using a conductive film. Examples include aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum ( Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), Platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (C o), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon (C ), scandium (Sc), zinc (Zn), gallium (Ga), indium (In), tin (Sn), zirconium (Zr), and cesium (Cs) It can be a film of a single element, or a compound containing one or more elements selected from a group. The single film or compound may contain phosphorus (P), boron (B), arsenic (As), and / or It is possible for the compound to contain oxygen (O). Alloys containing one or more elements selected from the elements (e.g., indium tin oxide (I TO), indium zinc oxide (IZO), indium tin oxide with silicon oxide (ITS O), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum Aluminum neodymium (Al-Nd), aluminum tungsten (Al-W), aluminum di Zr-Al, Al-Titanium (Al-Ti), and Aluminum Cesium (Al-Cs), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb), Molybdenum-tungsten (Mo-W), molybdenum-tantalum (Mo-Ta) and other alloy materials ), a compound of nitrogen with one or more elements selected from the above elements (e.g. , titanium nitride, tantalum nitride, molybdenum nitride, etc.), or a combination of the above elements Compounds of silicon with one or more elements selected from the group consisting of tungsten and silicon Silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum Other examples include carbon nanotubes, Nanotube materials include organic nanotubes, inorganic nanotubes, and metallic nanotubes. do.

[0378] Insulating layer 5265, insulating layer 5267, insulating layer 5269, insulating layer 5305, and insulating layer 535 Examples of the insulating layer 8 include a single-layer insulating layer and a laminated structure of these layers. The material may be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (Si Oxygen or silicon nitride (OxNy) (x>y>0), silicon oxynitride (SiNxOy) (x>y>0) or a film containing nitrogen, a film containing carbon such as DLC (diamond-like carbon), or oxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclohexyl Examples of the material include organic materials such as hydroxybenzoates and acrylics.

[0379] Note that an insulating layer functioning as an alignment film is provided over the insulating layer 5305 and the conductive layer 5306. It is possible to form an insulating layer or the like that functions as a protrusion.

[0380] Note that a color filter, a black matrix, or a protrusion may be formed on the conductive layer 5308. An insulating layer or the like that functions as an alignment film can be formed under the conductive layer 5308. It is possible to form an insulating layer that acts as a barrier.

[0381] The transistor of this embodiment can be applied to those described in the first to seventh embodiments. In particular, in FIG. 40(B), the semiconductor layer may be made of an amorphous semiconductor, a microcrystalline When a semiconductor, organic semiconductor, or oxide semiconductor is used, the transistor may deteriorate. Therefore, the transistor of this embodiment can be used in a semiconductor device, a shift register, a display, or the like. When used in display devices or various circuits, their lifespan is shortened. In the first to seventh embodiments, the deterioration of the transistor can be suppressed. Therefore, the transistor of this embodiment is not limited to those described in the first to seventh embodiments. By applying it, their lifespan can be extended.

[0382] (Embodiment 9) In this embodiment, an example of a cross-sectional structure of a display device will be described with reference to FIGS. The following description will be made with reference to C) of the liquid crystal display device as an example.

[0383] FIG. 41A is an example of a top view of a display device. A pixel portion 5393 is formed. An example of the driver circuit 5392 is a scanning line driver circuit. The pixel portion 5393 has pixels, and the pixels are connected to a driver circuit 53. For example, in the case of a liquid crystal display device, the output of the driver circuit 5392 The signal sets the voltage applied to the liquid crystal element of the pixel.

[0384] FIG. 41(B) shows an example of the cross section AB of FIG. 41(A). 5400, a conductive layer 5401 formed on the substrate 5400, and An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. and a semiconductor layer 5403b formed on the semiconductor layer 5403a. a conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402; an insulating layer 5405 having an opening formed on the edge layer 5402 and on the conductive layer 5404; a conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405; an insulating layer 5408 disposed on the layer 5405 and on the conductive layer 5406; a liquid crystal layer 5407 formed on the insulating layer 5408; 5 shows a conductive layer 5409 formed over the conductive layer 5409 and a substrate 5410 formed over the conductive layer 5409 .

[0385] The conductive layer 5401 can function as a gate electrode. The conductive layer 5404 can function as a gate insulating film. The insulating layer 5405 can function as an electrode, an electrode of a capacitor, or the like. The conductive layer 5406 can function as a wiring. The insulating layer 5408 can function as a sealant. The conductive layer 5409 can function as a counter electrode or a common electrode.

[0386] Here, a parasitic capacitance may occur between the driver circuit 5392 and the conductive layer 5409. As a result, the output signal of the driver circuit 5392 or the voltage of each node may be rounded or delayed. Or, the power consumption will increase. However, as shown in Figure 41(B), As shown in FIG. 5B, an insulating layer 5408 that can function as a sealant is formed on the driver circuit 5392. By forming the conductive layer 5409, the parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 is reduced. This is because the dielectric constant of the sealing material is lower than that of the liquid crystal layer. Therefore, the output signal of the driving circuit 5392 or the voltage of each node is Alternatively, the power consumption of the driver circuit 5392 can be reduced. This can be done.

[0387] As shown in FIG. 41C, a film that functions as a sealant is provided on a part of the driver circuit 5392. In this case, an insulating layer 5408 can be formed. The parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 can be reduced. Therefore, it is possible to reduce the distortion or delay of the output signal of the driver circuit 5392 or the voltage of each node. However, it is not limited to this, and a film that functions as a sealant can be provided on the driver circuit 5392. It is possible that the insulating layer 5408 is not formed.

[0388] In the above, an example of the cross-sectional structure of the display device has been described in the present embodiment. It is possible to combine the above with the above described in the first to seventh embodiments. For example, a semiconductor layer of a transistor may be formed of an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor. When using a nitride semiconductor, the channel width of the transistor often becomes large. However, if the parasitic capacitance of the driving circuit can be reduced as in this embodiment, the capacitance of the transistor This allows the width of the panel to be reduced, thereby reducing the layout area. This allows the frame of the display device to be narrowed, or allows the display device to have high definition. Cut.

[0389] (Embodiment 10) In this embodiment, an example of a manufacturing process of a transistor and a capacitor will be described. A manufacturing process in the case where an oxide semiconductor is used for the layer will be described.

[0390] Referring to FIGS. 42A to 42C, an example of a manufacturing process of a transistor and a capacitor will be described. 42A to 42C show a transistor 5441 and a capacitor 5442. The transistor 5441 is an example of an inverted staggered thin film transistor. and a wiring is provided on the oxide semiconductor layer via a source electrode or a drain electrode. This is an example of a transistor.

[0391] First, a first conductive layer is formed on the entire surface of the substrate 5420 by sputtering. A resist mask formed by a photolithography process using a first photomask is used. Then, the first conductive layer is selectively etched to form a conductive layer 5421 and a conductive layer 5422. The conductive layer 5421 can function as a gate electrode, and the conductive layer 542 2 can function as one electrode of a capacitor element. The conductive layers 5421 and 5422 are used as wirings, gate electrodes, or electrodes of a capacitor. After this, the resist mask is removed.

[0392] Next, the insulating layer 5423 is formed on the conductive layer 542 by using a plasma CVD method or a sputtering method. The insulating layer 5423 is formed on the entire surface of the substrate 5420 via the gate electrode 5421 and the conductive layer 5422. The conductive layer 5421 and the conductive layer 5422 can function as an insulating layer. The insulating layer 5423 is formed in such a manner that its thickness is 50 nm to 250 nm. many.

[0393] Next, a resist mask formed by a photolithography process using a second photomask 5423 to selectively etch the insulating layer 5423 to form a contact that reaches the conductive layer 5421. A hole 5424 is formed. After this, the resist mask is removed. However, the present invention is not limited to this. Therefore, the contact hole 5424 can be omitted. After forming the contact hole 5424, the contact hole 5424 can be formed. The cross section of this corresponds to FIG. 42(A).

[0394] Next, an oxide semiconductor layer is formed on the entire surface by sputtering. The oxide semiconductor layer is formed by sputtering, and a buffer layer (e.g., For example + The oxide semiconductor layer can be formed with a thickness of 5 nm to 2 00nm in most cases.

[0395] Next, a resist mask formed by a photolithography process using a third photomask The oxide semiconductor layer is selectively etched using the resist mask. do.

[0396] Next, a second conductive layer is formed on the entire surface by sputtering. The second conductive layer is selectively formed using a resist mask formed by a photolithography process. The conductive layer 5429, the conductive layer 5430, and the conductive layer 5431 are formed by etching the conductive layer 5429, the conductive layer 5430, and the conductive layer 5431. The conductive layer 5429 is connected to the conductive layer 5421 through a contact hole 5424. The conductive layer 5429 and the conductive layer 5430 function as a source electrode and a drain electrode. The conductive layer 5431 can function as the other electrode of the capacitor. However, the conductive layer 5429, the conductive layer 5430, and the conductive layer 54 31 is a part that functions as a wiring, a source or drain electrode, or an electrode of a capacitor element. The cross section at this stage corresponds to Figure 42(B).

[0397] Next, a heat treatment is performed at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere. The treatment causes rearrangement at the atomic level in the oxide semiconductor layer 5425. The stress that inhibits the movement of carriers is released by this treatment (including photo-annealing). The timing of the heat treatment is not limited, and various timings can be used as long as it is after the formation of the oxide semiconductor. This can be done in a group.

[0398] Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 may have a single-layer structure. For example, the insulating layer 5432 may be an organic insulating layer. When using the method described above, a composition that is a material for the organic insulating layer is applied, and the composition is then heated under an air atmosphere or a nitrogen atmosphere. Then, a heat treatment is performed at 200 to 600°C under an oxidized condition to form an organic insulating layer. By forming an organic insulating layer in contact with the compound semiconductor layer 5425, a highly reliable thin film transistor can be obtained. When an organic insulating layer is used as the insulating layer 5432, A silicon nitride film or a silicon oxide film can be provided under the organic insulating layer.

[0399] Next, a third conductive layer is formed on the entire surface. Next, a photolithography process is performed using a fifth photomask. The third conductive layer is selectively etched using the resist mask formed by the etching process. A conductive layer 5433 and a conductive layer 5434 are formed. A cross-sectional view of the process up to this stage is shown in FIG. The conductive layer 5433 and the conductive layer 5434 correspond to a wiring, a pixel electrode, a reflective electrode, a transparent electrode, and the like. The conductive layer 5434 can function as a photo-transistor or an electrode of a capacitor. Since the conductive layer 5422 is connected to the conductive layer 5422, the conductive layer 5422 can function as an electrode of the capacitor 5442. However, the present invention is not limited to this, and the conductive layer formed using the first conductive layer and the second conductive layer may be used. For example, the c...

Claims

1. having first to tenth transistors; one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a first wiring; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a first signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the power supply line; a gate of the sixth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the eighth transistor is always electrically connected to the first signal line; a gate of the eighth transistor is always electrically connected to the first signal line; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the ninth transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the first wiring; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, when the first wiring is in a conductive state with the first transistor, the sixth transistor, and the seventh transistor via at least a channel formation region of the third transistor, a potential having a value that turns on the first transistor, the sixth transistor, and the seventh transistor is input to a gate of the first transistor, the gate of the sixth transistor, and the gate of the seventh transistor via at least a channel formation region of the third transistor; When the first wiring is in a conductive state with the ninth transistor through at least a channel formation region of the tenth transistor, a potential having a value that turns on the ninth transistor is input to a gate of the ninth transistor through at least a channel formation region of the tenth transistor.

2. having first to tenth transistors; one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a first wiring; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a first signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the power supply line; a gate of the sixth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the eighth transistor is always electrically connected to the first signal line; a gate of the eighth transistor is always electrically connected to the first signal line; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the ninth transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the first wiring; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, when the first wiring is in a conductive state with the first transistor, the sixth transistor, and the seventh transistor via at least a channel formation region of the third transistor, a potential having a value that turns on the first transistor, the sixth transistor, and the seventh transistor is input to a gate of the first transistor, the gate of the sixth transistor, and the gate of the seventh transistor via at least a channel formation region of the third transistor; when the first wiring is in a conductive state with the ninth transistor through at least a channel formation region of the tenth transistor, a potential having a value that turns on the ninth transistor is input to a gate of the ninth transistor through at least a channel formation region of the tenth transistor; the W / L (W is a channel width, L is a channel length) of the first transistor is larger than the W / L of the second transistor; the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the first transistor is greater than the W / L of the fifth transistor; the W / L of the first transistor is greater than the W / L of the sixth transistor; the W / L of the first transistor is greater than the W / L of the seventh transistor; the W / L of the first transistor is greater than the W / L of the eighth transistor; the W / L of the first transistor is greater than the W / L of the ninth transistor; A semiconductor device in which the W / L of the first transistor is larger than the W / L of the tenth transistor.

3. having first to twelfth transistors, one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a first wiring; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a first signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the power supply line; a gate of the sixth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the eighth transistor is always electrically connected to the first signal line; a gate of the eighth transistor is always electrically connected to the first signal line; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the ninth transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the first wiring; one of the source and the drain of the eleventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the eleventh transistor is always electrically connected to the power supply line; the gate of the eleventh transistor is always electrically connected to the second signal line; one of the source and the drain of the twelfth transistor is always electrically connected to the gate of the ninth transistor; the other of the source and the drain of the twelfth transistor is always electrically connected to the power supply line; the gate of the twelfth transistor is always electrically connected to the second signal line; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, when the first wiring is in a conductive state with the first transistor, the sixth transistor, and the seventh transistor via at least a channel formation region of the third transistor, a potential having a value that turns on the first transistor, the sixth transistor, and the seventh transistor is input to a gate of the first transistor, the gate of the sixth transistor, and the gate of the seventh transistor via at least a channel formation region of the third transistor; When the first wiring is in a conductive state with the ninth transistor through at least a channel formation region of the tenth transistor, a potential having a value that turns on the ninth transistor is input to a gate of the ninth transistor through at least a channel formation region of the tenth transistor.

4. having first to twelfth transistors, one of the source and the drain of the first transistor is always electrically connected to a gate signal line; the other of the source and the drain of the first transistor is always electrically connected to a clock signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a first wiring; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to a first signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the power supply line; a gate of the sixth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the eighth transistor is always electrically connected to the first signal line; a gate of the eighth transistor is always electrically connected to the first signal line; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; one of the source and the drain of the tenth transistor is always electrically connected to the gate of the ninth transistor; the other of the source and the drain of the tenth transistor is always electrically connected to the first wiring; one of the source and the drain of the eleventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the eleventh transistor is always electrically connected to the power supply line; the gate of the eleventh transistor is always electrically connected to the second signal line; one of the source and the drain of the twelfth transistor is always electrically connected to the gate of the ninth transistor; the other of the source and the drain of the twelfth transistor is always electrically connected to the power supply line; the gate of the twelfth transistor is always electrically connected to the second signal line; when the other of the source or the drain of the second transistor is in a state of conduction with the gate signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the gate signal line via at least a channel formation region of the second transistor, when the first wiring is in a conductive state with the first transistor, the sixth transistor, and the seventh transistor via at least a channel formation region of the third transistor, a potential having a value that turns on the first transistor, the sixth transistor, and the seventh transistor is input to a gate of the first transistor, the gate of the sixth transistor, and the gate of the seventh transistor via at least a channel formation region of the third transistor; when the first wiring is in a conductive state with the ninth transistor through at least a channel formation region of the tenth transistor, a potential having a value that turns on the ninth transistor is input to a gate of the ninth transistor through at least a channel formation region of the tenth transistor; the W / L (W is a channel width, L is a channel length) of the first transistor is larger than the W / L of the second transistor; the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the first transistor is greater than the W / L of the fifth transistor; the W / L of the first transistor is greater than the W / L of the sixth transistor; the W / L of the first transistor is greater than the W / L of the seventh transistor; the W / L of the first transistor is greater than the W / L of the eighth transistor; the W / L of the first transistor is greater than the W / L of the ninth transistor; A semiconductor device in which the W / L of the first transistor is larger than the W / L of the tenth transistor.

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