Control device and control method

Abstract

To shorten the time for saving a log when abnormality is detected.SOLUTION: A control device according to the present disclosure includes a processor configured to execute software, and a circuit device configured to detect an abnormality, wherein when the circuit device detects the abnormality, the circuit device suppresses notification of the abnormality to the software and stores error information regarding the abnormality in a storage device.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a control device and a control method. [Background technology]

[0002] Various devices (also called modules or control devices) are used in PA (Process Automation) and FA (Factory Automation), such as field devices, controllers that control field devices, and monitoring devices that monitor the status of field devices and the entire plant including the field devices.

[0003] Such devices (modules) are equipped with a self-diagnostic function that, if the module detects an abnormality, the FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) notifies the software of the abnormality and saves the error information stored in the hardware registers in external non-volatile memory.

[0004] Specifically, when an FPGA or ASIC (also called hardware) detects an abnormality, it notifies the processor of the abnormality, and the processor obtains error information (hardware log) related to the abnormality from the hardware, and then stores the hardware log in external non-volatile memory of the processor (or FPGA / ASIC). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-70936 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the control device described above takes time to save the log when an abnormality is detected. Specifically, there are many processes involved in saving the error information to nonvolatile memory, and it takes a long time from the detection of an abnormality until the error information is saved in nonvolatile memory.

[0007] The present disclosure has been made in consideration of the above-described circumstances, and shortens the time required for saving logs when an abnormality is detected. [Means for solving the problem]

[0008] The control device of the present disclosure has a processor that executes software and a circuit device that detects abnormalities, and when the circuit device detects the abnormality, it suppresses notification of the abnormality to the software and stores error information related to the abnormality in a storage device. [Effects of the Invention]

[0009] The control device of the present disclosure can reduce the time required for saving logs when an abnormality is detected. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a conventional control device. [Figure 2] FIG. 2 is a diagram for explaining an outline of the operation of the control device according to the embodiment. [Figure 3] FIG. 2 is a diagram illustrating a configuration of a control device according to the first embodiment. [Figure 4] 4 is a flowchart for explaining the operation of the control device according to the first embodiment. [Figure 5] FIG. 10 is a diagram illustrating an error information storage circuit of the control device according to the second embodiment. [Figure 6] FIG. 10 is a diagram illustrating the configuration of a control device according to a third embodiment. [Figure 7] FIG. 11 is a diagram showing the relationship between a register, an RTC, and a nonvolatile memory in the circuit of the control device according to the third embodiment. [Figure 8] 10 is a flowchart illustrating the operation of the control device according to the third embodiment. [Figure 9] FIG. 10 is a diagram illustrating the configuration of a control device according to a fourth embodiment. [Figure 10] 10 is a diagram showing an example in which a checksum is added as an error detection code to error information of a control device according to a fourth embodiment. FIG. [Figure 11] 10 is a flowchart illustrating the operation of the control device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0012] (1. First embodiment) (1.1. Overview) 1 is a diagram showing the configuration of a conventional control device 100. When an abnormality occurs in the control device 100, the control device 100 stores error information indicating the nature of the abnormality in the control device 100 (for example, an abnormal voltage value) in an error information storage circuit 113. Then, a processor 102 of the control device 100 reads out the error information stored in the error information storage circuit 113 and stores it in a non-volatile memory 103. The error information stored in the non-volatile memory 103 is used to later investigate the cause of the abnormality.

[0013] 1, as an example, a control device 100 is provided in a plant. As shown in FIG. 1, the control device 100 includes a circuit 101 and a processor 102. The control device 100 also includes a non-volatile memory 103.

[0014] Circuit 101 is an FPGA or an ASIC. An FPGA is a device that integrates logic circuits (gates) whose configuration can be programmed by a designer in the field. Unlike an LSI (integrated circuit), whose circuit configuration cannot be changed after manufacturing, an FPGA is called programmable because its internal circuit configuration, i.e., the processing content of the device, can be rewritten by programming. Programmability means that users can change and automate the operation of modules, software, systems, etc. as needed. An ASIC is an application-specific IC, that is, a custom IC manufactured specifically for a specific application or end product. The name ASIC comes from its intended use, not its internal structure. An ASIC can be customized to incorporate a microcontroller, DSP, GPU, memory, dedicated circuits, etc., depending on the application.

[0015] When an abnormality occurs in the control device 100, the abnormality detection circuit 111 of the circuit 101 detects the abnormality and notifies the processor 102 of the abnormality detection signal indicating the detection of the abnormality (step a). Also, when the abnormality detection circuit 111 detects an abnormality in the control device 100 (step b), the abnormality content storage circuit 112 stores error information indicating the content of the failure of the control device 100 in a hardware manner in the error information storage circuit 113 having a plurality of registers (step c).

[0016] The processor 102 is responsible for overall control of the control device 100. When the processor 102 receives an abnormality detection signal from the abnormality detection circuit 111 of the circuit 101, the processor 102 reads out the error information stored in the register of the error information storage circuit 113 by software (step d). Then, the processor 102 stores the read out error information in the nonvolatile memory 103 (step e).

[0017] Abnormalities in the control device 100 include, for example, an abnormality in the main power supply voltage of the control device 100 (an abnormality in the external power supply that supplies voltage to the module), a software stop in the processor, an abnormality in the external temperature (high / low external temperature), and the like.

[0018] In the following, the "error information stored in the register of the error information storage circuit" may also be referred to as the "hardware log."

[0019] Specifically, the conventional control device 100 has the following improvements.

[0020] (a) Because the software acquires error information from the registers of the error information storage circuit 113, which is hardware, and stores the acquired information in an external non-volatile memory, there are many processes involved in storing the error information, and it takes a long time from detecting an abnormality to storing the error information.

[0021] (b) In software processing, peripheral / driver processing is required when accessing nonvolatile memory. Therefore, the conventional control device 100 cannot fully utilize the processing speed of the hardware of the nonvolatile memory, and the save process takes time.

[0022] (c) The time it takes to save the error information depends on the processing speed of the software, so the time it takes to save the error information changes each time.

[0023] (d) When multiple abnormalities occur in succession, the error information that occurs cannot be sent to an external non-volatile memory for each log because it is processed through software, and therefore the root cause of the error cannot be identified, which hinders the analysis of the error information.

[0024] As a specific problem caused by (a), (b), and (c), consider the case where the operation of the control device 100 stops due to a drop in the main power supply voltage of the module caused by a transient abnormality in the power line or hot-plugging. In this case, the control device 100 takes time to save the error information, so the cause of the module stopping cannot be determined.

[0025] As a specific example of the problem caused by (d), if another abnormality that causes an error occurs while error information is being saved, the error information may be overwritten. In this case, the content of the error information will be inconsistent, making it difficult to analyze the error information.

[0026] In other words, in the conventional control device 100, when an abnormality was detected in the control device 100, the processor 102 (software) acquired error information and stored it in the non-volatile memory 103, which caused a problem in that it took a long time from the occurrence of an abnormality in the control device 100 until the error information was stored.

[0027] Therefore, the control device of the present disclosure quickly and accurately stores error information indicating the details of the abnormality in the control device 100.

[0028] Next, an overview of the control device according to the embodiment will be described. Many PA and FA devices have a self-diagnosis function, and when an abnormality is detected, error information (hardware log) is often stored in a group of hardware registers. A conventional control device 100 with a self-diagnosis function stores error information in an external non-volatile memory using a processor or the like.

[0029] The control device of the embodiment implements this function in hardware, which allows the control device of the embodiment to store error information at high speed and at the same rate, without relying on software operations.

[0030] Furthermore, the control device of the embodiment utilizes a buffer within the hardware to reliably store all error information in non-volatile memory even when multiple events that cause errors occur consecutively.

[0031] 2 is a diagram for explaining an outline of the operation of the control device A according to the embodiment, and shows a case where an abnormality occurs in the control device A.

[0032] The control device A has a circuit 1, a processor 2, and a non-volatile memory 3. The circuit 1 is an FPGA or an ASIC. The processor 2 is responsible for the overall control of the control device A. The non-volatile memory 3 may be provided outside the control device A. When an abnormality occurs in the control device A, the circuit 1 does not notify the processor 2 of the occurrence of the abnormality, but stores error information indicating the nature of the abnormality in the non-volatile memory 3 by hardware, not via software. The control device A is not limited to being provided in a plant, and can also be provided in equipment other than a plant.

[0033] Therefore, according to the embodiment of the control device A, the circuit 1 can store the error information of the control device A in the non-volatile memory 3 by hardware without using software, so that the abnormality details of the control device A can be saved quickly and accurately.

[0034] The control device A of the embodiment can be used in a self-diagnosis function in devices used in PA or FA.

[0035] (1.2. Configuration) Next, a specific configuration of the control device A according to the first embodiment will be described. Fig. 3 is a diagram showing the configuration of the control device A according to the first embodiment. As shown in Fig. 3, the control device A has a circuit 1, a processor 2, and a non-volatile memory 3.

[0036] (Circuit 1) The circuit 1 is an example of a circuit device connected to each of the processor 2 and the non-volatile memory 3. The circuit 1 is an FPGA or an ASIC. The processor 2 is responsible for the overall control of the control device A. The circuit 1 has an abnormality detection circuit 11, an abnormality content storage circuit 12, and an error information storage circuit 13.

[0037] (Abnormality detection circuit 11) The abnormality detection circuit 11 is a circuit that detects an abnormality that occurs in the control device A. This abnormality detection circuit 11 may be connected to an abnormality content storage circuit 12. Furthermore, when the abnormality detection circuit 11 detects an abnormality, it suppresses notification of the abnormality to the software (processor).

[0038] (Abnormal content storage circuit 12) When the abnormality detection circuit 11 detects an abnormality, the abnormality content storage circuit 12 stores error information indicating the content of the abnormality of the control device A in the error information storage circuit 13.

[0039] (Error information storage circuit 13) The error information storage circuit 13 has a plurality of registers (register group). The error information storage circuit 13 stores the error information stored in these registers in the nonvolatile memory 3 by hardware, not via software. The error information stored in the nonvolatile memory 3 stores the entire history of the error information stored in the error information storage circuit 13.

[0040] (1.3.Operation) Next, the operation of the control device A shown in Fig. 3 will be described. Fig. 4 is a flowchart for explaining the operation of the control device A according to the first embodiment. Hereinafter, the operation of the control device A will be described with reference to Figs. 3 and 4.

[0041] When the abnormality detection circuit 11 of the control device A detects an abnormality in the control device A (step S11), the abnormality detection circuit 11 notifies the abnormality content storage circuit 12 that an abnormality has been detected (step S1 in FIG. 3).

[0042] The abnormality content storage circuit 12 directly stores error information indicating the content of the abnormality of the control device A in a register of the error information storage circuit 13 in a hardware manner (step S12, step S2 in FIG. 3).

[0043] Then, the error information saving circuit 13 stores the saved error information in the nonvolatile memory 3 by hardware, without using software (step S13, step S3 in FIG. 3). In other words, software is not involved in saving the error information.

[0044] (1.4.Effects) The control device A of the first embodiment suppresses notification of an abnormality to the processor 2 and autonomously stores error information without relying on software, thereby shortening the time from when the control device A detects an abnormality to when the error information is stored in the non-volatile memory 3.

[0045] Therefore, the control device A of the first embodiment can reliably acquire the error cause of the CPU module even when there is no time to save the error information in the non-volatile memory 3 (for example, due to a transient abnormality in the power line or removal of a live wire).

[0046] Furthermore, the control device A of the first embodiment stores error information in the nonvolatile memory 3 without relying on software processing, and therefore the time for storing error information can be made constant.

[0047] Furthermore, in the control device A of the first embodiment, the process of saving error information is completed by hardware, eliminating the need for software to acquire error information, and shortening the time required from detecting an abnormality to saving error information.

[0048] Furthermore, in the control device A of the first embodiment, even if software is running when an abnormality occurs, error information can be saved quickly and always at the same time.

[0049] Furthermore, in the control device A of the first embodiment, even if the software stops due to a failure of the processor 2, the error information can be saved.

[0050] (2. Second Embodiment) Next, a control device A' according to a second embodiment will be described. The control device A' according to the second embodiment differs from the control device according to the first embodiment in the configuration of the error information storage circuit 13.

[0051] (2.1. Configuration) Fig. 5 is a diagram showing an error information storage circuit 13' of a control device A' according to the second embodiment. As shown in Fig. 5, the error information storage circuit 13' has a register group 21 and buffers 22-1 to 22-3.

[0052] The register group 21 has a plurality of registers r21-1 to r21-N. Error information indicating the details of the detected abnormality in the control device A' is first stored in the registers r21-1 to r21-N.

[0053] Buffer 22-1 has a plurality of registers br-1-1 to br-1-N. Buffer 22-2 has a plurality of registers br-2-1 to br-2-N. Buffer 22-3 has a plurality of registers br-3-1 to br-3-N. Error information stored in a plurality of registers r21-1 to r21-N is sequentially copied to these plurality of registers br-1-1 to br-1-N, br-2-1 to br-2-N, and br-3-1 to br-3-N. The error information stored in buffers 22-1 to 22-3 is then sequentially stored in nonvolatile memory 3 without the intervention of software. That is, a history of the error information stored in buffers 22-1 to 22-3 is saved in nonvolatile memory 3.

[0054] (2.2.Operation) Hereinafter, with reference to Fig. 5, an operation of saving error information of the error information save circuit 13' according to the second embodiment in the nonvolatile memory 3 will be described. In the error information save circuit 13' shown in Fig. 5, when an abnormality occurs in the control device A', the registers r21-1 to r21-N in which the error information of the register group 21 is stored are copied to the registers br-1-1 to br-1-N of the buffer 22-1 (step S21). Next, the contents of the registers br-1-1 to br-1-N of the buffer 22-1 are saved in the nonvolatile memory 3 (step S22).

[0055] Thereafter, if another error factor occurs, the same processing as that of buffer 22-1 is performed in buffers 22-2 and 22-3. That is, if another error factor occurs, the error information stored in registers r21-1 to r21-N of register group 21 is copied to registers br-2-1 to br-2-N of buffer 22-2 (step S23). Then, the error information in registers br-2-1 to br-2-N of buffer 22-2 is saved in non-volatile memory 3 (step S24).

[0056] Furthermore, if another error factor occurs thereafter, the error information stored in registers r21-1 to r21-N of the register group 21 is copied to registers br-3-1 to br-3-N of the buffer 22-3 (step S25).Then, the error information stored in registers br-3-1 to br-3-N of the buffer 22-3 is saved in the nonvolatile memory 3 (step S26).

[0057] Furthermore, if another error factor occurs thereafter, the processes of steps S21 to S26 are repeated in sequence. Note that the number of buffers 22 and the order in which the error information is transferred from the register group 21 to the buffers 22-1 to 22-3 are not limited to the number and order shown in FIG.

[0058] (2.3. Effects) 5 has buffers 22-1 to 22-3 that temporarily store error information. Unlike the first embodiment, by having buffers 22-1 to 22-3, even if multiple error causes occur consecutively while error information is being stored, error information storage circuit 13' can store each piece of error information in a separate buffer 21-1 to 21-3. Therefore, error information storage circuit 13' can store all of the error information in non-volatile memory 3 without missing any of the error information for each log.

[0059] (3. Third Embodiment) The control device A'' according to the third embodiment differs from the control device A according to the first embodiment or the control device A' according to the second embodiment in that it is provided with an RTC information storage circuit 30 and operates an error information storage circuit 34. Due to these differences, the control device A'' according to the third embodiment stores in the non-volatile memory 3 time information and error information that are useful for error analysis, and can reliably store the error factors even when the data size of the error information is large.

[0060] (3.1. Configuration) A specific configuration of the control device A'' according to the third embodiment will be described. FIG. 6 is a diagram showing the configuration of the control device A'' according to the third embodiment. Note that the same parts as those in FIG. 3 will be described using the same reference numerals. As shown in FIG. 6, the circuit 1 of the control device A'' according to the third embodiment has an RTC information storage circuit 30 and an error information retention circuit 34.

[0061] The RTC information storage circuit 30 acquires time information when an abnormality in the control device A'' is detected from an RTC (Real Time Clock) provided outside the circuit 1, and stores the acquired time information in a register of the error information storage circuit 13. The error information storage circuit 34 selects error cause information indicating the cause of the error from the error information, and stores the selected error cause information in the non-volatile memory 3. The RTC may be provided inside the circuit 1. For example, the error cause information is extracted when, among the abnormalities to be detected, an abnormality of a specific cause is detected that has a short grace period in which the control device A'' can stop and save the error information, i.e., the time allowed for saving the error information is less than a threshold.

[0062] The error information storage circuit 34 has a plurality of registers (register group). The error information storage circuit 34 selects error cause information indicating the cause of the error from the error information stored in these plurality of registers. The error information storage circuit 34 then stores the time information acquired by the RTC information storage circuit 30 and the selected error cause information in the nonvolatile memory 3 by hardware, not via software. The error information stored in the nonvolatile memory 3 stores the entire history of the error information stored in the error information storage circuit 34.

[0063] 7 is a diagram showing the relationship between the registers of the circuit 1 of the control device A'' according to the third embodiment, the RTC 31, and the nonvolatile memory 3. As shown in FIG. 7, the registers of the error information storage circuit 34 of the circuit 1 of the control device A'' according to the third embodiment include a register 32 for time information and a register 33 for error causes.

[0064] The register 32 for time information is a register that stores time information when an abnormality in the control device A'' is detected, which is acquired by the RTC information storage circuit 30. The register 33 for error cause is a register that stores error cause information that indicates the error cause selected from the error information by the error information storage circuit 34.

[0065] The error information storage circuit 34 of the circuit 1 of the third embodiment stores in the nonvolatile memory 3 not all of the error information but error cause information and time information selected from the error information.

[0066] (3.2. Operation) Next, the operation of the control device A'' shown in FIG. 6 will be described. FIG. 8 is a flowchart for explaining the operation of the control device A'' according to the third embodiment. Hereinafter, the operation of the control device A'' will be described with reference to FIG. 8.

[0067] When the abnormality detection circuit 11 of the control device A'' detects an abnormality in the control device A'' (step S41), the abnormality detection circuit 11 notifies the abnormality details storage circuit 12 that an abnormality has been detected.

[0068] When the abnormality detection circuit 11 detects an abnormality in the control device A'', the abnormality content storage circuit 12 directly stores error information indicating the content of the abnormality in the control device A'' in a register of the error information storage circuit 34 in a hardware manner (step S42).

[0069] Next, the error information storage circuit 34 selects an error cause useful for error analysis from the error information indicating the details of the abnormality in the control device A'' (step S43). Then, the error information storage circuit 34 stores the error cause and time information stored in the register in the non-volatile memory 3 without using software (step S44).

[0070] The error information storage circuit 34 may have a plurality of buffers, like the error information storage circuit 13′ of the second embodiment shown in Fig. 5. In this case, the error cause and time information stored in the register of the error information storage circuit 34 are saved in the register of one of the buffers, and the error cause and time information saved in the buffer are saved in the non-volatile memory 3 without the intervention of software.

[0071] (3.3. Effects) When the control device A'' of the third embodiment detects an error cause (for example, a transient abnormality in the power line) in which the data size of the error information is large and there is no time to spare, it selects from the error information an error cause that is useful for error analysis and stores the error cause and time information in the non-volatile memory 3.

[0072] As a result, the control device A'' of the third embodiment can reduce the data size of the error information, and therefore can reliably store the cause of the error regardless of the data size of the error information.

[0073] Furthermore, the control device A'' of the third embodiment stores time information when an error occurs, so that when analyzing a module failure, it is possible to grasp the cause of the error in chronological order.

[0074] (4. Fourth Embodiment) The control device A''' according to the fourth embodiment differs from the control device A according to the first embodiment to the control device A'' according to the third embodiment in that it is provided with an error detection code assignment circuit 41 and the operation of an error information storage circuit 42. Due to these differences, the control device A''' according to the fourth embodiment assigns an error detection code to error information and stores it in the non-volatile memory 3. Therefore, like the control device A'' according to the third embodiment, the control device A''' according to the fourth embodiment reliably stores the error cause when the data size of the error information is large.

[0075] (4.1. Configuration) The specific configuration of the control device A''' according to the fourth embodiment will be described. FIG. 9 is a diagram showing the configuration of the control device A''' according to the fourth embodiment. Note that the same parts as in FIG. 3 will be described with the same reference numerals. As shown in FIG. 9, the circuit 1 of the control device A''' according to the fourth embodiment has an error detection code adding circuit 41 and an error information storage circuit 42.

[0076] The error detection code adding circuit 41 obtains an error detection code for each address in a predetermined range of the register of the error information storage circuit 42, and stores the obtained error detection code in the register of the error information storage circuit 42. Here, the error detection code is, for example, a checksum, a CRC (Cyclic Redundancy Code), an ECC (Error-Correcting Code), etc.

[0077] The error information storage circuit 42 stores the error information stored in the register of the error information storage circuit 42 and the error detection code obtained by the error detection code adding circuit 41 in the nonvolatile memory 3 .

[0078] (An example of adding an error detection code) FIG. 10 is a diagram showing an example of adding a checksum as an error detection code to error information of the control device A''' according to the fourth embodiment. As shown in FIG. 10, a checksum is added to each 0x20 of the address of the register of the error information storage circuit 42.

[0079] Specifically, checksums are assigned to addresses 0x0 to 0x1B, 0x20 to 0x3B, 0x4 to 0x5B, and 0x60 to 0x7B. The checksums assigned to addresses 0x0 to 0x1B, 0x20 to 0x3B, and 0x60 to 0x7B are consistent (correct). An error has been detected in the checksum assigned to addresses 0x4 to 0x5B.

[0080] (4.2. Operation) Next, the operation of the control device A''' shown in FIG. 9 will be described. FIG. 11 is a flowchart for explaining the operation of the control device A''' according to the fourth embodiment. Hereinafter, the operation of the control device A''' will be described with reference to FIG. 11.

[0081] When the abnormality detection circuit 11 of the control device A''' detects an abnormality in the control device A''' (step S51), the abnormality detection circuit 11 notifies the abnormality details storage circuit 12 that an abnormality has been detected.

[0082] The abnormality content storage circuit 12 directly stores error information indicating the content of the abnormality of the control device A''' in a register of the error information storage circuit 34 in a hardware manner (step S52).

[0083] Next, the error detection code assigning circuit 41 assigns an error detection code to each address in a predetermined range of the error information (step S53), and then directly stores the error detection code in a register of the error information storage circuit 42 in a hardware manner for each address in the predetermined range of the error information (step S54).

[0084] Next, the error information storage circuit 42 stores the error information and error detection code stored in the register directly in the nonvolatile memory 3 in a hardware manner (step S55).

[0085] The error information storage circuit 42 may have a plurality of buffers, like the error information storage circuit 13′ of the second embodiment shown in Fig. 5. In this case, the error information and error detection code stored in the register of the error information storage circuit 42 are saved in the register of one of the buffers, and the error information and error detection code saved in the buffer are saved in the non-volatile memory 3 without the intervention of software.

[0086] (4.3. Effects) Therefore, the control device A''' of the fourth embodiment adds an error detection code to the error information for each certain address area to check the consistency of the data. The control device A''' of the fourth embodiment then adds the error detection code to the error information. This makes it possible to check the reliability of the data for each area of ​​the error information.

[0087] When the data size of the error information is large and an error factor with no time to spare (for example, a transient abnormality in a power line) is detected, there is a possibility that a conventional control device will not be able to retrieve all of the error information.

[0088] However, the control device A''' of the fourth embodiment is able to ensure data consistency for each area by assigning a checksum to each specified area, and only valid error information can be used as information for error analysis.

[0089] In the example of Figure 10, an error was detected in the checksum assigned to addresses 0x40 to 0x5B, so the reliability of the data cannot be guaranteed. On the other hand, the checksums assigned to addresses 0x0 to 0x1B, 0x20 to 0x3B, and 0x60 to 0x7B are consistent, so the error information for those areas can be trusted.

[0090] Some examples of combinations of the disclosed technical features are set out below.

[0091] (1) a processor that executes the software; a circuit device for detecting an abnormality; The circuit device is When the abnormality is detected, notification of the abnormality to the software is suppressed; storing error information relating to the abnormality in a storage device; A control device characterized by:

[0092] (2) The circuit device is a register group including a plurality of registers for storing the error information; When an abnormality including an abnormality in the main power supply voltage of the control device, a stop of the software, or an abnormality in the external temperature of the control device is detected, the error information is read from the plurality of registers; storing the read error information in the storage device; The control device according to (1) is characterized in that:

[0093] (3) The circuit device is having a buffer, Copying the copy information of the register group including the register in which the error information is stored to the buffer; reading the error information from the copy information of the register group stored in the buffer and storing the error information in the storage device; The control device according to (2) above.

[0094] (4) The circuit device is It has multiple buffers, When a first abnormality is detected in the group of registers, first copy information of a group of registers including a register in which first error information related to the first abnormality is stored is copied to a first buffer; When a second abnormality is detected in the register group after the first abnormality, second copy information of the register group including a register in which second error information related to the second abnormality is stored is copied to a second buffer; reading the first error information from the first copy information stored in the first buffer and storing the first error information in the storage device; reading the second error information from the second copy information stored in the second buffer and storing the second error information in the storage device; The control device according to (3) above.

[0095] (5) The circuit device is extracting error cause information relating to a cause of the detected abnormality from the error information; acquiring the error cause information and time information at which the abnormality was detected, which is specified using a real-time clock; the error cause information and the time information are stored in the storage device in association with each other; Characterized by The control device according to any one of (2) to (4).

[0096] (6) The circuit device is extracting the error cause information when an abnormality of a specific cause is detected that has a short grace period in which the control device can stop and save the error information, the grace period being less than a threshold, among the abnormalities to be detected; (5) The control device described in (5).

[0097] (7) The circuit device is a register for storing the error information; calculating an error detection code for each predetermined address area of ​​the register to confirm data consistency; reading the error information including the error detection code for each of the predetermined address intervals from the register and storing the error information in the storage device; The control device according to any one of (2) to (6).

[0098] (8) The circuit device is storing the error information in a non-volatile memory; The control device according to any one of (1) to (7).

[0099] (9) the storage device stores the history of the plurality of buffers; The control device according to (3) or (4).

[0100] (10) The circuit device is an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), The control device according to any one of (1) to (9).

[0101] (11) a processor that executes the software; a circuit device for detecting an abnormality; The circuit device is When the abnormality is detected, notification of the abnormality to the software is suppressed; storing error information relating to the abnormality in a storage device; A control method comprising: executing a process. [Explanation of symbols]

[0102] A, A', A'', A''' control device 1 circuit 2 processors 3. Non-volatile memory 11 Abnormality detection circuit 12 Abnormal content storage circuit 13, 13', 34, 42 Error information storage circuit 21 Registers 22, 22-1 to 22-3 buffer 30 RTC information storage circuit 31 RTC 32 Registers for time information 33 Register for error cause 41 Error detection code adding circuit

Claims

1. a processor that executes the software; a circuit device for detecting an abnormality; The circuit device is When the abnormality is detected, notification of the abnormality to the software is suppressed; storing error information relating to the abnormality in a storage device; A control device characterized by:

2. The circuit device is a register group including a plurality of registers for storing the error information; When an abnormality including an abnormality in the main power supply voltage of the control device, a stop of the software, or an abnormality in the external temperature of the control device is detected, the error information is read from the plurality of registers; storing the read error information in the storage device; 2. The control device according to claim 1.

3. The circuit device is having a buffer, Copying the copy information of the register group including the register in which the error information is stored to the buffer; reading the error information from the copy information of the register group stored in the buffer and storing the error information in the storage device; 3. The control device according to claim 2.

4. The circuit device is It has multiple buffers, When a first abnormality is detected in the group of registers, first copy information of the group of registers including a register in which first error information related to the first abnormality is stored is copied to a first buffer; When a second abnormality is detected in the register group after the first abnormality, second copy information of the register group including a register in which second error information related to the second abnormality is stored is copied to a second buffer; reading the first error information from the first copy information stored in the first buffer and storing the first error information in the storage device; reading the second error information from the second copy information stored in the second buffer and storing the second error information in the storage device; 3. The control device according to claim 2.

5. The circuit device is extracting error cause information relating to a cause of the detected abnormality from the error information; acquiring the error cause information and time information at which the abnormality was detected, which is specified using a real-time clock; the error cause information and the time information are stored in the storage device in association with each other; 3. The control device according to claim 2.

6. The circuit device is extracting the error cause information when an abnormality of a specific cause is detected that has a short time margin for stopping the control device and saving the error information, that is, the time is less than a threshold, among the abnormalities to be detected; 6. The control device according to claim 5.

7. The circuit device is a register for storing the error information; calculating an error detection code for each predetermined address area of ​​the register to confirm data consistency; reading the error information including the error detection code for each of the predetermined address areas from the register and storing the error information in the storage device; 3. The control device according to claim 2.

8. The circuit device is storing the error information in a non-volatile memory; 2. The control device according to claim 1.

9. the storage device stores the history of the plurality of buffers; 5. The control device according to claim 4.

10. The circuit device is FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit), 2. The control device according to claim 1.

11. a processor that executes the software; a circuit device for detecting an abnormality; The circuit device is When the abnormality is detected, notification of the abnormality to the software is suppressed; storing error information relating to the abnormality in a storage device; A control method comprising: executing a process.

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