Semiconductor device

Abstract

To reduce on-resistance of a semiconductor device.SOLUTION: A semiconductor device includes a semiconductor layer, a gate trench 14, a plurality of mesa regions 60 surrounded by the gate trench 14 in plan view, a trench oxide film 17 provided in the gate trench 14, and a gate electrode 50 and a field plate electrode embedded in the gate trench 14 via the trench oxide film 17. The plurality of mesa regions 60 include a first mesa region 61 and a second mesa region 62 provided apart from each other in the X-axis direction in plan view, and a third mesa region 63 provided apart from the first mesa region 61 in a direction intersecting the X-axis direction in plan view. The gate trench 14 is formed in a mesh shape in a plan view by the plurality of mesa regions 60.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having multiple trench gate structures formed in a stripe pattern, each of which includes a gate trench and two electrodes embedded in the gate trench and separated in the depth direction. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-125649

[0004] [overview] There is a demand for reducing the on-resistance of semiconductor devices.

[0005] a gate electrode embedded in the trench with the oxide film interposed therebetween; and a field plate electrode disposed in the trench closer to the second surface than the gate electrode and embedded with the oxide film interposed therebetween. The semiconductor device according to one embodiment of the present disclosure includes: a semiconductor layer including a first surface and a second surface opposite the first surface; trenches extending from the first surface toward the second surface of the semiconductor layer; a plurality of mesa regions in the semiconductor layer between the trenches and surrounded by the trenches when viewed in a thickness direction of the semiconductor layer; an oxide film disposed on the first surface of the semiconductor layer and within the trench; a gate electrode embedded in the trench with the oxide film interposed therebetween; and a field plate electrode disposed in the trench closer to the second surface than the gate electrode and embedded with the oxide film interposed therebetween. The plurality of mesa regions include a first mesa region and a second mesa region spaced apart in a first direction when viewed in the thickness direction; and a third mesa region spaced apart from the first mesa region in a direction intersecting the first direction when viewed in the thickness direction. The trench is formed into a mesh shape by the plurality of mesa regions when viewed in the thickness direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an enlarged view of a part of the semiconductor layer in the semiconductor device of FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the semiconductor device taken at the position of the gate electrode. [Figure 4] FIG. 4 is a schematic cross-sectional view of the semiconductor device taken at the position of the field plate electrode. [Figure 5] FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of a semiconductor device according to a modified example, taken at the position of a gate electrode of the semiconductor device. [Figure 8] FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a modified example, taken at the position of a gate electrode of the semiconductor device. [Figure 9] FIG. 9 is a schematic cross-sectional view of a semiconductor device according to a modified example, taken at the position of a gate electrode of the semiconductor device. [Figure 10] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a modified example, taken at the position of a gate electrode of the semiconductor device. [Figure 11] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a modified example, taken at the position of a gate electrode of the semiconductor device. [Figure 12] FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a modified example, taken at the position of a gate electrode of the semiconductor device.

[0007] [Detailed explanation] Hereinafter, several embodiments of semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0011] [Planar structure of semiconductor device] Referring to FIG. 1, a schematic planar structure of a semiconductor device 10 according to one embodiment will be described. Fig. 1 schematically shows the planar structure of a semiconductor device 10. In Fig. 1, the internal structure of the semiconductor device 10 is indicated by dashed lines. Note that the term "planar view" used in this disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Fig. 1. Unless explicitly stated otherwise, "planar view" refers to viewing the semiconductor device 10 from above along the Z-axis.

[0012] 1, the semiconductor device 10 is, for example, a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) having a split gate structure. The semiconductor device 10 includes a semiconductor layer 12, a gate trench 14 provided in the semiconductor layer 12, and an oxide film 16 provided in the gate trench 14. Here, the gate trench 14 is an example of a "trench."

[0013] The semiconductor layer 12 can be made of, for example, silicon (Si). The semiconductor layer 12 includes a first surface 12A and a second surface 12B opposite to the first surface 12A (see FIG. 5 for both). The semiconductor layer 12 has a thickness in a direction (Z-axis direction) perpendicular to the first surface 12A. In other words, the Z-axis direction can be said to be the "thickness direction of the semiconductor layer 12."

[0014] The gate trench 14 has an opening in the first surface 12A of the semiconductor layer 12. The gate trench 14 extends in the Z-axis direction from the first surface 12A toward the second surface 12B. In other words, the gate trench 14 has a depth in the Z-axis direction. It can also be said that the gate trench 14 is provided in the first surface 12A. Furthermore, the gate trench 14 has a mesh-like shape in a plan view.

[0015] 5, a gate electrode 50 and a field plate electrode 52 can be disposed in the gate trench 14. The gate trench 14 has a first end 14P and a second end 14Q as opposite ends in the Y-axis direction.

[0016] The semiconductor device 10 may further include a peripheral trench 18 provided in the semiconductor layer 12. In one example, the peripheral trench 18 is spaced apart from the gate trench 14 and is provided so as to surround the gate trench 14 in a plan view. In the example shown in FIG. 1 , the peripheral trench 18 has a rectangular frame shape in a plan view, with the X-axis direction being the short side direction and the Y-axis direction being the long side direction. A peripheral electrode (not shown) can be disposed within the peripheral trench 18, and is provided along the shape of the peripheral trench 18 in a plan view.

[0017] The first surface 12A of the semiconductor layer 12 is an n-type impurity-containing - a p-type region 20 containing p-type impurities; - and an n-type region 22 containing n-type impurities. + and a mold region 24. - The mold region 20 may surround the peripheral trench 18 in a plan view. - Type regions 22 and n + Both of the mold regions 24 may be surrounded by the peripheral trench 18 in plan view. - Type region 20 and p - Type region and n + The mold region 24 is separated by a peripheral trench 18 .

[0018] p - Type regions 22 and n + The mold regions 24 are arranged in the Y-axis direction. - A plurality of mold regions 22 (two in the example shown in FIG. 1) may be provided. - The type region 22 is, for example, n + They are provided in a distributed manner on both sides of the mold region 24 in the Y-axis direction. + The mold region 24 has two p - It is provided between the mold areas 22.

[0019] The gate trench 14 is formed by p - The first end 14P of the gate trench 14 can be disposed adjacent to the first end 14P of the gate trench 14. -The second end 14Q of the gate trench 14 can be adjacent to one of the p-type regions 22, and the second end 14Q of the gate trench 14 can be adjacent to one of the p-type regions 22. - The middle portion of the gate trench 14 may be adjacent to the remaining one of the n-type regions 22. + It may be adjacent to the mold area 24 .

[0020] A plurality of first ends 14P (four in this embodiment) of the gate trench 14 are provided at intervals in the X-axis direction. + The p region from the gate wiring 26 - The second end 14Q is a portion that protrudes into the mold region 22. A plurality of second end portions 14Q (four in this embodiment) of the gate trench 14 are provided at intervals in the X-axis direction. The second end portions 14Q are n + The p-type region 24 on the opposite side to the gate wiring 26 - This is the part that protrudes into the mold area 22.

[0021] The oxide film 16 is formed on the n-type surface 12B of the second surface 12B of the semiconductor layer 12. + The oxide film 16 covers the region other than the mold region 24 and is embedded in the gate trench 14 and the peripheral trench 18. The oxide film 16 is a layer that insulates the gate electrode 50 and the field plate electrode 52 from the semiconductor layer 12. The oxide film 16 is made of a material containing, for example, SiO. In one example, the oxide film 16 is made of a silicon oxide film (SiO2).

[0022] The semiconductor device 10 may further include a gate wiring 26 and a source wiring 28 provided on the oxide film 16. Each of the gate wiring 26 and the source wiring 28 may be disposed so as to cover a part of the gate trench 14 and a part of the peripheral trench 18. The gate wiring 26 may be formed by two p - The source wiring 28 can be disposed so as to at least partially overlap one of the two p-type regions 22. - The source wiring 28 can be disposed so as to at least partially overlap the other of the two type regions 22. The source wiring 28 can be disposed so as to be spaced apart from the gate wiring 26 and at least n +It may cover the entire mold area 24 .

[0023] The gate wiring 26 and the source wiring 28 can be made of a material containing at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a Cu alloy, and an Al alloy.

[0024] The semiconductor device 10 may further include a plurality of gate contact portions 30. Each gate contact portion 30 may connect a gate electrode 50 disposed in the gate trench 14 to the gate wiring 26. The gate contact portion 30 may extend in the Z-axis direction to penetrate the oxide film 16 located between the gate electrode 50 and the gate wiring 26. The gate contact portion 30 may be disposed in a region where the gate trench 14 and the gate wiring 26 overlap in a plan view. More specifically, the gate contact portion 30 may be disposed in a region where a first end 14P of the gate trench 14 and the gate wiring 26 overlap in a plan view.

[0025] The semiconductor device 10 may further include a plurality of source contact portions 32. Each source contact portion 32 may connect a field plate electrode 52 (see FIGS. 5 and 6 ) disposed in the gate trench 14 to the source wiring 28. This electrically connects the field plate electrode 52 to the source wiring 28. The source contact portion 32 may extend in the Z-axis direction to penetrate the oxide film 16 located between the field plate electrode 52 and the source wiring 28. Each source contact portion 32 may be disposed in a region where the gate trench 14 and the source wiring 28 overlap in a plan view. More specifically, each source contact portion 32 may be disposed in a region where the second end 14Q of the gate trench 14 and the source wiring 28 overlap in a plan view.

[0026] The semiconductor device 10 may further include one or more contact portions 34 that connect a peripheral electrode (not shown) disposed in the peripheral trench 18 to the source wiring 28. The number and positions of the contact portions 34 are not limited to the example shown in FIG. 1 and can be changed as desired.

[0027] The gate contact portion 30, the source contact portion 32, and the contact portion 34 may be made of any metallic material. In one example, the contact portions 30, 32, and 34 may be made of a material including at least one of tungsten (W), Ti, and titanium nitride (TiN).

[0028] [Planar structure of part of semiconductor device] FIG. 2 shows an enlarged view of a part of the planar structure of the semiconductor device 10 of FIG. As shown in FIG. 2, the semiconductor device 10 includes a plurality of mesa regions 60, which are regions between the gate trenches 14 in the semiconductor layer 12. Each of the plurality of mesa regions 60 is surrounded by the gate trench 14 in a plan view. In this embodiment, the plurality of mesa regions 60 are arranged in a matrix. In this embodiment, each of the plurality of mesa regions 60 has a circular shape in a plan view. In this way, by arranging the plurality of mesa regions 60 in a matrix, the gate trenches 14 surrounding these mesa regions 60 have a mesh shape in a plan view.

[0029] Here, the gate trench 14 having a mesh shape in a plan view means that the gate trench 14 includes portions extending in at least two directions perpendicular to the Z-axis direction and includes portions where the gate trenches 14 extending in each direction intersect. In this embodiment, the gate trench 14 includes a first portion 14C extending in the X-axis direction, a second portion 14D extending in the Y-axis direction, and a third portion 14E where the first portion 14C and the second portion 14D intersect. The first portion 14C and the second portion 14D are connected by the third portion 14E.

[0030] The multiple mesa regions 60 include first to fourth mesa regions 61 to 64. The first mesa region 61 and the second mesa region 62 are spaced apart in the X-axis direction in a planar view. The third mesa region 63 is spaced apart from the first mesa region 61 in a direction intersecting the X-axis direction in a planar view. In this embodiment, the third mesa region 63 is spaced apart from the first mesa region 61 in a Y-axis direction orthogonal to the X-axis direction in a planar view. The third mesa region 63 is spaced apart from the second mesa region 62 in a direction intersecting both the X-axis and Y-axis directions in a planar view. The fourth mesa region 64 is spaced apart from the second mesa region 62 in a direction intersecting the X-axis direction in a planar view. In this embodiment, the fourth mesa region 64 is spaced apart from the second mesa region 62 in the Y-axis direction in a planar view. The fourth mesa region 64 is disposed apart from the first mesa region 61 in a direction intersecting both the X-axis direction and the Y-axis direction in a plan view. Here, the X-axis direction is an example of the "first direction."

[0031] The first distance D1, which is the distance between the first mesa region 61 and the second mesa region 62, is smaller than the second distance D2, which is the distance between the second mesa region 62 and the third mesa region 63. The first distance D1 is equal to the third distance D3, which is the distance between the first mesa region 61 and the third mesa region 63. The first distance D1 is smaller than the fourth distance D4, which is the distance between the first mesa region 61 and the fourth mesa region 64. The first distance D1 is equal to the fifth distance D5, which is the distance between the second mesa region 62 and the fourth mesa region 64. The first distance D1 is equal to the sixth distance D6, which is the distance between the third mesa region 63 and the fourth mesa region 64. In this way, the multiple mesa regions 60 arranged in a matrix are arranged at equal pitches in the X-axis direction and the Y-axis direction.

[0032] Here, the first distance D1 can be defined as the shortest distance in the X-axis direction between the first mesa region 61 and the second mesa region 62. The second distance D2 can be defined as the shortest distance in the X-axis direction between the second mesa region 62 and the third mesa region 63 in a direction intersecting the X-axis direction in a planar view. The third distance D3 can be defined as the shortest distance in the Y-axis direction between the first mesa region 61 and the third mesa region 63. The fourth distance D4 can be defined as the shortest distance in the Y-axis direction between the first mesa region 61 and the fourth mesa region 64 in a direction intersecting the X-axis direction in a planar view. The fifth distance D5 can be defined as the shortest distance in the Y-axis direction between the second mesa region 62 and the fourth mesa region 64. The sixth distance D6 can be defined as the shortest distance in the X-axis direction between the third mesa region 63 and the fourth mesa region 64.

[0033] In this embodiment, the areas of the multiple mesa regions 60 are equal to one another in a planar view. More specifically, the first to fourth mesa regions 61 to 64 have first to fourth areas in a planar view, respectively. The first to fourth areas are equal to one another. In other words, the first to fourth mesa regions 61 to 64, which are circular in a planar view, have equal diameters to one another.

[0034] In this embodiment, the first distance D1, the third distance D3, the fifth distance D5, and the sixth distance D6 are smaller than the diameter of the mesa region 60. The second distance D2 and the fourth distance D4 are larger than the diameter of the mesa region 60. The above-mentioned first to sixth distances D1 to D6 can also be said to be the width of the gate trench 14. Therefore, in this embodiment, the width of the gate trench 14 includes a portion smaller than the diameter of the mesa region 60. Furthermore, it can be said that the third portion 14E of the gate trench 14 has a larger width of the gate trench 14 in plan view than the first portion 14C and the second portion 14D of the gate trench 14.

[0035] In this embodiment, the total area of ​​the multiple mesa regions 60 in a plan view is smaller than the area of ​​the gate trench 14 in a plan view. In one example, the total area of ​​the multiple mesa regions 60 in a plan view is smaller than the area of ​​the gate electrode 50 in a plan view.

[0036] The semiconductor device 10 may further include one or more mesa contact portions 33 connected to the mesa regions 60 in a plan view. In this embodiment, the semiconductor device 10 includes a plurality of mesa contact portions 33. The plurality of mesa contact portions 33 are provided corresponding to the plurality of mesa regions 60, respectively. That is, the plurality of mesa contact portions 33 are arranged in a matrix corresponding to the plurality of mesa regions 60 arranged in a matrix. The plurality of mesa contact portions 33 are electrically connected to the source wiring 28 (see FIG. 1). In this embodiment, each mesa contact portion 33 is in contact with the source wiring 28. Each mesa contact portion 33 is also in contact with a body contact region 46 (described later) formed in the semiconductor layer 12. In this manner, the mesa contact portion 33 can connect the body contact region 46 (see FIG. 5) to the source wiring 28. The mesa contact portion 33 can extend in the Z-axis direction so as to penetrate the semiconductor layer 12 and the oxide film 16 located between the body contact region 46 and the source wiring 28. The mesa contact portion 33 penetrates the source region 44 of the semiconductor layer 12 .

[0037] In one example, the mesa contact portion 33 has a circular shape in a plan view. The diameter of the mesa contact portion 33 is smaller than the diameter of the mesa region 60. The mesa contact portion 33 may be arranged concentrically with the mesa region 60 in a plan view. Each mesa contact portion 33 may be made of a material including at least one of W, Ti, and TiN. In this embodiment, each mesa contact portion 33 is made of a material including W.

[0038] [Cross-sectional structure of semiconductor device] The cross-sectional structure of the semiconductor device 10 will be described with reference to FIGS. Fig. 3 shows a cross-sectional structure of the semiconductor device 10 taken along the XY plane at the position of the gate electrode 50 in the Z-axis direction. Fig. 4 shows a cross-sectional structure of the semiconductor device 10 taken along the XY plane at the position of the field plate electrode 52 in the Z-axis direction. Fig. 5 shows a cross-sectional structure of the semiconductor device 10 taken along line F5-F5 in Fig. 1. Fig. 6 shows a cross-sectional structure of the semiconductor device 10 taken along line F6-F6 in Fig. 1.

[0039] As shown in FIG. 5, the semiconductor layer 12 may include a semiconductor substrate 36 including the second surface 12B of the semiconductor layer 12, and an epitaxial layer 38 provided on the semiconductor substrate 36 and including the first surface 12A of the semiconductor layer 12.

[0040] The semiconductor substrate 36 may be made of a material containing Si. In one example, the semiconductor substrate 36 may be an n-type Si substrate. The semiconductor substrate 36 may correspond to the drain region of the MISFET. In one example, the thickness of the semiconductor substrate 36 may be 50 μm or more and 100 μm or less. In another example, the n-type impurity concentration of the semiconductor substrate 36 may be 1×10 18 cm -3 More than 1×10 21 cm -3 In this embodiment, the n-type impurity concentration of the semiconductor substrate 36 can be 1×10 19 cm -3 More than 1×10 20 cm -3 Hereinafter, the n-type will be referred to as the first conductivity type, and the p-type will be referred to as the second conductivity type. The n-type impurity may be, for example, phosphorus (P) or arsenic (As). The p-type impurity may be, for example, boron (B) or Al. In this embodiment, P is introduced into the semiconductor substrate 36 as the n-type impurity. In one example, the resistivity of the semiconductor substrate 36 can be set to 0.5 mΩ·cm or more and 5 mΩ·cm or less.

[0041] The epitaxial layer 38 may be a Si layer epitaxially grown on a Si substrate. The epitaxial layer 38 may include a drift region 40, a body region 42 provided on the drift region 40, and a source region 44 provided in a portion of the body region 42.

[0042] The body region 42 is provided in a surface layer portion closer to the first surface 12A of the semiconductor layer 12. The body region 42 is a p - The p-type impurity concentration of the body region 42 may be, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The body region 42 may have a thickness of, for example, 0.5 μm or more and 1.5 μm or less. The body region 42 is provided in each of the multiple mesa regions 60. The body region 42 is provided across the entirety of each mesa region 60 in plan view.

[0043] The source region 44 is provided in a surface layer portion of the body region 42. The source region 44 is a region that includes the first surface 12A of the semiconductor layer 12. The source region 44 includes an n-type impurity having a higher concentration than the drift region 40. + The surface of the source region 44 (second surface 12B) may be an n-type region shown in FIG. + The source region 44 corresponds to the n-type region 24. The impurity concentration of the source region 44 may be higher than the impurity concentration of the body region 42. The n-type impurity concentration of the source region 44 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following can be configured: The source region 44 is provided in each of the plurality of mesa regions 60. The source region 44 is provided across the entirety of each mesa region 60 in plan view.

[0044] The body region 42 is provided with a body contact region 46. More specifically, the body contact region 46 is provided between two gate trenches 14 adjacent to each other in the X-axis direction in the body region 42. A plurality of body contact regions 46 are provided corresponding to the plurality of mesa regions 60. Each body contact region 46 is partially provided in each mesa region 60 in plan view. In one example, each body contact region 46 is provided in the center of each mesa region 60 in plan view. In one example, the dimension of each body contact region 46 in the Y-axis direction is smaller than the dimension of the gate trench 14 in the Y-axis direction. In one example, the dimension of each body contact region 46 in the Y-axis direction is smaller than the dimension of the source region 44 in the Y-axis direction.

[0045] The body contact region 46 is a p-type region containing p-type impurities. + The p-type impurity concentration of the body contact region 46 is higher than that of the body region 42. The p-type impurity concentration of the body contact region 46 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The detailed structure of the epitaxial layer 38 will be described later.

[0046] The semiconductor device 10 includes a vertical transistor 48. In this embodiment, the vertical transistor 48 may be a trench-gate MOSFET. The semiconductor layer 12 constitutes a part of the vertical transistor 48. The vertical transistor 48 may be provided in a region where the gate trench 14 is disposed. The semiconductor device 10 may further include a drain electrode 54 provided on the second surface 12B of the semiconductor layer 12. The drain electrode 54 may be made of at least one of Ti, Ni, Au, Ag, Cu, Al, a Cu alloy, and an Al alloy. The vertical transistor 48 is configured to enable control of the flow of electrons in the vertical direction (Z-axis direction) between the source wiring 28 and the drain electrode 54 via a channel formed in the semiconductor layer 12.

[0047] The gate trench 14 includes a sidewall 14A and a bottom wall 14B. The sidewall 14A may extend along the Z-axis direction or may be inclined relative to the Z-axis direction. In one example, the sidewall 14A may be inclined relative to the Z-axis direction so that the width of the gate trench 14 decreases toward the bottom wall 14B of the gate trench 14. The bottom wall 14B does not necessarily have to be flat, and may be partially or entirely curved, for example.

[0048] 3 and 4, in this embodiment, the portion of the sidewall 14A of the gate trench 14 surrounding the mesa region 60 is circular in plan view. Therefore, the width of the gate trench 14 is smallest at the center of the adjacent mesa region 60. In other words, the width of the gate trench 14 increases with increasing distance from the center of the adjacent mesa region 60.

[0049] 5, the gate trench 14 penetrates the body region 42 of the semiconductor layer 12 to reach the drift region 40. In one example, the gate trench 14 may have a depth of 2 μm or more and 10 μm or less. In this embodiment, the depth of the gate trench 14 is approximately 2 μm. Here, the depth of the gate trench 14 can be defined as the distance in the Z-axis direction from the first surface 12A of the semiconductor layer 12 to the bottom wall 14B of the gate trench 14 (or the deepest part of the gate trench 14 if the bottom wall 14B is curved).

[0050] An oxide film 16 is buried in the gate trench 14. Here, the oxide film 16 buried in the gate trench 14 is referred to as a "trench oxide film 17." A gate electrode 50 and a field plate electrode 52 are buried in the gate trench 14 via the trench oxide film 17. The gate electrode 50 may be electrically connected to the gate wiring 26. This allows a gate voltage to be applied to the gate electrode 50. The field plate electrode 52 is disposed in the gate trench 14 between a bottom surface 50A of the gate electrode 50 and a bottom wall 14B of the gate trench 14. The field plate electrode 52 can be set to the same potential as the source region 44. Applying a source voltage to the field plate electrode 52 alleviates electric field concentration in the gate trench 14, thereby improving the dielectric strength of the semiconductor device 10.

[0051] As shown in FIGS. 3 and 4, the trench oxide film 17 surrounds the entire periphery of each mesa region 60 in plan view. 3, the trench oxide film 17 (hereinafter referred to as trench oxide film 17A) in contact with the side surface of the gate electrode 50 is provided so as to surround each mesa region 60 in a plan view. The trench oxide film 17A has an annular shape surrounding the mesa region 60 in a plan view. In one example, the thickness of the trench oxide film 17A is constant around the periphery of the mesa region 60 in a plan view.

[0052] As shown in FIG. 4, trench oxide film 17 (hereinafter referred to as trench oxide film 17B) in contact with the side surface of field plate electrode 52 is provided so as to surround each mesa region 60 in plan view. Trench oxide film 17B has a circular ring shape surrounding mesa region 60 in plan view. In one example, the thickness of trench oxide film 17B is constant around mesa region 60 in plan view. The thickness of trench oxide film 17B is thicker than the thickness of trench oxide film 17A shown in FIG. 3. The thickness of trench oxide film 17 is set depending on the breakdown voltage required for semiconductor device 10.

[0053] 5, the gate electrode 50 is disposed closer to the body region 42 than the drift region 40 in the Z-axis direction. In one example, the gate electrode 50 may be disposed such that its bottom surface 50A is not closer to the bottom wall 14B of the gate trench 14 than the boundary 41 between the drift region 40 and the body region 42 in the Z-axis direction. In one example, the gate electrode 50 may be disposed such that its bottom surface 50A is at the same position in the Z-axis direction as the boundary 41 between the drift region 40 and the body region 42. In another example, the gate electrode 50 may be disposed such that its bottom surface 50A is closer to the second surface 12B of the semiconductor layer 12 than the boundary 41 between the drift region 40 and the body region 42.

[0054] As shown in FIG. 3 , in this embodiment, the gate electrode 50 includes a gate curved portion 51 that is provided along the outer shape of the mesa region 60. The gate curved portion 51 is provided so as to surround the mesa region 60 in a plan view. Therefore, the width WG2 of the gate electrode 50 between the second mesa region 62 and the third mesa region 63 is greater than the width WG1 of the gate electrode 50 between the first mesa region 61 and the second mesa region 62. The width WG of the gate electrode 50 decreases toward the line LA that connects the centers of adjacent mesa regions 60. The width WG of the gate electrode 50 is smallest at the line LA. In other words, the width WG of the gate electrode 50 increases with increasing distance from the line LA that connects the centers of adjacent mesa regions 60.

[0055] Furthermore, the thickness TG1 of the gate electrode 50 shown in Fig. 5 is equal to the thickness TG2 of the gate electrode 50 shown in Fig. 6. In one example, the gate electrode 50 is configured to have a constant thickness throughout.

[0056] 5, the field plate electrode 52 has a generally rectangular shape with its length (longitudinal direction) in the Z-axis direction and its width (shortitudinal direction) in the X-axis direction. In the example shown in FIG. 5, the field plate electrode 52 has a tapered shape that narrows toward the bottom wall 14B of the gate trench 14. Both the gate electrode 50 and the field plate electrode 52 can be made of, for example, conductive polysilicon.

[0057] As shown in FIG. 4 , in this embodiment, the field plate electrode 52 includes a field curved portion 53 that is provided along the outer shape of the mesa region 60. The field curved portion 53 is provided so as to surround the mesa region 60 in a plan view. Therefore, the width WF2 of the field plate electrode 52 between the second mesa region 62 and the third mesa region 63 is greater than the width WF1 of the field plate electrode 52 between the first mesa region 61 and the second mesa region 62. The width WF of the field plate electrode 52 decreases toward the line LA connecting the centers of adjacent mesa regions 60. The width WF of the field plate electrode 52 is smallest at the line LA. In other words, the width WF of the field plate electrode 52 increases with increasing distance from the line LA connecting the centers of adjacent mesa regions 60. The thickness TF2 of the field plate electrode 52 shown in FIG. 6 is equal to the thickness TF1 of the field plate electrode 52 shown in FIG. 5 .

[0058] 5 and 6, in this embodiment, the mesa contact portion 33 has a cylindrical shape. Note that the mesa contact portion 33 may have a tapered shape that narrows from the surface of the oxide film 16 toward the second surface 12B of the semiconductor layer 12, which will be described later.

[0059] Here, the ratio (LZ / LX) of the length LZ of the mesa contact portion 33 in the Z-axis direction to the maximum length LX of the mesa contact portion 33 in the X-axis direction is equal to or greater than 1 and equal to or less than 5. When the mesa contact portion 33 is tapered, the maximum length LX of the mesa contact portion 33 in the X-axis direction is the length of the end face of the mesa contact portion 33 that contacts the source wiring 28 in the X-axis direction. The maximum length LX of the mesa contact portion 33 in the X-axis direction can also be said to be the maximum diameter of the mesa contact portion 33. The length LZ of the mesa contact portion 33 in the Z-axis direction can be defined as the distance in the Z-axis direction between the end face of the mesa contact portion 33 that contacts the source wiring 28 and the end face of the mesa contact portion 33 that contacts the body contact region 46 in the Z-axis direction. The shape of the mesa contact portion 33 in a plan view can be changed as desired.

[0060] [Operation of the embodiment] The operation of the semiconductor device 10 of this embodiment will now be described. A known conventional semiconductor device has a configuration in which multiple gate trenches are arranged in a stripe pattern in a plan view. An oxide film is provided within each gate trench. In the conventional semiconductor device, the region between adjacent gate trenches forms a mesa region. Therefore, the oxide film contacts both sides of the mesa region in the direction in which the gate trenches are arranged.

[0061] In the semiconductor device 10 of this embodiment, the multiple mesa regions 60 are spaced apart from one another. The trench oxide film 17 in the gate trench 14 is provided to surround each mesa region 60 in a planar view. As a result, the ratio of the length of the interface between the mesa region 60 and the trench oxide film 17 to the area of ​​the mesa region 60 in a planar view is larger than that of the semiconductor device of the comparative example. As a result, the stress applied to the mesa region 60 from the trench oxide film 17 is larger, making the mesa region 60 more likely to distort. Therefore, the electron mobility is increased due to the distortion of the mesa region 60, making it easier for current to flow from the drain electrode 54 to the source wiring 28. As a result, the on-resistance of the semiconductor device 10 can be reduced compared to that of the semiconductor device of the comparative example.

[0062] [Effects of the embodiment] According to the semiconductor device 10 of this embodiment, the following effects can be obtained. (1) The semiconductor device 10 includes a semiconductor layer 12 including a first surface 12A and a second surface 12B opposite the first surface 12A, gate trenches 14 extending from the first surface 12A toward the second surface 12B of the semiconductor layer 12, a plurality of mesa regions 60 in the semiconductor layer 12 between the gate trenches 14 and surrounded by the gate trenches 14 in a planar view, an oxide film 16 provided on the first surface 12A of the semiconductor layer 12 and in the gate trenches 14, a gate electrode 50 embedded in the gate trench 14 with the oxide film 16 interposed therebetween, and a field plate electrode 52 positioned in the gate trench 14 at a distance closer to the second surface 12B than the gate electrode 50 and embedded with the oxide film 16 interposed therebetween. The multiple mesa regions 60 include a first mesa region 61 and a second mesa region 62 that are spaced apart in the X-axis direction in a plan view, and a third mesa region 63 that is spaced apart from the first mesa region 61 in a direction intersecting the X-axis direction in a plan view. The multiple mesa regions 60 form the gate trench 14 in a mesh shape in a plan view.

[0063] With this configuration, since the oxide film 16 surrounds the entire periphery of each mesa region 60, the oxide film 16 tends to increase the stress applied to each mesa region 60. Since each mesa region 60 is distorted due to the stress, the electron mobility is improved. Therefore, the on-resistance of the semiconductor device 10 can be reduced.

[0064] (2) Each of the multiple mesa regions 60 is circular in plan view. According to this configuration, the ratio of the length of the interface between the mesa region 60 and the trench oxide film 17 to the area of ​​the mesa region 60 in a planar view is larger than when the mesa region 60 is rectangular in a planar view. Therefore, the stress applied to the mesa region 60 is larger.

[0065] (3) The gate electrode 50 includes a gate curved portion 51 provided along the outer shape of the mesa region 60 . According to this configuration, the gate curved portion 51 can make the distance between the gate electrode 50 and the mesa region 60 constant. Therefore, it is possible to prevent current from being unevenly distributed depending on the location of the mesa region 60 in plan view.

[0066] (4) The field plate electrode 52 includes a field curved portion 53 provided along the outer shape of the mesa region 60 . According to this configuration, the field curvature portion 53 can keep the distance between the field plate electrode 52 and the mesa region 60 constant. Therefore, it is possible to prevent the effect of alleviating electric field concentration from varying depending on the location of the mesa region 60 in plan view.

[0067] (5) The thickness of the trench oxide film 17B in contact with the side surface of the field plate electrode 52 is thicker than the thickness of the trench oxide film 17A in contact with the side surface of the gate electrode 50. With this configuration, the stress generated in the portion of the mesa region 60 that contacts the trench oxide film 17B is greater than the stress generated in the portion of the mesa region 60 that contacts the trench oxide film 17A. Therefore, the strain in the portion of the mesa region 60 that contacts the trench oxide film 17B is greater, which can improve the electron mobility in that portion.

[0068] (6) The semiconductor device 10 includes a body contact region 46 provided in the body region 42, and a mesa contact portion 33 that penetrates the oxide film 16 and the source region 44 and contacts the body contact region 46. The body contact region 46 has a higher impurity concentration than the body region 42. A plurality of mesa contact portions 33 are provided spaced apart from one another in correspondence with the plurality of mesa regions 60. The plurality of mesa contact portions 33 are electrically connected to the source wiring 28.

[0069] According to this configuration, the current flowing through each mesa region 60 flows to the source wiring 28 via the mesa contact portion 33 provided in each mesa region 60. Therefore, the on-resistance of the semiconductor device 10 can be reduced compared to a configuration including a mesa region 60 without a mesa contact portion 33.

[0070] <Example of change> The above embodiment can be modified as follows: Furthermore, the above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0071] The shape and size of the multiple mesa regions 60 can be changed as desired. For example, in a plan view, the area of ​​at least one mesa region 60 among the multiple mesa regions 60 may be different from the area of ​​the remaining mesa regions 60. For example, in a plan view, the shape of at least one mesa region 60 among the multiple mesa regions 60 may be different from the shape of the remaining mesa regions 60.

[0072] As modified examples of the plurality of mesa regions 60, first to third modified examples shown in FIGS. 7 to 9 can be given. As shown in Fig. 7, in the first modified example, the multiple mesa regions 60 are rectangular in plan view. In the example shown in Fig. 7, each mesa region 60 is square in plan view. Therefore, the gate trench 14 has a lattice shape in plan view. Furthermore, the gate electrode 50 also has a lattice shape in plan view.

[0073] 8, in the second modified example, the multiple mesa regions 60 are quadrangular in plan view. Both the first mesa region 61 and the third mesa region 63 are square in plan view. The second mesa region 62 is rectangular in plan view. The second mesa region 62 is arranged such that the X-axis direction is the long side direction and the Y-axis direction is the short side direction.

[0074] In the second modification, the first mesa region 61 has a first area in a plan view. The second mesa region 62 has a second area in a plan view. The first area is different from the second area. More specifically, the second area is at least twice the first area.

[0075] In this case, the mesa contact portion 33 corresponding to the second mesa region 62 may have a rectangular shape extending in the X-axis direction. In another example, a plurality of mesa contact portions 33 corresponding to the second mesa region 62 may be provided spaced apart in the X-axis direction.

[0076] As shown in FIG. 9 , in the third modified example, the multiple mesa regions 60 are rectangular in plan view. In the third modified example, curved portions 65 that convex outward from the mesa region 60 are provided at the four corners of each mesa region 60. In the third modified example, curved portions 65 are provided at all corners of each mesa region 60, but this is not limited to this. It is sufficient that at least one of the multiple mesa regions 60 has a curved portion 65 at its corner. In other words, it can be said that at least one of the multiple mesa regions 60 includes a curved portion 65 provided at the corner of the mesa region 60 in plan view.

[0077] Furthermore, the shape of at least one of the multiple mesa regions 60 in plan view is not limited to a rectangle or a circle, but may be a polygon with pentagons or more sides. Furthermore, the shape of at least one of the multiple mesa regions 60 in plan view may be an ellipse. In one example, as shown in FIG. 10 , each of the multiple mesa regions 60 may be a hexagon.

[0078] The arrangement of the multiple mesa regions 60 is not limited to a matrix and can be changed as desired. For example, the multiple mesa regions 60 may be arranged in a staggered pattern, as shown in FIGS. 11 and 12 . More specifically, the third mesa region 63 of the multiple mesa regions 60 is arranged offset in the X-axis direction relative to the first mesa region 61 and the second mesa region 62. For example, the third mesa region 63 is arranged between the first mesa region 61 and the second mesa region 62 in the X-axis direction. When viewed from the Y-axis direction, the third mesa region 63 may be arranged so as to partially overlap both the first mesa region 61 and the second mesa region 62.

[0079] 11, a first distance D1 between the first mesa region 61 and the second mesa region 62 is greater than a second distance D2 between the second mesa region 62 and the third mesa region 63. In one example, the first distance D1 is greater than a third distance D3 between the first mesa region 61 and the third mesa region 63. The second distance D2 is equal to the third distance D3.

[0080] 12, a first distance D1 between the first mesa region 61 and the second mesa region 62 is equal to a second distance D2 between the second mesa region 62 and the third mesa region 63. In one example, the first distance D1 is equal to a third distance D3 between the first mesa region 61 and the third mesa region 63. The second distance D2 is equal to the third distance D3.

[0081] 11 and 12 are circular in plan view, the staggered mesa regions 60 are not limited to this. The staggered mesa regions 60 may be, for example, hexagonal as shown in FIG.

[0082] In plan view, the areas of the multiple mesa regions 60 may be different from one another. The total area of ​​the multiple mesa regions 60 in plan view may be equal to or greater than the area of ​​the gate trench 14 in plan view.

[0083] The total area of ​​the plurality of mesa regions 60 in plan view may be equal to or greater than the area of ​​the gate electrode 50 in plan view. The number of mesa regions 60 can be changed arbitrarily. In one example, the number of mesa regions 60 may be one.

[0084] The shape of the gate electrode 50 in plan view can be changed as desired. For example, the gate electrode 50 does not need to have a shape that follows the outline of the mesa region 60 in plan view. In other words, the gate curved portion 51 may be omitted from the gate electrode 50.

[0085] The shape of the field plate electrode 52 in plan view can be changed as desired. For example, the field plate electrode 52 does not have to have a shape that follows the outline of the mesa region 60 in plan view. In other words, the field curved portion 53 may be omitted from the field plate electrode 52.

[0086] The width of the gate trench 14 does not have to include any portion that is smaller than the diameter of the mesa region 60. In other words, the width of the gate trench 14 may be equal to or larger than the diameter of the mesa region 60 throughout its entirety in a plan view. In another example, the width of the gate trench 14 may be smaller than the diameter of the mesa region 60 throughout its entirety in a plan view.

[0087] The configuration of the first end 14P and the second end 14Q of the gate trench 14 can be changed as desired. In one example, the number of each of the first end 14P and the second end 14Q may be three or less. That is, as long as a structure can be provided in which the field plate electrode 52 is electrically connected to the source wiring 28 via the source contact portion 32, the number of first end 14P may be one. Also, as long as a structure can be provided in which the gate electrode 50 is electrically connected to the gate wiring 26 via the gate contact portion 30, the number of second end 14Q may be one.

[0088] The ratio (LZ / LX) of the length LZ of the mesa contact portion 33 in the Z-axis direction to the maximum length LX of the mesa contact portion 33 in the X-axis direction can be changed as desired. For example, the ratio (LZ / LX) may be less than 1 or may be 5 or greater.

[0089] The semiconductor substrate 36 may be a SiC substrate instead of a Si substrate. One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent.

[0090] The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0091] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, the various structures according to this disclosure are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0092] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0093] [Appendix 1] a semiconductor layer (12) including a first surface (12A) and a second surface (12B) opposite to the first surface (12A); a trench (14) extending from the first surface (12A) of the semiconductor layer (12) toward the second surface (12B); a plurality of mesa regions (60) in the semiconductor layer (12) between the trenches (12), the mesa regions (60) being surrounded by the trenches (14) when viewed in the thickness direction (Z) of the semiconductor layer (12); an oxide film (17) provided on the first surface (12A) of the semiconductor layer (12) and in the trench (14); a gate electrode (50) embedded in the trench (14) via the oxide film (17); a field plate electrode (52) disposed in the trench (14) closer to the second surface (12B) than the gate electrode (50) and embedded via the oxide film (17); Equipped with The plurality of mesa regions (60) are a first mesa region (61) and a second mesa region (62) spaced apart in a first direction (X) when viewed from the thickness direction (Z); a third mesa region (63) provided apart from the first mesa region (61) in a direction intersecting the first direction (X) when viewed from the thickness direction (Z); Including, The trench (14) has a mesh shape when viewed from the thickness direction (Z) due to the plurality of mesa regions (60). A semiconductor device (10).

[0094] [Appendix 2] At least one of the plurality of mesa regions (60) is circular when viewed from the thickness direction (Z). 2. The semiconductor device according to claim 1.

[0095] [Appendix 3] Each of the plurality of mesa regions (60) is circular when viewed from the thickness direction (Z). 3. The semiconductor device according to claim 2.

[0096] [Appendix 4] At least one of the plurality of mesa regions (60) is rectangular when viewed from the thickness direction (Z). 2. The semiconductor device according to claim 1.

[0097] [Appendix 5] At least one of the plurality of mesa regions (60) is a polygon having five or more sides when viewed from the thickness direction (Z). 2. The semiconductor device according to claim 1.

[0098] [Appendix 6] At least one of the plurality of mesa regions (60) includes a curved portion (65) provided at a corner of the mesa region (60) when viewed from the thickness direction (Z). 6. The semiconductor device according to claim 4 or 5.

[0099] [Appendix 7] A first distance (D1) between the first mesa region (61) and the second mesa region (62) is smaller than a second distance (D2) between the second mesa region (62) and the third mesa region (63). 7. The semiconductor device according to any one of claims 1 to 6.

[0100] [Appendix 8] A first distance (D1) between the first mesa region (61) and the second mesa region (62) is equal to a third distance (D3) between the first mesa region (61) and the third mesa region (63). 8. The semiconductor device according to claim 7.

[0101] [Appendix 9] The plurality of mesa regions (60) are arranged in a matrix when viewed from the thickness direction (Z). 9. The semiconductor device according to claim 7 or 8.

[0102] [Appendix 10] A first distance (D1) between the first mesa region (61) and the second mesa region (62) is equal to a second distance (D2) between the second mesa region (62) and the third mesa region (63). 7. The semiconductor device according to any one of claims 1 to 6.

[0103] [Appendix 11] The third mesa region (63) is arranged to be shifted in the first direction (X) with respect to the first mesa region (61) and the second mesa region (62). 11. The semiconductor device according to claim 10.

[0104] [Appendix 12] the first mesa region (61) has a first area when viewed from the thickness direction (Z), the second mesa region (62) has a second area when viewed from the thickness direction (Z), The first area and the second area are different 12. The semiconductor device according to any one of claims 1 to 11.

[0105] [Appendix 13] The second area is at least twice the first area. 13. The semiconductor device according to claim 12.

[0106] [Appendix 14] The trench (14) has a predetermined width, The trench (14) includes a portion where the width of the trench (14) is smaller than the diameter of the mesa region (60). 4. The semiconductor device according to claim 2 or 3.

[0107] [Appendix 15] The gate electrode (50) includes a gate curved portion (51) provided along the outer shape of the mesa region (60). 4. The semiconductor device according to claim 2 or 3.

[0108] [Appendix 16] The field plate electrode (52) includes a field curved portion (53) provided along the outer shape of the mesa region (60). 4. The semiconductor device according to claim 2 or 3.

[0109] [Appendix 17] The total area of ​​the plurality of mesa regions (60) as viewed in the thickness direction (Z) is smaller than the area of ​​the trench (14) as viewed in the thickness direction (Z). 17. The semiconductor device according to any one of claims 1 to 16.

[0110] [Appendix 18] a body region (42) provided in a surface layer portion of the mesa region (60) closer to the first surface; a source region (44) provided in a surface layer portion of the body region (42); a source wiring (28) provided on the oxide film (16) and electrically connected to the source region (44); a drain electrode (54) provided on the second surface (12B); Contains 18. The semiconductor device according to any one of claims 1 to 17.

[0111] [Appendix 19] a body contact region (46) provided in the body region (42) and having a higher impurity concentration than the body region (42); a mesa contact portion (33) that penetrates the oxide film (16) and the source region (44) and contacts the body contact region (46); Including, The mesa contact portions (33) are provided in plurality, spaced apart from one another, corresponding to the plurality of mesa regions (60), The plurality of mesa contact portions (33) are electrically connected to the source wiring (28). 19. The semiconductor device according to claim 18.

[0112] [Appendix 20] the semiconductor layer (12) is made of a material containing Si, The oxide film (16 / 17) is made of a material containing SiO 20. The semiconductor device according to any one of appendices 1 to 19.

[0113] [Appendix 21] a semiconductor layer (12) including a first surface (12A) and a second surface (12B) opposite to the first surface (12A); a trench (14) extending from the first surface (12A) of the semiconductor layer (12) toward the second surface (12B); a mesa region (60) in the semiconductor layer (12) between the trenches (14), the mesa region (60) being surrounded by the trenches (14) when viewed in the thickness direction (Z) of the semiconductor layer (12); an oxide film (16 / 17) provided on the first surface (12A) of the semiconductor layer (12) and in the trench (14); a gate electrode (50) embedded in the trench (14) via the oxide film (17); a field plate electrode (52) disposed in the trench (14) closer to the second surface (12B) than the gate electrode (50) and embedded via the oxide film (16); Equipped with The entire periphery of the mesa region (60) is surrounded by the oxide film (17) when viewed from the thickness direction (Z). A semiconductor device (10).

[0114] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0115] 10...Semiconductor device 12...Semiconductor layer 12A…Side 1 12B…Second side 14...Gate trench 14A…Side wall 14B…Bottom wall 14P...1st end 14Q...Second end 14C…Part 1 14D…Second part 14E…3rd part 16...Oxide film 17, 17A, 17B...Trench oxide film 18...Peripheral trench 20...n - type area 22...p - type area 24...n + type area 26...Gate wiring 28...Source wiring 30...Gate contact part 32...Source contact part 33...Mesa contact part 34...Contact part 36...Semiconductor substrate 38...Epitaxial layer 38A...First epitaxial layer 38B: Second epitaxial layer 38C…boundary 40...Drift region 41…boundary 42...Body area 44...Source region 46...Body contact area 48...Vertical transistor 50...Gate electrode 50A...Bottom 51...Gate curved section 52...Field plate electrode 53...Field curve 54...Drain electrode 60...Mesa area 61~64...1st to 4th mesa regions 65...Bend D1: First distance between the first mesa region and the second mesa region D2: Second distance between the second mesa region and the third mesa region D3: Third distance between the first mesa region and the third mesa region TF1: Thickness of the field plate electrode between the first and second mesa regions TF2: Thickness of the field plate electrode between the second and third mesa regions TG1: Thickness of the gate electrode between the first mesa region and the second mesa region TG2: Thickness of the gate electrode between the second mesa region and the third mesa region WF: Width of field plate electrode WF1: Width of the field plate electrode between the first and second mesa regions WF2: Width of the field plate electrode between the second and third mesa regions WG: gate electrode width WG1: width of the gate electrode between the first mesa region and the second mesa region WG2: width of the gate electrode between the second mesa region and the third mesa region LA: A line connecting the centers of adjacent mesa areas

Claims

1. a semiconductor layer including a first surface and a second surface opposite the first surface; a trench extending from the first surface to the second surface of the semiconductor layer; a plurality of mesa regions in the semiconductor layer between the trenches, the mesa regions being surrounded by the trenches when viewed in a thickness direction of the semiconductor layer; an oxide film provided on the first surface of the semiconductor layer and in the trench; a gate electrode embedded in the trench via the oxide film; a field plate electrode disposed in the trench closer to the second surface than the gate electrode and embedded with the oxide film interposed therebetween; Equipped with The plurality of mesa regions include: a first mesa region and a second mesa region spaced apart in a first direction when viewed from the thickness direction; a third mesa region provided apart from the first mesa region in a direction intersecting the first direction when viewed from the thickness direction; Including, The trench has a mesh shape when viewed from the thickness direction due to the plurality of mesa regions. Semiconductor device.

2. At least one of the plurality of mesa regions is circular when viewed from the thickness direction. The semiconductor device according to claim 1 .

3. Each of the plurality of mesa regions is circular when viewed from the thickness direction. The semiconductor device according to claim 2 .

4. At least one of the plurality of mesa regions has a rectangular shape when viewed from the thickness direction. The semiconductor device according to claim 1 .

5. At least one of the plurality of mesa regions has a polygonal shape having five or more sides when viewed from the thickness direction. The semiconductor device according to claim 1 .

6. At least one of the plurality of mesa regions includes a curved portion provided at a corner of the mesa region when viewed from the thickness direction. The semiconductor device according to claim 4 .

7. A first distance between the first mesa region and the second mesa region is smaller than a second distance between the second mesa region and the third mesa region. The semiconductor device according to claim 1 .

8. A first distance between the first mesa region and the second mesa region is equal to a third distance between the first mesa region and the third mesa region. The semiconductor device according to claim 7 .

9. The plurality of mesa regions are arranged in a matrix when viewed from the thickness direction. The semiconductor device according to claim 7 .

10. A first distance between the first mesa region and the second mesa region is equal to a second distance between the second mesa region and the third mesa region. The semiconductor device according to claim 1 .

11. The third mesa region is arranged to be shifted in a first direction with respect to the first mesa region and the second mesa region. The semiconductor device according to claim 10.

12. the first mesa region has a first area when viewed in the thickness direction, the second mesa region has a second area when viewed in the thickness direction, The first area and the second area are different The semiconductor device according to claim 1 .

13. The second area is at least twice the first area. The semiconductor device according to claim 12.

14. the trench has a predetermined width; The trench includes a portion where the width of the trench is smaller than the diameter of the mesa region. The semiconductor device according to claim 2 .

15. The gate electrode includes a gate curved portion provided along the outer shape of the mesa region. The semiconductor device according to claim 2 .

16. The field plate electrode includes a field curvature portion provided along the outer shape of the mesa region. The semiconductor device according to claim 2 .

17. The total area of ​​the plurality of mesa regions as viewed in the thickness direction is smaller than the area of ​​the trench as viewed in the thickness direction. The semiconductor device according to claim 1 .

18. a body region provided in a surface layer portion of the mesa region closer to the first surface; a source region provided in a surface layer portion of the body region; a source wiring provided on the oxide film and electrically connected to the source region; a drain electrode provided on the second surface; Contains The semiconductor device according to claim 1 .

19. a body contact region provided in the body region and having a higher impurity concentration than the body region; a mesa contact portion that penetrates the oxide film and the source region and contacts the body contact region; Including, a plurality of the mesa contact portions are provided spaced apart from one another in correspondence with the plurality of mesa regions; The plurality of mesa contact portions are electrically connected to the source wiring.

19. The semiconductor device according to claim 18.

20. the semiconductor layer is made of a material containing Si, The oxide film is made of a material containing SiO. The semiconductor device according to any one of claims 1 to 19.

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