Vehicle-mounted device, memory updating method, and memory updating program

Abstract

To reduce processing delay of a core in a configuration in which a plurality of cores access a shared memory.SOLUTION: An in-vehicle device mounted on a vehicle includes three or more cores, three or more local memories respectively provided corresponding to the three or more cores, and a shared memory, wherein the core estimates a waiting time until an update process is performed when the core needs to wait for a turn to perform the update process of updating the shared memory, and the core performs a data saving process of temporarily storing update target data in the local memory corresponding to the core and performing another process different from the update process when the waiting time is equal to or longer than a predetermined time.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to an in-vehicle device, a memory updating method, and a memory updating program. [Background technology]

[0002] Technologies for reducing the processing load on a processor core in an in-vehicle device have been developed. For example, Patent Document 1 (JP 2018-67135 A) discloses the following technology. That is, a vehicle control device is a vehicle control device that controls the operation of a vehicle, and is characterized by including: a storage unit that stores a task table that defines a calculation unit that should execute a control task for controlling the operation of the vehicle; first and second calculation units that execute the control task according to the definitions in the task table; and an update unit that updates the task table when the vehicle control device starts or shuts down. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-67135 [Patent Document 2] Special Publication No. 2017-504089 [Patent Document 3] Special Publication No. 2021-520585 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, as vehicles have become more sophisticated, the processing load on in-vehicle devices has tended to increase, and there has been a demand for the widespread use of in-vehicle devices equipped with processors equipped with multiple cores.

[0005] In an in-vehicle device, for example, when multiple cores jointly execute a certain function, the multiple cores may access memory at the same time. To prevent such simultaneous access to memory, it is conceivable to restrict memory access by other cores while one core is accessing memory. In this case, a processing delay occurs in the function executed by the core whose memory access is restricted. The greater the number of cores waiting to access memory, the greater the processing delay in the in-vehicle device.

[0006] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide an in-vehicle device, a memory update method, and a memory update program that can reduce core processing delays in a configuration in which multiple cores access a shared memory. [Means for solving the problem]

[0007] The on-board device of the present disclosure is an on-board device mounted on a vehicle, and comprises three or more cores, three or more local memories provided corresponding to the three or more cores, respectively, and a shared memory, and when a core needs to wait its turn to perform an update process to update the shared memory, the core estimates the waiting time until the update process is performed, and when the waiting time is equal to or longer than a predetermined time, the core performs a data evacuation process in which the data to be updated is temporarily stored in the local memory corresponding to the core, and other processing different from the update process is performed.

[0008] One aspect of the present disclosure can be realized not only as an in-vehicle device equipped with such a characteristic processing unit, but also as a semiconductor integrated circuit that realizes part or all of the in-vehicle device, or as a system that includes the in-vehicle device. [Effects of the Invention]

[0009] According to the present disclosure, in a configuration in which multiple cores access a shared memory, it is possible to reduce the processing delay of the cores. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of an in-vehicle system according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of the vehicle-mounted relay device according to the embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram illustrating an example of core numbers assigned to each core in the vehicle-mounted relay device according to the embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating an example of data saving processing by a core in the vehicle-mounted relay device according to the embodiment of the present disclosure. [Figure 5] FIG. 5 is a flowchart defining an example of an operation procedure when the core of the in-vehicle relay device according to the embodiment of the present disclosure performs a data saving process. [Figure 6] FIG. 6 is a diagram for explaining an update process by the core in the first modification of the vehicle-mounted relay device according to the embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating an example of an update process by the first modification of the vehicle-mounted relay device according to the embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram illustrating an example of an update process by the first modification of the vehicle-mounted relay device according to the embodiment of the present disclosure. [Figure 9] FIG. 9 is a flowchart defining an example of an operation procedure when the core of the first modification of the vehicle-mounted relay device according to the embodiment of the present disclosure performs a data saving process. [Figure 10] FIG. 10 is a flowchart defining an example of an operation procedure when the core of the first modification of the vehicle-mounted relay device according to the embodiment of the present disclosure performs a data saving process. [Figure 11] FIG. 11 is a diagram illustrating a configuration of a second modified example of an in-vehicle system according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram illustrating a configuration of a third modification of the in-vehicle system according to the embodiment of the present disclosure. [Figure 13]FIG. 13 is a conceptual diagram illustrating functions executed by each core of the vehicle-mounted relay device according to the third modification of the embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] First, the contents of the embodiments of the present disclosure will be listed and described. (1) An on-board device according to an embodiment of the present disclosure is an on-board device mounted on a vehicle, and includes three or more cores, three or more local memories corresponding to the three or more cores, and a shared memory. When a core needs to wait its turn to perform an update process to update the shared memory, the core estimates the waiting time until the update process is performed. When the waiting time is equal to or longer than a predetermined time, the core performs a data evacuation process in which the data to be updated is temporarily stored in the local memory corresponding to the core, and other processing different from the update process is performed.

[0012] In this way, if the wait time until the update process to update the shared memory is equal to or longer than a predetermined time, the core temporarily stores the data to be updated in the local memory and performs other processing other than the update process, thereby reducing the processing delay of the core that has a long wait time until the update process. Therefore, in a configuration in which multiple cores access the shared memory, the processing delay of the core can be reduced.

[0013] (2) In (1) above, the core may determine whether to perform the data evacuation process or to wait without performing the data evacuation process depending on the number of cores that the core itself is performing the update process.

[0014] With this configuration, it is possible to determine whether or not to perform data saving processing based on simple criteria.

[0015] (3) In the above (2), the three or more cores may be given a period of a predetermined length in which each of the cores can perform the update process in turn.

[0016] This configuration allows each core to have a more equal opportunity to access the shared memory.

[0017] (4) In any of (1) to (3) above, the core may determine whether to perform the data evacuation process or to wait without performing the data evacuation process depending on the state of the vehicle.

[0018] This configuration allows the determination of whether to perform data evacuation processing to be made more appropriately depending on the state of the vehicle. For example, when the vehicle is running, the data evacuation processing is performed in the core that executes functions related to the running of the vehicle, thereby reducing the processing delay of that core.

[0019] (5) In any of (1) to (4) above, it may be preset to perform the data evacuation process or wait without performing the data evacuation process depending on the function executed by the core.

[0020] This configuration allows the core that performs the data backup process to be more appropriately determined depending on the function that the core is performing. For example, by performing the data backup process in a core that performs a function that requires a short response time, the processing delay of that core can be reduced.

[0021] (6) A memory update method according to an embodiment of the present disclosure is a memory update method for an on-board device mounted on a vehicle, the on-board device having three or more cores, three or more local memories corresponding to the three or more cores, respectively, and a shared memory, and includes the steps of: when a core needs to wait its turn to perform an update process to update the shared memory, estimating a waiting time until the update process is performed; and when the waiting time is equal to or longer than a predetermined time, performing a data evacuation process in which the core temporarily stores the data to be updated in the local memory corresponding to its own core and performs another process different from the update process.

[0022] In this way, if the wait time until the update process to update the shared memory is equal to or longer than a predetermined time, the core temporarily stores the data to be updated in its local memory and performs a process other than the update process, thereby reducing the processing delay of the core that has a long wait time until the update process. Therefore, in a configuration in which multiple cores access the shared memory, the processing delay of the core can be reduced.

[0023] (7) A memory update program according to an embodiment of the present disclosure is a memory update program used in an on-board device mounted in a vehicle, and includes three or more cores, three or more local memories corresponding to the three or more cores, and a shared memory. The memory update program is a program for causing a core to execute the following steps: when the core needs to wait its turn to perform an update process to update the shared memory, estimates a waiting time until the update process is performed; and when the waiting time is equal to or longer than a predetermined time, temporarily stores data to be updated in the local memory corresponding to the core, and performs a data evacuation process that is different from the update process.

[0024] In this way, if the wait time until the update process to update the shared memory is equal to or longer than a predetermined time, the core temporarily stores the data to be updated in the local memory and performs other processing other than the update process, thereby reducing the processing delay of the core that has a long wait time until the update process. Therefore, in a configuration in which multiple cores access the shared memory, the processing delay of the core can be reduced.

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, identical or corresponding parts are designated by the same reference numerals, and their description will not be repeated. Furthermore, at least some of the embodiments described below may be combined in any manner.

[0026] [In-vehicle system] 1 is a diagram illustrating an example of the configuration of an in-vehicle system according to an embodiment of the present disclosure. Referring to FIG. 1, the in-vehicle system 301 includes an in-vehicle relay device 101 and a plurality of in-vehicle devices 202. The in-vehicle system 301 is mounted on a vehicle 1. The in-vehicle relay device 101 is an example of an in-vehicle device.

[0027] In the example shown in FIG. 1, the in-vehicle system 301 includes the in-vehicle device 202, which are in-vehicle devices 202A, 202B, 202C, and 202D.

[0028] The in-vehicle devices 202 include an in-vehicle ECU (Electronic Control Unit), sensors, actuators, navigation devices, human-machine interfaces, cameras, etc. The in-vehicle ECUs include an autonomous driving ECU, an engine ECU, an ADAS (Advanced Driving Assistant System) ECU, a steering ECU, and a TCU (Telematics Communication Unit).

[0029] The in-vehicle repeater 101 and the plurality of in-vehicle devices 202 constitute an in-vehicle network 401. Each of the in-vehicle devices 202 is connected to the in-vehicle repeater 101 via an Ethernet (registered trademark) cable 51, for example.

[0030] Each in-vehicle device 202 transmits frames containing various information, such as information to assist the automatic driving performed by the vehicle 1 and information used for entertainment, to other in-vehicle devices 202 via the in-vehicle relay device 101.

[0031] In addition, in the in-vehicle network 401, the in-vehicle equipment 202 is not limited to being connected to the in-vehicle repeater 101 via an Ethernet cable 51, but may also be connected to the in-vehicle repeater 101 via a transmission line conforming to other communication standards such as CAN (Controller Area Network) (registered trademark), CAN FD (CAN with Flexible Data Rate), FlexRay (registered trademark), MOST (Media Oriented System Transport) (registered trademark), LIN (Local Interconnect Network), and CXPI (Clock Extension Peripheral Interface).

[0032] [In-vehicle relay device] 2 is a diagram illustrating an example of the configuration of an in-vehicle relay device according to an embodiment of the present disclosure. Referring to FIG. 2, the in-vehicle relay device 101 includes a communication port 10, a relay unit 11, and a processing unit 12. The processing unit 12 includes three or more cores 21, three or more local memories 22, and a shared memory 23. A part or all of the in-vehicle relay device 101 is realized, for example, by a processing circuit including one or more processors. Here, the core 21 corresponds to the processor.

[0033] The communication port 10 is, for example, a connector to which an Ethernet cable 51 can be connected. In the example shown in Fig. 2, the vehicle-mounted relay device 101 includes communication ports 10A, 10B, 10C, and 10D which are the communication ports 10.

[0034] In-vehicle devices 202A, 202B, 202C, and 202D are connected to the communication ports 10A, 10B, 10C, and 10D via Ethernet cables 51, respectively.

[0035] The vehicle-mounted relay device 101 is not limited to a configuration having four communication ports 10, but may be a configuration having two, three, five or more communication ports 10.

[0036] The relay unit 11 performs a relay process to relay frames transmitted and received between the in-vehicle devices 202. More specifically, when the relay unit 11 receives a frame from a certain in-vehicle device 202, it transmits the received frame to the in-vehicle device 202 of the destination.

[0037] In the example shown in FIG. 2, the processing unit 12 includes three or more cores 21: cores 21A, 21B, 21C, and 21D.

[0038] Each core 21 executes one or more functions. More specifically, for example, a program for the function executed by each core 21 is stored in the code area of ​​the shared memory 23. Each core 21 executes the corresponding function individually or in cooperation with other cores 21 by reading and executing the control program stored in the shared memory 23.

[0039] In this embodiment, each core 21 executes a relay function in cooperation with other cores 21. The relay function is a function for performing relay processing according to Layer 3, for example.

[0040] For example, the relay unit 11 includes a buffer (not shown). When the relay unit 11 receives a frame from a certain in-vehicle device 202, the relay unit 11 stores the received frame in the buffer and outputs a reception notification indicating that the frame has been received to the processing unit 12.

[0041] For example, the shared memory 23 stores an ARP (Address Resolution Protocol) table that indicates the correspondence between IP addresses and MAC (Media Access Control) addresses.

[0042] In the processing unit 12, when the core 21 receives a reception notification from the relay unit 11, it refers to the ARP table in the shared memory 23 to identify the MAC address corresponding to the destination IP address contained in the payload of the frame stored in the buffer as the destination MAC address.

[0043] The shared memory 23 stores an address table that indicates the correspondence between destination MAC addresses and communication ports 10.

[0044] When the core 21 identifies the destination MAC address, it identifies the communication port 10 corresponding to the destination MAC address by referring to the address table in the shared memory 23. Then, the core 21 notifies the relay unit 11 of the identified communication port 10.

[0045] When the relay unit 11 receives the notification from the core 21, it transmits the frame stored in the buffer to the in-vehicle device 202 as the destination from the communication port 10 of which the relay unit 11 has received the notification.

[0046] FIG. 3 is a diagram illustrating an example of core numbers assigned to each core in the vehicle-mounted relay device according to the embodiment of the present disclosure.

[0047] 3, a unique core number is assigned to each core 21. In the example shown in Fig. 3, the core numbers of cores 21A, 21B, 21C, and 21D are 1, 2, 3, and 4, respectively.

[0048] The processing unit 12 is not limited to a configuration including four cores 21, but may be a configuration including three, five or more cores 21.

[0049] 2, in the in-vehicle relay device 101, three or more local memories 22 are provided corresponding to three or more cores 21. In the example shown in FIG. 2, the processing unit 12 in the in-vehicle relay device 101 includes local memories 22A, 22B, 22C, and 22D, which are the local memories 22.

[0050] Each core 21 performs an update process to update the shared memory 23. More specifically, for example, each core 21 performs a process to write data to be updated into the shared memory 23.

[0051] (Estimated waiting time) When the core 21 needs to wait its turn to perform the update process, the core 21 estimates the waiting time until the update process is performed.

[0052] For example, the shared memory 23 stores information indicating the reception number of the update process (hereinafter also referred to as an "reception flag.") Furthermore, each local memory 22 stores a local flag.

[0053] When the core 21 desires to execute the update process, it reads the reception flag in the shared memory 23. Then, the core 21 checks whether the value F1 of the reception flag that it reads is the same as the core number of its own core 21.

[0054] If the value F1 of the reception flag that has been read is the same as the core number of the core 21 itself, the core 21 sets the value F1 as the value F3 of the local flag that corresponds to the core 21 itself.

[0055] Then, the core 21 increments the value F1 of the reception flag in the shared memory 23. If the read value F1 of the reception flag is "4", the core 21 sets the value F1 of the reception flag to "1".

[0056] On the other hand, if the read value F1 of the reception flag is different from the core number of the core 21, the core 21 does not increment the value F1 of the reception flag and waits until the value F1 and the core number become the same.

[0057] For example, the shared memory 23 stores information indicating the cores 21 that are permitted to execute update processing (hereinafter also referred to as "call flags").

[0058] After incrementing the value F1 of the reception flag in the shared memory 23, the core 21 reads the call flag in the shared memory 23. Then, the core 21 compares the value F2 of the read call flag with the value F3 of the local flag corresponding to its own core 21.

[0059] If the value F2 and the value F3 are the same, the core 21 performs an update process. Then, the core 21 increments the value F2 of the call flag. Note that if the value F1 of the read call flag is "4", the core 21 sets the value F1 of the call flag to "1".

[0060] On the other hand, when the values ​​F2 and F3 are different, the core 21 estimates the comparison result between the values ​​F2 and F3 as the waiting time until the update process is performed by the core 21. Specifically, for example, the core 21 estimates the absolute value of the difference D between the values ​​F2 and F3 as the waiting time.

[0061] (Data evacuation process) If the estimated waiting time is equal to or longer than a predetermined time, the core 21 temporarily stores the data to be updated in the local memory 22 corresponding to the core 21 itself, and performs a data saving process for performing a process other than the update process.

[0062] More specifically, for example, the core 21 determines whether to perform the data update process or to wait without performing the data update process depending on the ordinal number of the core 21 that itself is performing the update process.

[0063] Specifically, for example, the core 21 decides to perform data evacuation processing when the absolute value of the difference D between the value F2 of the call flag read from the shared memory 23 and the value F3 of the local flag corresponding to the core 21 is equal to or greater than a predetermined value A. For example, the predetermined value A is a value set according to the time required for the core 21 to finish the update processing from the start. Here, the predetermined value A is assumed to be "2." Note that the predetermined value A may also be a value set according to the time required for the core 21 to temporarily save the data to be updated.

[0064] On the other hand, if the absolute value of the difference D between the value F2 and the value F3 is less than the predetermined value A, the core 21 determines to wait without performing the data update process.

[0065] 4 is a diagram illustrating an example of a data saving process by a core in an in-vehicle relay device according to an embodiment of the present disclosure, showing an operation when the core 21C performs the data saving process.

[0066] 4, first, when the core 21C desires to execute an update process, the core 21C reads the reception flag in the shared memory 23. Here, it is assumed that the value F1 of the reception flag is "3" (step ST11).

[0067] Next, the core 21C compares the value F1 of the reception flag read from the shared memory 23 with the core number of its own core 21 (step ST12). The value F1 is the same as the core number "3" of the core 21C.

[0068] Next, the core 21C sets the value of the local flag in the local memory 22C to "3" (step ST13).

[0069] Next, the core 21C increments the value F1 of the reception flag in the shared memory 23. As a result, the value F1 is updated from "3" to "4" (step ST14).

[0070] Next, the core 21C reads the value F2 of the call flag in the shared memory 23. Here, it is assumed that the value F2 is "1" (step ST15).

[0071] Next, the core 21C compares the value F2 of the call flag read from the shared memory 23 with the value F3 of the local flag in the local memory 22C (step ST16).

[0072] Next, the core 21C performs an estimation process. Specifically, the core 21C estimates the waiting time to be "2", which is the absolute value of the difference D between the value F2 and the value F3 (step ST17).

[0073] Next, since the absolute value of the difference D between the value F2 and the value F3 is equal to or greater than the predetermined value A, the core 21C does not perform the update process but performs the data save process (step ST18).

[0074] Thereafter, the core 21C again reads the value F2 of the call flag in the shared memory 23. Here, it is assumed that the value F2 has been updated to "3" (step ST19).

[0075] Next, the core 21C compares the value F2 of the call flag read from the shared memory 23 with the value F3 of the local flag in the local memory 22C (step ST20).

[0076] Next, the core 21C performs an update process because the value F2 and the value F3 are the same. Specifically, the core 21C performs a process of writing the data to be updated into the shared memory 23 (step ST21).

[0077] Next, the core 21C increments the value F2 of the call flag in the shared memory 23. As a result, the value F2 is updated from "3" to "4" (step ST22).

[0078] [Operation flow] Next, the operation of the vehicle-mounted relay device 101 in the vehicle-mounted system 301 according to the embodiment of the present disclosure will be described with reference to the drawings.

[0079] FIG. 5 is a flowchart defining an example of an operation procedure when the core of the in-vehicle relay device according to the embodiment of the present disclosure performs a data saving process.

[0080] 5, first, in the vehicle-mounted relay device 101, when the core 21 desires to execute the update process (YES in step ST101), the core 21 reads the reception flag from the shared memory 23 (step ST102).

[0081] Next, the core 21 compares the value F1 of the reception flag read from the shared memory 23 with its own core number (step ST103).

[0082] If the value F1 of the reception flag is the same as the core number of the core 21 (YES in step ST103), the core 21 sets the value F3 of the local flag corresponding to the core 21 to the value F1 (step ST104).

[0083] Next, the core 21 sets the value F3 of the local flag corresponding to its own core 21, and then increments the value F1 of the reception flag (step ST105).

[0084] Next, the core 21 increments the value F1 of the reception flag and then reads the call flag from the shared memory 23 (step ST106).

[0085] Next, the core 21 compares the value F2 of the call flag read from the shared memory 23 with the value F3 of the local flag corresponding to its own core 21 (step ST107).

[0086] Then, if the value F2 of the call flag and the value F3 of the local flag are the same (YES in step ST107), the core 21 performs an update process to update the shared memory 23. For example, as described above, the core 21 performs a process to write the data to be updated to the shared memory 23 (step ST108).

[0087] Next, the core 21 increments the value F2 of the call flag in the shared memory 23 (step ST109), and if it desires to newly execute update processing (YES in step ST101), it reads the reception flag from the shared memory 23 (step ST102).

[0088] On the other hand, if the value F1 of the reception flag and its own core number are different (NO in step ST103), the core 21 reads the reception flag again from the shared memory 23 after a predetermined time has elapsed (step ST104).

[0089] Furthermore, if the value F2 of the call flag is different from the value F3 of the local flag corresponding to its own core 21 (NO in step ST107), the core 21 checks whether the absolute value of the difference D between the value F2 and the value F3 is greater than or equal to a predetermined value A (step ST110).

[0090] If the absolute value of the difference D between the value F2 and the value F3 is equal to or greater than the predetermined value A (YES in step ST110), the core 21 performs a data saving process (step ST111).

[0091] On the other hand, if the absolute value of the difference D between the value F2 and the value F3 is less than the predetermined value A (NO in step ST110), the core 21 waits without performing the data backup process (step ST112), and reads the call flag again from the shared memory 23 after a predetermined time has elapsed (step ST106).

[0092] In the in-vehicle system 301 according to the embodiment of the present disclosure, the in-vehicle relay device 101 is configured to include three or more cores 21, three or more local memories 22, and a shared memory 23, but this is not limited to this. A device other than the in-vehicle relay device 101 in the in-vehicle network 401 may also be configured to include three or more cores 21, three or more local memories 22, and a shared memory 23.

[0093] <Variation 1> FIG. 6 is a diagram for explaining an update process by the core in the first modification of the vehicle-mounted relay device according to the embodiment of the present disclosure.

[0094] 6, in the first modification, the cores 21A, 21B, 21C, and 21D are given in turn a period of a predetermined length during which each core 21 can perform an update process (hereinafter also referred to as an "update period").

[0095] For example, the shared memory 23 stores schedule information indicating the order of the update period Ta of the core 21A, the update period Tb of the core 21B, the update period Tc of the core 21C, and the update period Td of the core 21D.

[0096] In the example shown in FIG. 6, an update period Ta, an update period Tb, an update period Tc, and an update period Td are given in this order.

[0097] For example, the update periods Ta, Tb, Tc, and Td are periods set according to the time required for the corresponding core 21 to start and finish the update process.

[0098] The update periods Ta, Tb, Tc, and Td may be periods set according to the time required for the core 21 to perform a process other than the update process. Specifically, for example, the update periods Ta, Tb, Tc, and Td may be periods set according to the time required for each core 21 to temporarily store the data to be updated in the local memory 22.

[0099] 6, the update periods Ta, Tb, Tc, and Td are all periods of the same length. Note that the lengths of some of the update periods Ta, Tb, Tc, and Td may be different from the lengths of the other update periods.

[0100] The following describes a case where each core 21 performs update processing every time during the update period of its own core 21. Note that the core 21 may be configured not to perform update processing if there is no data to be updated during the update period of its own core 21.

[0101] For example, the core 21A acquires a reference time in the vehicle-mounted relay device 101. More specifically, for example, the core 21A includes a timer (not shown). The core 21A acquires a time based on the counter value of the timer as the reference time.

[0102] By referring to the schedule information in the shared memory 23, when the start time of the update period of each core 21 arrives, the core 21A notifies the cores 21B, 21C, and 21D of the core numbers of the cores 21 corresponding to the update period.

[0103] When the cores 21B, 21C, and 21D receive the notification from the core 21A, they check whether the notified core number (hereinafter also referred to as "notified core number") is the same as their own core number.

[0104] Then, if the notifying core number and its own core number are the same, the cores 21B, 21C, and 21D start the update process.

[0105] On the other hand, if the notified core number and its own core number are different, the cores 21B, 21C, and 21D check whether their own cores 21 are currently performing data evacuation processing.

[0106] If the core 21 itself is currently performing data evacuation processing, the cores 21B, 21C, and 21D continue the data evacuation processing.

[0107] On the other hand, when the core 21 itself is not performing data saving processing, the cores 21B, 21C, and 21D estimate the waiting time until the core 21 itself performs update processing.

[0108] Specifically, for example, when the cores 21B, 21C, and 21D have a larger core number than the notifying core number, they subtract the notifying core number from their own core number to calculate the value F10.

[0109] On the other hand, if the cores 21B and 21C have a smaller core number than the notifying core number, they add the total number of cores 21 to their own core number and subtract the notifying core number to calculate the value F10.

[0110] The cores 21B, 21C, and 21D estimate the value F10 as the waiting time. Then, the cores 21B, 21C, and 21D check whether the calculated value F10 is equal to or greater than a predetermined value B. Here, the predetermined value B is assumed to be "2."

[0111] If the calculated value F10 is equal to or greater than the predetermined value B, the cores 21B, 21C, and 21D perform data saving processing.

[0112] On the other hand, if the calculated value F10 is less than the predetermined value B, the cores 21B, 21C, and 21D wait without performing the data saving process.

[0113] When the start time of the update period Ta of the core 21 arrives, the core 21A starts the update process.

[0114] Furthermore, when the start time of the update period of another core 21 arrives, the core 21A checks whether its own core 21 is currently performing data evacuation processing. If its own core 21 is currently performing data evacuation processing, the core 21A continues the data evacuation processing.

[0115] On the other hand, when the core 21 is not performing the data evacuation process, the core 21A estimates the waiting time until the core 21 performs the update process. More specifically, for example, the core 21A estimates the waiting time using a method similar to the method for estimating the waiting time used by the cores 21B and 21C described above.

[0116] Specifically, for example, core 21A calculates a value F10 by adding the total number of cores 21 to its own core number "1" and subtracting the core number corresponding to the currently arriving update period. Core 21A estimates the calculated value F10 as the waiting time. Then, core 21A checks whether the calculated value F10 is equal to or greater than a predetermined value B.

[0117] The core 21A performs the data saving process when the value F10 is equal to or greater than the predetermined value B. On the other hand, when the value F10 is less than the predetermined value B, the core 21A waits without performing the data saving process.

[0118] 7 and 8 are diagrams illustrating an example of an update process by the first modification of the vehicle-mounted relay device according to the embodiment of the present disclosure.

[0119] 7 and 8, first, when the start time of the update period Ta indicated by the schedule information in the shared memory 23 arrives, the core 21A notifies the cores 21B, 21C, and 21D of the core number "1" (steps ST31, ST32, and ST33).

[0120] Furthermore, when the start time of the update period Ta arrives, the core 21A starts the update process (step ST34) and writes the data to be updated into the shared memory 23 (step ST35).

[0121] Next, when core 21B receives the notification from core 21A, it waits without performing data saving processing because the notifying core number "1" is different from its own core number "2" and the value F10 is less than the predetermined value B (step ST36).

[0122] Furthermore, when core 21C receives the notification from core 21A, it performs data saving processing because the notifying core number "1" is different from its own core number "3" and the value F10 is equal to or greater than the predetermined value B (step ST37).

[0123] Furthermore, when core 21D receives the notification from core 21A, it performs data saving processing because the notifying core number "1" is different from its own core number "4" and the value F10 is equal to or greater than the predetermined value B (step ST38).

[0124] Next, when the start time of the update period Tb indicated by the schedule information in the shared memory 23 arrives, the core 21A notifies the cores 21B, 21C, and 21D of the core number "2" (steps ST39, ST40, and ST41).

[0125] Furthermore, when the start time of the update period Tb arrives, the core 21A performs a data saving process because the value F10 is equal to or greater than the predetermined value B (step ST42).

[0126] Next, when core 21B receives the notification from core 21A, it starts the update process (step ST43) because the notifying core number "2" is the same as its own core number "2" and writes the data to be updated to shared memory 23 (step ST44).

[0127] Furthermore, when the core 21C receives the notification from the core 21A, the notifying core number "2" is different from the core number "3" of the core 21C, and the core 21C is currently performing data evacuation processing, so the core 21C continues the data evacuation processing (step ST45).

[0128] Furthermore, when the core 21D receives the notification from the core 21A, the notifying core number "2" is different from the core number "4" of the core 21D, and the core 21D is currently performing data evacuation processing, so the core 21D continues the data evacuation processing (step ST46).

[0129] Next, when the start time of the update period Tc indicated by the schedule information in the shared memory 23 arrives, the core 21A notifies the cores 21B, 21C, and 21D of the core number "3" (steps ST47, ST48, and ST49).

[0130] Furthermore, the core 21A is currently performing data evacuation processing when the start time of the update period Tc arrives, and therefore continues the data evacuation processing (step ST50).

[0131] Next, when core 21B receives the notification from core 21A, it performs data saving processing because the notifying core number "3" is different from its own core number "2" and the value F10 is equal to or greater than the predetermined value B (step ST51).

[0132] Furthermore, when core 21C receives the notification from core 21A, it starts the update process (step ST52) because the notifying core number "3" is the same as its own core number "3" and writes the data to be updated to shared memory 23 (step ST53).

[0133] Furthermore, when the core 21D receives the notification from the core 21A, the notifying core number "3" is different from the core number "4" of the core 21D, and the core 21D is currently performing data evacuation processing, so the core 21D continues the data evacuation processing (step ST54).

[0134] Next, when the start time of the update period Td indicated by the schedule information in the shared memory 23 arrives, the core 21A notifies the cores 21B, 21C, and 21D of the core number "4" (steps ST55, ST56, and ST57).

[0135] Furthermore, the core 21A is currently performing data evacuation processing when the start time of the update period Td arrives, and therefore continues the data evacuation processing (step ST58).

[0136] Next, when the core 21B receives the notification from the core 21A, the core 21B continues the data saving process because the notifying core number "4" is different from its own core number "2" and the data saving process is in progress (step ST59).

[0137] Furthermore, when core 21C receives the notification from core 21A, it performs data saving processing because the notifying core number "4" is different from its own core number "3" and the value F10 is equal to or greater than the predetermined value B (step ST60).

[0138] Furthermore, when the core 21D receives the notification from the core 21A, since the notifying core number "4" is the same as its own core number, the core 21D starts the update process (step ST61) and writes the data to be updated into the shared memory 23 (step ST62).

[0139] 9 and 10 are flowcharts illustrating an example of an operation procedure when a core of the first modification of the in-vehicle relay device according to the embodiment of the present disclosure performs a data saving process. The flowcharts illustrate the operation when the core 21B performs the data saving process.

[0140] 9 and 10, first, the core 21B waits for a notification from the core 21A (NO in step ST201).

[0141] Next, when core 21B receives the notification from core 21A (YES in step ST201), core 21B checks whether the notifying core number is the same as its own core number (step ST202).

[0142] If the notifying core number is the same as its own core number (YES in step ST202), the core 21B performs an update process (step ST203) and waits for a new notification from the core 21A (NO in step ST201).

[0143] On the other hand, if the notified core number and its own core number are different (NO in step ST202), core 21B checks whether its own core 21 is currently performing data evacuation processing (step ST204).

[0144] Then, if the core 21B itself is currently performing the data saving process (YES in step ST204), the core 21B continues the data saving process (step ST205).

[0145] On the other hand, if the core 21 is not performing data saving processing (NO in step ST204), the core 21B estimates the waiting time until the core 21 performs update processing. The core 21B estimates the value F10 calculated as described above as the waiting time (step ST206).

[0146] Next, the core 21B checks whether the value F10 is equal to or greater than a predetermined value B (step ST207).

[0147] If the value F10 is equal to or greater than the predetermined value B (YES in step ST207), the core 21B performs data saving processing (step ST208) and waits for a new notification from the core 21A (NO in step ST201).

[0148] On the other hand, if the value F10 is less than the predetermined value B (NO in step ST207), the core 21B waits without performing the data saving process (step ST209) and waits for a new notification from the core 21A (NO in step ST201).

[0149] Note that, in the first modification of the in-vehicle system 301 according to the embodiment of the present disclosure, time synchronization may be performed between the cores 21. In this case, the start times of the update periods are not notified to the other cores 21, and each core 21 performs update processing when the update period of its own core 21 arrives, as indicated by the schedule information in the shared memory 23. Furthermore, when the update period of another core 21 arrives, as indicated by the schedule information, each core 21 estimates the waiting time until its own core 21 performs update processing, using the method described above.

[0150] <Variation 2> 11 is a diagram illustrating a configuration of a second modified example of an in-vehicle system according to an embodiment of the present disclosure. Referring to FIG. 11, in the second modified example, an in-vehicle device 202A and an in-vehicle device 202B are a GPS (Global Positioning System) receiver and a vehicle speed sensor, respectively. In the following description, the in-vehicle device 202A and the in-vehicle device 202B are also referred to as the vehicle speed sensor 202A and the GPS receiver 202B, respectively.

[0151] The vehicle speed sensor 202A performs a measurement process to measure the vehicle speed of the vehicle 1, and transmits vehicle speed information indicating the measurement result and the measurement time to the in-vehicle relay device 101. The vehicle speed sensor 202A performs the measurement process and transmits the vehicle speed information, for example, periodically or irregularly.

[0152] The GPS receiver 202B receives GPS signals from one or more satellites and, based on the received GPS signals, detects the position of the vehicle 1. The position of the vehicle 1 is indicated by, for example, latitude and longitude.

[0153] The GPS receiver 202B transmits the detection result and position information indicating the detection time to the vehicle-mounted relay device 101. The GPS receiver 202B performs position detection and transmits the position information, for example, periodically or irregularly.

[0154] Referring again to FIG. 2, in the second modification, the core 21 determines, depending on the state of the vehicle 1, whether to perform the data saving process or to wait without performing the data saving process.

[0155] (a) Example 1 The cores 21 perform data evacuation processing when the vehicle 1 is traveling on a highway. Specifically, for example, in addition to the relay function, each core 21 executes a status management function of periodically or irregularly acquiring vehicle status information indicating the status of the vehicle 1. Here, the vehicle status information includes, for example, vehicle speed information, location information, and power supply information indicating the status of the ignition power supply of the vehicle 1.

[0156] The shared memory 23 stores map information for the area including the position indicated by the position information transmitted from the GPS receiver 202B.

[0157] When core 21 needs to wait its turn to perform the update process, it determines whether vehicle 1 is traveling on a highway using the location information received from GPS receiver 202B via relay unit 11 and the map information stored in shared memory 23.

[0158] If the core 21 determines that the vehicle 1 is traveling on a highway, it performs a data evacuation process. On the other hand, if the core 21 determines that the vehicle 1 is not traveling on a highway, it waits without performing the data evacuation process.

[0159] (b) Example 2 When the core 21 needs to wait its turn to perform the update process, the core 21 determines whether the vehicle 1 is stopped.

[0160] Specifically, the core 21 measures the output voltage of the ignition power supply, for example, periodically or irregularly, and then checks whether the measured voltage value is equal to or greater than a threshold value Th1.

[0161] If the measured voltage value is equal to or greater than the threshold value Th1, the core 21 determines that the ignition power supply is in the ON state. On the other hand, if the measured voltage value is less than the threshold value Th1, the core 21 determines that the ignition power supply is in the OFF state.

[0162] When the ignition power is on and the vehicle speed indicated by the vehicle speed information received from the vehicle speed sensor 202A is less than the threshold value Th2, the core 21 determines that the vehicle 1 is stopped. When the core 21 determines that the vehicle 1 is stopped in a case where it needs to wait its turn to perform the update process, the core 21 waits without performing the data saving process.

[0163] On the other hand, if the ignition power is on or if the vehicle speed indicated by the vehicle speed information received from the vehicle speed sensor 202A is equal to or greater than the threshold value Th2, the core 21 determines that the vehicle 1 is not stopped. If the core 21 determines that the vehicle 1 is not stopped when it needs to wait its turn to perform the update process, the core 21 performs the data saving process.

[0164] <Variation 3> 12 is a diagram illustrating a configuration of a third modification of an in-vehicle system according to an embodiment of the present disclosure. Referring to FIG. 12, in the third modification, an in-vehicle device 202A, an in-vehicle device 202B, and an in-vehicle device 202C are an autonomous driving ECU, an ADAS ECU, and an entertainment ECU, respectively. The entertainment ECU is an in-vehicle ECU that provides entertainment services in an in-vehicle network 401.

[0165] In the third modification, the in-vehicle relay device 101 is an integrated ECU that controls the operation of one or more in-vehicle devices 202 .

[0166] Specifically, for example, the in-vehicle relay device 101 generates control information for controlling the operation of a certain in-vehicle device 202 and transmits the generated control information to the in-vehicle device 202 .

[0167] FIG. 13 is a conceptual diagram illustrating functions executed by each core of the vehicle-mounted relay device according to the third modification of the embodiment of the present disclosure.

[0168] 13, in addition to the relay function, core 21A executes control function C1 of generating control information for controlling the operation of in-vehicle device 202A, which is an autonomous driving ECU. Core 21B executes control function C2 of generating control information for controlling the operation of in-vehicle device 202B, which is an ADAS ECU. In addition to the relay function, core 21C executes control function C3, in collaboration with core 21D, of generating control information for controlling the operation of in-vehicle device 202C, which is an entertainment ECU. In addition to the relay function, core 21D executes control function C3 in collaboration with core 21C.

[0169] In the third modification, whether to perform the data saving process or to wait without performing the data saving process is set in advance depending on the function to be executed by the core 21.

[0170] 13, core 21A executing control function C1 and core 21B executing control function C2 perform data evacuation processing when their own core 21 needs to wait its turn to perform update processing. Specifically, for example, when core 21A needs to wait its turn to perform update processing, core 21A temporarily stores the data to be updated in local memory 22A and performs processing to generate control information for controlling the operation of in-vehicle device 202A, which is an autonomous driving ECU. When core 21B needs to wait its turn to perform update processing, core 21B temporarily stores the data to be updated in local memory 22B and performs processing to generate control information for controlling the operation of in-vehicle device 202B, which is an ADAS ECU.

[0171] Furthermore, in the example shown in FIG. 13, when the cores 21C and 21D that execute the control function C3 need to wait their turn to perform the update process, they wait without performing the data saving process.

[0172] The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0173] Each process (each function) in the above-described embodiments is realized by a processing circuit including one or more processors. The processing circuit may be configured as an integrated circuit or the like that combines one or more memories, various analog circuits, and various digital circuits in addition to the one or more processors. The one or more memories store programs (instructions) that cause the one or more processors to execute each of the processes. The one or more processors may execute each of the processes according to the programs read from the one or more memories, or according to logic circuits pre-designed to execute each of the processes. The processor may be various processors suitable for computer control, such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), and an ASIC (Application Specific Integrated Circuit). Note that the physically separate processors may execute each of the processes in cooperation with each other. For example, the processors mounted on a plurality of physically separated computers may cooperate with each other to execute the above processes via a network such as a LAN (Local Area Network), a WAN (Wide Area Network), the Internet, etc. The program may be installed into the memory from an external server device or the like via the network, or may be distributed in a state stored on a recording medium such as a CD-ROM (Compact Disc Read Only Memory), a DVD-ROM (Digital Versatile Disc Read Only Memory), or a semiconductor memory, and installed into the memory from the recording medium. [Explanation of symbols]

[0174] 1 vehicle 10, 10A, 10B, 10C, 10D communication port 11 Relay Section 12 Processing section 21, 21A, 21B, 21C, 21D Core 22, 22A, 22B, 22C, 22D Local memory 23 Shared Memory 51 Ethernet cable 101 Vehicle relay device 202,202A,202B,202C,202D Vehicle equipment

Claims

1. An in-vehicle device mounted on a vehicle, Three or more cores; three or more local memories provided corresponding to the three or more cores, respectively; a shared memory; When the core needs to wait its turn to perform an update process to update the shared memory, the core estimates a waiting time until the update process is performed; When the waiting time is equal to or longer than a predetermined time, the core performs a data evacuation process in which the data to be updated is temporarily stored in the local memory corresponding to the core and other processing different from the update process.

2. 2. The in-vehicle device according to claim 1, wherein the core determines whether to perform the data evacuation process or to wait without performing the data evacuation process depending on the ordinal number of the core that performs the update process.

3. The in-vehicle device according to claim 2 , wherein the three or more cores are given a period of a predetermined length in which each of the cores can perform the update process in turn.

4. 3. The in-vehicle device according to claim 1, wherein the core determines whether to perform the data saving process or to wait without performing the data saving process, depending on the state of the vehicle.

5. 3. The in-vehicle device according to claim 1, wherein whether to perform the data saving process or to wait without performing the data saving process is set in advance depending on a function to be executed by the core.

6. A memory updating method for an in-vehicle device mounted on a vehicle, comprising: The in-vehicle device Three or more cores; three or more local memories provided corresponding to the three or more cores, respectively; a shared memory; a step of estimating a waiting time until the core performs an update process to update the shared memory when the core needs to wait its turn to perform the update process; a step in which, when the waiting time is equal to or longer than a predetermined time, the core temporarily stores the data to be updated in the local memory corresponding to the core and performs a data evacuation process that performs another process different from the update process.

7. A memory update program used in an in-vehicle device mounted in a vehicle, comprising: Three or more cores; three or more local memories provided corresponding to the three or more cores, respectively; a shared memory; The core a step of estimating a waiting time until the core performs an update process to update the shared memory when the core needs to wait for its turn to perform the update process; a memory update program for executing, if the waiting time is equal to or longer than a predetermined time, a step of temporarily storing the data to be updated in the local memory corresponding to the core itself and performing a data evacuation process that performs another process different from the update process.

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