Semiconductor device and method of manufacturing the same

Abstract

To achieve both reduction in on-resistance and improvement in breakdown voltage in a semiconductor device.SOLUTION: A first gate trench side 24A and a second gate trench side 24B, a first gate electrode side 24A and a second gate electrode side 24B respectively located in the first gate trench side 50A and the second gate trench side 50B, a front surface insulating layer 44 extending over the source region 20 and the first gate trench side 24A and the second gate trench side 24B, and a first contact trench side 70A and a first contact side wall passing through the front surface insulating layer 44. 74A. The semiconductor layer 12 includes a mesa region 30 between the two gate trenches. The first contact trench side 70A extends across both the mesa region 30 and the first gate trench side 24A. The mesa region 30 includes a source exposed region 70A and a body exposed region 20A that are exposed by the first contact trench 18A. The first contact 74A is in contact with both exposed regions 20A, 18A.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a metal insulator semiconductor field effect transistor (MISFET) having a trench gate structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-129378

[0004] [overview] In a semiconductor device having a trench gate structure, there is room for improvement in achieving both a reduction in on-resistance and an improvement in breakdown voltage.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer having a drift region, a body region provided on the drift region, and a source region provided on the body region; a first gate trench and a second gate trench having a predetermined width in a first direction and a predetermined depth in a second direction perpendicular to the first direction and spaced apart in the first direction; a first trench insulating layer located in the first gate trench and in contact with a sidewall of the first gate trench; and a second trench insulating layer located in the second gate trench and in contact with a sidewall of the second gate trench. an insulating layer, a first gate electrode facing the body region in the first gate trench while being surrounded by the first trench insulating layer, a second gate electrode facing the body region in the second gate trench while being surrounded by the second trench insulating layer, a surface insulating layer provided across the source region and the first and second gate trenches, a source wiring located on the surface insulating layer, a first contact trench penetrating the surface insulating layer and reaching the first trench insulating layer, and a gate electrode in front of the source wiring. the semiconductor layer includes a mesa region constituted by the drift region, the body region, and the source region between the first gate trench and the second gate trench, the first contact trench being offset from the first gate electrode when viewed from the second direction and being provided across both the mesa region and the first gate trench, the mesa region including a first source exposed region and a first body exposed region exposed by the first contact trench, the first gate trench including a first contact sidewall located on the mesa region side and a first gate sidewall facing the first contact sidewall, the first source exposed region including a first side exposed region constituting a part of the first contact sidewall, the first body exposed region constituting a part of the first contact sidewall, the first contact including a first buried portion located in the first gate trench, the first buried portion reaching a position facing the first gate electrode in the first direction via the first trench insulating layer,It is in contact with both the first side surface exposed area and the first body exposed area. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view showing an exemplary formation pattern of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an enlarged example of a formation pattern of a part of the semiconductor device according to one embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is an enlarged view of a portion of FIG. [Figure 5] FIG. 5 is an enlarged view of a part of FIG. 3 different from that of FIG. [Figure 6] 6A to 6C are schematic cross-sectional views illustrating an exemplary manufacturing process of a semiconductor device according to an embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 17]FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 24] FIG. 24 is a schematic plan view showing a modified example of the exemplary formation pattern of the semiconductor device. [Figure 25] FIG. 25 is a schematic plan view showing a modified example of the exemplary formation pattern of the semiconductor device.

[0007] [Detailed explanation] Hereinafter, embodiments of a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. For simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Furthermore, cross-sectional views may omit hatching lines to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying example embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The term "plan view" used in this disclosure refers to viewing a semiconductor device in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1. For ease of explanation, the direction along the Z-axis direction is referred to as the "Z direction," the direction along the X-axis direction as the "X direction," and the direction along the Y-axis direction as the "Y direction." Furthermore, the +Z direction is defined as up, the -Z direction as down, the +X direction as right, and the -X direction as left. Unless explicitly stated otherwise, "plan view" refers to viewing from above along the Z direction.

[0010] <Embodiment> The configuration of a semiconductor device 10 according to an embodiment will be described with reference to FIGS. Fig. 1 is an exemplary schematic plan view of a semiconductor device 10. Fig. 2 is an exemplary schematic plan view of the semiconductor device 10. Fig. 3 is a schematic cross-sectional view taken along line F3-F3 in Fig. 2. Figs. 4 and 5 are enlarged views of a portion of Fig. 3.

[0011] [Schematic planar structure of semiconductor device] 1 and 2, a schematic planar structure showing an exemplary formation pattern of a semiconductor device 10 will be described. For ease of understanding, similar components are denoted by the same reference numerals in FIGS. 1 and 2. For simplicity, some components located below a source wiring 72 and a gate wiring 112, which will be described below, are not shown in FIGS. 1 and 2.

[0012] The semiconductor device 10 may be, for example, a MISFET having a split gate structure. The semiconductor device 10 includes a semiconductor layer 12. The semiconductor layer 12 includes a first surface 12F (see FIG. 3) and a second surface 12G opposite to the first surface 12F. The semiconductor layer 12 has a thickness in a direction perpendicular to the first surface 12F (Z direction). In this embodiment, the Z direction can also be referred to as the thickness direction of the semiconductor layer 12. The semiconductor layer 12 may be made of, for example, silicon (Si).

[0013] As shown in FIG. 1, the semiconductor device 10 includes a plurality of gate trenches 24 aligned in a stripe pattern and a peripheral trench 102 . The gate trenches 24 have a constant width in the X direction. In this embodiment, the width of each gate trench is shorter than the distance in the X direction between adjacent gate trenches 24. The gate trenches 24 have a constant depth in the Z direction and extend in the Y direction. In this embodiment, the X direction corresponds to the "first direction" and the Z direction corresponds to the "second direction." Details of the gate trenches 24 will be described later with reference to FIGS. 3 to 5, which are schematic cross-sectional views.

[0014] In this disclosure, unless otherwise specified, the "depth direction" refers to the depth direction of the gate trench 24. In this embodiment, the depth direction corresponds to the Z direction. In other words, the Z direction can also be said to be the depth direction of the gate trench 24. Furthermore, unless otherwise specified, the "width direction" refers to the width direction of the gate trench 24, which corresponds to the X direction in this embodiment. In other words, the X direction can also be said to be the width direction of the gate trench 24. The Y direction is the direction in which the gate trench 24 extends, and is perpendicular to the X and Z directions.

[0015] The peripheral trench 102 may be formed in a rectangular frame shape in plan view so as to surround the multiple gate trenches 24. In this case, the peripheral trench 102 may include two portions extending along the X direction and two portions extending along the Y direction that are provided so as to connect the two portions extending along the X direction.

[0016] The formation pattern of the semiconductor device 10 in plan view is not limited to the above. Although five gate trenches 24 are provided in FIG. 1 , the number may be, for example, two, six, or more. The gate trenches 24 do not have to be striped. Furthermore, the peripheral trench 102 does not have to be rectangular in plan view. The semiconductor device 10 does not have to include the peripheral trench 102.

[0017] The semiconductor device 10 includes a peripheral electrode 104. The peripheral electrode 104 is provided in the peripheral trench 102. The peripheral electrode 104 may be formed in the shape of a rectangular frame along the peripheral trench 102, for example.

[0018] The second surface 12G of the semiconductor layer 12 includes a p-type region 106 and a source region 20. In this embodiment, the p-type region 106 and the source region 20 are surrounded by a peripheral trench 102. The peripheral trench 102 prevents the pn junction interface between the p-type region 106 and the source region 20 from being exposed. This allows the breakdown voltage of the semiconductor device 10 to be improved.

[0019] The p-type regions 106 are rectangular with their longer sides extending in the X direction. The p-type regions 106 are spaced apart in the Y direction. The p-type regions 106 include a first p-type region 108 provided on the +Y side and a second p-type region 110 provided on the −Y side.

[0020] The source region 20 is provided between the first p-type region 108 and the second p-type region 110 in the Y direction. The source region 20 is provided between a plurality of adjacent gate trenches 24. The source region 20 is also provided between a portion of the peripheral trench 102 extending in the Y direction and a gate trench 24 adjacent to the peripheral trench 102. The source regions 20 are separated in the X direction by the plurality of gate trenches 24. The source regions 20 extend in the Y direction. Details of the source region 20 will be described later with reference to FIGS. 3 to 5.

[0021] The first p-type region 108 and the second p-type region 110 are in contact with the source region 20. In this embodiment, the interfaces between the first p-type region 108 and the second p-type region 110 and the source region 20 are located between the multiple gate trenches 24 and between the gate trench 24 and the peripheral trench 102.

[0022] The multiple gate trenches 24 are provided so as to contact both the p-type region 106 and the source region 20. First ends of the multiple gate trenches 24 are adjacent to the first p-type region 108. Second ends of the multiple gate trenches 24 opposite the first ends are adjacent to the second p-type region 110. An intermediate portion of the multiple gate trenches 24 between the first ends and the second ends in the Y direction is adjacent to the source region 20.

[0023] The semiconductor device 10 includes an insulating layer 40 provided on the semiconductor layer 12. The insulating layer 40 covers the second surface 12G of the semiconductor layer 12 and is embedded in the gate trenches 24 and the peripheral trench 102. In one example, the insulating layer 40 may be made of a silicon oxide (SiO2) film. Additionally or alternatively, the insulating layer 40 may include a film made of an insulating material other than SiO2, such as a silicon nitride (SiN) film.

[0024] The semiconductor device 10 includes a source wiring 72 and a gate wiring 112. The source wiring 72 and the gate wiring 112 are provided on an insulating layer 40. The source wiring 72 and the gate wiring 112 are provided spaced apart from each other.

[0025] The source wiring 72 and the gate wiring 112 can each be provided so as to cover a portion of the plurality of gate trenches 24 and the peripheral trench 102. The source wiring 72 is provided across both the gate trench 24 and the source region 20 in plan view. The source wiring 72 may also be provided so as to cover at least the entire source region 20.

[0026] The source wiring 72 is provided so as to overlap one side of the p-type region 106. In this embodiment, the source wiring 72 is provided so as to overlap the first p-type region 108. The gate wiring 112 is provided so as to overlap the other side of the p-type region 106. In this embodiment, the gate wiring 112 is provided so as to overlap the second p-type region 110.

[0027] 2, the semiconductor device 10 includes a plurality of gate electrodes 50 and a plurality of contacts 74. The plurality of gate electrodes 50 have a generally rectangular shape with the X direction as the short side direction and the Y direction as the long side direction in a plan view. The plurality of gate electrodes 50 are each provided in each gate trench 24 closer to the −X direction in a plan view. The plurality of gate electrodes 50 are provided spaced apart from the sidewalls 26 of the respective gate trenches 24.

[0028] In a plan view, each of the multiple gate electrodes 50 extends in the Y direction along each gate trench 24. The Y-direction end of the gate electrode 50 is provided closer to the peripheral trench 102 than the boundary between the source region 20 and the p-type region 106 in the Y direction.

[0029] The contact 74 has a generally rectangular shape with its short side in the X direction and its long side in the Y direction in plan view. The contact 74 is provided across the gate trench 24 and the source region 20 in plan view. The contact 74 includes a portion that is provided closer to the +X direction of the gate trench 24 so as not to overlap with the gate electrode 50.

[0030] The multiple contacts 74 extend in the Y direction in plan view. The Y direction ends of the multiple contacts 74 are provided closer to the peripheral trench 102 in the Y direction than the boundary between the source region 20 and the p-type region 106. Furthermore, the Y direction ends of the multiple contacts 74 are provided closer to the source region 20 than the Y direction end of the gate electrode 50. In other words, the Y direction ends of the multiple contacts 74 are provided between the Y direction end of the gate electrode 50 and the boundary between the source region 20 and the p-type region 106. Details of the gate electrode 50 and the contacts 74 will be described later with reference to FIGS. 3 to 5.

[0031] As shown in FIG. 1 , the semiconductor device 10 may further include a plurality of gate contacts 114. Each gate contact 114 may connect the gate electrode 50 disposed in each gate trench 24 to the gate wiring 112. The gate contact 114 may extend in the Z direction to penetrate the insulating layer 40 located between the gate electrode 50 and the gate wiring 112. The gate contact 114 may be disposed in a region where the gate trench 24 and the gate wiring 112 overlap in a plan view. Specifically, the gate contact 114 may be disposed in a region where one of the two ends of the gate trench 24 and the gate wiring 112 overlap in a plan view. In this embodiment, the gate contact 114 is disposed in a region where the −Y-direction end of the gate trench 24 and the gate wiring 112 overlap.

[0032] The semiconductor device 10 may further include a plurality of source contacts 116. Each source contact 116 may connect a field plate electrode 60 (see FIG. 3 ) disposed in each gate trench 24 to a source wiring 72. The source contact 116 may extend in the Z direction to penetrate the insulating layer 40 located between the field plate electrode 60 and the source wiring 72. The source contact 116 may be disposed in a region where the gate trench 24 and the source wiring 72 overlap in a planar view. Specifically, the source contact 116 may be disposed in a region where the other of the two ends of the gate trench 24 and the source wiring 72 overlap in a planar view. In this embodiment, the source contact 116 is disposed in a region where a first end of the gate trench 24 and the source wiring 72 overlap.

[0033] The semiconductor device 10 may further include a plurality of peripheral contacts 118. Each peripheral contact 118 may connect the peripheral electrode 104 disposed in the peripheral trench 102 to the source wiring 72. The peripheral contacts 118 may extend in the Z direction to penetrate the insulating layer 40 located between the peripheral electrode 104 and the source wiring 72. The peripheral contacts 118 may be disposed in a region where the peripheral trench 102 and the source wiring 72 overlap in a plan view. In particular, the peripheral contacts 118 may be disposed in a region where a portion of the peripheral trench 102 extending along the Y direction and the source wiring 72 overlap in a plan view. In this embodiment, the peripheral contacts 118 are provided in a portion of the peripheral trench 102 extending along the Y direction.

[0034] 2, at the first end of the gate trench 24, a first electrode 120 connected to the field plate electrode 60 extends from the bottom of the gate trench 24 to the opening. The first electrode 120 is connected to the source wiring 72. This allows the source voltage to be applied to the field plate electrode 60 via the first electrode 120.

[0035] Although not shown, at the second end of the gate trench 24, a second electrode connected to the gate electrode 50 similarly extends from the bottom of the gate trench 24 to the opening. The second electrode is connected to the gate wiring 112. This allows the gate voltage to be applied to the gate electrode 50 via the second electrode.

[0036] [Schematic structure of semiconductor layer] A schematic cross-sectional structure of the semiconductor device 10 will be described below with reference to Fig. 3. For ease of understanding, in Fig. 3, the same components as those in Figs. 1 and 2 are denoted by the same reference numerals.

[0037] The semiconductor layer 12 has a drain region 14 , a drift region 16 provided on the drain region 14 , a body region 18 provided on the drift region 16 , and a source region 20 provided on the body region 18 .

[0038] In this embodiment, the drain region 14 is made of a Si substrate, and the drift region 16, the body region 18, and the source region 20 are made of Si epitaxial layers.

[0039] The drift region 16, the body region 18, and the source region 20 are sequentially stacked on the drain region 14. The drain region 14 includes a first surface 12F of the semiconductor layer 12. That is, the drain region 14 constitutes the lowermost layer of the semiconductor layer 12, and the lower surface of the drain region 14 constitutes the first surface 12F of the semiconductor layer 12.

[0040] The source region 20 includes at least a part of the second surface 12G of the semiconductor layer 12. That is, the source region 20 constitutes the uppermost layer of the semiconductor layer 12, and the upper surface of the source region 20 constitutes at least a part of the second surface 12G of the semiconductor layer 12.

[0041] The drain region 14 is an n-type region containing n-type impurities. The n-type impurity concentration of the drain region 14 is 1×10 18 cm -3 More than 1×10 20 cm -3 The drain region 14 may have a thickness of 50 μm or more and 450 μm or less.

[0042] The drift region 16 is an n-type region containing n-type impurities at a lower concentration than the drain region 14. The n-type impurity concentration of the drift region 16 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 16 may have a thickness of 1 μm or more and 25 μm or less.

[0043] The body region 18 is a p-type region containing p-type impurities. The p-type impurity concentration of the body region 18 is 1×10 16 cm -3 More than 1×10 18 cm-3 The body region 18 may have a thickness of not less than 0.5 μm and not more than 1.5 μm.

[0044] The source region 20 is an n-type region containing n-type impurities at a higher concentration than the drift region 16. The n-type impurity concentration of the source region 20 is 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 20 may have a thickness of 0.1 μm or more and 1 μm or less.

[0045] In this embodiment, the thickness of the body region 18 is greater than the thickness of the source region 20. In particular, the thickness of the body region 18 is more than twice the thickness of the source region 20. The n-type impurity may be, for example, phosphorus (P), arsenic (As), etc. The p-type impurity may be, for example, boron (B), aluminum (Al), etc.

[0046] The semiconductor device 10 further includes a drain electrode 11 provided on the first surface 12F of the semiconductor layer 12. The drain electrode 11 is electrically connected to the drain region 14. The drain electrode 11 may be made of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy. In this embodiment, the drain electrode 11 is provided on the entire first surface 12F of the semiconductor layer 12.

[0047] The semiconductor device 10 includes a plurality of gate trenches 24 provided in the second surface 12G of the semiconductor layer 12. The plurality of gate trenches 24 penetrate the source region 20 of the semiconductor layer 12. The plurality of gate trenches 24 penetrate the body region 18. The plurality of gate trenches 24 reach the drift region 16. In other words, the depth of the plurality of gate trenches 24 is greater than the combined thickness of the source region 20 and the body region 18. For example, the gate trenches 24 can have a depth of, for example, 1 μm or more and 10 μm or less.

[0048] Each of the multiple gate trenches 24 includes a sidewall 26 and a bottom wall 28. The sidewall 26 of the gate trench 24 is formed by a side surface of the drift region 16, a side surface of the body region 18, and a side surface of the source region 20. The bottom wall 28 of the multiple gate trenches 24 is located in the drift region 16.

[0049] 3, the sidewalls 26 of the gate trench 24 extend in a direction substantially perpendicular to the first surface 12F and the second surface 12G of the semiconductor layer 12. However, the sidewalls 26 do not have to extend in a direction substantially perpendicular to the first surface 12F and the second surface 12G of the semiconductor layer 12. For example, the gate trench 24 may be provided so that its width decreases toward the bottom wall 28. Also, in FIG. 3, the bottom wall 28 of the gate trench 24 extends in a direction substantially parallel to the first surface 12F and the second surface 12G of the semiconductor layer 12. However, the bottom wall 28 does not necessarily have to be flat, and may be curved in part or in its entirety, for example.

[0050] In this embodiment, for convenience of explanation, among the multiple gate trenches 24 and their surrounding components, two gate trenches 24 adjacent to each other in the X direction and their surrounding components will be described in detail.

[0051] 3, in this embodiment, the multiple gate trenches 24 include a first gate trench 24A and a second gate trench 24B. The first gate trench 24A and the second gate trench 24B are spaced apart in the X direction. The first gate trench 24A is provided on the −X side with respect to the second gate trench 24B, and the second gate trench 24B is provided on the +X side with respect to the first gate trench 24A.

[0052] The first gate trench 24A includes a first gate sidewall 26A1, a first contact sidewall 26A2, and a first bottom wall 28A. The first gate sidewall 26A1 faces the first contact sidewall 26A2 in the X direction. The first gate sidewall 26A1 and the first contact sidewall 26A2 are the sidewalls on the −X and +X sides, respectively, of the sidewalls 26 of the first gate trench 24A.

[0053] The second gate trench 24B includes a second gate sidewall 26B1, a second contact sidewall 26B2, and a second bottom wall 28B. The second gate sidewall 26B1 faces the second contact sidewall 26B2 in the X direction. The second gate sidewall 26B1 and the second contact sidewall 26B2 are the sidewalls on the −X and +X sides, respectively, of the sidewalls 26 of the second gate trench 24B.

[0054] [About the mesa region] The semiconductor layer 12 includes a mesa region 30. The mesa region 30 is provided between the first gate trench 24A and the second gate trench 24B. Specifically, the mesa region 30 is formed by the drift region 16, the body region 18, and the source region 20 located between the first contact sidewall 26A2 and the second gate sidewall 26B1. The first contact sidewall 26A2 and the second gate sidewall 26B1 can be said to form the side surfaces of the mesa region 30.

[0055] The mesa region 30 has a mesa width T, which is the width in the X direction. The mesa width T can also be said to be the distance in the X direction between the first contact sidewall 26A2 and the second gate sidewall 26B1. The mesa width T can be configured to be shorter than the width in the X direction of the gate trench 24. This allows the width in the X direction of the drift region 16 that constitutes the mesa region 30 to be shortened. Similarly, the width in the X direction of the body region 18 and the source region 20 that constitute the mesa region 30 can be shortened.

[0056] 4 and 5, the mesa region 30 includes a first interface 38, which is the interface between the drift region 16 and the body region 18. The mesa region 30 includes a second interface 39, which is the interface between the body region 18 and the source region 20.

[0057] The source region 20 of the mesa region 30 includes a first source upper surface 34A. In detail, of the source region 20 that constitutes the mesa region 30, the surface that constitutes the second surface 12G of the semiconductor layer 12 is the first source upper surface 34A.

[0058] The semiconductor layer 12 includes a connection region 36. The connection region 36 can be said to be a region that becomes a second mesa region when a third gate trench is provided on the +X side of the second gate trench 24B. The connection region 36 is provided on the +X side of the second gate trench 24B. Specifically, the connection region 36 includes the drift region 16, the body region 18, and the source region 20, which are provided on the +X side of the second contact sidewall 26B2. The second contact sidewall 26B2 can be said to constitute a side surface of the connection region 36.

[0059] 4 and 5, the connection region 36 includes a first interface 38, which is the interface between the drift region 16 and the body region 18. The connection region 36 includes a second interface 39, which is the interface between the body region 18 and the source region 20.

[0060] The source region 20 of the connection region 36 includes the second source upper surface 34B. In detail, of the source region 20 that constitutes the connection region 36, the surface that constitutes the second surface 12G of the semiconductor layer 12 is the second source upper surface 34B.

[0061] [Schematic structure inside the gate trench] 3, the semiconductor device 10 includes an insulating layer 40, a plurality of gate electrodes 50, and a plurality of field plate electrodes 60. In one example, the insulating layer 40 may be made of SiO2. In one example, the gate electrodes 50 and the field plate electrodes 60 may be made of conductive polysilicon.

[0062] The insulating layer 40 includes a plurality of trench insulating layers 42 provided in the plurality of gate trenches 24. In this embodiment, the plurality of trench insulating layers 42 include a first trench insulating layer 42A and a second trench insulating layer 42B.

[0063] The first trench insulation layer 42A is provided in the first gate trench 24A. The first trench insulation layer 42A contacts the sidewall 26 of the first gate trench 24A. In this embodiment, the first trench insulation layer 42A contacts the first gate sidewall 26A1, the first contact sidewall 26A2, and the first bottom wall 28A.

[0064] The second trench insulation layer 42B is provided in the second gate trench 24B. The second trench insulation layer 42B contacts the sidewall 26 of the second gate trench 24B. In this embodiment, the second trench insulation layer 42B contacts the second gate sidewall 26B1, the second contact sidewall 26B2, and the second bottom wall 28B.

[0065] The insulating layer 40 includes a surface insulating layer 44. The surface insulating layer 44 is provided on the semiconductor layer 12. Specifically, the surface insulating layer 44 is provided on the semiconductor layer 12 in contact with a portion of the second surface 12G of the semiconductor layer 12. In this embodiment, the surface insulating layer 44 is provided across the source region 20 and the first and second gate trenches 24A and 24B.

[0066] The surface insulating layer 44 includes an insulating upper surface 44A that forms the upper surface. The surface insulating layer 44 is provided integrally with the trench insulating layer 42. In this embodiment, the surface insulating layer 44 is integrated with the first trench insulating layer 42A and the second trench insulating layer 42B.

[0067] The trench insulating layer 42 and the surface insulating layer 44 may be made of the same material. In one example, the trench insulating layer 42 and the surface insulating layer 44 may be made of SiO2. The trench insulating layer 42 and the surface insulating layer 44 may be made of different materials.

[0068] The plurality of gate electrodes 50 are respectively provided in the corresponding plurality of gate trenches 24. In this embodiment, the plurality of gate electrodes 50 include a first gate electrode 50A and a second gate electrode 50B.

[0069] 4, the first gate electrode 50A is provided in the first gate trench 24A. Specifically, the first gate electrode 50A is provided in the first gate trench 24A, closer to the first gate sidewall 26A1. The first gate electrode 50A is surrounded by a first trench insulating layer 42A. The first gate electrode 50A is provided in a position facing the body region 18 in the first gate trench 24A. Specifically, the first gate electrode 50A faces the side surface of the body region 18 that constitutes the first gate sidewall 26A1, via the first trench insulating layer 42A.

[0070] In this embodiment, the first gate electrode 50A is configured in a substantially rectangular shape in the XZ plane, with the X direction as the short side direction and the Z direction as the long side direction. The length of the first gate electrode 50A in the Z direction is configured to be substantially equal to the length of the opposing body region 18 in the Z direction. The length of the first gate electrode 50A in the Z direction may be configured to be longer or shorter than the length of the body region 18 in the Z direction, taking into account the threshold value, resistance, etc.

[0071] The first gate electrode 50A includes a first gate upper surface 52A and a first gate lower surface 53A as both end surfaces in the Z direction. The first gate electrode 50A also includes a first body-side gate side surface 54A and a first contact-side gate side surface 55A as both end surfaces in the X direction. The first gate electrode 50A also includes a first body-side corner portion 56A, which is a corner portion between the first body-side gate side surface 54A and the first gate lower surface 53A. The first gate electrode 50A also includes a first contact-side corner portion 57A, which is a corner portion between the first contact-side gate side surface 55A and the first gate lower surface 53A.

[0072] The first body-side corner 56A and the first contact-side corner 57A have different shapes. Specifically, the first body-side corner 56A has a constant radius of curvature. The first body-side corner 56A can also be described as having an outwardly convex curve. On the other hand, the first contact-side corner 57A is substantially vertical.

[0073] 5, the second gate electrode 50B is provided in the second gate trench 24B. Specifically, the second gate electrode 50B is provided in the second gate trench 24B, closer to the second gate sidewall 26B1. The second gate electrode 50B is surrounded by the second trench insulating layer 42B. The second gate electrode 50B is provided in the second gate trench 24B at a position facing the body region 18. Specifically, the second gate electrode 50B faces the side surface of the body region 18 that constitutes the second gate sidewall 26B1, via the second trench insulating layer 42B.

[0074] In this embodiment, the second gate electrode 50B is configured in a substantially rectangular shape in the XZ plane, with the X direction as the short side direction and the Z direction as the long side direction. The length of the second gate electrode 50B in the Z direction is configured to be substantially equal to the length of the opposing body region 18 in the Z direction. The length of the second gate electrode 50B in the Z direction may be configured to be longer or shorter than the length of the body region 18 in the Z direction, taking into account the threshold value, resistance, etc.

[0075] The second gate electrode 50B includes a second gate upper surface 52B and a second gate lower surface 53B as its two end surfaces in the Z direction. It also includes a second body-side gate side surface 54B and a second contact-side gate side surface 55B as its two end surfaces in the X direction. The second gate electrode 50B includes a second body-side corner portion 56B, which is the corner between the second body-side gate side surface 54B and the second gate lower surface 53B. The second gate electrode 50B includes a second contact-side corner portion 57B, which is the corner between the second contact-side gate side surface 55B and the second gate lower surface 53B.

[0076] The second body-side corner 56B and the second contact-side corner 57B have different shapes. Specifically, the second body-side corner 56B has a constant radius of curvature. The second body-side corner 56B can also be described as having an outwardly convex curve. On the other hand, the second contact-side corner 57B is substantially vertical.

[0077] 3, a plurality of field plate electrodes 60 may be provided in the gate trench 24. In this embodiment, the semiconductor device 10 includes a first field plate electrode 60A provided in the first gate trench 24A and a second field plate electrode 60B provided in the second gate trench 24B.

[0078] The first field plate electrode 60A is embedded in the first gate trench 24A and is surrounded by the first trench insulating layer 42A. The first field plate electrode 60A is disposed in the first gate trench 24A closer to the first bottom wall 28A than the first gate electrode 50A. The first field plate electrode 60A and the first gate electrode 50A face each other in the Z direction with the first trench insulating layer 42A interposed therebetween.

[0079] 4, first field plate electrode 60A includes a first field plate upper surface 62A as its upper end surface in the Z direction. First field plate upper surface 62A is provided on the −Z side in the Z direction with respect to first gate lower surface 53A.

[0080] In this embodiment, the length in the X direction of the first gate electrode 50A is shorter than the length in the X direction of the first field plate electrode 60A. The first gate electrode 50A is disposed at a position facing, in the Z direction, a portion of the first field plate upper surface 62A closer to the first gate sidewall 26A1.

[0081] Applying a source voltage to the first field plate electrode 60A can alleviate the electric field concentration in the first gate trench 24A and improve the breakdown voltage of the semiconductor device 10. Therefore, the first field plate electrode 60A can be set to the same potential as the source region 20.

[0082] 3, the second field plate electrode 60B is embedded in the second gate trench 24B and is surrounded by the second trench insulating layer 42B. The second field plate electrode 60B is disposed in the second gate trench 24B closer to the second bottom wall 28B than the second gate electrode 50B. The second field plate electrode 60B and the second gate electrode 50B face each other in the Z direction with the second trench insulating layer 42B interposed therebetween.

[0083] 5, second field plate electrode 60B includes second field plate upper surface 62B as its upper end surface in the Z direction. Second field plate upper surface 62B is provided on the −Z side in the Z direction with respect to second gate lower surface 53B.

[0084] In this embodiment, the length in the X direction of the second gate electrode 50B is shorter than the length in the X direction of the second field plate electrode 60B. The second gate electrode 50B is disposed at a position facing, in the Z direction, a portion of the second field plate upper surface 62B closer to the second gate sidewall 26B1.

[0085] Applying a source voltage to the second field plate electrode 60B can alleviate the electric field concentration in the second gate trench 24B and improve the breakdown voltage of the semiconductor device 10. Therefore, the second field plate electrode 60B can be set to the same potential as the source region 20.

[0086] As shown in FIG. 3, the semiconductor device 10 includes a plurality of contact trenches 70. In this embodiment, the plurality of contact trenches 70 include a first contact trench 70A and a second contact trench 70B. The first contact trench 70A extends from the insulating upper surface 44A of the surface insulating layer 44 toward the drain electrode 11, and in this embodiment, extends in the Z direction. The first contact trench 70A penetrates the surface insulating layer 44. In this embodiment, the first contact trench 70A penetrates the surface insulating layer 44 and reaches the first trench insulating layer 42A. That is, a portion of the first contact trench 70A is also provided within the first gate trench 24A.

[0087] The first contact trench 70A is provided at a position offset from the first gate electrode 50A when viewed from the Z direction. Specifically, the first gate electrode 50A is disposed closer to the first gate sidewall 26A1, and accordingly, the first contact trench 70A is disposed closer to the first contact sidewall 26A2 in the first gate trench 24A. This prevents the first contact trench 70A and the first gate electrode 50A from overlapping.

[0088] The first contact trench 70A is provided at a position straddling both the mesa region 30 and the first gate trench 24A when viewed from the Z direction. In particular, the first contact trench 70A is provided straddling a region of the first gate trench 24A closer to the first contact sidewall 26A2 and a region of the first source upper surface 34A of the mesa region 30 closer to the first gate trench 24A.

[0089] The second contact trench 70B is provided at a position offset from the second gate electrode 50B when viewed in the Z direction. Specifically, the second gate electrode 50B is disposed closer to the second gate sidewall 26B1, and accordingly, the second contact trench 70B is disposed closer to the second contact sidewall 26B2 in the second gate trench 24B. This prevents the second contact trench 70B and the second gate electrode 50B from overlapping.

[0090] The second contact trench 70B is provided at a position spanning both the connection region 36 and the second gate trench 24B when viewed from the Z direction. In detail, the second contact trench 70B is provided across a region of the second gate trench 24B closer to the second contact sidewall 26B2 and a region of the second source upper surface 34B of the connection region 36 closer to the second gate trench 24B.

[0091] 4, the mesa region 30 includes a first source exposed region 20A and a first body exposed region 18A. The first source exposed region 20A is a region of the source region 20 that constitutes the mesa region 30 and that is exposed from the insulating layer 40 by the first contact trench 70A. The first source exposed region 20A includes a first side surface exposed region 21A and a first top surface exposed region 22A.

[0092] The first side surface exposed region 21A is a region of the first source exposed region 20A that constitutes the first contact sidewall 26A2. In this embodiment, the entire side surface of the source region 20 in the Z direction is the first side surface exposed region 21A.

[0093] The first upper surface exposed region 22A is a region of the first source exposed region 20A that constitutes the first source upper surface 34A of the mesa region 30. In detail, the first upper surface exposed region 22A is a portion of the first source upper surface 34A that is exposed by the first contact trench 70A. In this embodiment, the first upper surface exposed region 22A includes an end of the first source upper surface 34A of the mesa region 30 that is closer to the first gate trench 24A.

[0094] The first side surface exposed region 21A and the first upper surface exposed region 22A are integrally formed. In this embodiment, the first side surface exposed region 21A and the first upper surface exposed region 22A are smoothly connected with rounded edges. In the following description, the Z-direction length of the first side surface exposed region 21A refers to the Z-direction length D2 from the first source upper surface 34A of the mesa region 30 to the second interface 39. Furthermore, the X-direction length of the first upper surface exposed region 22A refers to the X-direction length D1 from the +X-side interface between the first contact trench 70A and the surface insulating layer 44 to the first contact sidewall 26A2.

[0095] The first body exposed region 18A is a part of the side surface of the body region 18. More specifically, the first body exposed region 18A is a part of the side surface of the body region 18 that constitutes the first contact sidewall 26A2. The first body exposed region 18A is a portion of the body region 18 that constitutes the mesa region 30 and is exposed from the insulating layer 40 by the first contact trench 70A.

[0096] Note that the first body exposed region 18A may include, in the Z direction, the entire side surface of the body region 18 that constitutes the first contact sidewall 26A2. In other words, the bottom surface of the first contact trench 70A may reach the first interface 38 in the Z direction.

[0097] As shown in FIG. 5, the connection region 36 includes a second source exposed region 20B and a second body exposed region 18B. The second source exposed region 20B is a region of the source region 20 that constitutes the connection region 36 and that is exposed from the insulating layer 40 by the second contact trench 70B. The second source exposed region 20B includes a second side surface exposed region 21B and a second top surface exposed region 22B.

[0098] The second side surface exposed region 21B is a region of the second source exposed region 20B that forms the second contact sidewall 26B2. In this embodiment, the entire side surface of the source region 20 in the Z direction is the second side surface exposed region 21B.

[0099] The second upper surface exposed region 22B is a region of the second source exposed region 20B that constitutes the second source upper surface 34B of the connection region 36. In detail, the second upper surface exposed region 22B is a portion of the second source upper surface 34B that is exposed by the second contact trench 70B. In this embodiment, the second upper surface exposed region 22B includes an end of the second source upper surface 34B of the connection region 36 that is closer to the second gate trench 24B.

[0100] The second side surface exposed region 21B and the second upper surface exposed region 22B are integrally formed. In this embodiment, the second side surface exposed region 21B and the second upper surface exposed region 22B are smoothly connected with rounded edges. In the following description, the Z-direction length of the second side surface exposed region 21B refers to the Z-direction length D13 from the second source upper surface 34B of the connection region 36 to the second interface 39. Furthermore, the X-direction length of the second upper surface exposed region 22B refers to the X-direction length D12 from the +X-side interface between the second contact trench 70B and the surface insulating layer 44 to the second contact sidewall 26B2.

[0101] The second body exposed region 18B is a part of the side surface of the body region 18. More specifically, the second body exposed region 18B is a part of the side surface of the body region 18 that constitutes the second contact sidewall 26B2. The second body exposed region 18B is a portion of the body region 18 that constitutes the connection region 36 and is exposed from the insulating layer 40 by the second contact trench 70B.

[0102] The second body exposed region 18B may include, in the Z direction, the entire side surface of the body region 18 that constitutes the second contact sidewall 26B2. In other words, the bottom surface of the second contact trench 70B may reach the first interface 38 in the Z direction.

[0103] [Contact structure] 3, each of the plurality of contacts 74 is connected to a source wiring 72. The source wiring 72 and the plurality of contacts 74 may be provided integrally.

[0104] The source wiring 72 and the plurality of contacts 74 may be provided separately. The source wiring 72 and the plurality of contacts 74 may be made of different materials. The source wiring 72 may be made of, for example, a metal with relatively low resistance. In one example, the source wiring 72 may be made of a material containing Al. The materials that make up the plurality of contacts 74 and the source wiring 72 are not limited to those mentioned above.

[0105] The contacts 74 may be made of a material containing a metal that is relatively easy to fill in the contact trench 70. In one example, the contacts 74 may be made of a material containing tungsten (W). The contacts 74 and the source wiring 72 may also be made of the same material.

[0106] The source wiring 72 is provided on the semiconductor layer 12. The source wiring 72 is provided on and in contact with the surface insulating layer 44. Specifically, the source wiring 72 is in contact with the insulating upper surface 44A of the surface insulating layer 44. The source wiring 72 is provided across the source region 20 and the first and second gate trenches 24A and 24B.

[0107] The plurality of contacts 74 are provided to fill the corresponding contact trenches 70. In this embodiment, the plurality of contacts 74 include a first contact 74A and a second contact 74B.

[0108] The first contact 74A is provided to fill the first contact trench 70A. A portion of the first contact 74A is provided within the first gate trench 24A. The first contact 74A is in contact with both the first body exposed region 18A and the first source exposed region 20A.

[0109] The first contact 74A includes a first buried portion 80A provided in the first gate trench 24A, and a first connection portion 76A provided in the surface insulating layer 44 and connecting the first buried portion 80A and the source wiring 72.

[0110] 4, the first buried portion 80A fills the portion of the first contact trench 70A that is located inside the first gate trench 24A. In other words, the first buried portion 80A is a portion of the first contact trench 70A that is provided on the -Z side of the second surface 12G.

[0111] The first buried portion 80A is in contact with the first body exposed region 18A. The first buried portion 80A is in contact with a part of the first source exposed region 20A. Specifically, the first buried portion 80A is in contact with the first side surface exposed region 21A.

[0112] In this embodiment, the first buried portion 80A has a generally rectangular shape in the XZ plane, with the X direction as the short side direction and the Z direction as the long side direction. The first buried portion 80A includes a first buried lower surface 82A as the lower end surface in the Z direction. The first buried portion 80A also includes a first mesa-side buried side surface 83A and a first gate-side buried side surface 84A as both end surfaces in the X direction.

[0113] The first mesa-side buried side surface 83A is the side surface on the -X side of the first buried portion 80A. The first gate-side buried side surface 84A is the side surface on the +X side of the first buried portion 80A. Therefore, the first mesa-side buried side surface 83A of the first buried portion 80A contacts the first body exposed region 18A and the first side surface exposed region 21A.

[0114] The first buried portion 80A reaches a position within the first gate trench 24A that faces the first gate electrode 50A. Specifically, the first buried lower surface 82A is located closer to the first bottom wall 28A than the first gate upper surface 52A. The first buried lower surface 82A is in contact with the bottom surface of the first contact trench 70A. In other words, it can be said that the bottom surface of the first contact trench 70A is located closer to the first bottom wall 28A in the Z direction than the first gate upper surface 52A. Therefore, it can be said that the first gate-side buried side surface 84A of the first buried portion 80A is a side surface that faces the first gate electrode 50A in the X direction.

[0115] The first connection portion 76A is a portion of the first contact 74A that connects the first buried portion 80A and the source wiring 72. The first connection portion 76A is a portion of the first contact 74A that is provided between the second surface 12G and the source wiring 72 in the Z direction.

[0116] In this embodiment, the first connecting portion 76A has a generally rectangular shape in the XZ plane, with the X direction as the longitudinal direction and the Z direction as the lateral direction. The first connecting portion 76A includes a first connecting upper surface 77A (see FIG. 3) as its upper end surface in the Z direction.

[0117] The first connection portion 76A is connected to the source wiring 72 at one end in the Z direction. More specifically, the first connection upper surface 77A is in contact with the source wiring 72. The first connection portion 76A is provided integrally with the first buried portion 80A. This connects the first connection portion 76A and the first buried portion 80A.

[0118] The length of the first connection portion 76A in the X direction is longer than the length of the first buried portion 80A in the X direction. The first connection portion 76A is in contact with a portion of the source exposed region 20A. More specifically, the first connection portion 76A is in contact with the first upper surface exposed region 22A. That is, in this embodiment, the first contact 74A is in contact with the entire first source exposed region 20A and the entire first body exposed region 18A exposed by the first contact trench 70A.

[0119] The positional relationship between components in this embodiment will be described with reference to FIG. The length D1 in the X direction of the first upper surface exposed region 22A is preferably short. In one example, the length D1 in the X direction of the first upper surface exposed region 22A is preferably shorter than the length D2 in the Z direction of the first side surface exposed region 21A. Furthermore, the length D1 in the X direction of the first upper surface exposed region 22A is preferably shorter than the length D3 in the X direction of the first embedded portion 80A.

[0120] The first contact 74A is provided so as to be in contact with the body region 18 but not in contact with the drift region 16. In particular, a first buried lower surface 82A of the first buried portion 80A is provided flush with the first interface 38 or closer to the source wiring 72 than the first interface 38. In this embodiment, the first buried lower surface 82A is provided closer to the source wiring 72 in the Z direction than the first interface 38. In other words, a length D4 in the Z direction of a contact region between the first buried portion 80A and the first body exposed region 18A is shorter than a length D5 in the Z direction of the body region 18.

[0121] The Z-direction length of the contact region between the first contact 74A and the body region 18 can be set in consideration of the breakdown voltage, capacitance between the components, etc. The first buried lower surface 82A may be located closer to the first interface 38 than the center of the body region 18 in the Z direction. Specifically, the Z-direction length D4 of the contact region between the first buried portion 80A and the first body exposed region 18A may be longer than half the Z-direction length D5 of the body region 18. With this configuration, the contact region between the first contact 74A and the body region 18 is large.

[0122] The first buried lower surface 82A may be located closer to the second interface 39 than the center of the body region 18 in the Z direction. Specifically, the length D4 in the Z direction of the contact region between the first buried portion 80A and the first body exposed region 18A may be shorter than half the length D5 in the Z direction of the body region 18. In this configuration, the area where the first contact 74A and the first gate electrode 50A face each other is reduced.

[0123] Furthermore, the first buried lower surface 82A may be disposed closer to the source wiring 72 in the Z direction than the first gate lower surface 53A of the first gate electrode 50A. In particular, a distance D6 in the Z direction between the first gate lower surface 53A and the second surface 12G is greater than a distance D7 in the Z direction between the first buried lower surface 82A and the second surface 12G.

[0124] The positions of the first gate electrode 50A and the first field plate electrode 60A can be set taking into consideration the threshold voltage, capacitance between the structures, etc. The distance in the Z direction between the first contact 74A and the first field plate electrode 60A is greater than the distance in the Z direction between the first gate electrode 50A and the first field plate electrode 60A. Specifically, the distance D8 in the Z direction between the first buried lower surface 82A and the first field plate upper surface 62A is greater than the distance D9 in the Z direction between the first gate lower surface 53A and the first field plate upper surface 62A.

[0125] Furthermore, the distance in the X direction between the first contact 74A and the first gate electrode 50A is greater than the distance in the X direction between the first gate electrode 50A and the first gate sidewall 26A1. Specifically, the distance D10 between the first gate-side buried side surface 84A and the first contact-side gate side surface 55A is greater than the distance D11 between the first body-side gate side surface 54A and the first gate sidewall 26A1.

[0126] 3, the second contact 74B is provided to fill the second contact trench 70B. A portion of the second contact 74B is provided within the second gate trench 24B. The second contact 74B is in contact with both the second body exposed region 18B and the second source exposed region 20B.

[0127] The second contact 74B includes a second buried portion 80B provided in the second gate trench 24B, and a second connection portion 76B provided in the surface insulating layer 44 and connecting the second buried portion 80B and the source wiring 72.

[0128] 5, the second buried portion 80B fills the portion of the second contact trench 70B that is located inside the second gate trench 24B. In other words, the second buried portion 80B is a portion of the second contact trench 70B that is provided on the -Z side of the second surface 12G.

[0129] The second buried portion 80B is in contact with the second body exposed region 18B. The second buried portion 80B is in contact with a part of the second source exposed region 20B. Specifically, the second buried portion 80B is in contact with the second side surface exposed region 21B.

[0130] In this embodiment, the second buried portion 80B has a generally rectangular shape in the XZ plane, with the X direction as the short side direction and the Z direction as the long side direction. The second buried portion 80B includes a second buried lower surface 82B as its lower end surface in the Z direction. The second buried portion 80B also includes a second mesa-side buried side surface 83B and a second gate-side buried side surface 84B as its opposite end surfaces in the X direction.

[0131] The second mesa-side buried side surface 83B is the side surface on the -X side of the second buried portion 80B. The second gate-side buried side surface 84B is the side surface on the +X side of the second buried portion 80B. Therefore, the second mesa-side buried side surface 83B of the second buried portion 80B contacts the second body exposed region 18B and the second side surface exposed region 21B.

[0132] The second buried portion 80B reaches a position within the second gate trench 24B facing the second gate electrode 50B. Specifically, the second buried lower surface 82B is located closer to the second bottom wall 28B than the second gate upper surface 52B. The second buried lower surface 82B is in contact with the bottom surface of the second contact trench 70B. In other words, it can be said that the bottom surface of the second contact trench 70B is located closer to the second bottom wall 28B in the Z direction than the second gate upper surface 52B.

[0133] 5, the second connection portion 76B is a portion of the second contact 74B that connects the second buried portion 80B and the source wiring 72. The second connection portion 76B is a portion of the second contact 74B that is provided between the second surface 12G and the source wiring 72 in the Z direction.

[0134] In this embodiment, the second connection portion 76B has a generally rectangular shape in the XZ plane, with the X direction as the longitudinal direction and the Z direction as the lateral direction. The second connection portion 76B includes a second upper connection surface 77B as its upper end surface in the Z direction.

[0135] The second connection portion 76B is connected to the source wiring 72 at one end in the Z direction. More specifically, the second connection upper surface 77B is in contact with the source wiring 72. The second connection portion 76B is provided integrally with the second buried portion 80B. This connects the second connection portion 76B and the second buried portion 80B.

[0136] The length in the X direction of the second connection portion 76B is longer than the length in the X direction of the second buried portion 80B. The second connection portion 76B is in contact with a portion of the source exposed region 20B. More specifically, the second connection portion 76B is in contact with the second upper surface exposed region 22B. That is, in this embodiment, the second contact 74B is in contact with the entire second source exposed region 20B and the entire second body exposed region 18B exposed by the second contact trench 70B.

[0137] The positional relationship between components in this embodiment will be described with reference to FIG. The length D12 in the X direction of the second upper surface exposed region 22B is preferably short. In one example, the length D12 in the X direction of the second upper surface exposed region 22B is preferably shorter than the length D13 in the Z direction of the second side surface exposed region 21B. Furthermore, the length D12 in the X direction of the second upper surface exposed region 22B is preferably shorter than the length D14 in the X direction of the second embedded portion 80B.

[0138] The second contact 74B is provided so as to be in contact with the body region 18 but not in contact with the drift region 16. In particular, a second buried lower surface 82B of the second buried portion 80B is provided flush with the first interface 38 or closer to the source wiring 72 than the first interface 38. In this embodiment, the second buried lower surface 82B is provided closer to the source wiring 72 in the Z direction than the first interface 38. In other words, a length D15 in the Z direction of a contact region between the second buried portion 80B and the second body exposed region 18B is shorter than a length D16 in the Z direction of the body region 18.

[0139] The Z-direction length of the contact region between the second contact 74B and the body region 18 can be set taking into consideration the breakdown voltage, capacitance between the components, etc. The second buried lower surface 82B may be located closer to the first interface 38 than the center of the body region 18 in the Z direction. Specifically, the Z-direction length D15 of the contact region between the second buried portion 80B and the second body exposed region 18B may be longer than half the Z-direction length D16 of the body region 18. With this configuration, the contact region between the second contact 74B and the body region 18 is large.

[0140] The second buried lower surface 82B may be located closer to the second interface 39 than the center of the body region 18 in the Z direction. Specifically, the length D15 in the Z direction of the contact region between the second buried portion 80B and the second body exposed region 18B may be shorter than half the length D16 in the Z direction of the body region 18. In this configuration, the area where the second contact 74B and the second gate electrode 50B face each other is reduced.

[0141] The second buried lower surface 82B may be disposed closer to the source wiring 72 in the Z direction than the second gate lower surface 53B of the second gate electrode 50B. In particular, a distance D17 in the Z direction between the second gate lower surface 53B and the second surface 12G is greater than a distance D18 in the Z direction between the second buried lower surface 82B and the second surface 12G.

[0142] The positions of the second gate electrode 50B and the second field plate electrode 60B can be set taking into consideration the threshold voltage, capacitance between the structures, etc. The distance in the Z direction between the second contact 74B and the second field plate electrode 60B is greater than the distance in the Z direction between the second gate electrode 50B and the second field plate electrode 60B. Specifically, the distance D19 in the Z direction between the second buried lower surface 82B and the second field plate upper surface 62B is greater than the distance D20 in the Z direction between the second gate lower surface 53B and the second field plate upper surface 62B.

[0143] Furthermore, the distance in the X direction between the second contact 74B and the second gate electrode 50B is greater than the distance in the X direction between the second gate electrode 50B and the second gate sidewall 26B1. Specifically, the distance D21 between the second gate-side buried side surface 84B and the second contact-side gate side surface 55B is greater than the distance D22 between the second body-side gate side surface 54B and the second gate sidewall 26B1.

[0144] [Method of manufacturing semiconductor device] Next, an example of a method for manufacturing the semiconductor device 10 will be described. Figures 6 to 23 are schematic cross-sectional views showing exemplary manufacturing steps for the semiconductor device 10. For ease of understanding, in Figures 6 to 23, components similar to those in Figure 3 are denoted by the same reference numerals.

[0145] As shown in FIG. 6 , a semiconductor layer 12 is formed, which includes a semiconductor substrate 300, which is, for example, a Si substrate, and an epitaxial layer 302 formed on the semiconductor substrate 300. The semiconductor substrate 300 can be a Si substrate containing n-type impurities. The epitaxial layer 302 may be an n-type Si layer epitaxially grown on the semiconductor substrate 300 while being doped with n-type impurities. The semiconductor layer 12 includes a first surface 12F and a second surface 12G opposite to the first surface 12F. The semiconductor substrate 300 includes the first surface 12F of the semiconductor layer 12, and the epitaxial layer 302 includes the second surface 12G of the semiconductor layer 12.

[0146] FIG. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 6. As shown in FIG. 7, the manufacturing method of the semiconductor device 10 includes forming a plurality of gate trenches 24 in the semiconductor layer 12, each having a predetermined width and depth, extending in a direction perpendicular to both the width direction and the depth direction, and spaced apart in the width direction. In one example, a portion of the epitaxial layer 302 is selectively removed to form the gate trenches 24 in the second surface 12G of the semiconductor layer 12. In more detail, a mask (not shown) having a predetermined pattern is formed on the second surface 12G of the semiconductor layer 12, and a portion of the epitaxial layer 302 is selectively removed by etching through the mask. The gate trenches 24 have sidewalls 26 and a bottom wall 28, and extend in a direction perpendicular to both the width direction and the depth direction.

[0147] 8 is a schematic cross-sectional view showing a manufacturing step subsequent to that shown in FIG. 7. As shown in FIG. 7, a first insulating layer 304 is formed on the second surface 12G of the semiconductor layer 12 and in the gate trench 24. The first insulating layer 304 is formed along the second surface 12G of the semiconductor layer 12 and the sidewall 26 and bottom wall 28 of the gate trench 24. In one example, the first insulating layer 304 is SiO formed by thermal oxidation. In another example, the first insulating layer 304 may be formed by chemical vapor deposition (CVD).

[0148] 9 is a schematic cross-sectional view showing a manufacturing step subsequent to that shown in FIG. 9. As shown in FIG. 9, a first conductive layer 306 is formed on a first insulating layer 304. The first conductive layer 306 may be, for example, conductive polysilicon. The gate trench 24 is filled with the first insulating layer 304 and the first conductive layer 306 formed on the first insulating layer 304.

[0149] FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 9 . As shown in FIG. 10 , the manufacturing method of the semiconductor device 10 may include forming a field plate electrode 60. The field plate electrode 60 is formed by etching away a portion of the first conductive layer 306 (see FIG. 9 ). Next, a second insulating layer 308 is formed to cover the field plate electrode 60 and fill the gate trench 24. The second insulating layer 308 may be made of the same material as the first insulating layer 304. The second insulating layer 308 may be SiO formed by, for example, a CVD method or a thermal oxidation method. Note that, prior to forming the second insulating layer 308, a portion of the first insulating layer 304 may be removed by etching. In FIG. 10 , the second insulating layer 308 is shown integral with at least a portion of the first insulating layer 304.

[0150] 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 10. As shown in FIG. 11, the manufacturing method of the semiconductor device 10 includes forming a lower insulating layer 310 in the gate trench 24. The first insulating layer 304 and the second insulating layer 308 (see FIG. 10) are partially removed to form the lower insulating layer 310. The lower insulating layer 310 corresponds to the remaining portions of the first insulating layer 304 and the second insulating layer 308 after etching. As a result, the second surface 12G and a portion of the sidewall 26 of the semiconductor layer 12 are exposed.

[0151] 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11. As shown in FIG. 12, the manufacturing method of the semiconductor device 10 may include forming a third insulating layer 312 on the semiconductor layer 12 and the lower insulating layer 310. The third insulating layer 312 has a relatively thin thickness. The third insulating layer 312 may cover the sidewall 26 of the gate trench 24 and a portion of the second surface 12G of the semiconductor layer 12. In one example, the third insulating layer 312 may be SiO formed by thermal oxidation. In another example, the third insulating layer 312 may be formed by CVD.

[0152] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 12. As shown in FIG. 13, the manufacturing method of the semiconductor device 10 includes forming a gate electrode 50 in the gate trench 24. The gate electrode 50 can be formed by forming a conductive layer (not shown) on the third insulating layer 312 and then etching away the excess portion. The gate electrode 50 may be made of, for example, conductive polysilicon. As a result, the gate electrode 50 faces the sidewall 26 of the gate trench 24 with the third insulating layer 312 sandwiched therebetween.

[0153] The method of manufacturing the semiconductor device 10 includes forming a drift region 16 in the semiconductor layer 12, a body region 18 formed on the drift region 16, and a source region 20 formed on the body region 18.

[0154] Fig. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to Fig. 13. As shown in Fig. 14, p-type region 314 and drift region 16 are formed in epitaxial layer 302 (see Fig. 13). In detail, p-type impurities are implanted from the surface (second surface 12G of semiconductor layer 12) of epitaxial layer 302, which is an n-type Si layer, by ion implantation using an ion implantation mask (not shown), thereby forming p-type region 314 in the surface portion of epitaxial layer 302. The remaining portion of epitaxial layer 302 becomes n-type drift region 16. The ion implantation for forming p-type region 314 is performed in multiple stages with different acceleration energies.

[0155] 15 is a schematic cross-sectional view showing a manufacturing step subsequent to that shown in FIG. 14. As shown in FIG. 15, a source region 20 and a body region 18 are formed in a p-type region 314 (see FIG. 14). In detail, n-type impurities are implanted from the surface of the p-type region 314 (the second surface 12G of the semiconductor layer 12) by ion implantation using an ion implantation mask (not shown), thereby forming an n-type source region 20 in a surface portion of the p-type region 314. The remaining portion of the p-type region 314 becomes the p-type body region 18. The semiconductor substrate 300 corresponds to the drain region 14 in FIG. 3.

[0156] Fig. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 15. As shown in Fig. 16, a first opening mask 316 is formed on the gate electrode 50 and the third insulating layer 312. The first opening mask 316 is formed on a portion of the gate electrode 50 and the third insulating layer 312. The first opening mask 316 is formed such that a portion of the gate electrode 50 and the third insulating layer 312 is exposed from the first opening mask 316.

[0157] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 16. As shown in FIG. 17, the manufacturing method for semiconductor device 10 includes forming a first opening 318 that exposes portions of body region 18 and source region 20 and removes a portion of gate electrode 50. Parts of gate electrode 50, lower insulating layer 310, and third insulating layer 312 are selectively removed by etching using a first opening mask 316 (see FIG. 16). This forms first opening 318. Parts of body region 18 and source region 20 are exposed through first opening 318. In FIG. 16, in addition to the side surface of source region 20, a portion of the top surface of source region 20 is also exposed.

[0158] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 17. As shown in FIG. 18, the manufacturing method of the semiconductor device 10 includes forming an upper insulating layer 320 to fill the first opening 318 (see FIG. 17). The upper insulating layer 320 can be made of the same material as the lower insulating layer 310. This prevents an increase in the number of materials required. Furthermore, by making the upper insulating layer 320 and the lower insulating layer 310 of the same material, the bonding strength between the upper insulating layer 320 and the lower insulating layer 310 is improved. The upper insulating layer 320 can be made of the same material as the lower insulating layer 310. The upper insulating layer 320 may be SiO2 formed by, for example, a CVD method or a thermal oxidation method. The upper insulating layer 320 and the lower insulating layer 310 may be made of different materials.

[0159] Fig. 19 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 18. As shown in Fig. 18, a second opening mask 322 is formed on the upper insulating layer 320. The second opening mask 322 is formed so as to expose a portion of the top surface of the upper insulating layer 320.

[0160] 20 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 20. As shown in FIG. 20, the manufacturing method for the semiconductor device 10 includes forming a second opening 324 in which portions of the body region 18 and the source region 20 are exposed and in which the gate electrode 50 is covered by the upper insulating layer 320. A portion of the upper insulating layer 320 is selectively removed by etching using the second opening mask 322. This forms the second opening 324. Portions of the body region 18 and the source region 20 are exposed through the second opening 324. In FIG. 20, in addition to the side surface of the source region 20, a portion of the top surface of the source region 20 is also exposed.

[0161] 21 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 21. As shown in FIG. 21, a second conductive layer 326 is formed on the upper insulating layer 320 and in the second opening 324. The second opening 324 is filled with the second conductive layer 326. The second conductive layer 326 may be made of a conductive material. The second conductive layer 326 may be made of a metallic material including, for example, tungsten.

[0162] Fig. 22 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 21. As shown in Fig. 22, the manufacturing method for semiconductor device 10 includes forming contact 74 that is embedded in second opening 324, contacts both exposed body region 18 and source region 20, and faces gate electrode 50 in the width direction of gate trench 24 with upper insulating layer 320 interposed therebetween.

[0163] The contact 74 is formed by etching away a portion of the second conductive layer 326 (see FIG. 20 ). The second conductive layer 326 is removed except for the portion embedded in the second opening 324. The etching may also remove a portion of the upper insulating layer 320 and the second conductive layer 326 embedded in the second opening 324. The contact 74 contacts the portions of the body region 18 and the source region 20 exposed by the second opening 324.

[0164] Fig. 23 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 22. As shown in Fig. 23, the manufacturing method of the semiconductor device 10 includes forming a source wiring 72 that straddles both the gate trench 24 and the source region 20 when viewed from the depth direction of the gate trench 24 and is in contact with the contact 74. The source wiring 72 is formed on the upper insulating layer 320 and the contact 74. The source wiring 72 is formed so as to be in contact with the contact 74. The source wiring 72 may be made of a metal material containing, for example, Al. Through the above steps, the semiconductor device 10 is manufactured.

[0165] [Operation of the embodiment] The operation of the semiconductor device 10 of this embodiment will now be described. In the semiconductor device 10, when a bias voltage is applied between the source wiring 72 and the drain electrode 11, a depletion layer spreads in the semiconductor layer 12. This depletion layer provides a barrier between the source and the drain.

[0166] In the semiconductor device 10, the depletion layer starts from the first gate trench 24A and the second gate trench 24B and spreads to the mesa region 30. Therefore, the narrower the mesa width T of the mesa region 30, the more likely it is that a depletion layer will be formed to connect the trenches. The absence of discontinuous portions of the depletion layer between the trenches improves the breakdown voltage.

[0167] In the semiconductor device 10, in a plan view, the first contact 74A is provided across the first gate trench 24A and the mesa region 30. A portion of the first contact 74A is provided within the first gate trench 24A. The first contact trench 70A provides the first source exposed region 20A and the first body exposed region 18A in the mesa region 30. The first contact 74A is connected to the first source exposed region 20A and the first body exposed region 18A.

[0168] [Effects of the embodiment] The semiconductor device 10 of this embodiment has the following advantages. (1) The semiconductor layer 12 includes a mesa region 30 that is configured by a drift region 16, a body region 18, and a source region 20 that are located between the first gate trench 24A and the second gate trench 24B. The first contact trench 70A is positioned offset from the first gate electrode 50A when viewed in the Z direction, and is provided across both the mesa region 30 and the first gate trench 24A.

[0169] The mesa region 30 includes a first source exposed region 20A and a first body exposed region 18A exposed by the first contact trench 70A. The first source exposed region 20A includes a first side exposed region 21A that forms part of the first contact sidewall 26A2. The first body exposed region 18A forms part of the first contact sidewall 26A2.

[0170] The first contact 74A includes a first buried portion 80A located in the first gate trench 24A. The first contact 74A reaches a position facing the first gate electrode 50A in the X direction through the first trench insulating layer 42A, and is in contact with both the first side surface exposed region 21A and the first body exposed region 18A.

[0171] This configuration makes it possible to narrow the mesa width T while ensuring contact between the source region 20 and the body region 18 and the source wiring 72. This makes it possible to improve the breakdown voltage and reduce the on-resistance.

[0172] That is, the distance between the first gate trench 24A and the second gate trench 24B is shortened by narrowing the mesa width T. This makes it easier for the depletion layers generated by the first gate trench 24A and the second gate trench 24B to connect, thereby improving the breakdown voltage.

[0173] Furthermore, the on-resistance of the semiconductor device 10 can be reduced by increasing the impurity concentration of the drift region 16. However, increasing the impurity concentration of the drift region 16 makes it difficult for the depletion layer to expand, which tends to reduce the breakdown voltage. In this regard, by narrowing the mesa width T, the depletion layers can be made more easily connected even if they are less likely to expand, thereby suppressing a decrease in the breakdown voltage.

[0174] Here, narrowing the mesa width T makes it difficult to ensure contact between the source wiring 72 and the source region 20 and the body region 18. For example, when attempting to connect the source region and the body region via a contact trench provided near the center of the mesa region, narrowing the mesa width T makes it difficult to ensure contact.

[0175] In this regard, in this embodiment, the first contact 74A includes a first buried portion 80A buried in the first gate trench 24A, and the first buried portion 80A is in contact with the first side surface exposed region 21A. In addition, the buried portion 80A reaches a depth at which a portion facing the first gate electrode 50A is generated. This increases the contact area between the first body exposed region 18A and the first contact 74A.

[0176] (2) The source region 20 in the mesa region 30 includes a first source upper surface 34A. The first source exposed region 20A includes a first upper surface exposed region 22A that includes an end of the first source upper surface 34A closer to the first gate trench 24A. The first contact 74A contacts both the first upper surface exposed region 22A and the first side surface exposed region 21A.

[0177] According to this configuration, the contact area between the first contact 74A and the source region 20 can be increased while keeping the mesa width T narrow. (3) The length D1 in the X direction of the first upper surface exposed region 22A is shorter than the length D2 in the Z direction of the first side surface exposed region 21A. With this configuration, the length of the contact region between the first contact 74A and the first source upper surface 34A can be shortened, thereby keeping the mesa width T narrower.

[0178] (4) The length D1 in the X direction of the first upper surface exposed region 22A is shorter than the length D3 in the X direction of the first buried portion 80A. With this configuration, the length of the contact region between the first contact 74A and the first source upper surface 34A can be shortened, thereby keeping the mesa width T narrower.

[0179] (5) The semiconductor device 10 includes a first field plate electrode 60A located in the first gate trench 24A. The first field plate electrode 60A is located closer to the bottom wall 28 of the first gate trench 24A than the first gate electrode 50A. The first field plate electrode 60A is insulated from the first gate electrode 50A by the first trench insulating layer 42A.

[0180] According to this configuration, the provision of the first field plate electrode 60A improves the breakdown voltage and switching speed. (6) Distance D8 between first contact 74A and first field plate electrode 60A in the Z direction is greater than distance D9 between first gate electrode 50A and first field plate electrode 60A in the Z direction. With this configuration, field plate electrode 60 can be provided in a position that contacts body region 18 but does not contact drift region 16.

[0181] (7) The distance D10 between the first contact 74A and the first gate electrode 50A in the X direction is greater than the distance D11 between the first gate electrode 50A and the first gate sidewall 26A1 in the X direction. This configuration reduces the capacitance generated between the first gate electrode 50A and the first contact 74A.

[0182] (8) The lower surface of the first buried portion 80A is located closer to the source wiring 72 in the Z direction than the first interface 38. This configuration reduces the area of ​​the region where the first gate electrode 50A and the first contact 74A face each other, thereby reducing the capacitance generated between the first gate electrode 50A and the first contact 74A.

[0183] (9) The bottom surface of the first buried portion 80A is located closer to the first interface 38 than the center of the body region 18 in the Z direction. This configuration increases the contact area between the first contact 74A and the body region 18. This allows current due to excessive voltage generated between the source and drain to escape efficiently.

[0184] (10) The lower surface of the first buried portion 80A is located closer to the second interface 39 than the center of the body region 18 in the Z direction. This configuration reduces the area of ​​the region where the first gate electrode 50A and the first contact 74A face each other in the width direction. This reduces the capacitance generated between the first gate electrode 50A and the first contact 74A.

[0185] (11) The lower surface of the first buried portion 80A is located closer to the source wiring 72 in the Z direction than the lower surface of the first gate electrode 50A. This configuration reduces the area of ​​the region where the first gate electrode 50A and the first contact 74A face each other. This reduces the capacitance generated between the first gate electrode 50A and the first contact 74A.

[0186] (12) The first contact 74A is made of a material different from that of the source wiring 72. With this configuration, the first contact 74A can be made of a metal that is easy to form the first buried portion 80A in. Also, the source wiring 72 can be made of a metal that has a relatively low resistance.

[0187] [Example of change] This embodiment can be modified as follows: This embodiment and the following modifications can be combined and implemented within the scope of technical compatibility.

[0188] The source exposed region 20A does not have to include the first upper surface exposed region 22A. The first contact 74A may contact only the side surface of the source region 20. According to this configuration, the mesa width T can be made shorter by the amount that does not include the first upper surface exposed region 22A.

[0189] The length of the first upper surface exposed region 22A in the X direction can be changed as desired. For example, the length of the first upper surface exposed region 22A in the X direction may be longer than the length of the first side surface exposed region 21A in the second direction. Furthermore, the length of the exposed upper surface in the first direction may be longer than the length of the first embedded portion 80A in the first direction.

[0190] This configuration can increase the contact area between the first contact 74A and the source region 20. This makes it possible to improve connectivity and reduce contact resistance. The semiconductor device 10 does not need to include the first field plate electrode 60 A. This configuration simplifies the manufacturing process.

[0191] The positional relationship between the first gate electrode 50A, the first field plate electrode 60A, and the first contact 74A can be changed as desired. The distance between the first contact 74A and the first field plate electrode 60A in the second direction may be smaller than the distance between the first gate electrode 50A and the first field plate electrode 60A in the second direction. Increasing the distance between the first contact 74A and the first gate electrode 50A in the first direction reduces the capacitance generated between the first contact 74A and the first gate electrode 50A.

[0192] The distance in the first direction between the first contact 74A and the first gate electrode 50A may be smaller than the distance in the first direction between the first gate electrode 50A and the first gate sidewall 26A1. By adjusting the distance in the first direction between the first gate electrode 50A and the first gate sidewall 26A1, the threshold voltage of the semiconductor device 10 can be adjusted to a desired value.

[0193] The position of the lower surface of the first buried portion 80A can be changed as desired. The lower surface of the first buried portion 80A may be located closer to the bottom wall 28 than the lower surface of the first gate electrode 50A in the second direction.

[0194] [Modification of the formation pattern of the semiconductor device 10] 24 and 25 are schematic plan views showing modified examples of the formation pattern of the semiconductor device 10 shown in Fig. 1. For ease of understanding, the same reference numerals are used in Fig. 24 and 25 to designate components similar to those in Fig. 1. For simplification, some components located below the source wiring 72 and gate wiring 112 described below are not shown.

[0195] 24 shows a formation pattern including a plurality of gate trenches 24 aligned in a stripe pattern and two trenches 402. The two trenches 402 extend in the same direction as the extension direction of each gate trench 24 (the Y direction in the example of FIG. 24). Therefore, the plurality of gate trenches 24 and the two trenches 402 may be parallel to each other.

[0196] The multiple gate trenches 24 are disposed between the two trenches 402. In the example of Fig. 24, one of the two trenches 402, the multiple gate trenches 24, and the other of the two trenches 402 are aligned in this order in the X direction. In addition, each of the two trenches 402 can have approximately the same length as each of the gate trenches 24.

[0197] The multiple gate trenches 24 and the two trenches 402 are partially covered by the source wiring 72 and the gate wiring 112 spaced apart from the source wiring 72. The source wiring 72 may be disposed so as to cover at least the entire source region 20.

[0198] FIG. 25 shows a formation pattern including a plurality of gate trenches 24 aligned in a stripe pattern and a trench 502 surrounding the plurality of gate trenches 24. The trench 502 may be formed in a rectangular frame shape in a plan view so as to surround the plurality of gate trenches 24. In this case, the trench 502 may include two portions extending along the X direction and two portions extending along the Y direction that are provided so as to connect the two portions extending along the X direction. Two ends of each gate trench 24 communicate with the trench 502 (specifically, the two portions extending along the X direction). The plurality of gate trenches 24 and the trench 502 are partially covered by a source wiring 72 and a gate wiring 112 spaced apart from the source wiring 72. The source wiring 72 may be arranged so as to cover at least the entire source region 20.

[0199] As used in this disclosure, the term "on" includes the meanings "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0200] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 3) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0201] [Note] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0202] (Appendix 1) a semiconductor layer (12) having a drift region (16), a body region (18) provided on the drift region (16), and a source region (20) provided on the body region (18); a first gate trench (24A) and a second gate trench (24B) having a predetermined width in a first direction (X) and a predetermined depth in a second direction (Z) perpendicular to the first direction (X), the first gate trench (24A) and the second gate trench (24B) being spaced apart in the first direction (X); a first trench insulating layer (42A) located in the first gate trench (24A) and in contact with a sidewall of the first gate trench (24A); a second trench insulating layer (42B) located in the second gate trench (24B) and in contact with a sidewall of the second gate trench (24B); a first gate electrode (50A) facing the body region (18) in the first gate trench (24A) while being surrounded by the first trench insulating layer (42A); a second gate electrode (50B) facing the body region (18) in the second gate trench (24B) while being surrounded by the second trench insulating layer (42B); a surface insulating layer (44) provided across the source region (20) and the first and second gate trenches (24A and 24B); a source wiring (72) located on the surface insulating layer (44); a first contact trench (70A) that penetrates the surface insulating layer (44) and reaches the first trench insulating layer (42A); a first contact (74A) connecting the source wiring (72) to the source region (20) and the body region (18); Including, the semiconductor layer (12) includes a mesa region (30) formed by the drift region (16), the body region (18), and the source region (20) between the first gate trench (24A) and the second gate trench (24B); the first contact trench (70A) is located at a position displaced from the first gate electrode (50A) when viewed from the second direction (Z), and is provided across both the mesa region (30) and the first gate trench (24A); the mesa region (30) includes a first source exposed region (20A) and a first body exposed region (18A) exposed by the first contact trench (70A); the first gate trench (24A) includes a first contact sidewall (26A2) located on the mesa region (30) side and a first gate sidewall (26A1) facing the first contact sidewall (26A2); the first source exposed region (20A) includes a first side surface exposed region (21A) that forms a part of the first contact sidewall (26A2); the first body exposed region (18A) constitutes a part of the first contact sidewall (26A2); the first contact (74A) includes a first buried portion (80A) located in the first gate trench (24A); the first buried portion (80A) reaches a position facing the first gate electrode (50A) in the first direction (X) through the first trench insulating layer (42A), and is in contact with both the first side surface exposed region (21A) and the first body exposed region (18A). Semiconductor device.

[0203] (Appendix 2) the source region (20) of the mesa region (30) includes a first source upper surface (34A); the first source exposed region (20A) includes a first upper surface exposed region (22A) including an end of the first source upper surface (34A) closer to the first gate trench (24A), the first contact (74A) is in contact with both the first upper surface exposed region (22A) and the first side surface exposed region (21A); 2. The semiconductor device according to claim 1.

[0204] (Appendix 3) a length (D1) of the first upper surface exposed region (22A) in the first direction (X) is shorter than a length (D2) of the first side surface exposed region (21A) in the second direction (Z); 3. The semiconductor device according to claim 2.

[0205] (Appendix 4) a length (D1) in the first direction (X) of the first upper surface exposed region (22A) is shorter than a length (D3) in the first direction (X) of the first embedded portion (80A); 3. The semiconductor device according to claim 2.

[0206] (Appendix 5) a first field plate electrode (60A) located in the first gate trench (24A); the first field plate electrode (60A) is located closer to a bottom wall (28A) of the first gate trench (24A) than the first gate electrode (50A) is, and is insulated from the first gate electrode (50A) by the first trench insulating layer (42A). 5. The semiconductor device according to any one of claims 1 to 4.

[0207] (Appendix 6) a distance (D8) between the first contact (74A) and the first field plate electrode (60A) in the second direction (Z) is greater than a distance (D9) between the first gate electrode (50A) and the first field plate electrode (60A) in the second direction (Z); 6. The semiconductor device according to claim 5.

[0208] (Appendix 7) a distance (D10) between the first contact (74A) and the first gate electrode (50A) in the first direction (X) is greater than a distance (D11) between the first gate electrode (50A) and the first gate sidewall (26A1) in the first direction (X); 7. The semiconductor device according to any one of claims 1 to 6.

[0209] (Appendix 8) the mesa region (30) includes a first interface (38) that is an interface between the drift region (16) and the body region (18); a lower surface of the first buried portion (80A) is located closer to the source wiring (72) than the first interface (38) in the second direction (Z); 8. The semiconductor device according to any one of claims 1 to 7.

[0210] (Appendix 9) the mesa region (30) includes a first interface (38) that is an interface between the drift region (16) and the body region (18); a lower surface of the first embedded portion (80A) is located closer to the first interface (38) than the center of the body region (18) in the second direction (Z); 9. The semiconductor device according to any one of appendices 1 to 8.

[0211] (Appendix 10) the mesa region (30) includes a second interface (39) that is an interface between the body region (18) and the source region (20); a lower surface of the first embedded portion (80A) is located closer to the second interface (39) than the center of the body region (18) in the second direction (Z); 9. The semiconductor device according to any one of appendices 1 to 8.

[0212] (Appendix 11) a lower surface of the first buried portion (80A) is located closer to the source wiring (72) than a lower surface of the first gate electrode (50A) in the second direction (Z); 11. The semiconductor device according to any one of claims 1 to 10.

[0213] (Appendix 12) The first contact (74A) is made of a material different from that of the source wiring (72). 12. The semiconductor device according to any one of claims 1 to 11.

[0214] (Appendix 13) forming a plurality of gate trenches (24) in the semiconductor layer (12) having a predetermined width and depth, extending in a direction perpendicular to both the width direction and the depth direction, and spaced apart in the width direction; forming a lower insulating layer (310) in the gate trench (24); forming a gate electrode (50) in the gate trench (24); forming a drift region (16) in the semiconductor layer (12), a body region (18) formed on the drift region (16), and a source region (20) formed on the body region (18); forming a first opening (318) in which a portion of the body region (18) and the source region (20) are exposed and a portion of the gate electrode (50) is removed; forming an upper insulating layer (320) to fill the first opening (318); forming a second opening (324) exposing a portion of the body region (18) and the source region (20) and covering the gate electrode (50) with the upper insulating layer (320); forming a contact (74) embedded in the second opening (324), in contact with both the exposed body region (18) and the exposed source region (20), and facing the gate electrode (50) across the upper insulating layer (320) in the width direction of the gate trench (24); forming a source wiring (72) that straddles both the gate trench (24) and the source region (20) when viewed from the depth direction of the gate trench (24) and that contacts the contact (74); A method for manufacturing a semiconductor device, comprising:

[0215] (Appendix 14) The lower insulating layer (310) and the upper insulating layer (320) are made of the same material. 14. A method for manufacturing a semiconductor device according to claim 13.

[0216] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0217] 10...Semiconductor device 11...Drain electrode 12...Semiconductor layer 12F…First page 12G…Second side 14...Drain region 16...Drift region 18...Body area 18A…First exposed body area 18B...Second exposed body area 20...Source region 20A…First source exposed area 20B...Second source exposed area 21A…1st side exposed area 21B…Second side exposed area 22A…1st top exposed area 22B…Second top exposed area 24...Gate trench 24A...First gate trench 24B...Second gate trench 26…Side wall 26A1...First gate side wall 26A2...First contact side wall 26B1...Second Gate side wall 26B2...Second contact sidewall 28...Bottom wall 28A...First bottom wall 28B...Second bottom wall 30...Mesa area 34A…Top of first source 36...Connection area 34B...Top of second source 38…1st interface 39…Second interface 40...insulating layer 42...Trench insulating layer 42A...First trench insulating layer 42B...Second trench insulating layer 44...Surface insulating layer 44A...insulated top 44B...Insulated bottom 50...Gate electrode 50A...First gate electrode 50B...Second gate electrode 52A...Top of the first gate 52B...Top of the second gate 53A...Underside of the first gate 53B...Underside of the second gate 54A...First body side gate side 54B...Second body side gate side 55A...First contact gate side 55B...Second contact gate side 56A...First body corner 56B...Second body corner 57A...First contact corner 57B...Second contact side corner 60...Field plate electrode 60A...First field plate electrode 60B...Second field plate electrode 62A...Top surface of first field plate 62B...Top surface of second field plate 70...Contact trench 70A...First contact trench 70B...Second contact trench 72...Source wiring 74...Contact 74A...First contact 74B...Second contact 76A...First connection part 76B...Second connection part 77A...First connection top 77B...Second connection top 80A...First embedded part 80B...Second embedded part 82A...First embedded bottom 82B...Second embedded bottom 83A...First mesa side embedded side 83B... Second mesa side embedded side 84A...First gate side embedded side 84B...Second gate side embedded side 102...Peripheral trench 104...Peripheral electrode 106...p-type region 108...1st p-type region 110...2nd p-type region 112...Gate wiring 114...Gate contact 116…Source Contact 118...Peripheral contact 120…1st electrode 300...Semiconductor substrate 302...Epitaxial layer 304...First insulating layer 306...First conductive layer 308...Second insulating layer 310...Lower insulating layer 312...Third insulating layer 314...p-type region 316...First opening mask 318...First opening 320...Upper insulating layer 322...Second opening mask 324...Second opening 326...Second conductive layer 402,502...Trench T: Mesa width

Claims

1. a semiconductor layer having a drift region, a body region provided on the drift region, and a source region provided on the body region; a first gate trench and a second gate trench having a predetermined width in a first direction and a predetermined depth in a second direction perpendicular to the first direction, the first gate trench and the second gate trench being spaced apart in the first direction; a first trench insulating layer located within the first gate trench and in contact with a sidewall of the first gate trench; a second trench insulating layer located within the second gate trench and in contact with a sidewall of the second gate trench; a first gate electrode facing the body region in the first gate trench while being surrounded by the first trench insulating layer; a second gate electrode facing the body region in the second gate trench while being surrounded by the second trench insulating layer; a surface insulating layer provided across the source region, the first gate trench, and the second gate trench; a source wiring located on the surface insulating layer; a first contact trench that penetrates the surface insulating layer and reaches the first trench insulating layer; a first contact connecting the source wiring to the source region and the body region; Including, the semiconductor layer includes a mesa region formed by the drift region, the body region, and the source region between the first gate trench and the second gate trench; the first contact trench is positioned offset from the first gate electrode when viewed from the second direction and is provided across both the mesa region and the first gate trench; the mesa region includes a first source exposure region and a first body exposure region exposed by the first contact trench; the first gate trench includes a first contact sidewall located on the mesa region side and a first gate sidewall facing the first contact sidewall, the first source exposure region includes a first side surface exposure region that forms a part of the first contact sidewall; the first body exposure region forms a part of the first contact sidewall; the first contact includes a first buried portion located in the first gate trench; the first buried portion reaches a position facing the first gate electrode in the first direction via the first trench insulating layer, and is in contact with both the first side surface exposed region and the first body exposed region. Semiconductor device.

2. the source region of the mesa region includes a first source top surface; the first source exposed region includes a first upper surface exposed region including an end portion of the first source upper surface that is closer to the first gate trench; the first contact contacts both the first top surface exposed region and the first side surface exposed region; The semiconductor device according to claim 1 .

3. a length of the first upper surface exposed region in the first direction is shorter than a length of the first side surface exposed region in the second direction; The semiconductor device according to claim 2 .

4. a length in the first direction of the first upper surface exposed region is shorter than a length in the first direction of the first buried portion; The semiconductor device according to claim 2 .

5. a first field plate electrode located in the first gate trench; the first field plate electrode is located closer to a bottom wall of the first gate trench than the first gate electrode, and is insulated from the first gate electrode by the first trench insulating layer; The semiconductor device according to claim 1 .

6. a distance between the first contact and the first field plate electrode in the second direction is greater than a distance between the first gate electrode and the first field plate electrode in the second direction; The semiconductor device according to claim 5 .

7. a distance between the first contact and the first gate electrode in the first direction is greater than a distance between the first gate electrode and the first gate sidewall in the first direction; The semiconductor device according to claim 1 .

8. the mesa region includes a first interface that is an interface between the drift region and the body region; a lower surface of the first buried portion is located closer to the source line than the first interface in the second direction; The semiconductor device according to claim 1 .

9. the mesa region includes a first interface that is an interface between the drift region and the body region; a lower surface of the first buried portion is located closer to the first interface than a center of the body region in the second direction; The semiconductor device according to claim 1 .

10. the mesa region includes a second interface that is an interface between the body region and the source region; a lower surface of the first buried portion is located closer to the second interface than a center of the body region in the second direction; The semiconductor device according to claim 1 .

11. a lower surface of the first buried portion is located closer to the source line than a lower surface of the first gate electrode in the second direction; The semiconductor device according to claim 1 .

12. the first contact is made of a material different from that of the source line; The semiconductor device according to claim 1 .

13. forming a plurality of gate trenches in the semiconductor layer, each having a predetermined width and depth, extending in a direction perpendicular to both the width direction and the depth direction, and spaced apart from each other in the width direction; forming a lower insulating layer in the gate trench; forming a gate electrode in the gate trench; forming a drift region in the semiconductor layer, a body region formed on the drift region, and a source region formed on the body region; forming a first opening in which a portion of the body region and a portion of the source region are exposed and a portion of the gate electrode is removed; forming an upper insulating layer to fill the first opening; forming a second opening in which the body region and a portion of the source region are exposed and the gate electrode is covered by the upper insulating layer; forming a contact embedded in the second opening, in contact with both the exposed body region and the exposed source region, and facing the gate electrode in the width direction via the upper insulating layer; forming a source wiring that straddles both the gate trench and the source region when viewed from the depth direction of the gate trench and that is in contact with the contact; A method for manufacturing a semiconductor device, comprising:

14. the lower insulating layer and the upper insulating layer are made of the same material. The method for manufacturing a semiconductor device according to claim 13.

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