Semiconductor device

Abstract

To suppress generation of a leakage current between a drain and a gate in a semiconductor device.SOLUTION: A semiconductor device includes a gate trench 36, a floating trench 52, and a plurality of protective trenches 44 provided outside the floating trench 52. The gate trench 36 includes a first peripheral gate trench portion side 38A provided in the peripheral region 28 and a second peripheral gate trench portion side 38A provided farther outward than the first peripheral gate trench portion side 38B. The floating trench 52 is provided outside the outer peripheral gate trench portions 38A and 38B. The floating trench 52 and each of the outer peripheral gate trench portions 38A and 38B have larger widths than the protection trench 44.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having a basic structure as a trench-gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) that includes a semiconductor substrate, an epitaxial layer epitaxially grown on the surface of the semiconductor substrate, and a plurality of gate trenches.

[0003] The epitaxial layer has a drift region, a channel region stacked on the drift region, and a source region stacked on the channel region. The drift region is exposed at the bottom of the gate trench. A gate insulating film is formed on the inner surface of the gate trench. A polysilicon gate is embedded in the gate trench, on the inner surface of the gate insulating film. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-194881

[0005] [overview] There is a demand for suppressing the occurrence of leakage current between the drain and gate in semiconductor devices.

[0006] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer provided with an active region and a peripheral region surrounding the active region, a gate trench provided in the semiconductor layer, a gate insulating film provided in the gate trench, a gate electrode embedded in the gate insulating film within the gate trench, a floating trench provided in the peripheral region, a floating insulating film provided in the floating trench, a floating electrode embedded in the floating insulating film within the floating trench, a plurality of protection trenches provided outward from the floating trench, and a plurality of protection electrodes. and a protective insulating film provided in each of the plurality of protective trenches, and a protective electrode embedded in the protective insulating film within each of the plurality of protective trenches, wherein the gate trench includes a first peripheral gate trench portion provided in the peripheral region and a second peripheral gate trench portion provided outward from the first peripheral gate trench portion, the floating trench is provided outward from both the first peripheral gate trench portion and the second peripheral gate trench portion, and each of the floating trench, the first peripheral gate trench portion, and the second peripheral gate trench portion has a width greater than that of the protective trench. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment. [Figure 2] FIG. 2 is a schematic plan view for explaining metal layers of the semiconductor device of FIG. [Figure 3] FIG. 3 is a schematic plan view for explaining a configuration provided in a semiconductor layer of the semiconductor device of FIG. [Figure 4] FIG. 4 is a partial enlarged view of the area indicated by F4 in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a partial enlarged view of the area indicated by F6 in FIG. [Figure 7]FIG. 7 is a partial enlarged view of the area indicated by F7 in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of the semiconductor device taken along line F8-F8 in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of the semiconductor device taken along line F9-F9 in FIG. [Figure 10] FIG. 10 is a partial enlarged view of the area indicated by F10 in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view of the first outer periphery gate trench, the second outer periphery gate trench, and the surrounding area. [Figure 12] FIG. 12 is a schematic plan view for explaining a configuration provided in a semiconductor layer in the peripheral region of the semiconductor device of the first comparative example. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the results of a simulation of the expansion of the depletion layer in the peripheral region in the semiconductor device of the first comparative example. [Figure 14] FIG. 14 is a schematic cross-sectional view showing the simulation results of the electric field intensity in the outer periphery region of the semiconductor device of the first comparative example. [Figure 15] FIG. 15 is a schematic cross-sectional view of the first outer periphery gate trench, the second outer periphery gate trench, and the surrounding areas in the semiconductor device of the first comparative example. [Figure 16] FIG. 16 is a schematic plan view for explaining a configuration provided in a semiconductor layer in the peripheral region of a semiconductor device of a second comparative example. [Figure 17] FIG. 17 is a schematic cross-sectional view showing the results of a simulation of the expansion of the depletion layer in the peripheral region in the semiconductor device of the second comparative example. [Figure 18] FIG. 18 is a schematic cross-sectional view showing the simulation results of the electric field intensity in the outer periphery region of the semiconductor device of the second comparative example. [Figure 19] FIG. 19 is a schematic cross-sectional view showing the results of a simulation of the expansion of a depletion layer in the peripheral region of the semiconductor device according to the embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view showing the results of a simulation of the electric field intensity in the outer periphery region of the semiconductor device according to the embodiment. [Figure 21] FIG. 21 is a schematic plan view for explaining a configuration provided in a semiconductor layer in the peripheral region in a semiconductor device of a modified example.

[0008] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] Terms such as "first," "second," and "third" are used in this disclosure merely to label and are not necessarily intended to dictate any ordering of their objects. The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0011] As used in this disclosure, "the dimensions (width, length, depth) of A are equal to the dimensions (width, length, depth) of B" or "the dimensions (width, length, depth) of A and the dimensions (width, length, depth) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length, depth) of A and the dimensions (width, length, depth) of B is, for example, within 10% of the dimensions (width, length, depth) of A.

[0012] <Embodiment> [Plane layout of semiconductor device] The planar layout of a semiconductor device 10 according to one embodiment will be described with reference to FIGS. 1 to 3. FIGS. 1 to 3 schematically show the planar structure of the semiconductor device 10 according to one embodiment. FIGS. 2 and 3 show some components of the semiconductor device 10 in a see-through manner. More specifically, FIG. 2 is a schematic plan view of the semiconductor device 10, in which a passivation layer 12, which will be described later from FIG. 1, is shown see-through. FIG. 3 is a schematic plan view of the semiconductor device 10, in which a metal layer 18 (a source wiring 20, a gate wiring 22, and a peripheral electrode 24), which will be described later from FIG. 2, is shown see-through. For ease of understanding, the metal layer 18 is indicated by a dashed line in FIG. 3. For ease of understanding, a floating trench 52, which will be described later, is omitted from FIGS. 1 to 3.

[0013] The term "plan view" used in this disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Figure 1. Unless explicitly stated otherwise, "plan view" refers to viewing the semiconductor device 10 from above along the Z-axis.

[0014] As shown in FIG. 1, the semiconductor device 10 may have a rectangular shape in a plan view. For example, the semiconductor device 10 may have a rectangular parallelepiped shape. For example, the semiconductor device 10 may be formed in a flat plate shape with the Z-axis direction as the thickness direction. The semiconductor device 10 may include a passivation layer 12. The passivation layer 12 may be made of any material capable of protecting the underlying structure. For example, the passivation layer 12 may be made of a silicon nitride (SiN) film. The passivation layer 12 may include pad openings 14 and 16. The material of the passivation layer 12 may be changed as desired. For example, the passivation layer 12 may be made of a silicon oxide (SiO2) film. Alternatively, the passivation layer 12 may be made of a stacked structure of a SiN film and a SiO2 film.

[0015] The semiconductor device 10 may further include a metal layer 18. The passivation layer 12 at least partially covers the metal layer 18. The metal layer 18 may be formed of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a Cu alloy, and an Al alloy. In one example, the metal layer 18 may be formed of an AlCu alloy. In one example, the metal layer 18 may have a stacked structure (see FIG. 11 ) of a first conductive layer 19A and a second conductive layer 19B provided on the first conductive layer 19A. The first conductive layer 19A may be formed of a material containing Ti, for example. The second conductive layer 19B may be formed of a material containing Al, for example. In one example, the second conductive layer 19B may be formed of an AlCu alloy.

[0016] The metal layer 18 may include a source line 20, a gate line 22, and a peripheral electrode 24. The source line 20, the gate line 22, and the peripheral electrode 24 are spaced apart from one another. The gate line 22 is spaced apart from the source line 20 and surrounds it. The peripheral electrode 24 is spaced apart from the gate line 22 and surrounds it. Further details of the source line 20, the gate line 22, and the peripheral electrode 24 will be described below with reference to FIG. 2.

[0017] The pad opening 14 can at least partially expose the source wiring 20. The pad opening 16 can at least partially expose the gate wiring 22. The pad openings 14 and 16 can be provided to enable external connection to the source wiring 20 and the gate wiring 22, respectively. On the other hand, the peripheral electrode 24 may be completely covered by the passivation layer 12. The configuration (e.g., position, shape, size, number, etc.) of the pad openings 14 and 16 can be determined appropriately depending on, for example, the design and usage of the semiconductor device 10, and is not limited to the example of FIG. 1.

[0018] As shown in Fig. 2, the semiconductor device 10 may include a semiconductor layer 26. The metal layer 18 is formed on the semiconductor layer 26. The semiconductor layer 26 includes a first surface 26A and a second surface 26B opposite to the first surface 26A (see Fig. 5). The Z-axis direction shown in Fig. 2 corresponds to a direction perpendicular to the first surface 26A and the second surface 26B of the semiconductor layer 26.

[0019] The semiconductor layer 26 can be formed of at least one of silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). In one example, the semiconductor layer 26 may be formed of Si. The second surface 26B of the semiconductor layer 26 includes two sides 26X1 and 26X2 extending along the X-axis direction and two sides 26Y1 and 26Y2 extending along the Y-axis direction. The outer edge of the semiconductor layer 26 can include four sides 26X1, 26X2, 26Y1, and 26Y2 in a plan view. The area defined by the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26 can correspond to one chip (die).

[0020] The semiconductor layer 26 can include, in plan view, a peripheral region 28 and an active region 30 surrounded by the peripheral region 28. It can also be said that the semiconductor layer 26 is provided with the active region 30 and the peripheral region 28 surrounding the active region 30. The boundary between the peripheral region 28 and the active region 30 is indicated by a two-dot chain line in FIG. 2 .

[0021] The active region 30 is a region that contributes to the operation of the semiconductor device 10 as a transistor. The peripheral region 28 is a region that does not contribute to the operation of the semiconductor device 10 as a transistor. The peripheral region 28 may include four sides 26X1, 26X2, 26Y1, and 26Y2 that form the outer edges of the semiconductor layer 26. The peripheral region 28 may have a rectangular frame shape that surrounds the active region 30 in a plan view. Further details of the semiconductor layer 26 will be described later with reference to FIG. 5.

[0022] The source wiring 20 may include a recess 20A by having a cutout that is substantially rectangular in plan view. The recess 20A may be formed at an end of the source wiring 20 that is close to one of the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26. In the example of Fig. 2, the recess 20A may be formed at the center in the X-axis direction of the source wiring 20 that is close to the side 26X2 of the semiconductor layer 26. The recess 20A may be open toward the side 26X2.

[0023] The gate wiring 22 may include gate finger portions 32 and a gate pad portion 34. The gate finger portions 32 may be arranged in the periphery region 28. The gate finger portions 32 may extend along at least a portion of the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26, thereby at least partially surrounding the source wiring 20. The gate pad portion 34 may be arranged in the periphery region 28. The gate pad portion 34 may be at least partially arranged within the recess 20A of the source wiring 20. The gate pad portion 34 may be integrally connected to the gate finger portions 32. In the example of FIG. 2 , the gate pad portion 34 may be arranged to connect two portions of the gate finger portions 32 extending along the side 26X2 in a plan view.

[0024] The peripheral electrode 24 may have a closed ring shape in a plan view. The peripheral electrode 24 may extend along the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26. The peripheral electrode 24 may be spaced apart from the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26.

[0025] 3 schematically shows some components provided in the semiconductor layer 26. The semiconductor device 10 may further include a gate trench 36 provided in the semiconductor layer 26. The gate trench 36 is provided across both the periphery region 28 and the active region 30 of the semiconductor layer 26. The gate trench 36 may include a periphery gate trench portion 38 provided in the periphery region 28, a plurality of inner gate trench portions 40 (see FIG. 4) provided in the active region 30, and a connecting gate trench portion 42 that connects the periphery gate trench portion 38 to the inner gate trench portion 40.

[0026] The active region 30 may be formed at a position overlapping the source wiring 20 in a planar view. The active region 30 may have a similar shape to the source wiring 20 including the recess 20A in a planar view. The active region 30 may be slightly smaller than the source wiring 20 including the recess 20A in a planar view. The active region 30 is covered by the source wiring 20 but is not covered by the gate pad portion 34. The inner gate trench portion 40 may be disposed in the active region 30. Therefore, the inner gate trench portion 40 may be disposed at a position overlapping the source wiring 20 in a planar view. The connection gate trench portion 42 connected to the inner gate trench portion 40 may be disposed at a position partially overlapping the source wiring 20 in a planar view.

[0027] The peripheral region 28 may have a shape similar to that of the gate finger portions 32 and the gate pad portion 34 in a plan view. The peripheral region 28 may include a region that extends into the recess 20A of the source wiring 20 in a plan view. The peripheral region 28 is covered by the gate finger portions 32 and the gate pad portion 34.

[0028] The peripheral gate trench 38 disposed in the peripheral region 28 can have a shape that surrounds the source wiring 20. In one example, the peripheral gate trench 38 can have a shape similar to that of the source wiring 20, including the recess 20A, in a planar view in the peripheral region 28. The peripheral gate trench 38 may be slightly larger than the source wiring 20, including the recess 20A, in a planar view. In this manner, the peripheral gate trench 38 can be formed in a closed ring shape having a recess that conforms to the recess 20A in a planar view. The peripheral gate trench 38 is disposed in a position that does not overlap with both the gate finger 32 and the gate pad 34 in a planar view. Furthermore, the peripheral gate trench 38 is disposed in a position that does not overlap with the source wiring 20 in a planar view. In other words, the peripheral gate trench 38 is disposed between the source wiring 20 and the gate finger 32 and the gate pad 34 in a planar view.

[0029] The semiconductor device 10 may further include a protection trench 44 formed in the semiconductor layer 26. The protection trench 44 may be arranged to surround the peripheral gate trench portion 38. The protection trench 44 may have a shape similar to that of the peripheral gate trench portion 38 in a plan view. It can also be said that the peripheral gate trench portion 38 is surrounded by the protection trench 44 in a plan view. The semiconductor device 10 includes a plurality of protection trenches 44.

[0030] Active Area The detailed configuration of the active region 30 will be described with reference to FIGS. Fig. 4 is a schematic diagram showing a partially enlarged planar structure of the active region 30 of the semiconductor device 10 of Fig. 1. Fig. 5 is a schematic diagram showing a cross-sectional structure of the active region 30 taken along line F5-F5 in Fig. 4.

[0031] 5, the semiconductor layer 26 can include a semiconductor substrate 54 including a first surface 26A of the semiconductor layer 26, and an epitaxial layer 56 formed on the semiconductor substrate 54 and including a second surface 26B of the semiconductor layer 26. In this embodiment, the semiconductor substrate 54 can be a Si substrate. The semiconductor substrate 54 can correspond to the drain region of the MISFET. The drain region (semiconductor substrate 54) can be a p-type impurity-containing epitaxial layer 56. + The impurity concentration of the semiconductor substrate 54 may be 1×10 18 cm -3 More than 1×10 20 cm -3 The semiconductor substrate 54 may have a thickness of 50 μm to 450 μm, and the epitaxial layer 56 may be a Si layer epitaxially grown on a Si substrate.

[0032] The semiconductor layer 26 (epitaxial layer 56) may include a drift region 68, a body region 70 formed on the drift region 68, and a source region 72 formed on the body region 70. The source region 72 may include a second surface 26B of the semiconductor layer 26. The semiconductor layer 26 (epitaxial layer 56) may further include a contact region 74 located below the source contact portion 46. The source wiring 20 is electrically connected to the contact region 74 via the source contact portion 46.

[0033] The drift region 68 is a p-type impurity region containing a lower concentration of p-type impurities than the drain region (semiconductor substrate 54). - The impurity concentration of the drift region 68 may be 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 68 may have a thickness of at least 1 μm and at most 25 μm.

[0034] The body region 70 is an n-type impurity-containing - The impurity concentration of the body region 70 may be 1×10 16 cm -3 More than 1×1018 cm -3 The body region 70 may have a thickness of not less than 0.5 μm and not more than 1.5 μm.

[0035] The source region 72 is a p-type impurity region containing a higher concentration of p-type impurities than the drift region 68. + The impurity concentration of the source region 72 may be higher than that of the body region 70. The impurity concentration of the source region 72 may be 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 72 may have a thickness of at least 0.1 μm and at most 1 μm.

[0036] The contact region 74 is an n-type impurity-containing + The impurity concentration of the contact region 74 is higher than that of the body region 70, and is 1×10 19 cm -3 More than 1×10 21 cm -3 It can be as follows:

[0037] In this disclosure, p-type is also referred to as the first conductivity type, and n-type is also referred to as the second conductivity type. P-type impurities may be, for example, boron (B) or aluminum (Al). N-type impurities may be, for example, phosphorus (P) or arsenic (As).

[0038] The semiconductor device 10 may further include a drain electrode 58 formed on the first surface 26A of the semiconductor layer 26. The drain electrode 58 is electrically connected to the drain region (semiconductor substrate 54). The drain electrode 58 may be formed of at least one of Ti, Ni, Au, Ag, Cu, Al, a Cu alloy, and an Al alloy.

[0039] The semiconductor device 10 may further include an insulating layer 60 formed on the semiconductor layer 26. In one example, the insulating layer 60 may be formed of SiO2. Additionally or alternatively, the insulating layer 60 may include a film formed of an insulating material other than SiO2, such as SiN. The insulating layer 60 may be configured with a stacked structure of a SiN film and a SiO2 film.

[0040] The insulating layer 60 is in contact with the second surface 26B of the semiconductor layer 26. The source wiring 20, the gate wiring 22, and the peripheral electrode 24 (all see FIG. 3) are formed on the insulating layer 60. The passivation layer 12 (see FIG. 1) at least partially covers the source wiring 20, the gate wiring 22, and the peripheral electrode 24 formed on the insulating layer 60. Portions of the insulating layer 60 that are not covered by the source wiring 20, the gate wiring 22, and the peripheral electrode 24 may also be covered by the passivation layer 12.

[0041] The gate trench 36 includes an inner gate trench portion 40 disposed in the active region 30. The inner gate trench portion 40 has an opening in the second surface 26B of the semiconductor layer 26 and has a depth in the Z-axis direction. The inner gate trench portion 40 penetrates the source region 72 and the body region 70 and reaches the drift region 68. As shown in FIG. 4 , the inner gate trench portion 40 surrounds the drift region 68, the body region 70, and the source region 72, thereby defining a transistor cell 73 (semiconductor element structure) including the drift region 68, the body region 70, and the source region 72. The transistor cell 73 is provided at a position overlapping the source wiring 20 in a plan view. In other words, the transistor cell 73 is covered by the source wiring 20 but is not covered by the gate wiring 22 or the peripheral electrode 24.

[0042] As shown in FIG. 4, a plurality of transistor cells 73 are provided. The plurality of transistor cells 73 are arranged in a staggered pattern. Each transistor cell 73 has a quadrangular shape in a plan view. In one example, each transistor cell 73 has a rectangular shape in a plan view. The arrangement of the plurality of transistor cells 73 can be changed as desired. In one example, the plurality of transistor cells 73 may be arranged in a matrix or stripe pattern.

[0043] The inner gate trench portion 40 is provided between the plurality of transistor cells 73. The inner gate trench portion 40 includes a sidewall 40A and a bottom wall 40B. The inner gate trench portion 40 may have a tapered shape, for example, with its width gradually narrowing in the Z-axis direction. That is, a pair of sidewalls 40A facing each other in the X-axis direction are inclined so as to approach each other toward the bottom wall 40B. The bottom wall 40B is curved and convex downward. The shape of the inner gate trench portion 40 can be arbitrarily changed. In one example, the sidewall 40A may extend along the Z-axis direction. In one example, the bottom wall 40B may be a plane extending in a direction perpendicular to the Z-axis direction.

[0044] The width of the inner gate trench portion 40 can be, for example, 0.17 μm or more and 0.22 μm or less at the opening end of the gate trench 36. The depth of the inner gate trench portion 40 can be, for example, 0.8 μm or more and 1.2 μm or less. Here, the width of the inner gate trench portion 40 can be defined by the dimension in a direction perpendicular to the direction in which the inner gate trench portion 40 extends in a plan view. The depth of the inner gate trench portion 40 can be defined by the distance in the Z-axis direction between the opening end of the inner gate trench portion 40 and the bottom wall 40B of the inner gate trench portion 40.

[0045] The arrangement pitch P1 of adjacent inner gate trench portions 40 is, for example, 1 μm or less. When the inner gate trench portions 40 are provided so as to surround each of a plurality of transistor cells 73 as shown in Fig. 4, the arrangement pitch P1 of the inner gate trench portions 40 may be defined as, for example, the distance between the inner gate trench portions 40 that face each other with one transistor cell 73 interposed therebetween.

[0046] The semiconductor device 10 may further include a gate electrode 62 embedded in the gate trench 36 with an insulating layer 60 interposed therebetween. The gate electrode 62 may be formed, for example, from conductive polysilicon. The insulating layer 60 may include a gate insulating film 64 provided in the gate trench 36 and an interlayer insulating film 66 provided between the metal layer 18 and the semiconductor layer 26. The gate insulating film 64 is interposed between the gate electrode 62 and the semiconductor layer 26 and covers the gate trench 36. Therefore, the gate electrode 62 is separated from the semiconductor layer 26 by the gate insulating film 64. It can also be said that the gate electrode 62 is embedded in the gate insulating film 64 within the gate trench 36.

[0047] FIG. 5 shows a gate insulating film 64 that is interposed between the gate electrode 62 and the semiconductor layer 26 and covers the inner gate trench portion 40, and an interlayer insulating film 66 that is provided between the source wiring 20 and the semiconductor layer 26.

[0048] The gate electrode 62 faces the body region 70 via the gate insulating film 64. In the body region 70, a side portion 71 facing the gate electrode 62 is a channel portion. When a predetermined voltage is applied to the gate electrode 62, the n-type - A channel is formed in the side portion 71 of the body region 70. The semiconductor device 10 receives p-type charge via this channel. + Type source region 72 and p - This allows control of the flow of holes in the Z-axis direction between the transistor cell 73 and the gate electrode 62. In this manner, in the semiconductor device 10, the transistor cell 73 and the gate electrode 62 form a vertical element structure in which current flows in the thickness direction of the semiconductor layer 26.

[0049] The semiconductor device 10 may further include a source contact portion 46 connected to the source wiring 20. The source contact portion 46 may be disposed in a transistor cell 73 surrounded by the inner gate trench portion 40.

[0050] [Outer area] Next, the detailed configuration of the outer peripheral region 28 will be described with reference to FIGS. FIG. 6 is a schematic enlarged plan view of the outer peripheral region 28, shown by the dashed-dotted frame F6 in FIG. 3. FIG. 7 is a schematic enlarged plan view of a portion of FIG. 6. FIG. 8 is a schematic cross-sectional view of the outer peripheral region 28 taken along line F8-F8 in FIG. 7. FIG. 9 is a schematic cross-sectional view of the outer peripheral region 28 taken along line F9-F9 in FIG. 7. FIG. 10 is a schematic enlarged cross-sectional view of a portion of FIG. 9. FIG. 11 is a schematic cross-sectional view of a portion of FIG. 10.

[0051] 6 , the perimeter gate trench 38 disposed in the perimeter region 28 may include a first perimeter gate trench 38A and a second perimeter gate trench 38B located outward from the first perimeter gate trench 38A. In plan view, the second perimeter gate trench 38B may be located on the opposite side of the first perimeter gate trench 38A from the active region 30. In plan view, the second perimeter gate trench 38B may be located farther from the active region 30 than the first perimeter gate trench 38A. In other words, the first perimeter gate trench 38A may be located closer to the active region 30 than the second perimeter gate trench 38B. The first perimeter gate trench 38A and the second perimeter gate trench 38B may have similar shapes in plan view.

[0052] Each of the outer periphery gate trench portions 38A, 38B may have a width greater than that of the inner gate trench portion 40. Each of the outer periphery gate trench portions 38A, 38B may have a width greater than that of the protection trench 44. Specifically, as shown in FIG. 7 , the width W1A of the first outer periphery gate trench portion 38A is greater than the width W3 of the protection trench 44. The width W1B of the second outer periphery gate trench portion 38B is greater than the width W3 of the protection trench 44. In one example, the width W1A of the first outer periphery gate trench portion 38A is equal to the width W1B of the second outer periphery gate trench portion 38B. Here, the width W1A of the first outer periphery gate trench portion 38A can be defined by the dimension in a direction perpendicular to the extension direction of the first outer periphery gate trench portion 38A in a plan view. Similarly, the width W1B of the second outer periphery gate trench portion 38B can be defined by the dimension in a direction perpendicular to the extension direction of the second outer periphery gate trench portion 38B in a plan view.

[0053] 6, the first outer periphery gate trench portion 38A has a quadrangular ring shape in plan view. The first outer periphery gate trench portion 38A includes a first linear portion 38AA extending along the X-axis direction, a second linear portion 38AB extending along the Y-axis direction, and a corner portion 38AC connecting the first linear portion 38AA and the second linear portion 38AB. The corner portion 38AC is curved so as to convex outward from the outer periphery region 28. In one example, the corner portion 38AC may be curved to have a predetermined radius of curvature R (e.g., 15 μm or more and 50 μm or less).

[0054] Like the first outer periphery gate trench 38A, the second outer periphery gate trench 38B has a rectangular ring shape in plan view. The second outer periphery gate trench 38B includes a first linear portion 38BA extending along the X-axis direction, a second linear portion 38BB extending along the Y-axis direction, and a corner portion 38BC connecting the first linear portion 38BA and the second linear portion 38BB. The first linear portion 38BA is disposed adjacent to the first linear portion 38AA of the first outer periphery gate trench 38A in the X-axis direction. The second linear portion 38BB is disposed adjacent to the second linear portion 38AB of the first outer periphery gate trench 38A in the Y-axis direction. The corner portion 38BC is disposed adjacent to the corner portion 38AC of the first outer periphery gate trench 38A.

[0055] The semiconductor device 10 may further include a gate contact portion 48 connected to the gate wiring 22 (gate finger portion 32). The gate contact portion 48 may be arranged in a region overlapping with each of the peripheral gate trench portions 38A, 38B in a plan view. The semiconductor device 10 may include multiple gate contact portions 48. The multiple gate contact portions 48 are arranged on the first linear portions 38AA, 38BA and the second linear portions 38AB, 38BB of each of the peripheral gate trench portions 38A, 38B. On the other hand, the multiple gate contact portions 48 are not arranged on the corner portions 38AC, 38BC of each of the peripheral gate trench portions 38A, 38B.

[0056] The connection gate trench 42 connects the multiple inner gate trenches 40 and the first outer periphery gate trench 38A. The connection gate trench 42 is located closer to the active region 30 than the first outer periphery gate trench 38A. The connection gate trench 42 is connected to the first outer periphery gate trench 38A. On the other hand, the connection gate trench 42 is not connected to the second outer periphery gate trench 38B. The connection gate trench 42 is arranged across both the outer periphery region 28 and the active region 30. A plurality of connection gate trenches 42 may be arranged in a striped pattern. The multiple connection gate trenches 42 are connected to both the first linear portion 38AA and the second linear portion 38AB of the first outer periphery gate trench 38A. Of the multiple connection gate trenches 42, the connection gate trench 42 connected to the first linear portion 38AA can extend in a direction intersecting the extension direction of the first linear portion 38AA. Of the multiple connection gate trench portions 42, the connection gate trench portions 42 connected to the second linear portions 38AB can extend in a direction intersecting the direction in which the second linear portions 38AB extend. On the other hand, the multiple connection gate trench portions 42 are not connected to the corner portions 38AC.

[0057] A plurality of protective trenches 44 (18 in the example of FIG. 6 ) surrounding each of the peripheral gate trench portions 38A, 38B are arranged in the peripheral region 28. The semiconductor device 10 may include one or more protective trenches 44. The number of protective trenches 44 can be set appropriately depending on the desired performance and layout of the semiconductor device 10. In the example of FIG. 6 , the multiple protective trenches 44 are arranged at equal pitches.

[0058] 6, when a plurality of protective trenches 44 are provided, some of the protective trenches 44 may be arranged at positions overlapping the gate finger portions 32 in a plan view. Alternatively, all of the plurality of protective trenches 44 may be arranged at positions overlapping the gate finger portions 32 in a plan view.

[0059] The semiconductor device 10 may further include a peripheral contact portion 50 connected to the peripheral electrode 24. The peripheral contact portion 50 may be formed in a closed ring shape. The ring-shaped peripheral contact portion 50 may surround the protection trench 44 in a plan view. The semiconductor device 10 may include multiple peripheral contact portions 50.

[0060] The source contact portion 46, the gate contact portion 48, and the peripheral contact portion 50 may be formed of any metallic material. In one example, each of the contact portions 46, 48, and 50 may be made of at least one of tungsten (W), Ti, and titanium nitride (TiN).

[0061] 8, the source contact portion 46 extends through the insulating layer 60 between the source wiring 20 and the semiconductor layer 26, thereby connecting the source wiring 20 and the semiconductor layer 26. The peripheral contact portion 50 extends through the insulating layer 60 between the peripheral electrode 24 and the semiconductor layer 26, thereby connecting the peripheral electrode 24 and the semiconductor layer 26.

[0062] 6, the semiconductor device 10 may include a floating trench 52 provided in the periphery region 28. The floating trench 52 is located, for example, between the connection gate trench portion 42 and the plurality of protection trenches 44. In other words, the plurality of protection trenches 44 are located outward from the floating trench 52. The floating trench 52 is also located outward from the first periphery gate trench portion 38A and the second periphery gate trench portion 38B. Further details of the floating trench 52 will be described later with reference to FIGS. 6 and 10.

[0063] As shown in FIG. 8 , each of the outer periphery gate trench portions 38A, 38B, like the inner gate trench portion 40 (see FIG. 5 ), has an opening in the second surface 26B of the semiconductor layer 26 and a depth in the Z-axis direction. Similarly, the protection trench 44 also has an opening in the second surface 26B of the semiconductor layer 26 and a depth in the Z-axis direction. In the illustrated example, the outer periphery gate trench portions 38A, 38B and the protection trench 44 are shown to have approximately the same depth, but in other examples, they may have different depths. For example, the protection trench 44 may be formed deeper in the semiconductor layer 26 than the outer periphery gate trench portions 38A, 38B. Alternatively, the protection trench 44 may be formed shallower in the semiconductor layer 26 than the outer periphery gate trench portions 38A, 38B. In yet another example, the outer periphery gate trench portions 38A, 38B and the inner gate trench portion 40 may have different depths. For example, the outer gate trench portions 38A, 38B may be formed deeper than the inner gate trench portion 40.

[0064] 8 shows a cross section along the longitudinal direction of one connection gate trench portion 42. The two ends of the connection gate trench portion 42 are respectively connected to the first outer periphery gate trench portion 38A and the inner gate trench portion 40. In this manner, the gate trench 36 can be formed by the first outer periphery gate trench portion 38A, the inner gate trench portion 40, and the connection gate trench portion 42 communicating with each other, and by the second outer periphery gate trench portion 38B spaced outward from the first outer periphery gate trench portion 38A.

[0065] As with the inner gate trench 40, a gate electrode 62 is embedded in each of the outer periphery gate trenches 38A, 38B and the connecting gate trench 42 via an insulating layer 60. Because the first outer periphery gate trench 38A, the inner gate trench 40, and the connecting gate trench 42 are interconnected, the integrally formed gate electrode 62 can be embedded across the first outer periphery gate trench 38A, the inner gate trench 40, and the connecting gate trench 42. A gate electrode 62 other than the integrally formed gate electrode 62 can be embedded in the second outer periphery gate trench 38B.

[0066] 9 shows the portion of the first perimeter gate trench portion 38A that is not in direct communication with the connecting gate trench portion 42, and the second perimeter gate trench portion 38B. As described above and shown, each perimeter gate trench portion 38A, 38B can have a width greater than that of the inner gate trench portion 40. In one example, each perimeter gate trench portion 38A, 38B can have a width that is at least 1.2 times and at most 2.5 times the width of the inner gate trench portion 40.

[0067] The gate contact portion 48 extends through the insulating layer 60 to connect the gate finger portion 32 to the gate electrodes 62 embedded in the outer gate trenches 38A and 38B (see FIG. 10). Therefore, the gate wiring 22 is electrically connected to the gate electrodes 62.

[0068] FIG. 10 shows a cross-sectional view of the outer periphery region 28 (see FIG. 3), particularly the region covered by the gate finger portion 32. Each of the outer gate trenches 38A, 38B has an opening in the second surface 26B of the semiconductor layer 26 and extends through the body region 70 to reach the drift region 68. Each of the outer gate trenches 38A, 38B includes a sidewall 38P, a bottom wall 38Q, and a corner portion 38R connecting the sidewall 38P and the bottom wall 38Q. Each of the outer gate trenches 38A, 38B may have a tapered shape, gradually narrowing in width in the Z-axis direction. That is, a pair of opposing sidewalls 38P in the X-axis direction are inclined toward each other toward the bottom wall 38Q. The bottom wall 38Q has a curved shape that convex downward. The corner portion 38R has a curved shape that convex outward from each of the outer gate trenches 38A, 38B. The radius of curvature of the corner portion 38R is smaller than the radius of curvature of the bottom wall 38Q. The shape of each of the outer gate trench portions 38A, 38B can be changed as desired. For example, the sidewall 38P may extend along the Z-axis direction. For example, the bottom wall 38Q may be a flat surface extending in a direction perpendicular to the Z-axis direction.

[0069] As described above, the gate electrode 62 is also embedded in each of the outer gate trenches 38A, 38B via the insulating layer 60. Because each of the outer gate trenches 38A, 38B has a width greater than that of the inner gate trench 40, the gate insulating film 64 may be formed thicker in each of the outer gate trenches 38A, 38B than in the inner gate trench 40. This allows the gate electrode 62 in the outer gate trench 38 to have the same thickness as the gate electrode 62 in the inner gate trench 40. Note that the gate electrode 62 in each of the outer gate trenches 38A, 38B may have a width greater than or smaller than that of the gate electrode 62 in the inner gate trench 40.

[0070] The gate contact portion 48 extends through the insulating layer 60 (interlayer insulating film 66) located between the gate electrode 62 and the gate finger portion 32, thereby connecting the gate electrode 62 embedded in each outer gate trench portion 38A, 38B to the gate finger portion 32.

[0071] The detailed configuration of the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B will be described with reference to Fig. 11. Fig. 11 shows the cross-sectional structure of the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B.

[0072] As shown in FIG. 11, the gate electrode 62 provided in each of the outer gate trench portions 38A, 38B includes a side surface 62A, a bottom surface 62B, and a corner portion 62C connecting the side surface 62A and the bottom surface 62B.

[0073] The gate electrode 62 may have a tapered shape, for example, with its width gradually narrowing in the Z-axis direction. That is, a pair of side surfaces 62A, which form both end surfaces of the gate electrode 62 in the X-axis direction, are inclined so as to approach each other toward the bottom walls 38Q of each of the outer peripheral gate trench portions 38A, 38B. The inclination angle of the pair of side surfaces 62A with respect to the Z-axis direction is smaller than the inclination angle of the pair of side walls 38P of each of the outer peripheral gate trench portions 38A, 38B with respect to the Z-axis direction. Therefore, the distance between the pair of side surfaces 62A and the pair of side walls 38P decreases toward the bottom walls 38Q of each of the outer peripheral gate trench portions 38A, 38B.

[0074] The bottom surface 62B of the gate electrode 62 includes a flat surface perpendicular to the Z-axis direction. In one example, the distance in the Z-axis direction between the bottom surface 62B and the bottom wall 38Q of each outer gate trench portion 38A, 38B is approximately constant. The shape of the bottom surface 62B of the gate electrode 62 can be changed as desired. In one example, the bottom surface 62B of the gate electrode 62 may be curved so as to be convex downward.

[0075] The corner portions 62C of the gate electrode 62 are curved and convex outward. The corner portions 62C are smaller than the corner portions 38R of the outer peripheral gate trench portions 38A, 38B. Therefore, the distance between the corner portions 62C and 38R is smaller than the shortest distance between the pair of side surfaces 62A and the pair of sidewalls 38P.

[0076] Due to this relationship between the outer periphery gate trench portions 38A, 38B and the gate electrode 62, the thickness of the gate insulating film 64 varies within each of the outer periphery gate trench portions 38A, 38B.

[0077] The gate insulating film 64 in each of the outer gate trench portions 38A, 38B includes a first insulating film 64A provided on the sidewall 38P, a second insulating film 64B provided on the bottom wall 38Q, and a third insulating film 64C provided on the corner portion 38R.

[0078] The first insulating film 64A is interposed between the sidewall 38P and the side surface 62A of the gate electrode 62. The first insulating film 64A is in contact with both the sidewall 38P and the side surface 62A of the gate electrode 62. The thickness T1 of the first insulating film 64A becomes thinner toward the bottom wall 38Q.

[0079] The second insulating film 64B is interposed between the bottom wall 38Q and the bottom surface 62B of the gate electrode 62. The second insulating film 64B is in contact with both the bottom wall 38Q and the bottom surface 62B of the gate electrode 62. The thickness T2 of the second insulating film 64B is generally constant. The thickness T2 of the second insulating film 64B is smaller than the minimum value of the thickness T1 of the first insulating film 64A.

[0080] The third insulating film 64C is interposed between the corner portion 38R and the corner portion 62C of the gate electrode 62. The third insulating film 64C is in contact with both the corner portion 38R and the corner portion 62C of the gate electrode 62. The thickness T3 of the third insulating film 64C is thinner than the thickness T1 of the first insulating film 64A. The thickness T3 of the third insulating film 64C is equal to or smaller than the thickness T2 of the second insulating film 64B.

[0081] As shown in FIG. 10 , the protective trench 44 can be spaced apart from each of the outer periphery gate trench portions 38A, 38B. When multiple protective trenches 44 are provided, the multiple protective trenches 44 can also be spaced apart from each other. The protective trench 44 may be located outward from the second outer periphery gate trench portion 38B. The protective trench 44 is located so as to surround the second outer periphery gate trench portion 38B. In plan view, the protective trench 44 can also be said to be located on the opposite side of the second outer periphery gate trench portion 38B from the active region 30. In plan view, the protective trench 44 can also be said to be located farther from the active region 30 than the second outer periphery gate trench portion 38B. In other words, in plan view, the second outer periphery gate trench portion 38B can also be said to be located closer to the active region 30 than the protective trench 44.

[0082] In the illustrated example, the protection trench 44 can have a width smaller than that of each of the perimeter gate trench portions 38A, 38B. In other words, each of the perimeter gate trench portions 38A, 38B can have a width larger than that of the protection trench 44. That is, the widths W1A, W1B of each of the perimeter gate trench portions 38A, 38B are larger than the width W3 of the protection trench 44.

[0083] Furthermore, the protective trench 44 can have the same width as the inner gate trench portion 40 (see FIG. 7). In another example, the protective trench 44 may have a width smaller than or larger than the inner gate trench portion 40. Here, the width of the protective trench 44 can be defined by the dimension in a direction perpendicular to the direction in which the protective trench 44 extends in a plan view.

[0084] The protective trench 44 has an opening in the second surface 26B of the semiconductor layer 26 and reaches the drift region 68 by penetrating the body region 70. The sidewalls of the protective trench 44 may extend in a direction perpendicular to the second surface 26B of the semiconductor layer 26 (the Z-axis direction). In the illustrated example, the protective trench 44 may have sidewalls that are slightly inclined with respect to the Z-axis direction. In the illustrated example, the bottom wall of the protective trench 44 is formed in an overall curved shape, but is not limited to this. For example, the bottom wall of the protective trench 44 may have both ends in the X-axis direction that are curved, or may have a flat surface along the XY plane.

[0085] The semiconductor device 10 may further include a shielding electrode 76 embedded in the protection trench 44 via the insulating layer 60. The shielding electrode 76 may be formed of conductive polysilicon, for example. Since the protection trench 44 is formed in a closed ring shape in plan view, the shielding electrode 76 may also be formed in a closed ring shape in plan view.

[0086] The insulating layer 60 may further include a protective insulating film 78 provided in each of the multiple protection trenches 44. The shielding electrode 76 is embedded in the protective insulating film 78 in each of the multiple protection trenches 44. As such, the protective insulating film 78 is interposed between the shielding electrode 76 and the semiconductor layer 26 and covers the protection trenches 44, so that the shielding electrode 76 is separated from the semiconductor layer 26 by the protective insulating film 78. The shielding electrode 76 embedded in the protection trench 44 is not connected to other metal members (e.g., the gate finger portion 32) and may be in an electrically floating state. In one example, the shielding electrode 76 may have the same width as the gate electrode 62 in the inner gate trench portion 40. Note that the shielding electrode 76 may have a width larger than or smaller than the gate electrode 62 in the inner gate trench portion 40.

[0087] The thickness T4 of the protective insulating film 78 is thinner than the thickness TA of the gate insulating film 64 in the first and second outer gate trench portions 38A, 38B. In other words, the thickness TA of the gate insulating film 64 in the first and second outer gate trench portions 38A, 38B is thicker than the thickness T4 of the protective insulating film 78. More specifically, the thickness T1 of the first insulating film 64A in the gate insulating film 64 is thicker than the thickness T4 of the protective insulating film 78. The thickness T2 of the second insulating film 64B in the gate insulating film 64 is thicker than the thickness T4 of the protective insulating film 78. The thickness T3 of the third insulating film 64C in the gate insulating film 64 is thicker than the thickness T4 of the protective insulating film 78.

[0088] 10, in a region other than the active region 30 (see FIG. 3), the semiconductor layer 26 does not include the source region 72 (see FIG. 5), but includes the drift region 68 and the body region 70. Therefore, in the region shown in FIG. 10, the second surface 26B of the semiconductor layer 26 is included in the body region 70.

[0089] The floating trench 52 has an opening in the second surface 26B of the semiconductor layer 26 and reaches the drift region 68 by penetrating the body region 70. The floating trench 52 includes sidewalls 52P, a bottom wall 52Q, and corner portions 52R connecting the sidewalls 52P and the bottom wall 52Q. The floating trench 52 may be tapered, for example, so that its width gradually narrows in the Z-axis direction. That is, the pair of sidewalls 52P facing each other in the X-axis direction are inclined toward each other toward the bottom wall 52Q. The bottom wall 52Q has a curved shape that convex downward. The corner portion 52R has a curved shape that convex outward from the floating trench 52. The radius of curvature of the corner portion 52R is smaller than the radius of curvature of the bottom wall 52Q. In one example, as shown in FIG. 10 , the cross-sectional shape of the floating trench 52 is the same as the shape of each of the outer periphery gate trench portions 38A and 38B. The shape of the floating trench 52 can be changed as desired. For example, the sidewall 52P may extend along the Z-axis direction. For example, the bottom wall 52Q may be a flat surface extending in a direction perpendicular to the Z-axis direction.

[0090] The floating trench 52 has a width greater than that of the protection trench 44. That is, the width W2 of the floating trench 52 is greater than the width W3 of the protection trench 44. In one example, the width W2 of the floating trench 52 is equal to the widths W1A and W1B of the respective perimeter gate trench portions 38A and 38B.

[0091] The semiconductor device 10 may include a floating electrode 80 embedded in the floating trench 52 via an insulating layer 60. The floating electrode 80 may be made of conductive polysilicon, for example. The floating trench 52 is formed in a shape similar to that of each of the outer periphery gate trench portions 38A, 38B in a plan view. Therefore, the floating electrode 80 may also be formed in a shape similar to that of each of the outer periphery gate trench portions 38A, 38B in a plan view.

[0092] The insulating layer 60 may include a floating insulating film 82. The floating insulating film 82 is provided in the floating trench 52. The floating electrode 80 is embedded in the floating insulating film 82. As the floating insulating film 82 is interposed between the floating electrode 80 and the semiconductor layer 26 in this manner, the floating electrode 80 is separated from the semiconductor layer 26 by the floating insulating film 82. The floating electrode 80 is not connected to other metal members (e.g., the gate finger portion 32) and is in an electrically floating state.

[0093] 10 , the size and shape of the floating electrode 80 are the same as those of the gate electrode 62. Furthermore, as described above, because the width of the floating trench 52 is equal to the width of each of the outer periphery gate trench portions 38A, 38B, the floating insulating film 82 has the same size and shape as the gate insulating film 64 provided in each of the outer periphery gate trench portions 38A, 38B. Therefore, the thickness of the floating insulating film 82 is equal to the thickness of the gate insulating film 64 provided in each of the outer periphery gate trench portions 38A, 38B. In other words, the thickness of the floating insulating film 82 is thicker than the thickness of the protective insulating film 78.

[0094] [Trench layout] 7 and 10, the following describes the positional relationship between the outer periphery gate trench portions 38A, 38B, the floating trench 52, and the multiple protective trenches 44. In the following description, the protective trench 44 that is closest to the floating trench 52 among the multiple protective trenches 44 is referred to as the "inner end protective trench 44E."

[0095] As shown in FIG. 7, the first outer perimeter gate trench 38A and the second outer perimeter gate trench 38B are arranged adjacent to each other. That is, no other trenches are provided between the first outer perimeter gate trench 38A and the second outer perimeter gate trench 38B. The second outer perimeter gate trench 38B is provided further outward than the first outer perimeter gate trench 38A. That is, the second outer perimeter gate trench 38B is located on the opposite side of the active region 30 from the first outer perimeter gate trench 38A in a plan view. Also, the second outer perimeter gate trench 38B is located farther from the active region 30 than the first outer perimeter gate trench 38A in a plan view.

[0096] The floating trench 52 is provided outward from both the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B. In other words, the floating trench 52 is provided on the opposite side of the active region 30 from both the outer periphery gate trench portions 38A, 38B in plan view. In other words, the floating trench 52 is provided at a position farther from the active region 30 than the outer periphery gate trench portions 38A, 38B in plan view.

[0097] The first distance D1 between the inner end protective trench 44E and the floating trench 52 is smaller than the second distance D2 between the floating trench 52 and the second outer periphery gate trench portion 38B. The third distance D3 between two adjacent protective trenches 44 among the multiple protective trenches 44 is smaller than the second distance D2. Here, since the multiple protective trenches 44 are arranged at an equal pitch, the third distances D3 in the multiple protective trenches 44 are all equal. In one example, the first distance D1 can be equal to or smaller than the third distance D3. The first distance D1 is, for example, 0.64 μm. The third distance D3 is, for example, 0.76 μm.

[0098] Furthermore, the first distance D1 is smaller than the fourth distance D4 between the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B. The second distance D2 is larger than the fourth distance D4. The third distance D3 is smaller than the fourth distance D4. The fourth distance D4 is larger than the fifth distance D5 between adjacent connection gate trench portions 42 among the multiple connection gate trench portions 42.

[0099] The first distance D1 is equal to or less than the width W2 of the floating trench 52. The first distance D1 is equal to or less than the width W1A of the first outer periphery gate trench portion 38A. The first distance D1 is equal to or less than the width W1B of the second outer periphery gate trench portion 38B. The first distance D1 is greater than the width W3 of the protection trench 44.

[0100] The third distance D3 is equal to or less than the width W2 of the floating trench 52. The third distance D3 is equal to or less than the width W1A of the first outer periphery gate trench portion 38A. The third distance D3 is equal to or less than the width W1B of the second outer periphery gate trench portion 38B. The third distance D3 is greater than the width W3 of the protection trench 44.

[0101] In this way, because the first distance D1 is small, the region RP in which the multiple protection trenches 44 are arranged is provided adjacent to the floating trench 52 in the arrangement direction of the multiple protection trenches 44. And, because the third distance D3 is small, many protection trenches 44 are spread out in the region RP. Here, in the arrangement direction of the multiple protection trenches 44, the region RP is larger than the distance D6 between the first outer periphery gate trench portion 38A and the floating trench 52 in the arrangement direction.

[0102] [Operation of the embodiment] The operation of the semiconductor device 10 of this embodiment will be described with reference to FIG. 7 and FIGS.

[0103] 12 is a schematic diagram showing the planar structure of the peripheral region 28 of the semiconductor device 10X of the first comparative example, and mainly shows the layout of the peripheral gate trench portions 38AX, 38BX, the floating trench 52X, and the multiple protection trenches 44X.

[0104] FIG. 13 schematically illustrates the cross-sectional structure of the peripheral region 28 of the semiconductor device 10X of the first comparative example. FIG. 13 primarily illustrates the expansion of the depletion layer DLX in the peripheral region 28 of the semiconductor device 10X of the first comparative example. For convenience, the semiconductor substrate 54 and drain electrode 58 are omitted from FIG. 13. FIG. 14 illustrates an enlarged cross-sectional structure of the peripheral gate trenches 38AX and 38BX, the floating trench 52X, and their surroundings in FIG. 13. FIG. 14 primarily illustrates the electric field intensity of the peripheral gate trenches 38AX and 38BX, the floating trench 52X, and their surroundings. In FIG. 14, the darker the dots, the higher the electric field intensity. FIG. 15 illustrates an enlarged cross-sectional structure of the floating trench 52X, the second peripheral gate trench 38BX, and their surroundings.

[0105] As shown in FIG. 12 , in the peripheral region 28 of the semiconductor device 10X of the first comparative example, a floating trench 52X is disposed between the first peripheral gate trench portion 38AX and the second peripheral gate trench portion 38BX. The floating trench 52X is disposed closer to the second peripheral gate trench portion 38BX than to the first peripheral gate trench portion 38AX. The semiconductor device 10X also includes an outer floating trench 53X disposed between the second peripheral gate trench portion 38BX and the protection trench 44X. The outer floating trench 53X includes an insulating layer 60 and an outer floating electrode embedded in the insulating layer 60. The distance between the second peripheral gate trench portion 38BX and the outer floating trench 53X is greater than the distance between the second peripheral gate trench portion 38BX and the floating trench 52X. Furthermore, the distance between the second outer periphery gate trench portion 38BX and the inner end protective trench 44EX is greater than the distance between the second outer periphery gate trench portion 38BX and the floating trench 52X. Therefore, in the outer periphery region 28 of the semiconductor device 10X of the first comparative example, the region where the multiple protective trenches 44X are formed is smaller. Therefore, the number of protective trenches 44X is smaller than the number of protective trenches 44 in the embodiment.

[0106] As shown in FIG. 14 , when the semiconductor device 10X of the first comparative example is in an operating state, the electric field strength at the corner portion 38RX between the sidewall and bottom wall of the second outer gate trench portion 38BX is higher than that at the first outer gate trench portion 38AX, the floating trench 52X, and the outer floating trench 53X. If the semiconductor device 10X of the first comparative example operates continuously for, for example, 1000 hours, a void GX may be formed in the gate insulating film 64 at the corner portion 38RX of the second outer gate trench portion 38BX, as shown in FIG. 15 . This may cause electrical conduction between the gate electrode 62 and the drift region 68 via the void GX. As a result, leakage current may flow from the drift region 68 to the gate electrode 62.

[0107] As a structure for suppressing electric field concentration in the second outer periphery gate trench portion in order to suppress the occurrence of such leakage current, a semiconductor device 10Y of a second comparative example shown in Figures 16 to 18 can be considered. Hereinafter, the semiconductor device 10Y of the second comparative example will be described with reference to Figures 16 to 18.

[0108] FIG. 16 schematically illustrates the planar structure of the peripheral region 28 of the semiconductor device 10Y of the second comparative example. FIG. 16 mainly illustrates the layout of the peripheral gate trench portions 38AY, 38BY, the floating trench 52Y, and the multiple protection trenches 44Y. FIG. 17 schematically illustrates the cross-sectional structure of the peripheral region 28 of the semiconductor device 10Y of the second comparative example. FIG. 17 mainly illustrates the expansion of the depletion layer DLY in the peripheral region 28 of the semiconductor device 10Y of the second comparative example. FIG. 18 illustrates an enlarged cross-sectional structure of the peripheral gate trench portions 38AY, 38BY, the floating trench 52Y, and their surroundings in FIG. 17. FIG. 18 mainly illustrates the electric field intensity of the peripheral gate trench portions 38AY, 38BY, the floating trench 52Y, and their surroundings.

[0109] As shown in FIG. 16 , the floating trench 52Y is disposed outward from both the first outer periphery gate trench portion 38AY and the second outer periphery gate trench portion 38BY. The distance between the floating trench 52Y and the second outer periphery gate trench portion 38BY is greater than the distance between the first outer periphery gate trench portion 38AY and the second outer periphery gate trench portion 38BY. Like the semiconductor device 10X of the first comparative example, the semiconductor device 10Y includes an outer floating trench 53Y disposed between the floating trench 52Y and the protective trench 44Y. The distance between the floating trench 52Y and the outer floating trench 53Y is greater than the distance between the first outer periphery gate trench portion 38AY and the second outer periphery gate trench portion 38BY. Furthermore, the distance between the outer floating trench 53Y and the inner end protective trench 44EY is greater than the distance between the first outer periphery gate trench portion 38AY and the second outer periphery gate trench portion 38BY. Therefore, in the peripheral region 28 of the semiconductor device 10Y of the second comparative example, the region where the multiple protective trenches 44Y are formed is smaller, and therefore the number of protective trenches 44Y is smaller than the number of protective trenches 44 in the embodiment.

[0110] As shown in FIG. 18 , in the semiconductor device 10Y of the second comparative example, the floating trench 52Y is positioned outward relative to the outer periphery gate trench portions 38AY, 38BY, resulting in a lower electric field strength at the corner portions between the sidewalls and bottom walls of the second outer periphery gate trench portion 38BY. For example, the electric field strength at the corner portions 38RX of the second outer periphery gate trench portion 38BX of the semiconductor device 10X of the first comparative example is 8.57 MV / cm, while the electric field strength at the corner portions of the second outer periphery gate trench portion 38BY of the semiconductor device 10Y of the second comparative example is 4.18 MV / cm. This reduced electric field strength at the corner portions of the second outer periphery gate trench portion 38BY prevents voids from forming in the gate insulating film 64 at the corner portions of the second outer periphery gate trench portion 38BY. As a result, leakage current flowing from the drift region 68 to the gate electrode 62 can be suppressed.

[0111] 17, in the semiconductor device 10Y of the second comparative example, the floating trench 52Y is located outward from the outer gate trench portions 38AY and 38BY, and the outer floating trench 53Y is located away from the floating trench 52Y. Therefore, the depletion layer DLY does not extend further outward than the depletion layer DLX of the semiconductor device 10X of the first comparative example shown in FIG. 14. As a result, a walk-in phenomenon may occur. Here, the walk-in phenomenon is a phenomenon in which the drain-source breakdown voltage during the second measurement of the IV characteristics is lower than the drain-source breakdown voltage during the first measurement of the IV characteristics, for example.

[0112] 7, in the semiconductor device 10 of this embodiment, the inner end protective trench 44E of the multiple protective trenches 44 is disposed adjacent to the floating trench 52. In other words, the formation area of ​​the multiple protective trenches 44 is expanded to a position adjacent to the floating trench 52. Furthermore, in the semiconductor device 10 of this embodiment, similar to the semiconductor device 10Y of the second comparative example, the floating trench 52 is disposed outward from each of the outer periphery gate trench portions 38A, 38B.

[0113] The formation mode of the depletion layer DL and the electric field intensity of the semiconductor device 10 of this embodiment are shown in Figures 19 and 20. Figure 19 schematically shows the cross-sectional structure of the peripheral region 28 of the semiconductor device 10 of this embodiment. Figure 19 mainly shows the spread of the depletion layer DL in the peripheral region 28 of the semiconductor device 10. Figure 20 shows an enlarged cross-sectional structure of the peripheral gate trench portions 38A, 38B, the floating trench 52, and their surroundings in Figure 19. Figure 20 mainly shows the electric field intensity of the peripheral gate trench portions 38A, 38B, the floating trench 52, and their surroundings.

[0114] 19, in the semiconductor device 10, an inner end protective trench 44E is disposed adjacent to the floating trench 52, and then multiple protective trenches 44 are disposed. That is, the formation region of the multiple protective trenches 44 extends inward from both the multiple protective trenches 44X of the semiconductor device 10X of the first comparative example and the multiple protective trenches 44Y of the semiconductor device 10Y of the second comparative example. As a result, the depletion layer DL in the semiconductor device 10 extends to the outermost protective trench 44 of the multiple protective trenches 44. That is, the depletion layer DL in the semiconductor device 10 extends outward from the depletion layer DLY of the semiconductor device 10Y of the second comparative example. As a result, the occurrence of the walk-in phenomenon can be suppressed.

[0115] 20, in the semiconductor device 10, similar to the semiconductor device 10Y of the second comparative example, the floating trench 52 is disposed outward from each of the outer periphery gate trench portions 38A, 38B, and therefore the electric field strength is low at the corner portion 38R between the sidewall 38P and bottom wall 38Q of the second outer periphery gate trench portion 38B. In one example, the electric field strength at the corner portion of the second outer periphery gate trench portion 38B is 3.16 MV / cm.

[0116] [Effects of the embodiment] According to the semiconductor device 10 of this embodiment, the following effects can be obtained. (1) The semiconductor device 10 includes a semiconductor layer 26 having an active region 30 and a peripheral region 28 surrounding the active region 30, a gate trench 36 provided in the semiconductor layer 26, a gate insulating film 64 provided in the gate trench 36, a gate electrode 62 embedded in the gate insulating film 64 within the gate trench 36, a floating trench 52 provided in the peripheral region 28, a floating insulating film 82 provided in the floating trench 52, a floating electrode 80 embedded in the floating insulating film 82 within the floating trench 52, a plurality of protective trenches 44 provided outward from the floating trench 52, protective insulating films 78 provided in each of the plurality of protective trenches 44, and protective electrodes 76 embedded in the protective insulating films 78 within each of the plurality of protective trenches 44. The gate trench 36 includes a first perimeter gate trench portion 38A provided in the perimeter region 28 and a second perimeter gate trench portion 38B provided outward from the first perimeter gate trench portion 38A. The floating trench 52 is provided outward from both the first perimeter gate trench portion 38A and the second perimeter gate trench portion 38B. The floating trench 52, the first perimeter gate trench portion 38A, and the second perimeter gate trench portion 38B each have a width greater than that of the protection trench 44.

[0117] With this configuration, the floating trench 52 is disposed outward from each of the outer periphery gate trench portions 38A, 38B, which makes it possible to suppress the occurrence of leakage current in the second outer periphery gate trench portion 38B. In addition, each of the floating trench 52, first outer periphery gate trench portion 38A, and second outer periphery gate trench portion 38B has a width greater than that of the protection trench 44, which makes it possible to alleviate electric field concentration in the floating trench 52 and each of the outer periphery gate trench portions 38A, 38B.

[0118] (2) A first distance D1 between the floating trench 52 and an inner end protection trench 44E that is closest to the floating trench 52 among the multiple protection trenches 44 is smaller than a second distance D2 between the floating trench 52 and the second outer periphery gate trench portion 38B. A third distance D3 between two adjacent protection trenches 44 among the multiple protection trenches 44 is smaller than the second distance D2.

[0119] According to this configuration, a plurality of closely spaced protective trenches 44 are provided in the vicinity of the floating trench 52. This makes it possible to suppress the occurrence of the walk-in phenomenon, and therefore to suppress a decrease in the breakdown voltage of the semiconductor device 10.

[0120] (3) The first distance D1 is smaller than the fourth distance D4 between the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B. According to this configuration, the multiple protective trenches 44 are provided even closer to the floating trench 52. This makes it possible to suppress the occurrence of the walk-in phenomenon, and therefore to suppress a decrease in the breakdown voltage of the semiconductor device 10.

[0121] (4) The third distance D3 is smaller than the fourth distance D4. According to this configuration, the intervals between the multiple protective trenches 44 become even narrower, and therefore, multiple protective trenches 44 can be provided with narrow intervals near the floating trench 52. This makes it possible to suppress the occurrence of the walk-in phenomenon, and therefore to suppress a decrease in the breakdown voltage of the semiconductor device 10.

[0122] (5) The fourth distance D4 is greater than the fifth distance D5 between adjacent connection gate trench portions 42 among the multiple connection gate trench portions 42. According to this configuration, the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B are not disposed too close to each other, so that electric field concentration in each of the outer periphery gate trench portions 38A, 38B can be alleviated.

[0123] (6) The first distance D1 is equal to or less than the third distance D3. According to this configuration, the multiple protective trenches 44 are provided even closer to the floating trench 52. This makes it possible to suppress the occurrence of the walk-in phenomenon, and therefore to suppress a decrease in the breakdown voltage of the semiconductor device 10.

[0124] (7) The first distance D1 is equal to or less than the width W2 of the floating trench 52. According to this configuration, the multiple protective trenches 44 are provided even closer to the floating trench 52. This makes it possible to suppress the occurrence of the walk-in phenomenon, and therefore to suppress a decrease in the breakdown voltage of the semiconductor device 10.

[0125] (8) The first distance D1 is equal to or less than the width W1A of the first outer periphery gate trench portion 38A. According to this configuration, the multiple protective trenches 44 are provided even closer to the floating trench 52. This makes it possible to suppress the occurrence of the walk-in phenomenon, and therefore to suppress a decrease in the breakdown voltage of the semiconductor device 10.

[0126] (9) The third distance D3 is equal to or less than the width W2 of the floating trench 52. According to this configuration, the intervals between the multiple protective trenches 44 become even narrower, and therefore, multiple protective trenches 44 can be provided with narrow intervals near the floating trench 52. This makes it possible to suppress the occurrence of the walk-in phenomenon, and therefore to suppress a decrease in the breakdown voltage of the semiconductor device 10.

[0127] (10) The third distance D3 is equal to or less than the width W1A of the first outer periphery gate trench portion 38A. According to this configuration, the intervals between the multiple protective trenches 44 become even narrower, and therefore, multiple protective trenches 44 can be provided with narrow intervals near the floating trench 52. This makes it possible to suppress the occurrence of the walk-in phenomenon, and therefore to suppress a decrease in the breakdown voltage of the semiconductor device 10.

[0128] (11) The first distance D1 is greater than the width W3 of the protective trench 44. According to this configuration, the protective trench 44 is not too close to the floating trench 52, so that the protective trench 44 can be stably provided near the floating trench 52.

[0129] (12) The third distance D3 is greater than the width W3 of the protective trench 44. According to this configuration, the multiple protective trenches 44 are not too close to each other, so that the multiple protective trenches 44 can be provided stably.

[0130] (13) In the arrangement direction of the multiple protection trenches 44, the region RP in which the multiple protection trenches 44 are arranged is larger than the distance between the first outer periphery gate trench portion 38A and the floating trench 52 in the arrangement direction.

[0131] This configuration allows a large area to be provided for the multiple protective trenches 44. Therefore, the depletion layer DL can be extended, which can prevent the walk-in phenomenon from occurring and prevent a decrease in the breakdown voltage of the semiconductor device 10.

[0132] (14) The second distance D2 between the floating trench 52 and the second outer periphery gate trench portion 38B is greater than the fourth distance D4 between the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B.

[0133] According to this configuration, the floating trench 52 can be disposed outward, which makes it easier for the depletion layer DL to spread outward, thereby preventing a decrease in the breakdown voltage of the semiconductor device 10.

[0134] (15) The thickness of the floating insulating film 82 is greater than the thickness T4 of the protective insulating film 78. According to this configuration, the electric field concentration in the floating trench 52 can be alleviated.

[0135] (16) The thickness TA of the gate insulating film 64 in the first outer gate trench portion 38A and the second outer gate trench portion 38B is greater than the thickness T4 of the protective insulating film 78. This configuration can alleviate electric field concentration in the outer gate trench portions 38A, 38B.

[0136] <Example of change> The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment are assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0137] The arrangement of the multiple protective trenches 44 can be changed as desired. In one example, at least some of the multiple protective trenches 44 may be arranged at different pitches. Figure 21 shows an example of a modified example of the multiple protective trenches 44.

[0138] 21 , the arrangement pitch PA1 of the multiple protective trenches 44 closer to the floating trench 52 may be smaller than the arrangement pitch PA2 of the multiple protective trenches 44 further from the floating trench 52. In other words, the multiple protective trenches 44 in the region closer to the floating trench 52 are arranged densely. Compared to the densely arranged protective trenches 44, the multiple protective trenches 44 on the side farther from the floating trench 52 are arranged sparsely. In one example, although not shown, the arrangement pitch of the multiple protective trenches 44 may increase with increasing distance from the floating trench 52.

[0139] Although not shown, in an example different from that of Figure 21, the arrangement pitch PA1 of the multiple protective trenches 44 closer to the floating trench 52 may be larger than the arrangement pitch PA2 of the multiple protective trenches 44 away from the floating trench 52.

[0140] The first distance D1 between the floating trench 52 and an inner end protection trench 44E, which is the closest to the floating trench 52 among the multiple protection trenches 44, can be changed as desired. In one example, the first distance D1 may be equal to or greater than the second distance D2 between the floating trench 52 and the second outer periphery gate trench portion 38B. In one example, the first distance D1 may be equal to or greater than the fourth distance D4 between the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B. In one example, the first distance D1 may be greater than the third distance D3 between two adjacent protection trenches 44 among the multiple protection trenches 44. In one example, the first distance D1 may be greater than the width W2 of the floating trench 52. In one example, the first distance D1 may be equal to or less than the width W3 of the protection trench 44. In one example, the first distance D1 may be smaller than the width W1A of the first outer periphery gate trench portion 38A. In one example, the first distance D1 may be less than the width W1B of the second outer perimeter gate trench portion 38B.

[0141] The third distance D3 between two adjacent protection trenches 44 among the multiple protection trenches 44 can be changed arbitrarily. In one example, the third distance D3 may be equal to or greater than the second distance D2 between the floating trench 52 and the second periphery gate trench portion 38B. In one example, the third distance D3 may be equal to or greater than the fourth distance D4 between the first periphery gate trench portion 38A and the second periphery gate trench portion 38B. In one example, the third distance D3 may be greater than the width W2 of the floating trench 52. In one example, the third distance D3 may be greater than the width W1A of the first periphery gate trench portion 38A. In one example, the third distance D3 may be greater than the width W1B of the second periphery gate trench portion 38B. In one example, the third distance D3 may be equal to or less than the width W3 of the protection trench 44.

[0142] The fourth distance D4 between the first outer periphery gate trench portion 38A and the second outer periphery gate trench portion 38B can be changed as desired. For example, the fourth distance D4 may be equal to or less than the fifth distance D5 between adjacent connection gate trench portions 42 among the multiple connection gate trench portions 42.

[0143] The second distance D2 between the floating trench 52 and the second periphery gate trench portion 38B can be changed as desired. In one example, the second distance D2 may be equal to or less than the fourth distance D4 between the first periphery gate trench portion 38A and the second periphery gate trench portion 38B.

[0144] In the arrangement direction of the multiple protection trenches 44, the region RP in which the multiple protection trenches 44 are arranged may be equal to or smaller than the distance D6 between the first outer periphery gate trench portion 38A and the floating trench 52 in the arrangement direction.

[0145] The thickness TA of the gate insulating film 64 in the first outer periphery gate trench portion 38A may be equal to or less than the thickness T4 of the protective insulating film 78 in the protective trench 44. In one example, the thickness T1 of the first insulating film 64A in the gate insulating film 64 may be equal to or less than the thickness T4 of the protective insulating film 78. In one example, the thickness T2 of the second insulating film 64B in the gate insulating film 64 may be equal to or less than the thickness T4 of the protective insulating film 78. In one example, the thickness T3 of the third insulating film 64C in the gate insulating film 64 may be equal to or less than the thickness T4 of the protective insulating film 78. Note that the thickness TA of the gate insulating film 64 in the second outer periphery gate trench portion 38B may also be equal to or less than the thickness T4 of the protective insulating film 78.

[0146] The thickness T1 of the first insulating film 64A of the gate insulating film 64 in the first outer gate trench portion 38A may be constant toward the bottom wall 38Q of the first outer gate trench portion 38A. Note that the thickness T1 of the first insulating film 64A of the gate insulating film 64 in the second outer gate trench portion 38B can also be changed in a similar manner.

[0147] The thickness T2 of the second insulating film 64B of the gate insulating film 64 in the first outer peripheral gate trench portion 38A may be equal to or greater than the thickness T1 of the first insulating film 64A. Note that the thickness of the second insulating film 64B of the gate insulating film 64 in the second outer peripheral gate trench portion 38B can be changed in the same way.

[0148] The thickness T3 of the third insulating film 64C of the gate insulating film 64 in the first outer peripheral gate trench portion 38A may be greater than the thickness T2 of the second insulating film 64B. Note that the thickness of the third insulating film 64C of the gate insulating film 64 in the second outer peripheral gate trench portion 38B can be changed in the same way.

[0149] The thickness T3 of the third insulating film 64C of the gate insulating film 64 in the first outer peripheral gate trench portion 38A may be equal to or greater than the thickness T1 of the first insulating film 64A. Note that the thickness of the third insulating film 64C of the gate insulating film 64 in the second outer peripheral gate trench portion 38B can be changed in the same way.

[0150] The thickness of the floating insulating film 82 in the floating trench 52 may be equal to or smaller than the thickness T4 of the protective insulating film 78 in the protective trench 44. The guarding electrode 76 is not limited to being electrically floating. In one example, the guarding electrode 76 may be configured to have a source potential applied thereto.

[0151] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the phrase "a first element is mounted on a second element" means that in some embodiments, the first element may be placed directly on the second element in contact with the second element, while in other embodiments, the first element may be placed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0152] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z-axis direction described in this specification being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0153] <Additional Notes> The technical ideas that can be understood from the above-described embodiment and each modified example are described below. Note that the reference numerals of the components of the embodiment corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0154] [Appendix 1] a semiconductor layer (26) provided with an active region (30) and a peripheral region (28) surrounding the active region (30); a gate trench (36) provided in the semiconductor layer (26); a gate insulating film (64) provided in the gate trench (36); a gate electrode (62) embedded in the gate insulating film (64) within the gate trench (36); a floating trench (52) provided in the outer peripheral region (28); a floating insulating film (82) provided in the floating trench (52); a floating electrode (80) embedded in the floating insulating film (82) within the floating trench (52); a plurality of protective trenches (44) provided outward from the floating trench (52); a protective insulating film (78) provided in each of the plurality of protective trenches (44); protective electrodes (76) embedded in the protective insulating film (78) in the plurality of protective trenches (44); Equipped with The gate trench (36) a first outer periphery gate trench portion (38A) provided in the outer periphery region (28); a second outer periphery gate trench portion (38B) provided outward from the first outer periphery gate trench portion (38A); Including, the floating trench (52) is provided outward from both the first outer periphery gate trench portion (38A) and the second outer periphery gate trench portion (38B); The floating trench (52), the first perimeter gate trench portion (38A), and the second perimeter gate trench portion (38B) each have a width greater than that of the protection trench (44). A semiconductor device (10).

[0155] [Appendix 2] a first distance (D1) between the floating trench (52) and an inner end protection trench (44E) of the plurality of protection trenches (44) that is closest to the floating trench (52) is smaller than a second distance (D2) between the floating trench (52) and the second outer periphery gate trench portion (38B); A third distance (D3) between two adjacent protection trenches (44) among the plurality of protection trenches (44) is smaller than the second distance (D2). 2. The semiconductor device according to claim 1.

[0156] [Appendix 3] The first distance (D1) is smaller than a fourth distance (D4) between the first outer gate trench portion (38A) and the second outer gate trench portion (38B). 3. The semiconductor device according to claim 2.

[0157] [Appendix 4] The third distance (D3) is smaller than the fourth distance (D4). 4. The semiconductor device according to claim 3.

[0158] [Appendix 5] The first distance (D1) is equal to or less than the third distance (D3). 5. The semiconductor device according to any one of claims 2 to 4.

[0159] [Appendix 6] The first distance (D1) is equal to or less than the width (W2) of the floating trench (52). 6. The semiconductor device according to any one of appendices 2 to 5.

[0160] [Appendix 7] The first distance (D1) is equal to or less than the width (W1A) of the first outer gate trench portion (38A). 7. The semiconductor device according to any one of claims 2 to 6.

[0161] [Appendix 8] The third distance (D3) is equal to or less than the width (W2) of the floating trench (52). 8. The semiconductor device according to any one of appendices 2 to 7.

[0162] [Appendix 9] The third distance (D3) is equal to or less than the width (W1A) of the first outer gate trench portion (38A). 9. The semiconductor device according to any one of appendices 2 to 8.

[0163] [Appendix 10] The first distance (D1) is greater than the width (W3) of the protective trench (44). 10. The semiconductor device according to any one of appendices 2 to 9.

[0164] [Appendix 11] The third distance (D3) is greater than the width (W3) of the protective trench (44). 11. The semiconductor device according to any one of claims 2 to 10.

[0165] [Appendix 12] In the arrangement direction of the protection trenches (44), a region (RP) in which the protection trenches (44) are arranged is larger than a distance (D6) between the first outer periphery gate trench portion (38A) and the floating trench (52) in the arrangement direction. 12. The semiconductor device according to any one of claims 1 to 11.

[0166] [Appendix 13] The plurality of protective trenches (44) are arranged at equal pitches. 13. The semiconductor device according to any one of claims 1 to 12.

[0167] [Appendix 14] The arrangement pitch (PA1) of the plurality of protection trenches (44) closer to the floating trench (52) is smaller than the arrangement pitch (PA2) of the plurality of protection trenches (44) farther from the floating trench (52). 13. The semiconductor device according to any one of claims 1 to 12.

[0168] [Appendix 15] The protective electrode (44) is in an electrically floating state. 15. The semiconductor device according to any one of claims 1 to 14.

[0169] [Appendix 16] A second distance (D2) between the floating trench (52) and the second outer periphery gate trench portion (38B) is greater than a fourth distance (D4) between the first outer periphery gate trench portion (38A) and the second outer periphery gate trench portion (38B). 16. The semiconductor device according to any one of claims 1 to 15.

[0170] [Appendix 17] The thickness of the floating insulating film (82) is greater than the thickness (T4) of the protective insulating film (78). 17. The semiconductor device according to any one of claims 1 to 16.

[0171] [Appendix 18] The thickness (TA) of the gate insulating film (64) in the first outer periphery gate trench portion (38A) and the second outer periphery gate trench portion (38B) is greater than the thickness (T4) of the protective insulating film (78). 18. The semiconductor device according to any one of claims 1 to 17.

[0172] [Appendix 19] The gate trench (36) a plurality of inner gate trench portions (40) provided in the active region (30); a plurality of connecting gate trench portions (42) connecting the plurality of inner gate trench portions (40) and the first outer periphery gate trench portion (38A); Contains 19. The semiconductor device according to any one of appendices 1 to 18.

[0173] [Appendix 20] A fourth distance (D4) between the first outer periphery gate trench portion (38A) and the second outer periphery gate trench portion (38B) is greater than a fifth distance (D5) between adjacent connection gate trench portions (42) among the plurality of connection gate trench portions (42). 20. The semiconductor device according to claim 19.

[0174] [Appendix 21] each of the first outer periphery gate trench portion (38A) and the second outer periphery gate trench portion (38B) includes a side wall (38P), a bottom wall (38Q), and a corner portion (38R) provided between the side wall (38P) and the bottom wall (38Q); The gate insulating film (64) in the first outer periphery gate trench portion (38A) and the second outer periphery gate trench portion (38B) a first insulating film (64A) provided on the side wall (38P); a second insulating film (64B) provided on the bottom wall (38Q); a third insulating film (64C) provided in the corner portion (38R); Including, The thickness (T3) of the third insulating film (64C) is thinner than the thickness (T1) of the first insulating film (64A). 21. The semiconductor device according to any one of appendices 1 to 20.

[0175] [Appendix 22] The thickness (T3) of the third insulating film (64C) is equal to or less than the thickness (T2) of the second insulating film (64B). 22. The semiconductor device according to claim 21.

[0176] [Appendix 23] The thickness (T1) of the first insulating film (64A) becomes thinner toward the bottom wall (38Q). 23. The semiconductor device according to claim 21 or 22.

[0177] [Appendix 24] The thickness (T1) of the first insulating film (64A) is greater than the thickness (T4) of the protective insulating film (78). 24. The semiconductor device according to any one of claims 21 to 23.

[0178] [Appendix 25] The thickness (T2) of the second insulating film (64B) is greater than the thickness (T4) of the protective insulating film (78). 25. The semiconductor device according to any one of claims 21 to 24.

[0179] [Appendix 26] The thickness (T3) of the third insulating film (64C) is greater than the thickness (T4) of the protective insulating film (78). 26. The semiconductor device according to any one of claims 21 to 25.

[0180] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0181] 10...Semiconductor device 12...passivation layer 14,16...Pad opening 18...Metal layer 19A...First conductive layer 19B...Second conductive layer 20...Source wiring 20A...recess 22...Gate wiring 24...Outer electrode 26...Semiconductor layer 26X1, 26X2, 26Y1, 26Y2...sides 26A…Side 1 26B…Second side 28…Outer area 30…Active area 32...Gate finger part 34...Gate pad section 36...Gate trench 38...Outer gate trench section 38A: First outer gate trench 38B: Second outer gate trench 38AA,38BA…1st straight section 38AB,38BB…2nd straight section 38AC, 38BC...Corner part 38P…Side wall 38Q…Bottom wall 38R...Corner 40...Inner gate trench 40A...Side wall 40B…Bottom wall 42...Connection gate trench section 44...Protective trench 44E…Inner end protection trench 46...Source contact part 48...Gate contact part 50...Outer contact area 52...Floating trench 52P…Side wall 52Q…Bottom wall 52R...Corner 54...Semiconductor substrate 56...Epitaxial layer 58...Drain electrode 60...insulating layer 62...Gate electrode 62A…Side wall 62B…Bottom wall 62C...Corner part 64...Gate insulating film 64A...First insulating film 64B...Second insulating film 64C...Third insulating film 66...Interlayer insulating film 68...Drift area 70...Body area 71...Side 72...Source region 73...Transistor cell 74...Contact area 76...Protective electrode 78...Protective insulating film 80...Floating electrode 82...Floating insulating film RP: Area where multiple protective trenches are provided DL…depletion layer GX…Gap R…curvature radius D1: First distance D2…Second distance D3: Third distance D4: Fourth distance D5…5th distance D6: Distance between the first outer gate trench and the floating trench W1A: Width of the first outer gate trench W1B: Width of second outer gate trench W2: Floating trench width W3: Width of protective trench P1: Arrangement pitch of inner gate trench PA1, PA2...Pitch of multiple protective trenches TA: Gate insulating film thickness T1: Thickness of the first insulating film T2: Thickness of the second insulating film T3: Thickness of the third insulating film T4: Thickness of protective insulating film

Claims

1. a semiconductor layer provided with an active region and a peripheral region surrounding the active region; a gate trench provided in the semiconductor layer; a gate insulating film provided in the gate trench; a gate electrode embedded in the gate insulating film within the gate trench; a floating trench provided in the outer periphery region; a floating insulating film provided in the floating trench; a floating electrode embedded in the floating insulating film within the floating trench; a plurality of protection trenches provided outward from the floating trench; a protective insulating film provided in each of the plurality of protective trenches; protection electrodes embedded in the protection insulating film in each of the plurality of protection trenches; Equipped with The gate trench is a first outer periphery gate trench portion provided in the outer periphery region; a second outer periphery gate trench portion provided outward from the first outer periphery gate trench portion; Including, the floating trench is provided outward from both the first outer periphery gate trench portion and the second outer periphery gate trench portion, The floating trench, the first perimeter gate trench portion, and the second perimeter gate trench portion each have a width greater than that of the protection trench. Semiconductor device.

2. a first distance between the floating trench and an inner end protection trench among the plurality of protection trenches that is closest to the floating trench is smaller than a second distance between the floating trench and the second outer periphery gate trench portion; A third distance between two adjacent protection trenches among the plurality of protection trenches is smaller than the second distance. The semiconductor device according to claim 1 .

3. The first distance is smaller than a fourth distance between the first outer gate trench portion and the second outer gate trench portion. The semiconductor device according to claim 2 .

4. The third distance is smaller than the fourth distance. The semiconductor device according to claim 3 .

5. The first distance is equal to or less than the third distance. The semiconductor device according to claim 2 .

6. The first distance is equal to or less than the width of the floating trench. The semiconductor device according to claim 2 .

7. The first distance is equal to or less than the width of the first outer gate trench portion. The semiconductor device according to claim 2 .

8. The third distance is equal to or less than the width of the floating trench. The semiconductor device according to claim 2 .

9. The third distance is equal to or less than the width of the first outer periphery gate trench portion. The semiconductor device according to claim 2 .

10. The first distance is greater than the width of the protection trench. The semiconductor device according to claim 2 .

11. The third distance is greater than the width of the protection trench. The semiconductor device according to claim 2 .

12. In the arrangement direction of the protection trenches, an area in which the protection trenches are arranged is larger than a distance in the arrangement direction between the first outer periphery gate trench portion and the floating trench. The semiconductor device according to claim 1 .

13. The plurality of protective trenches are arranged at equal pitches. The semiconductor device according to claim 1 .

14. The arrangement pitch of the protection trenches closer to the floating trench among the plurality of protection trenches is smaller than the arrangement pitch of the protection trenches farther from the floating trench. The semiconductor device according to claim 1 .

15. The protective electrode is in an electrically floating state. The semiconductor device according to claim 1 .

16. A second distance between the floating trench and the second outer periphery gate trench portion is greater than a fourth distance between the first outer periphery gate trench portion and the second outer periphery gate trench portion. The semiconductor device according to claim 1 .

17. The thickness of the floating insulating film is greater than the thickness of the protective insulating film. The semiconductor device according to claim 1 .

18. The thickness of the gate insulating film in the first outer gate trench portion and the second outer gate trench portion is greater than the thickness of the protective insulating film. The semiconductor device according to claim 1 .

19. The gate trench is a plurality of inner gate trench portions provided in the active region; a plurality of connection gate trench portions connecting the plurality of inner gate trench portions and the first outer periphery gate trench portion; Contains The semiconductor device according to any one of claims 1 to 18.

20. A fourth distance between the first outer periphery gate trench portion and the second outer periphery gate trench portion is greater than a fifth distance between adjacent connection gate trench portions among the plurality of connection gate trench portions.

20. The semiconductor device according to claim 19.

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