Acoustic wave device and method of manufacturing the same
The acoustic wave device design addresses the challenge of forming larger bumps on a reduced pad area by using an insulating intermediate layer, enabling efficient pattern expansion and preventing short-circuits, suitable for both CSP and WLP structures.
Patent Information
- Application Number
- JP2024102407
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-06-25
- Publication Date
- 2026-01-14
AI Technical Summary
In acoustic wave devices with a CSP structure, reducing the area of the pad formation region is challenging due to the necessity of bumps, limiting the area for other patterns and complicating the miniaturization of the device chip.
The acoustic wave device design includes a bump receiving portion with a lower layer covered by an insulating intermediate portion, allowing an upper layer to be larger than the lower layer, enabling bumps of a certain size to be formed even with a reduced pad area, and preventing short-circuiting with inter-resonator wiring.
This design allows for the formation of larger bumps without issues, increasing the area for other patterns and preventing short-circuits, facilitating both CSP and WLP structure devices with consistent pattern formation.
Smart Images
Figure 2026004153000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to an improvement in an acoustic wave device suitable for use as a frequency filter in a mobile communication device or the like. [Background technology]
[0002] Acoustic wave devices are classified into those with a CSP (Chip Size Package) structure and those with a WLP (Wafer Level Package) structure.
[0003] An outline of the configuration of an acoustic wave device with a CSP structure is shown in Fig. 25. In Fig. 25, reference numeral 100 denotes a device chip, reference numeral 101 denotes a package substrate, reference numeral 102 denotes a sealing resin, reference numeral 103 denotes a bump, reference numeral 104 denotes a pad on the device chip 100 side, reference numeral 105 denotes a pad on the package substrate 101 side, reference numeral 106 denotes an internal space, and reference numeral 107 denotes a resonator.
[0004] An outline of the configuration of an acoustic wave device with a WLP structure is shown in Fig. 26. In Fig. 26, reference numeral 100 denotes a device chip, reference numeral 104 denotes a pad, reference numeral 106 denotes an internal space, reference numeral 107 denotes a resonator, reference numeral 109 denotes a support layer, reference numeral 110 denotes a cover layer, reference numeral 111 denotes a via, reference numeral 112 denotes wiring within the via, and reference numeral 113 denotes a bump.
[0005] In either structure of the acoustic wave device, it is preferable to make the area of the region where the pad 104 is formed as small as possible, because this contributes to increasing the area of the region where patterns other than the pad 104 are formed, improving the degree of freedom in pattern design, and miniaturizing the device chip.
[0006] The area of the region where the pad 104 is formed is easy to reduce in an acoustic wave device with a WLP structure due to its structure. In contrast, the area of the region where the pad 104 is formed is difficult to reduce in an acoustic wave device with a CSP structure due to its structure. In an acoustic wave device with a CSP structure, a device chip 100 having bumps 103 formed on a package substrate 101 is mounted, and these bumps 103 form gaps that become the internal space 106. Therefore, the bumps 103 must have a certain size, and therefore the pads 104 that receive the bumps 103 must also have a certain area or more. Summary of the Invention [Problem to be solved by the invention]
[0007] If bumps 103 of a certain size can be formed on the device chip 100 without any problems even if the area of the area where the pads 104 are formed is reduced, it is possible to increase the area of the area where patterns other than the pads 104 are formed as much as possible in an acoustic wave device with a CSP structure. Moreover, it becomes possible to manufacture both an acoustic wave device with a WLP structure and an acoustic wave device with a CSP structure based on a device chip on which the same patterns are formed.
[0008] The main problem that this invention aims to solve is to make it possible to form a bump of a certain size on a device chip without any problems, even if the area of the formation region of the part of the pattern of the device chip corresponding to the pad 104 (the lower layer part that forms part of the external connection wiring described below) is made as small as possible. [Means for solving the problem]
[0009] In order to achieve the above object, from a first viewpoint, the present invention provides an acoustic wave device comprising a plurality of resonators, a plurality of bump receiving portions, inter-resonator wiring connecting the resonators to each other, and external connection wiring connecting the resonators to the bump receiving portions, formed on a functional surface of a device chip that is made of a piezoelectric material, At least one of the bump receiving portions has a lower layer portion connected to the external connection wiring, an insulating intermediate portion, and a conductive upper layer portion, The lower layer portion is formed such that a part of the formation area of the lower layer portion is an uncovered area, and the formation area of the lower layer portion other than the uncovered area is covered by the insulating intermediate portion; the upper layer portion is formed on the insulating intermediate portion so as to be electrically connected to the lower layer portion through the uncovered region, Moreover, the upper layer portion is formed so as to have a larger area than the lower layer portion when viewed in a direction perpendicular to the functional surface.
[0010] One aspect of the present invention is that, at the location where the bump receiving portion is formed, the insulating intermediate portion is formed so as to cover the lower layer portion and a predetermined area on the functional surface near the lower layer portion that surrounds the lower layer portion. In this case, it is another aspect of the present invention that at least a part of the inter-resonator wiring is positioned to the side of the lower layer and below the upper layer with the insulating intermediate portion interposed therebetween.
[0011] In order to achieve the above object, from a second viewpoint, the present invention provides a method for manufacturing the acoustic wave device, comprising the steps of: forming, on the functional surface of the device chip, the resonators, the lower layer portion, inter-resonator wiring connecting the resonators to each other, and external connection wiring connecting the resonators to the lower layer portion, all from a conductive metal; a step of covering the lower layer portion in a region that will become the bump receiving portion with the insulating intermediate portion so that a part of the formation region of the lower layer portion is left as a non-covered region and the formation region other than the non-covered region is covered with the insulating intermediate portion; forming the upper layer portion of the insulating intermediate portion in the region that will become the bump receiving portion, by using a conductive metal, so as to be electrically connected to the lower layer portion through the non-covered region; In the step of forming the upper layer portion, the upper layer portion is formed so as to have a larger area than the lower layer portion when viewed in a direction perpendicular to the functional surface. [Effects of the Invention]
[0012] According to this invention, even if the area of the formation region of the lower layer that forms part of the external connection wiring in the device chip is made as small as possible, bumps of a certain size can be formed on the device chip without any problems. [Brief explanation of the drawings]
[0013] [Figure 1] FIG. 1 is a functional configuration diagram of a device chip of an acoustic wave device (first example) according to one embodiment of the present invention, and an insulating intermediate layer is not shown. [Figure 2] FIG. 2 is a cross-sectional view of the first example taken along line AA in FIG. [Figure 3] FIG. 3 is a cross-sectional view of a main part showing one step in the manufacturing process of the first example. [Figure 4] FIG. 4 is a cross-sectional view of the essential part showing a step performed after the step shown in FIG. 3 in the manufacturing process of the first example. [Figure 5] FIG. 5 is a cross-sectional view of the essential part showing a step performed after the step shown in FIG. 4 in the manufacturing process of the first example. [Figure 6] FIG. 6 is a cross-sectional view showing a main part of another variation of the step performed after the step shown in FIG. 4 in the manufacturing process of the first example. [Figure 7] FIG. 7 is a functional configuration diagram of a device chip of an acoustic wave device (second example) according to one embodiment of the present invention, and an insulating intermediate layer is not shown. [Figure 8] FIG. 8 is a cross-sectional view of the second example taken along line BB in FIG. [Figure 9] FIG. 9 is a cross-sectional view of the essential part showing one step in the manufacturing process of the second example. [Figure 10] FIG. 10 is a cross-sectional view of the essential part showing a step performed after the step shown in FIG. 9 in the manufacturing process of the second example. [Figure 11] FIG. 11 is a cross-sectional view of the essential part showing a step performed after the step shown in FIG. 10 in the manufacturing process of the second example. [Figure 12] FIG. 12 is a cross-sectional view of the essential part showing a step performed after the step shown in FIG. 11 in the manufacturing process of the second example. [Figure 13] FIG. 13 is a cross-sectional view showing a main part of another variation of the step performed after the step shown in FIG. 11 in the manufacturing process of the second example. [Figure 14] FIG. 14 is a functional configuration diagram of a device chip of an acoustic wave device (third example) according to one embodiment of the present invention, and an insulating intermediate layer is omitted. [Figure 15] FIG. 15 is a cross-sectional view of the third example taken along line CC in FIG. [Figure 16] FIG. 16 is a cross-sectional view of the essential part showing one step in the manufacturing process of the third example. [Figure 17] FIG. 17 is a cross-sectional view of the essential part showing a step performed after the step shown in FIG. 16 in the manufacturing process of the third example. [Figure 18] FIG. 18 is a cross-sectional view of the essential part showing a step performed after the step shown in FIG. 17 in the manufacturing process of the third example. [Figure 19] FIG. 19 is a cross-sectional view of the essential part showing a step performed after the step shown in FIG. 18 in the manufacturing process of the third example. [Figure 20] FIG. 20 is a cross-sectional view of a main part showing another variation of the step performed after the step shown in FIG. 18 in the manufacturing process of the third example. [Figure 21] FIG. 21 is an enlarged view of the part surrounded by the dashed line in FIG. [Figure 22]FIG. 22 is a plan view showing a modified example of the configuration of the upper layer portion that constitutes the bump receiving portion. [Figure 23] FIG. 23 is a plan view showing a modified example of the configuration of the upper layer portion that constitutes the bump receiving portion. [Figure 24] FIG. 24 is a configuration diagram showing an example of a resonator. [Figure 25] FIG. 25 is a cross-sectional view of an acoustic wave device having a CSP structure. [Figure 26] FIG. 26 is a cross-sectional view of an acoustic wave device having a WLP structure. DETAILED DESCRIPTION OF THE INVENTION
[0014] Exemplary embodiments of the present invention will now be described with reference to Figures 1 to 24. An acoustic wave device 1 according to this embodiment is suitable for use as a frequency filter in mobile communication devices and the like.
[0015] The acoustic wave device 1 is configured by forming, on a functional surface 2a of a device chip 2 made of a piezoelectric material, a plurality of resonators 3, a plurality of bump receiving portions 4, inter-resonator wiring 5 connecting the resonators 3 to each other, and external connection wiring 6 connecting the resonators 3 to the bump receiving portions 4. As a result, a desired electronic circuit such as a frequency filter is formed on the functional surface 2a of the device chip 2.
[0016] The device chip 2 has the function of propagating elastic waves. The surface of the device chip 2 that has the function of propagating elastic waves is the functional surface 2a. The device chip 2 typically uses lithium tantalate or lithium niobate as a piezoelectric material, and the device chip 2 may also be configured by laminating sapphire, silicon, alumina, spinel, quartz, glass, or the like on top of these. Typically, the device chip 2 is configured as a rectangular plate with a side length of 0.5 to 1 mm and a thickness of 0.15 to 0.2 mm, and when viewed from a direction perpendicular to the functional surface 2a, the outline of the functional surface 2a is rectangular.
[0017] The M1 layer 7 formed on the device chip 2, which will be described later, typically has a thickness of 0.15 to 0.4 μm. Furthermore, the M2 layer 8, which will be described later, typically has a thickness of 2 to 4 μm. Furthermore, the M3 layer 9 described below typically has a thickness of 2 to 4 μm. Furthermore, the inorganic insulating layer 10 described below typically has a thickness of 10 to 20 nm. Furthermore, the organic insulating layer 11, which will be described later, typically has a thickness of 0.3 to 3 μm.
[0018] In each drawing, the thickness of the components of the acoustic wave device 1 is exaggerated to make it easier to understand the configuration of the device.
[0019] The resonators 3 are configured by a conductive metal layer formed on the functional surface 2a. In the illustrated example, a plurality of resonators 3 are formed on the functional surface 2a.
[0020] Figure 24 shows an example of the configuration of one resonator 3. The resonator 3 has an IDT electrode 3a and a reflector 3b formed so as to sandwich the IDT electrode 3a. The IDT electrode 3a consists of an electrode pair, and each electrode pair has multiple electrode fingers 3c arranged in parallel so that their length direction intersects the propagation direction x of the acoustic wave, and each electrode pair has one end connected to each other by a busbar 3d. The reflector 3b has multiple electrode fingers 3e arranged in parallel so that their length direction intersects the propagation direction y of the acoustic wave, and each electrode finger 3e has its end connected by a busbar 3f.
[0021] The inter-resonator wires 5 are formed of a conductive metal layer formed on the functional surface 2a. In the examples shown in Figures 1, 7 and 14, a plurality of inter-resonator wires 5 are formed on the functional surface 2a. The inter-resonator wiring 5 includes a single-layer portion formed solely of a first metal layer (hereinafter referred to as the M1 layer 7) formed simultaneously with the resonators 3, a laminated portion formed solely of the M1 layer 7 and a second metal layer (hereinafter referred to as the M2 layer 8) formed in a process subsequent to the formation of the M1 layer 7, and a single-layer portion formed solely of the M2 layer 8. The laminated portion also includes a three-dimensional wiring structure portion indicated by reference numeral 12 in FIGS. 1, 7, and 14. In the three-dimensional wiring structure portion 12, an insulating layer formed after the formation of the M1 layer 7 and before the formation of the M2 layer 8 is interposed between the M1 layer 7 and the M2 layer 8, thereby preventing a short circuit between the M1 layer 7 and the M2 layer 8. In this embodiment, the insulating layer and the insulating intermediate portion 4b (described later) can be formed of an inorganic insulating layer 10 such as silicon dioxide (SiO2), an organic insulating layer 11 such as polyimide, or both.
[0022] The external connection wiring 6 is made of a conductive metal layer formed on the functional surface 2a. In the illustrated example, a plurality of external connection wirings 6 are formed on the functional surface 2a. The external connection wiring 6 also includes a single layer portion formed only by the M1 layer 7, a laminated portion formed by the M1 layer 7 and the M2 layer 8, and a single layer portion formed only by the M2 layer 8. The terminal of the external connection wiring 6 is the lower layer 4a of the bump receiving portion 4, which will be described later. Even if the area of the formation region of this lower layer 4a is made as small as possible and part of the inter-resonator wiring 5 is positioned near this lower layer 4a, the structure of the bump receiving portion 4, which will be described later, prevents short-circuiting between the inter-resonator wiring 5 and the upper layer 4c, which will be described later.
[0023] The bump receiving portions 4 serve as seats for forming bumps 13 on the device chip 2, which are used to connect the circuitry on the device chip 2 to the outside. That is, the regions directly below the bumps 13 formed as described below on the functional surface 2a of the device chip 2 are considered to be the formation locations of the bump receiving portions 4. A plurality of bump receiving portions 4 are formed on the functional surface 2a of the device chip 2. In the illustrated example, when the device chip 2 is viewed in a direction perpendicular to the functional surface 2a, the bump receiving portions 4 are formed at the four corners of the rectangular functional surface 2a and near two long sides of the functional surface 2a at a position midway along its length. At least one of the bump receiving portions 4 is composed of a lower layer portion 4a forming a part of the external connection wiring 6, an insulating intermediate portion 4b, and an upper layer portion 4c.
[0024] In the illustrated example, all six bump receiving portions 4 are composed of a lower layer portion 4a, an insulating intermediate portion 4b, and an upper layer portion 4c. Although not shown, some of the bump receiving portions 4 may be configured without the insulating intermediate portion 4b, as long as bumps 13 of a certain size can be formed thereon without any problems.
[0025] The lower layer portion 4a is covered with the insulating intermediate portion 4b such that a part of the formation area of the lower layer portion 4a is left as a non-covered area 4d. At the same time, the upper layer 4c is formed on the lower layer 4a, with the insulating intermediate portion 4b positioned between the upper layer 4c and the lower layer 4a, and electrically connected to the lower layer 4a through the non-coated region 4d. In each bump receiving portion 4, which has an insulating intermediate portion 4b between a lower layer portion 4a and an upper layer portion 4c, the area of the upper layer portion 4c is larger (wider) than the area of the lower layer portion 4a. Typically, the area of the lower layer 4a is 900 to 6400 μm 2 The area of the upper layer 4c is set to a range of 8100 to 14400 μm 2 is set to the range.
[0026] This makes it possible to make the area of the formation region of the lower layer 4a, which forms part of the external connection wiring 6, as small (narrow) as possible to increase the area on the functional surface 2a where the resonators 3 and the inter-resonator wiring 5 can be formed, while making the area of the upper layer 4c large (wide) so that a bump 13 of a certain size can be formed thereon, and also makes it possible to prevent the upper layer 4c thus configured by the insulating intermediate portion 4b from shorting out to the inter-resonator wiring 5 in the vicinity of the bump receiving portion 4.
[0027] In the illustrated example, in the bump receiving portion 4 near which the inter-resonator wiring 5 is located, a portion of the inter-resonator wiring 5 is located to the side of the lower layer portion 4a and below the upper layer portion 4c via the insulating intermediate portion 4b.
[0028] When the device chip 2 is viewed in a direction perpendicular to the functional surface 2a, the upper layer 4c may be configured to have a rectangular outline in the formation area of the bump receiving portion 4 as shown in Figure 21, an elliptical outline as shown in Figure 22, or a circular outline as shown in Figure 23, and the outline shape may be set as needed.
[0029] When the device chip 2 is viewed in a direction perpendicular to the functional surface 2a, the upper layer 4c is formed so that the lower layer 4a is positioned inside its outer periphery 4e (see Figures 21 to 23) at any position around its center. In the illustrated example, the uncoated region 4d is a region within a hole formed in the insulating intermediate portion 4b at a location on the upper surface of the lower layer portion 4a, allowing communication between the upper surface of the lower layer portion 4a and the upper layer portion 4c. The surface of the lower layer portion 4a other than the uncoated region 4d is covered by the insulating intermediate portion 4b. The upper layer portion 4c is formed in a process after the formation of the lower layer portion 4a, and a portion of it extends into the uncoated region 4d and is fixed to the upper surface of the lower layer portion 4a within the uncoated region 4d. The insulating intermediate portion 4b is formed so as to insulate the lower layer portion 4a from the upper layer portion 4c except for the uncovered region 4d. At the location where the bump receiving portion 4 is formed, the insulating intermediate portion 4b is formed so as to cover the lower layer portion 4a and a predetermined region on the functional surface 2a near the lower layer portion 4a that surrounds the lower layer portion 4a, and the insulating intermediate portion 4b formed in this manner makes it possible to form the upper layer portion 4c that has a larger area than the lower layer portion 4a.
[0030] (Example 1) In the first example shown in Figures 1 and 2, the resonator 3 is composed of an M1 layer 7, and the inter-resonator wiring 5, the external connection wiring 6, and the lower layer 4a of the bump receiving portion 4 are composed of the M1 layer 7 and the M2 layer 8. The insulating intermediate portion 4b is formed by a part of the inorganic insulating layer . The insulating intermediate portion 4b is provided in the bump receiving portion 4 so that an uncovered region 4d is formed on the M2 layer 8 of the lower layer portion 4a. In this uncovered region 4d, a part of the upper surface of the M2 layer 8 is exposed. In addition, in the three-dimensional wiring structure portion 12, the inorganic insulating layer 10 is located between the M1 layer 7 and the M2 layer 8 to insulate them from each other. The upper layer 4c is formed of a third metal layer (hereinafter referred to as M3 layer 9) formed in a step after the insulating intermediate portion 4b is formed. The lower surface of the upper layer 4c is in close contact with the upper surface of the M2 layer 8 in the non-covered region 4d. The bumps 13 are formed on the upper layer 4c of the bump receiving portion 4 configured in this manner.
[0031] The device chip 2 is fixed to pads 14a on the package substrate 14 via bumps 13. A gap is formed between the device chip 2 and the package substrate 14 by the bumps 13, and an internal space 16 in which the resonator 3 faces is formed in the acoustic wave device 1 by the sealing resin 15.
[0032] 3 to 6 show the main parts of the manufacturing process of the first example. First, the resonators 3, the lower layer 4a, inter-resonator wiring 5 connecting the resonators 3 to each other, and external connection wiring 6 connecting the resonators 3 to the lower layer 4a are formed on the functional surface 2a of the device chip 2 using a conductive metal (Figure 3).
[0033] Specifically, (1) an M1 layer 7 is formed, (2) an inorganic insulating layer 10 is then formed in the three-dimensional wiring structure portion 12 so that the inorganic insulating layer 10 covers the M1 layer 7, (3) an M2 layer 8 is then formed on the M1 layer 7, and (4) an inorganic insulating layer 10 is then formed on the M2 layer 8.
[0034] In the region that will become the bump receiving portion, the lower layer 4a consisting of the M1 layer 7 and the M2 layer 8 is formed so that a portion of the formation region is left as a non-covered region 4d, and the formation region other than this non-covered region 4d is covered with an insulating intermediate portion 4b consisting of a portion of the inorganic insulating layer 10 (Figure 3).
[0035] The M1 layer 7 and the M2 layer 8 are typically formed by photolithography and etching for each region constituting one device chip 2 on the wafer 17 that will become the device chip 2. Furthermore, the inorganic insulating layer 10 is typically formed by a CVD method, a sputtering method or the like for each region constituting one device chip 2 on the wafer 17 that will become the device chip 2.
[0036] The wafer 17 configured in this manner can also be used as the wafer 17 for producing the acoustic wave device 1 having a WLP structure.
[0037] Next, the upper layer 4c is formed on the insulating intermediate portion 4b using a conductive metal so as to be electrically connected to the lower layer 4a through the uncovered region 4d, and the area of the upper layer 4c is formed to be larger than that of the lower layer 4a (FIG. 4). More specifically, for each region constituting one device chip 2 on the wafer 17 that will become the device chip 2, the M3 layer 9 that will become the upper layer 4c is formed, typically by photolithography and etching.
[0038] Next, as shown in FIG. 5, solder bumps 13 are formed on the bump receiving portions 4, typically by solder printing and reflow processing. Alternatively, as another variation, as shown in FIG. 6, the bumps 13 are formed on the bump receiving portions 4 by melting conductive metal wires.
[0039] Thereafter, the device chips 2 generated from the wafer 17 by dicing are mounted on an aggregate substrate that will become the package substrate 14 using the bumps 13, and then a sealing resin 15 is formed to generate multiple acoustic wave devices 1 having the cross-sectional structure shown in Figure 2.
[0040] (Example 2) In the second example shown in Figures 7 and 8, the resonator 3 is made up of the M1 layer 7, the inter-resonator wiring 5 and the external connection wiring 6 are made up of both or either of the M1 layer 7 and the M2 layer 8, and the lower layer 4a of the bump receiving portion 4 is made up of the M1 layer 7. In the bump receiving portion 4, the insulating intermediate portion 4b is composed of an inorganic insulating layer 10 and an organic insulating layer 11 formed thereon. The insulating intermediate portion 4b is provided in the bump receiving portion 4 so that an uncovered region 4d is formed on the M1 layer 7 of the lower layer portion 4a. A part of the upper surface of the M1 layer 7 is exposed in this uncovered region 4d. In addition, the inorganic insulating layer 10 is located between the M1 layer 7 and the M2 layer 8 in the three-dimensional wiring structure portion 12 to insulate them from each other. The upper layer 4c is formed by the M2 layer 8, which is formed in a step after the insulating intermediate portion 4b is formed. The lower surface of the upper layer 4c is in close contact with the upper surface of the M1 layer 7 in the non-covered region 4d. In this second example, the bump 13 is formed on the upper layer 4c of the bump receiving portion 4 configured in this manner, via an additional plating layer 18 (Under Bump Metal).
[0041] The device chip 2 is fixed to pads 14a on the package substrate 14 via bumps 13. A gap is formed between the device chip 2 and the package substrate 14 by the bumps 13, and an internal space 16 in which the resonator 3 faces is formed in the acoustic wave device 1 by the sealing resin 15.
[0042] 9 to 13 show the main parts of the manufacturing process of the second example. First, on the functional surface 2a of the device chip 2, an M1 layer 7 that will become the resonator 3, an M1 layer 7 that will become the lower layer 4a, an M1 layer 7 that will become the inter-resonator wiring 5 that connects the resonators 3 to each other, and an M1 layer 7 that will become the external connection wiring 6 that connects the resonator 3 to the lower layer 4a are formed using a conductive metal (Figure 9). More specifically, in each region of the wafer 17 that will become the device chips 2, which will form one device chip 2, the M1 layer 7 that will become the resonator 3 and the like is formed, typically by photolithography and etching.
[0043] Next, the functional surface 2a of the device chip 2 is covered with an inorganic insulating layer 10 (FIG. 9). More specifically, the inorganic insulating layer 10 is formed, typically by a CVD method or a sputtering method, in each region constituting one device chip 2 on the wafer 17 that will become the device chip 2.
[0044] Next, the inorganic insulating layer 10 is removed as needed, so that in the area that will become the bump receiving portion 4, the lower layer 4a is partially formed as an uncovered region 4d, and the entire region other than the uncovered region 4d is covered with the inorganic insulating layer 10 (FIG. 10). Thereafter, an organic insulating layer 11 is formed on the inorganic insulating layer 10 in a required area in the area that will become the bump receiving portion 4 but is not in the non-covered area 4d (FIG. 10). By doing so, the bump receiving portion 4 can be endowed with advantageous mechanical strength when the device chip 2 is mounted on an aggregate substrate that will become the package substrate 14 using the bumps 13.
[0045] Next, the upper layer 4c is formed on the insulating intermediate portion 4b using a conductive metal so as to be electrically connected to the lower layer 4a through the uncovered region 4d, and the area of the upper layer 4c is formed to be larger than that of the lower layer 4a (FIG. 11). More specifically, the upper layer 4c is formed for each region constituting one device chip 2 on the wafer 17 that will become the device chip 2, typically by photolithography and etching. In this second example, the upper layer portion 4c is formed by the M2 layer 8, and the three-dimensional wiring structure portion 12 is also formed by the M2 layer 8.
[0046] Next, as shown in FIG. 12, solder bumps 13 are formed on the bump receiving portions 4, typically by printing and reflow processing. Alternatively, as another variation, as shown in FIG. 13, bumps 13 are formed on bump receiving portions 4 by melting conductive metal wires.
[0047] Thereafter, the device chips 2 generated from the wafer 17 by dicing are mounted on an aggregate substrate that forms a package substrate 14 using the bumps 13, and then a sealing resin 15 is formed to generate multiple acoustic wave devices 1 having the cross-sectional structure shown in Figure 8.
[0048] (Example 3) In the third example shown in Figures 14 and 15, the resonator 3 is composed of an M1 layer 7, and the inter-resonator wiring 5, the external connection wiring 6, and the lower layer 4a of the bump receiving portion 4 are composed of the M1 layer 7 and the M2 layer 8. In the bump receiving portion 4, the insulating intermediate portion 4b is composed of an inorganic insulating layer 10 and an organic insulating layer 11 formed thereon. The insulating intermediate portion 4b is provided in the bump receiving portion 4 so that an uncovered region 4d is formed on the M2 layer 8 of the lower layer portion 4a. In this uncovered region 4d, a part of the upper surface of the M2 layer 8 is exposed. In addition, the inorganic insulating layer 10 is located between the M1 layer 7 and the M2 layer 8 in the three-dimensional wiring structure portion 12 to insulate them from each other. The upper layer 4c is formed by the M3 layer 9, which is formed in a step after the insulating intermediate portion 4b is formed. The lower surface of the upper layer 4c is in close contact with the upper surface of the M2 layer 8 in the non-covered region 4d. The bumps 13 are formed on the upper layer 4c of the bump receiving portion 4 configured in this manner. In addition, in the three-dimensional wiring structure portion 12, the inorganic insulating layer 10 is located between the M1 layer 7 and the M2 layer 8 to insulate them from each other.
[0049] The device chip 2 is fixed to pads 14a on the package substrate 14 via bumps 13. A gap is formed between the device chip 2 and the package substrate 14 by the bumps 13, and an internal space 16 in which the resonator 3 faces is formed in the acoustic wave device 1 by the sealing resin 15.
[0050] 16 to 20 show the main parts of the manufacturing process of the third example. First, the resonators 3, the lower layer 4a, inter-resonator wiring 5 connecting the resonators 3 to each other, and external connection wiring 6 connecting the resonators 3 to the lower layer 4a are formed on the functional surface 2a of the device chip 2 using a conductive metal (Figure 16). Specifically, (1) an M1 layer 7 is formed, (2) an inorganic insulating layer 10 is then formed in the three-dimensional wiring structure portion 12 so that the inorganic insulating layer 10 covers the M1 layer 7, (3) an M2 layer 8 is then formed on the M1 layer 7, and (4) an inorganic insulating layer 10 is then formed on the M2 layer 8. In the region that will become the bump receiving portion, the lower layer 4a consisting of the M1 layer 7 and the M2 layer 8 is formed so that a portion of the formation region is made into a non-covered region 4d, and the formation region other than this non-covered region 4d is covered with a portion of the inorganic insulating layer 10 (Figure 16).
[0051] The M1 layer 7 and the M2 layer 8 are typically formed by photolithography and etching for each region constituting one device chip 2 on the wafer 17 that will become the device chip 2. Furthermore, the inorganic insulating layer 10 is typically formed by a CVD method, a sputtering method or the like for each region constituting one device chip 2 on the wafer 17 that will become the device chip 2.
[0052] The wafer 17 configured in this manner can also be used as the wafer 17 for producing the acoustic wave device 1 having a WLP structure.
[0053] Next, an organic insulating layer 11 is formed on the inorganic insulating layer 10 in a required area in the area that will become the bump receiving portion 4 but is not in the non-covered area 4d (FIG. 17). By doing so, the bump receiving portion 4 can be endowed with mechanical strength that is advantageous when the device chip 2 is mounted on an aggregate substrate that forms the package substrate 14 using the bumps 13.
[0054] Next, the upper layer 4c is formed on the insulating intermediate portion 4b using a conductive metal so as to be electrically connected to the lower layer 4a through the uncovered region 4d, and the area of the upper layer 4c is formed to be larger than that of the lower layer 4a (FIG. 18). More specifically, the upper layer 4c is formed for each region constituting one device chip 2 on the wafer 17 that will become the device chip 2, typically by photolithography and etching.
[0055] Next, as shown in FIG. 19, solder bumps 13 are formed on the bump receiving portions 4, typically by printing and reflow processing. Alternatively, as another variation, as shown in FIG. 20, bumps 13 are formed on bump receiving portions 4 by melting conductive metal wires.
[0056] Thereafter, the device chips 2 generated from the wafer 17 by dicing are mounted on an aggregate substrate that forms a package substrate 14 using the bumps 13, and then a sealing resin 15 is formed to generate multiple acoustic wave devices 1 having the cross-sectional structure shown in Figure 15.
[0057] It should be noted that the present invention is not limited to the above-described embodiments, but includes all embodiments that can achieve the object of the present invention. [Explanation of symbols]
[0058] x Propagation direction 1. Acoustic wave devices 2. Device chip 2a Functional aspect 3 resonator 3a IDT electrode 3b reflector 3c electrode finger 3D Busbar 3e electrode finger 3F bus bar 4 Bump receiving part 4a Lower part 4b Insulating intermediate section 4c upper level 4d uncovered area 4e Outer Wall 5 Inter-resonator wiring 6 External connection wiring 7 M1 layer 8 M2 layer 9 M3 layer 10 Inorganic insulating layer 11 Organic insulating layer 12 Three-dimensional wiring structure part 13 Bump 14 Package substrate 14a pad 15 Sealing resin 16 Interior Space 17 wafers 18 Additional plating layer
Claims
1. An acoustic wave device comprising: a plurality of resonators, a plurality of bump receiving portions, inter-resonator wiring connecting the resonators to each other, and external connection wiring connecting the resonators to the bump receiving portions, formed on a functional surface of a device chip made of a piezoelectric material; At least one of the bump receiving portions has a lower layer portion connected to the external connection wiring, an insulating intermediate portion, and a conductive upper layer portion, The lower layer portion is formed such that a part of the formation area of the lower layer portion is an uncovered area, and the formation area of the lower layer portion other than the uncovered area is covered by the insulating intermediate portion; the upper layer portion is formed on the insulating intermediate portion so as to be electrically connected to the lower layer portion through the uncovered region, Moreover, in the acoustic wave device, the upper layer portion is formed to have a larger area than the lower layer portion when viewed in a direction perpendicular to the functional surface.
2. 2. The acoustic wave device according to claim 1, wherein the insulating intermediate portion is formed so as to cover the lower layer portion and a predetermined area on the functional surface near the lower layer portion surrounding the lower layer portion at the location where the bump receiving portion is formed.
3. 3. The acoustic wave device according to claim 2, wherein at least a portion of the inter-resonator wiring is located to the side of the lower layer and below the upper layer, with the insulating intermediate portion interposed therebetween.
4. 3. A method for manufacturing an acoustic wave device according to claim 1, further comprising the steps of: forming, on the functional surface of the device chip, the resonators, the lower layer portion, inter-resonator wiring connecting the resonators to each other, and external connection wiring connecting the resonators to the lower layer portion, using a conductive metal; a step of covering the lower layer portion in a region that will become the bump receiving portion with the insulating intermediate portion so that a part of the formation region of the lower layer portion is left as a non-covered region and the formation region other than the non-covered region is covered with the insulating intermediate portion; forming the upper layer portion of the insulating intermediate portion in the region that will become the bump receiving portion, by using a conductive metal, so as to be electrically connected to the lower layer portion through the non-covered region; In the step of forming the upper layer portion, the upper layer portion is formed so as to have a larger area than the lower layer portion when viewed in a direction perpendicular to the functional surface.