Sic-based electronic device with enhanced robustness and method for manufacturing the same

Abstract

To provide an electronic device that improves adhesion between an underlying layer and a passivation layer.SOLUTION: It comprises a body 53 of silicon-carbide having a 53a and an edge zone. The edge structure 52 extends above said edge zone and is formed by the metallization 58, the first insulation layer 61 and the passivation layer 69. The metal layer extends on said surface of the semiconductor body, the first insulating layer extends partly above the metal layer and partly above said surface of the semiconductor body, the interface layer 63 extends partly above the first insulating layer and partly above the metal layer, and the passivation layer extends partly on the metal layer, partly on the surface and completely covers the interface layer. The first insulating layer is made of a first electrically insulating material, the interface layer is made of a second electrically insulating material, and the passivation layer is made of a third electrically insulating material.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to Italian Patent Application No. 102024000014080, filed June 19, 2024, and entitled "DISPOSITIVO ELETTRONICO BASATO SU SIC CON ROBUSTEZZA MIGLIORATA E METODO DI FABBRICAZIONE DEL DISPOSITIVO ELETTRONICO," which is incorporated herein by reference to the fullest extent permitted by law.

[0002] The present disclosure relates to SiC-based electronic devices with enhanced robustness and methods for manufacturing the electronic devices. [Background technology]

[0003] Silicon carbide (SiC) is of great interest in the semiconductor industry, especially for the manufacture of electronic components such as diodes or transistors, especially for power applications.

[0004] Electronic devices fabricated on substrates of different polytypes of silicon carbide (e.g., 3C-SiC, 4H-SiC, 6H-SiC) have many advantages, including low output resistance, low leakage current, high temperature operation, and high frequency operation.

[0005] Typically, in these devices, the substrate is covered with one or more passivation layers using polymeric materials (e.g., polyimide). These layers provide protection against the external environment, particularly preventing moisture from entering the device, allowing the electronic device to withstand high operating temperatures. They also have high dielectric strengths, e.g., greater than 400 kV / mm. In particular, the high dielectric strength of the polymeric materials ensures that the passivation layers can withstand high electric fields, so that they do not break or perforate even when subjected to large potential differences.

[0006] However, polymer materials have a high coefficient of thermal expansion (CTE) (e.g., polybenzobisoxazole material, or "PIX," has a CTE of 43e -6 1 / K), which results in a low coefficient of thermal expansion (CTE=3.8e -6 1 / K) causes adhesion problems of the passivation layer to SiC.

[0007] In particular, such adhesion problems between the passivation layer and SiC can occur when the electronic device is subjected to high thermal expansion (e.g., an operating temperature difference of about 200°C or more) during thermal cycling tests, for example, performed from about -50°C to about +150°C, or during use of the electronic device. Due to the large difference in CTE between the passivation layer and SiC, such large thermal expansion can generate mechanical stress at the interface between the passivation layer and SiC, which can lead to at least partial delamination of the passivation layer relative to the SiC semiconductor body.

[0008] If this delamination progresses (e.g., when two metallizations of an electronic device set at different potentials are exposed to air), discharges can occur at the interface, potentially damaging the same electronic device. The risk of damaging the electronic device increases, especially when the electronic device is used under reverse bias conditions, because the voltage difference it can withstand is large (e.g., 1000 V or more).

[0009] Known solutions to this problem include using multiple dielectric layers of different materials (e.g., silicon nitride, silicon oxide, and polyimide, successively arranged) to form a multi-layer passivation to limit mechanical stress at the interface with the SiC semiconductor body.

[0010] FIG. 1 shows, in a cross-sectional side view in an orthogonal (three-axis) reference system of axes X, Y and Z, part of an electronic device 1 of a known type (here exemplarily a "Junction Barrier Schottky" diode (JBS)).

[0011] The JBS device 1 comprises a semiconductor body 3 of N-type SiC having an upper surface 3a and a lower surface 3b. The semiconductor body 3 may include, for example, a substrate and one or more regions epitaxially grown on the substrate, the regions being N-type and having respective doping concentration values.

[0012] The JBS device 1 also comprises a plurality of junction barrier elements 9 (hereinafter also referred to as JB, junction barrier, elements 9) within the semiconductor body 3, the JB elements 9 facing the top surface 3a and each including a respective region of P type implanted within the semiconductor body 3 and an ohmic contact (not shown) on the implanted region at the top surface 3a of the semiconductor body 3.

[0013] The JBS device 1 further comprises a first metallization 8 extending over the top surface 3a and in electrical contact with the JB elements 9 via respective ohmic contacts (not shown).

[0014] The JBS device 1 further comprises an edge termination region 10 (or guard ring) that completely surrounds the JB element 9, specifically the P-type implant region.

[0015] Schottky diode 12 is formed at the interface between first metallization 8 and semiconductor body 3, where a semiconductor-metal Schottky junction is formed. The region of JBS device 1 that includes JB element 9 and Schottky diode 12 (i.e., the region contained within guard ring 10) is the active region 4 of JBS device 1.

[0016] The JBS device 1 further comprises a second metallization 6 extending onto the lower surface 3b. The first and second metallizations 8, 6 form anode and cathode electrical terminals, respectively, that can be biased during use of the JBS device 1.

[0017] Electrically passive region 16 extends outside edge termination region 10 .

[0018] An insulating layer 18, specifically silicon oxide (SiO 2 ), extends partially above the edge termination region 10.

[0019] First metallization 8 is in electrical contact with the portion of edge termination region 10 not covered by insulating layer 18 and extends partially above insulating layer 18 .

[0020] Here an interfacial layer 20 of silicon nitride (SiN) extends above the first metallization 8 and the insulating layer 18 .

[0021] Furthermore, the JBS device 1 comprises a passivation layer 22, in particular made of polyimide, which extends above the interface layer 20. In other words, the interface layer 20 serves as an interface between the passivation layer 22 and the underlying layers, here the first metallization 8 and the insulating layer 18.

[0022] Here, a protective layer 24 of resin, for example Bakelite, extends above the passivation layer 22 to protect the JBS device 1 and form a package.

[0023] However, while the interface layer 20 improves adhesion between the underlying layer and the passivation layer 22, as described above, under certain critical conditions during use of the JBS device 1 or during thermal or thermomechanical testing, stresses may develop that can cause delamination or partial separation of the passivation layer 22 from the interface layer 20. This occurs particularly in the presence of high operating temperatures (e.g., above 150°C). This effect not only weakens the JBS device 1 structurally but can also promote the generation of undesirable electrical discharges, causing the JBS device 1 to malfunction or completely impair its functionality. In fact, Applicant has observed that, under certain conditions of thermomechanical or mechanical stress after assembly processing, the interface layer 20 may exhibit one or more localized cracks throughout its thickness, which can cause electrical discharges in the first metallization 8. This problem becomes more pronounced when the JBS device 1 is subjected to high thermal expansion and high voltage differentials under reverse bias conditions.

[0024] Therefore, a need is felt to overcome the aforementioned problems. Summary of the Invention

[0025] In accordance with the present disclosure, there are provided SiC-based electronic devices and methods for their manufacture, as defined in the accompanying claims.

[0026] According to some embodiments, an exemplary electronic device is provided, comprising: a semiconductor body of silicon carbide having a surface and an edge zone; and an edge structure extending above the edge zone of the semiconductor body, the edge structure including: a metal layer extending on the surface of the semiconductor body; a first insulating layer made of a first electrically insulating material extending partially above the metal layer and partially above the surface of the semiconductor body; an interfacial layer made of a second electrically insulating material different from the first electrically insulating material extending partially above the first insulating layer and partially above the metal layer; and a passivation layer made of a third electrically insulating material different from the second electrically insulating material extending partially over the metal layer and partially over the surface and completely covering the interfacial layer.

[0027] In some embodiments, the interfacial layer has first and second edge portions, and the passivation layer completely covers and encapsulates the first and second edge portions of the interfacial layer and is in direct contact with the metal layer and the surface of the semiconductor body along the first and second edge portions of the interfacial layer.

[0028] In some embodiments, the first insulating layer has a first end and a second end, and the interfacial layer completely covers and encapsulates the first and second ends of the first insulating layer and directly contacts the metal layer and the surface of the semiconductor body along the first and second ends of the first insulating layer.

[0029] In some embodiments, the metal layer has an outer edge and the first insulating layer covers and seals the outer edge of the metal layer.

[0030] In some embodiments, the second insulating layer extends partially over the surface of the semiconductor body beneath the first insulating layer and the metal layer, a second end of the first insulating layer is overlaid on an outer side edge of the second insulating layer, and an interface layer further covers the outer side edge of the second insulating layer.

[0031] In some embodiments, the first electrically insulating material is silicon oxide or TEOS.

[0032] In some embodiments, the second electrically insulating material is silicon nitride.

[0033] In some embodiments, the third electrically insulating material is a polyimide.

[0034] In some embodiments, the second insulating layer is silicon oxide or TEOS.

[0035] In some embodiments, a method for manufacturing an electronic device is provided. An exemplary method includes forming an edge structure on a silicon carbide semiconductor body having a surface and an edge zone, where forming the edge structure includes forming a metal layer on the surface of the semiconductor body, forming a first insulating layer comprised of a first electrically insulating material partially on the surface of the semiconductor body and partially on the metal layer, forming an interfacial layer comprised of a second electrically insulating material partially on the first insulating layer and partially on the metal layer, and forming a passivation layer on the interfacial layer partially on the metal layer and partially on the first surface of the semiconductor body, the passivation layer comprised of a third electrically insulating material partially on the metal layer and partially on the first surface of the semiconductor body, the passivation layer completely covering the interfacial layer.

[0036] In some embodiments, forming the interfacial layer includes forming first and second edge portions, and forming the passivation layer includes completely covering and encapsulating the first and second edge portions of the interfacial layer and directly contacting the metal layer and surfaces of the semiconductor body along the first and second edge portions of the interfacial layer.

[0037] In some embodiments, forming the first insulating layer includes forming a first end and a second end, and forming the interfacial layer includes completely covering and encapsulating the first and second ends of the first insulating layer and directly contacting the metal layer and surfaces of the semiconductor body along the first and second ends of the first insulating layer.

[0038] In some embodiments, forming the metal layer includes forming an outer edge, and forming the first insulating layer includes covering and sealing the outer edge of the metal layer.

[0039] In some embodiments, forming a second insulating layer on the surface of the semiconductor body partially below the first insulating layer and the metal layer, wherein forming the interface layer includes covering side edges of the second insulating layer.

[0040] In some embodiments, the second insulating layer defines an active region, and the metal layer overlies and is in direct electrical contact with the surface of the semiconductor body in the active region. [Brief explanation of the drawings]

[0041] In order that the present disclosure may be better understood, embodiments will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Figure 1] 1 shows a cross-sectional view of an electronic device of a known type; [Figure 2] 1 illustrates a cross-sectional view of an electronic device, according to one embodiment. [Figure 3A] 3A-3C illustrate, in cross-sectional views, steps in fabricating the electronic device of FIG. 2, according to one embodiment. [Figure 3B] 3A-3C illustrate, in cross-sectional views, steps in fabricating the electronic device of FIG. 2, according to one embodiment. [Figure 3C] 3A-3C illustrate, in cross-sectional views, steps in fabricating the electronic device of FIG. 2, according to one embodiment. [Figure 3D] 3A-3C illustrate, in cross-sectional views, steps in fabricating the electronic device of FIG. 2, according to one embodiment. [Figure 4] 1 illustrates, in cross-section, an electronic device according to a further embodiment; [Figure 5A] 5A-5C illustrate, in cross-sectional views, steps for fabricating the electronic device of FIG. 4, according to one embodiment. [Figure 5B] 5A-5C illustrate, in cross-sectional views, steps for fabricating the electronic device of FIG. 4, according to one embodiment. [Figure 5C] 5A-5C illustrate, in cross-sectional views, steps for fabricating the electronic device of FIG. 4, according to one embodiment. [Figure 5D] 5A-5C illustrate, in cross-sectional views, steps for fabricating the electronic device of FIG. 4, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0042] 2 shows an electronic device 50. In particular, device 50 is a JBS diode, although the present disclosure is not limited to this device and finds application in other types of electronic devices, particularly power devices such as MOSFETs, IGBTs, MPSs, Schottky diodes, PN diodes, PiN diodes, etc.

[0043] In particular, FIG. 2 shows an edge of an electronic device 50 arranged around a die 90 of semiconductor material on which the same electronic device 50 is integrated.

[0044] Device 50 comprises a semiconductor body 53 having a front surface 53a and a back surface 53b. In particular, in Figure 2, semiconductor body 53 comprises a substrate 53' and, optionally, one or more epitaxial layers 53" grown thereon that function as drift layers for electronic device 50. Although reference will be made hereinafter to a single epitaxial layer 53", the teachings shown also apply to the case of multiple epitaxial layers.

[0045] The semiconductor body 53 is made of N-type or P-type silicon carbide (SiC) (hereinafter, only N-type will be referred to non-limitingly). In particular, the semiconductor body 53 is of 4H-SiC type, although other polytypes such as 2H-SiC, 3C-SiC, and 6H-SiC can also be used. For example, the substrate 53' may be 1·10 19 at / cm 3 ~1·10 22 at / cm 3 and has a thickness, measured between surfaces 53a and 53b (along vertical axis Z of the cartesian reference system XYZ), comprised between 300 μm and 450 μm, in particular equal to about 360 μm. The epitaxial layer 53″ has a respective dopant concentration lower than that of the substrate 53′ and a thickness of, for example, 5 to 15 μm.

[0046] A metallization 57, in this example made of, for example, Ti / NiV / Ag or Ti / NiV / Au, extends on the rear surface 53b. An ohmic contact layer (e.g., nickel silicide), not shown, may extend on the rear surface 53b between the substrate 53' and the metallization 57.

[0047] One or more barrier doped regions 59', here of P type, extend within the semiconductor body 53 (in particular within the epitaxial layer 53"), starting from the front surface 53a and spaced apart from one another along the X-axis.

[0048] The barrier doped region 59' may have a width of, for example, 0.5 to 10 μm along the X axis.

[0049] In this embodiment, the electronic device 50 also optionally comprises, for each barrier-doped region 59', a respective ohmic contact region 59'' housed in the barrier-doped region 59' at the front surface 53a.

[0050] Each barrier doped region 59' and each ohmic contact region 59'' form a junction barrier element 59, also referred to hereinafter as a JB (junction barrier) element 59.

[0051] The electronic device 50 includes an edge structure 52 extending annularly around the die 90, only a portion of which is shown in cross section in FIG.

[0052] Here, the edge structure 52 comprises a terminal anode region 51 extending into the epitaxial layer 53 ″ around the zone containing the JB element 59 .

[0053] The edge structure 52 further comprises an edge termination region or guard ring 60 .

[0054] Edge termination region 60 is formed by a further doped region, here P-type, that extends into epitaxial layer 53'' and faces front surface 53a, completely surrounding JB element 59 in plan view on the XY plane defined by horizontal axes X and Y of a Cartesian coordinate system XYZ. Edge termination region 60 defines active area 54 and may be partially overlapping terminal anode region 51.

[0055] However, edge termination region 60 is not required and may be omitted.

[0056] The edge structure 52 also includes a portion of a metallization 58, in this example an anode metallization 58 of, for example, Ti / AlSiCu or Ni / AlSiCu, which extends over a portion of the front surface 53a in the active region 54.

[0057] One or more Schottky diodes 62 are formed laterally and between the barrier-doped regions 59′ at the interface between the semiconductor body 53 and the anode metallization 58. In particular, the Schottky diodes are formed by semiconductor-metal junctions formed by portions of the semiconductor layer 53 in direct contact with the anode metallization 58.

[0058] Furthermore, each ohmic contact region 59" forms an electrical connection region between the anode metallization 58 and a respective barrier-doped region 59' above the respective barrier-doped region 59'. This electrical connection region has a lower resistance than the respective same barrier-doped region 59'. Therefore, the JB element 59 is a PiN diode.

[0059] The edge structure 52 further comprises an insulating layer 61 , an interfacial layer 63 , and a passivation layer 69 .

[0060] The insulating layer 61 is made of, in particular, a dielectric or insulating material (such as silicon oxide or TEOS - tetraethyl orthosilicate) and extends partially above the anode metallization 58 (sealing the outer edges at the ends of the electronic device 50) and partially above the front surface 53a.

[0061] For example, the insulating layer 61 has a thickness along the vertical axis Z of 0.2 to 2 μm.

[0062] Here, the silicon nitride (SiN) interface layer 63 extends continuously partially above the insulating layer 61 and partially onto the anode metallization 58, as well as along the outer periphery of the insulating layer 61 and partially onto the front surface 53a.

[0063] For example, the interface layer 63 has a thickness along the vertical axis Z of 0.2 to 2 μm.

[0064] The passivation layer 69 is made of an organic material, in particular a polymeric material such as polyimide (e.g., PIX), and completely covers the interface layer 63 and also extends along the inner and outer edges of the interface layer 63, over the anode metallization 58 and partially over the front surface 53a.

[0065] In other words, the interface layer 63 extends between the passivation layer 69 and the underlying layer (here, the insulating layer 61 ) and aids in the adhesion of the overlying passivation layer 69 .

[0066] A protective layer 74 made of a resin, such as Bakelite, extends over the passivation layer 69 to package the electronic device 50 .

[0067] In this manner, the edge structure 52 of the electronic device 50 comprises a triple layer (insulating layer 61, interfacial layer 63, and passivation layer 69) that protects the electronic device 50 from the external environment, and in particular prevents moisture from reaching the high voltage structures and metallization (e.g., anode metallization 58).

[0068] In particular, here, insulating layer 61 surrounds and seals the periphery of anode metallization 58. Interfacial layer 63 surrounds and seals insulating layer 61 at both its top and its side edges. Passivation layer 69 surrounds and seals interfacial layer 63 at both its top and its side edges.

[0069] Thus, the edge structure 52 has a packaging configuration in which each layer covers and seals the underlying layer, ensuring high robustness even in the event of multiple thermal cycles and / or harsh environmental conditions.

[0070] 3A-3D, the manufacturing steps of the electronic device 50 of FIG. 2 will be described below, focusing on those manufacturing steps that are useful for understanding the present disclosure. FIGS. 3A-3D are expressed in the same reference system XYZ as FIG. 2.

[0071] Referring to FIG. 3A, wafer 95 is first processed to form JB element 59, terminal anode region 51, and edge termination region 60 in a semiconductor body 53 of SiC in a manner known per se.

[0072] 3B, anode metallization 58 is formed, for example, by evaporation or "sputtering," followed by lithographic definition and etching of the deposited metal layer. Anode metallization 58 may include one or more layers, for example, a layer of titanium or nickel and a thick layer of an Al-based alloy, such as AlSiCu, AlCu, or Al.

[0073] Subsequently, an insulating or dielectric material is deposited to form insulating layer 61. This step is carried out, for example, by a CVD (Chemical Vapor Deposition) or LPCVD (Low Pressure Chemical Vapor Deposition) process, in which the insulating or dielectric material is deposited over the entire top surface of the wafer (repeatedly indicated by 53 a) and then selectively removed by phototechnique and etching so as to completely cover the outer edges of anode metallization 58.

[0074] 3C, an interfacial layer 63 is then formed, for example by CVD deposition of silicon nitride and definition of the deposited layer by photolithography and etching, such that the interfacial layer 63 surrounds and seals the insulating layer 61. The interfacial layer 63 also extends partially onto both the surface of the anode metallization 58 and onto the front surface 53a of the semiconductor body 53.

[0075] Next, in Figure 3D, a passivation layer 69 is formed. This step involves the deposition of an insulating material, for example polyimide, by a deposition process such as spinning, followed by a definition and a "curing" treatment.

[0076] The passivation layer 69 therefore completely covers the interface layer 63, surrounding and sealing it from the outside, and extending partly above the anode metallization 58 and the front surface 53a.

[0077] In particular, the passivation layer 69 leaves uncovered zones that need to be accessible from the outside, such as the central zone of the anode metallization 58, to allow electrical contact thereto.

[0078] The manufacturing process then continues with known subsequent steps not described in detail here to form further elements of electronic device 50 (e.g., to form ohmic contact layers (if any) and cathode metallization 57, not shown), and to dice wafer 95 into single dies.

[0079] 4 shows an electronic device 100 according to a further embodiment, which is represented in the same Cartesian (three-axis) reference system XYZ as in FIG.

[0080] In particular, the electronic device 100 is a JBS diode, similar to that described with reference to Figures 1 and 2. However, even in this case, the present disclosure is not limited to JBS devices and also finds application in other types of electronic devices, particularly power devices such as, for example, MOSFETs, IGBTs, MPSs, Schottky diodes, PN diodes, PiN diodes, etc.

[0081] Elements of electronic device 100 that are common to electronic device 50 of FIG. 2 are indicated with the same reference numerals and will not be described further.

[0082] The edge structure 52 includes a further insulating layer 64 of a dielectric or insulating material (such as silicon oxide or TEOS - tetraethyl orthosilicate).

[0083] A further insulating layer 64 extends onto the front surface 53 a of the semiconductor body 53 partially beneath the insulating layer 61 (hence also referred to herein as the first insulating layer 61 ) and the anode metallization 58 .

[0084] The further insulating layer 64 may be of the same material as the first insulating layer 61 and may therefore be indistinguishable from the first insulating layer 61 in the overlap zone. The boundary between the two insulating layers 61 and 64 is therefore shown by a dashed line in Figure 4.

[0085] Here, the interface layer 63 also covers the outer side edges of the further insulating layer 64 .

[0086] The anode metallization 58 extends onto the inner edge of a further insulating layer 64 .

[0087] Thus, again an interfacial layer 63 of silicon nitride (SiN) extends along and seals both the outer periphery of the first insulating layer 61 and the outer periphery of the further insulating layer 64 .

[0088] The further insulating layer 64 has a thickness along the vertical axis Z of, for example, 0.5 to 2 μm.

[0089] A passivation layer 69 of a polymeric material such as polyimide (e.g., PIX) completely covers the interfacial layer 63 and also extends along the inner and outer edges of the interfacial layer 63, over the anode metallization 58 and partially over the front surface 53a.

[0090] 5A-5D, the steps for fabricating the electronic device 100 of FIG. 4 will now be described, focusing on those steps useful for understanding the present disclosure.

[0091] Referring to FIG. 5A, wafer 195 is first processed to form JB element 59, terminal anode region 51, and edge termination region 60 in a semiconductor body 53 of SiC in a manner known per se.

[0092] Now, an insulating or dielectric material is deposited on the front side 53a to form a further insulating layer 64, so as to form an active region 54 in the semiconductor body 53 of SiC, in a manner known per se.

[0093] The step of forming the further insulating layer 64 is carried out, for example, by a CVD (chemical vapor deposition) or LPCVD (low pressure chemical vapor deposition) process, in which an insulating or dielectric material is deposited over the entire upper surface 53a of the wafer 195 and then selectively removed by photolithography techniques and etching so as to completely cover the edge termination region 60 and partially cover the terminal anode region 51.

[0094] 5B, anode metallization 58 is formed, for example, by "sputtering" followed by lithographic definition and etching of the deposited metal layer. An insulating or dielectric material is then deposited by the process described above to form a first insulating layer 61 so as to completely cover and seal the outer edges of anode metallization 58.

[0095] Next, in FIG. 5C, an interface layer 63 is formed, for example by the process described above, so that the interface layer 63 surrounds and seals the insulating layer 61 and the further insulating layer 64, and also extends partially onto both the surface of the anode metallization 58 and onto the front surface 53a of the semiconductor body 53.

[0096] Next, in Figure 5D, a passivation layer 69 is formed. This step involves the deposition of an insulating material, for example by spinning polyimide, followed by a definition and curing process.

[0097] The passivation layer 69 therefore completely covers the interface layer 63, surrounding and sealing it from the outside, and extends partially above the anode metallization 58 and the front surface 53a.

[0098] Again, the passivation layer 69 leaves uncovered zones that need to be accessible from the outside, for example the central zone of the anode metallization 58 .

[0099] The manufacturing process then continues with subsequent steps not described in detail here to form further elements of the electronic device 100 (e.g., to form an ohmic contact layer (if present) and cathode metallization 57, not shown), and to dice the wafer 195 to form the electronic device 100.

[0100] The electronic devices and manufacturing processes described herein have many advantages.

[0101] First, the edge structure 52 comprises a triple layer (first insulating layer 61, interface layer 63, and passivation layer 69) that protects the electronic device 50, 100 from the external environment, and in particular prevents moisture from reaching the high voltage structures and metallization.

[0102] Furthermore, the passivation layer 69 extends above the interface layer 63 and the front surface 53a, thereby protecting the edge structure, which is therefore particularly robust and reliable during thermal stress testing of the electronic device 50, 100. Furthermore, the passivation layer 69 reduces the propagation of stresses that could damage the interface layer 63.

[0103] In other words, the edge structure 52 ensures high electrical performance of the electronic device 50,100, while eliminating structural problems associated with damage to the interface layer 63 that may occur after thermal cycling or use of the electronic device 50,100.

[0104] Finally, it will be apparent that modifications and variations can be made to the electronic devices and manufacturing processes described and illustrated herein without departing from the scope of the present disclosure, as defined in the appended claims.

Claims

1. 1. An electronic device comprising: a semiconductor body made of silicon carbide having a surface and an edge zone; an edge structure extending above the edge zone of the semiconductor body; and the edge structure comprises: a metal layer extending over the surface of the semiconductor body; a first insulating layer of a first electrically insulating material extending partially above the metal layer and partially above the surface of the semiconductor body; an interface layer of a second electrically insulating material different from the first electrically insulating material, the second electrically insulating material extending over the first insulating layer and partially over the metal layer; a passivation layer made of a third electrically insulating material different from the second electrically insulating material, extending partially on the metal layer, partially on the surface, and completely covering the interface layer; , an electronic device.

2. 2. The electronic device of claim 1, wherein the interfacial layer has first and second edge portions, and the passivation layer completely covers and encapsulates the first and second edge portions of the interfacial layer and directly contacts the metal layer and the surface of the semiconductor body along the first and second edge portions of the interfacial layer.

3. 2. The electronic device of claim 1, wherein the first insulating layer has a first end and a second end, and the interfacial layer completely covers and encapsulates the first and second ends of the first insulating layer and directly contacts the metal layer and the surface of the semiconductor body along the first and second ends of the first insulating layer.

4. The electronic device of claim 1 , wherein the metal layer has an outer edge, and the first insulating layer covers and encapsulates the outer edge of the metal layer.

5. 4. The electronic device of claim 3, further comprising a second insulating layer on the surface of the semiconductor body and extending partially beneath the first insulating layer and the metal layer, the second end of the first insulating layer overlying an outer side edge of the second insulating layer, and the interface layer further covering the outer side edge of the second insulating layer.

6. The electronic device of claim 1 , wherein the first electrically insulating material is silicon oxide or TEOS.

7. The electronic device of claim 1 , wherein the second electrically insulating material is silicon nitride.

8. The electronic device of claim 1 , wherein the third electrically insulating material is a polyimide.

9. The electronic device of claim 5 , wherein the second insulating layer is silicon oxide or TEOS.

10. 1. A method for manufacturing an electronic device, comprising forming an edge structure on a silicon carbide semiconductor having a surface and an edge zone; forming an edge structure; forming a metal layer on the surface of the semiconductor body; forming a first insulating layer of a first electrically insulating material over a portion of the surface of the semiconductor body and over a portion of the metal layer; forming an interface layer made of a second electrically insulating material different from the first electrically insulating material on the first insulating layer and on a portion of the metal layer; forming a passivation layer on the interface layer, partially on the metal layer and partially on the first surface of the semiconductor body, the passivation layer being made of a third electrically insulating material different from the second electrically insulating material, the passivation layer completely covering the interface layer; 1. A method for manufacturing an electronic device, comprising:

11. 11. The method for manufacturing an electronic device of claim 10, wherein forming the interface layer includes forming first and second edge portions, and forming the passivation layer includes completely covering and encapsulating the first and second edge portions of the interface layer and directly contacting the metal layer and the surface of the semiconductor body along the first and second edge portions of the interface layer.

12. 11. The method for manufacturing an electronic device of claim 10, wherein forming the first insulating layer includes forming a first end and a second end, and forming the interfacial layer includes completely covering and encapsulating the first and second ends of the first insulating layer and directly contacting the metal layer and the surface of the semiconductor body along the first and second ends of the first insulating layer.

13. 11. The method for manufacturing an electronic device of claim 10, wherein forming the metal layer includes forming an outer edge, and forming the first insulating layer includes covering and sealing the outer edge of the metal layer.

14. 11. The method for manufacturing an electronic device of claim 10, further comprising forming a second insulating layer on the surface of the semiconductor body partially below the first insulating layer and the metal layer, and wherein forming the interface layer comprises covering side edges of the second insulating layer.

15. 14. The method for manufacturing an electronic device of claim 13, wherein the second insulating layer defines an active area, and the metal layer overlies and is in direct electrical contact with the surface of the semiconductor body in the active area.

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