Store buffer entry allocation

Abstract

To provide an apparatus, a system, a method, a computer-readable medium, and computer code with a store buffer for merging overlapping store data.SOLUTION: The load / store unit 12 comprised in the data processing apparatus 2 comprises allocation circuitry to allocate store data comprising N portions to a store buffer. The store buffer comprises a data buffer holding data entries each holding one of the N portions of store data, and an address buffer in which a given address entry indicates a memory address at which the store data is to be stored and is associated with N indications identifying one or more of the data entries containing the store data. The allocation circuitry is responsive to a determination that the M portions of the N portions of store data each comprise duplicate data to set M indications of the N indications to identify given data entries holding duplicate data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates to data processing, and more particularly to managing the allocation of entries in a store buffer. [Background technology]

[0002] A data processing apparatus may perform operations to store data in a memory system. The process of storing data may take some time to complete, and therefore, to enable the data processing apparatus to continue performing further operations, a store buffer may be implemented in which data is temporarily held before being passed to the memory system for storage. Thus, the available capacity of the store buffer affects the rate at which store operations can be performed, as the store operation may need to stall if the store buffer is already full with data that has not yet been stored in the memory system. Summary of the Invention

[0003] In one exemplary embodiment described herein, an apparatus is provided comprising: an allocation circuit configured to allocate store data in a store buffer, the store data comprising N portions, N>1; the store buffer comprising: a data buffer configured to hold data entries, each data entry configured to hold one of the N portions of the store data; and an address buffer configured to hold address entries, a given address entry indicating a memory address where the store data is to be stored and associated with N instructions that identify one or more of the data entries that include the store data; and wherein, in response to a determination that M portions of the N portions of the store data each include duplicate data, the allocation circuit sets M of the N instructions to identify the given data entry that holds the duplicate data.

[0004] In another exemplary embodiment described herein, there is provided a system comprising the above-described apparatus implemented in at least one packaged chip, at least one system component, and a substrate, wherein the at least one packaged chip and the at least one system component are assembled on the substrate.

[0005] In another exemplary embodiment described herein, a chip-containing product is provided that includes the system described above, where the system is assembled on a further substrate along with at least one other product component.

[0006] In another exemplary embodiment described herein, a method is provided that includes allocating store data in a store buffer, the store data including N portions, where N>1; maintaining data entries, each data entry configured to hold one of the N portions of the store data; maintaining address entries, a given address entry indicating a memory address where the store data is to be stored and associated with N instructions that identify one or more of the data entries that include the store data; and in response to a determination that M portions of the N portions of the store data each include duplicate data, setting M of the N instructions to identify the given data entry that holds the duplicate data.

[0007] In another exemplary embodiment described herein, a non-transitory computer-readable medium storing computer-readable code for fabricating an apparatus is provided, the non-transitory computer-readable medium comprising: an allocation circuit configured to allocate store data in a store buffer, the store data comprising N portions, where N>1; the store buffer comprising: a data buffer configured to hold data entries, each data entry configured to hold one of the N portions of the store data; and an address buffer configured to hold address entries, a given address entry indicating a memory address where the store data should be stored and associated with N instructions that identify one or more of the data entries that include the store data; and wherein, in response to determining that M portions of the N portions of the store data each include duplicate data, the allocation circuit sets M of the N instructions to identify the given data entry that holds the duplicate data. [Brief explanation of the drawings]

[0008] The present invention will now be further described, by way of example only, with reference to embodiments thereof as illustrated in the accompanying drawings, in which: [Figure 1] 1 illustrates a schematic diagram of a data processing system including an apparatus in accordance with some illustrative embodiments; [Figure 2] 1 illustrates a schematic diagram of a load / store unit according to some example embodiments; [Figure 3A] 10 shows an example comparison of how an indication associated with an address entry can be set to identify one or more data entries. [Figure 3B] 10 shows an example comparison of how an indication associated with an address entry can be set to identify one or more data entries. [Figure 3C] 10 shows an example comparison of how an indication associated with an address entry can be set to identify one or more data entries. [Figure 4A] 10 illustrates another comparative example of how an indication associated with an address entry can be set to identify one or more data entries. [Figure 4B] 10 illustrates another comparative example of how an indication associated with an address entry can be set to identify one or more data entries. [Figure 4C] 10 illustrates another comparative example of how an indication associated with an address entry can be set to identify one or more data entries. [Figure 5] 1 illustrates a series of steps for determining how to set the instruction associated with a given address entry. [Figure 6] 1 illustrates a schematic diagram of a load / store unit according to some example embodiments; [Figure 7] Shows how store data can be merged. [Figure 8] 1 illustrates a series of steps for determining how to set the instruction associated with a given address entry depending on the fusible data. [Figure 9] 1 illustrates a series of steps for performing a store-to-load forwarding. [Figure 10] 10A-10C schematically illustrate the use of a computer-readable medium for manufacturing an apparatus according to some exemplary embodiments. [Figure 11] 1A-1C are schematic illustrations of systems and chip-containing products according to some illustrative embodiments; DETAILED DESCRIPTION OF THE INVENTION

[0009] Before discussing the embodiments with reference to the accompanying drawings, the following embodiments will be described.

[0010] According to one exemplary configuration, an apparatus is provided that includes an allocation circuit configured to allocate store data in a store buffer, the store buffer including a data buffer and an address buffer. The data buffer is configured to hold data entries, each configured to hold a portion of the store data. In some examples, the store data is divided N times to form N equal-sized portions. For example, if the store data includes two portions, the store data may be held by two data entries. The address buffer includes address entries each indicating a memory address where the store data is to be stored. For example, the memory addresses may be specified by a store instruction executed by the data processing circuit. In examples in which the store data is stored across a range of memory addresses, the memory address indicated by the address entry may define a start address or an end address of the range of memory addresses. It will therefore be understood that a given address entry may correspond to store data held by up to N data entries. To track this correspondence, a given address entry is associated with a set of N instructions that identify one or more data entries that include the store data.

[0011] For example, when the store buffer is heavily used due to a high frequency of store operations being performed, it is possible for the data buffer to be filled with a portion of the store data while the address buffer still has available capacity. Thus, the capacity of the data buffer presents a bottleneck that prevents more store data from being allocated. One approach to eliminating this bottleneck is to simply increase the size of the data buffer, for example, by a factor of N, so that the data buffer and address buffer are filled proportionally. However, such an approach increases power consumption and the required circuit area.

[0012] According to this technique, in response to a determination that a plurality (M) of N parts of the stored data contain duplicate data, the assignment circuit sets M instructions for identifying a given data entry (i.e., one data entry) that holds the duplicate data. Using an example where the stored data contains two parts as described above (i.e., N = 2), if both parts are identical (i.e., M = 2), a given data entry that holds one part is identified by both instructions associated with a given address entry. Thus, both parts of the stored data can be represented in the data buffer using one entry instead of two entries, and thus, the capacity of the data buffer can be effectively increased by only one, without incurring the hardware cost of implementing a buffer with a higher capacity.

[0013] It will be understood that the examples of N and M given above are merely examples and that they can take on any value such that 1 < M ≤ N. In fact, as the values of N and M are higher, a larger number of parts can be represented by a given data entry, resulting in a larger effective increase in the capacity of the data buffer. For example, when N = M = 8, all eight parts can be represented by one data entry, thereby effectively increasing the capacity of the data buffer by only seven entries.

[0014] Since all parts of the duplicate data can be represented by a single data entry, it is not necessary to hold all N parts within an individual data entry. Thus, in some examples, the assignment circuit is configured to prevent data entries other than a given data entry from holding duplicate data. Thus, the data buffer stores only one instance of the duplicate data so that the remaining capacity of the data buffer can be used for stored data of other store operations.

[0015] The existence of the M overlapping portions may be determined in a variety of different ways. In some examples, a data processing instruction of a predetermined type is expected to cause a store operation that specifies store data having overlapping portions. Accordingly, the apparatus may include a determination circuit for determining that the M portions include overlapping data in response to detecting that the store data is specified by an instruction of the predetermined type. The determination circuit may detect the data processing instruction by receiving a signal from an instruction decode circuit in the data processing apparatus.

[0016] In some examples, the predetermined type of data processing instruction is a memory set instruction that causes a specified block of memory to be set to a repeating set value or pattern of values. Thus, the store data will contain duplicate data in the form of the repeating set value or pattern of values. Several variations of memory set instructions may exist depending on the instruction set architecture supported by the device, including prologue, main, and epilogue variations that are expected to be executed sequentially. A prologue memory set instruction causes operations to be performed to set an initial block of memory to the set value up to an alignment boundary in memory. A main memory set instruction then causes operations to be performed to set intermediate blocks of memory to the set value, repeating as many times as necessary. An epilogue memory set instruction then causes operations to be performed to set a final block of memory to the set value, thereby completing the memory set. In such examples, any one or more of a prologue instruction, a main instruction, or an epilogue instruction may be considered a predetermined type of instruction according to the present technology.

[0017] A more convenient approach to detecting the M duplicate portions is to compare each of the N portions with one another before allocation to the store buffer. Accordingly, some examples of the apparatus may include a comparison circuit configured to compare two or more of the N portions before allocation and identify whether the M portions contain duplicate data. Thus, the M portions may be identified as containing duplicate data independent of any type of instruction. It will be understood that some examples may include either the comparison circuit or the determination circuit described above, while other examples may include both.

[0018] In some examples, a store operation may specify store data in predefined units that the memory system is configured to process. In particular, a memory system that implements one or more data caches may process data movement between the cache and main memory in units of cache lines. It will be understood that the amount of data contained in a cache line varies by implementation. N portions, and by extension, data entries in a data buffer, then correspond to a fixed amount of cache lines.

[0019] In a particular example, the N portions correspond to 1 / N of a cache line. Using the example above where N=2, a data entry in the data buffer would therefore be configured to hold half a cache line.

[0020] In some examples, the store buffer may support store buffer merging, such that store data specified by an older store operation is overwritten (partially or entirely) by store data specified by a newer store operation. This allows the memory system to be correctly updated with fewer accesses. It will be appreciated that, in order to perform merging, the N portions are preferably held by separate data entries rather than represented by a single data entry in accordance with the present technique. In particular, this is so that the store buffer can identify which portions of the older store data should be overwritten by the newer store data portions. If the M portions are represented by a single entry as described above, the individual portions may not be separated and overwritten for purposes of merging. To solve this problem, the device in such examples includes a merge circuit configured to identify whether the M portions can be merged with further store data (e.g., store data already present in the data buffer). In response to identifying that the M portions can be merged, the merge circuit is configured to cause the allocation circuit to set M instructions to identify different data entries, each of which stores one of the M portions. In such instances, the merge circuitry may override the allocation circuitry to disable the optimizations provided by the present techniques in favor of facilitating store buffer merging.

[0021] For the above purposes, the merge circuitry may therefore monitor the address entries assigned to the address buffer to detect when two address entries point to the same memory address.

[0022] In some examples, the store buffer may support store-load forwarding, such that the store buffer can return store data in response to a load operation that specifies a memory address indicated in one of the address entries. In particular, because the most recent data is in the store buffer due to the store operation that precedes the load operation, it is more efficient to retrieve the store data from the store buffer rather than waiting for the store buffer to write the data to memory and then refetching the data from memory. Thus, the device may include forwarding circuitry configured to retrieve store data based on N instructions associated with a given address entry in response to a load operation that specifies the same memory address. Because the present technique still provides N instructions, the forwarding circuitry can reconstruct the store data by duplicating the duplicate data M times to reconstruct all N portions of the store data.

[0023] According to another exemplary configuration, a method is provided that includes allocating store data in a store buffer, the store data including N portions, where N>1; maintaining data entries, each data entry configured to hold one of the N portions of the store data; maintaining address entries, a given address entry indicating a memory address where the store data is to be stored and associated with N instructions that identify one or more of the data entries that include the store data; and in response to a determination that M portions of the N portions of the store data each include duplicate data, setting M of the N instructions to identify the given data entry that holds the duplicate data.

[0024] According to another exemplary configuration, a non-transitory computer-readable medium storing computer-readable code for fabricating an apparatus is provided, the non-transitory computer-readable medium comprising: an allocation circuit configured to allocate store data in a store buffer, the store data including N portions, where N>1; the store buffer comprising: a data buffer configured to hold data entries, each data entry configured to hold one of the N portions of the store data; and an address buffer configured to hold address entries, a given address entry indicating a memory address where the store data should be stored and associated with N instructions that identify one or more of the data entries that include the store data; and in response to determining that M portions of the N portions of the store data each include duplicate data, the allocation circuit sets M of the N instructions to identify the given data entry that holds the duplicate data.

[0025] Specific embodiments will now be described with reference to the drawings.

[0026] 1 illustrates schematically an example of a data processing apparatus 2 (e.g., a CPU or GPU) comprising processing circuitry 4 for performing data processing operations in response to instructions decoded by an instruction decoder 6. The instructions decoded by the instruction decoder 6 are fetched from a cache or memory by instruction fetch circuitry 8.

[0027] Based on the decoded instruction, the instruction decoder 6 generates control signals for controlling the processing circuitry 4 to perform the data processing operation represented by the instruction. Operands for the data processing operation are obtained from registers (selected as source registers) in a register file 10, which includes a specific number of registers. The results of the operation are written back to the registers 10 (selected as destination registers) by the processing circuitry 4. For load / store instructions that request that data from a cache or memory be loaded into the registers 10, or that data in the registers 10 be stored into the cache or memory, the load / store unit 12 may be instructed to perform the load / store operation. When performing a store operation, the load / store unit 12 may receive the store data from the registers 10 and the memory address where the store data is to be stored in memory. It will be understood that FIG. 1 is a simplified example of a CPU or GPU 2, and that a CPU or GPU may include many other elements that are not shown in FIG. 1 for the sake of brevity.

[0028] The load / store unit 12 corresponds to an example of an apparatus defined in the appended claims. FIG. 2 illustrates an example of the load / store unit 12 in more detail. In particular, the load / store unit 12 includes an allocation circuit 14 for allocating store data received from the register 10 to a store buffer 16. The store buffer 16 includes a data buffer 18 configured to hold multiple data entries for temporarily holding portions of the store data. The store data is divided into N portions, where N depends on the size of the store data and the capacity of each data entry. For example, if the store data is equivalent to one cache line, e.g., 64 bytes, handled by the data cache and each entry in the data buffer is configured to store 32 bytes, then N=2. The store buffer 16 further includes an address buffer 20 configured to hold memory addresses where the store data is to be written to memory. Each address entry is associated with a set of N data pointers that identify data entries containing portions of the store data. Thus, when writing data to memory, the load / store unit 12 uses the data entries to construct the store data to be communicated to the memory system.

[0029] According to the present technique, the load / store unit 12 includes a comparison circuit 22 and / or a determination circuit 24 for determining whether any two or more (hereinafter, M) of the N portions contain duplicate (i.e., identical) data. If so, the allocation circuit responds by setting the corresponding M data pointers to identify the same data entry in the data buffer 18. Thus, fewer data entries are required to represent the store data in the data buffer 18. This effect is illustrated in the comparative example below.

[0030] 3A shows an example of store data 30 being written to memory address 0x20. Store data 30 may have been generated in register 10 by performing one or more data processing operations before the store instruction was executed by processing circuitry 4. In this example, store data 30 includes four portions (i.e., N=4) that specify data values ​​“a,” “b,” “a,” and “c,” respectively. Using the previous example in which store data 30 corresponds to a cache line of a data cache, store data 30 may have a total size of 32 bytes (i.e., each portion is 8 bytes). Thus, a memory address may define the starting address of the cache line in memory such that “a” is written to 0x20, “b” is written to 0x28, “a” is written to 0x30, and “c” is written to 0x38.

[0031] 3B illustrates one approach for assigning store data 30 and memory addresses to data buffer 18 and address buffer 20, respectively. Memory addresses are held by address entries in address buffer 20, and each portion of store data is held in a data entry in data buffer 18. In this approach, four data entries are required to store store data 30. The arrows represent data pointers associated with the address entries to identify the data entry containing the portion of store data 30 to be stored at address 0x20. In the approach of FIG. 3B, each entry in address buffer 20 corresponds to four entries in data buffer 18; therefore, it can be seen that data buffer 18 can fill up quickly when large amounts of data are being stored, for example, due to frequent execution of store instructions.

[0032] FIG. 3C illustrates an approach according to the present technique that allows information to be compressed within data buffer 18, thus increasing the available capacity of data buffer 18. Allocation circuit 14 responds to a determination that identifies two of the portions of store data 30 as specifying data value “a” (i.e., M=2). This determination may be performed, for example, by comparison circuit 22, which receives store data 30 and compares each portion with each other before allocation. In this example, data value “a” is therefore identified as duplicate data when the first and third portions are compared by comparison circuit 22. Memory addresses are held by address entries, as described above, but here allocation circuit 14 prevents two or more data entries from holding duplicate data value “a.” Furthermore, allocation circuit 14 sets two of the data pointers associated with the address entries to identify the same data entry containing “a.” Thus, when reconstructing store data 30 for writing to the memory system, store buffer 16 can reference the pointers to identify that data value “a” exists twice in store data 30. Using this approach, the four portions of store data 30 in this example can be represented in data buffer 18 using only three entries, thus leaving entries available to store further store data.

[0033] It will be appreciated that the values ​​of N and M are not limited to those used in the examples of Figures 3A-3C. Furthermore, in some examples, for example, if store data specifies data values ​​"a," "b," "a," and "b," there may be multiple different instances of duplicate data, and the present techniques may be applied to each instance of the duplicate data such that data buffer 18 has one data entry that holds "a" and one data entry that holds "b," with the data pointer identifying each data entry twice.

[0034] It will also be appreciated that the amount by which store data can be compressed within data buffer 18 increases as more portions of the store data contain duplicate data (i.e., as M increases). In some examples, store data may contain completely duplicate data, for example, during execution of certain types of instructions, such as memory set instructions, where multiple store operations are performed across a block of memory to set the block to a repeating data value or a repeating pattern of data values. FIG. 4A illustrates such an example in which two store operations are performed consecutively. The first operation specifies store data 40 to be stored at memory address 0x20. The second operation specifies store data 45 to be stored at memory address 0x40. Using the above example in which the store data corresponds to a 32-byte cache line, these operations therefore define store data for adjacent cache lines. Store data 40, 45 each include four portions, as in the previous example (i.e., N=4), with each portion including a repeating data value "a."

[0035] 4B shows an approach in which no optimization is used. Memory address 0x20 is stored in address buffer 20 as described above, and portions of store data 40 are stored in data entries in data buffer 18. The data pointers associated with address entry 0x20 point to each of the four data entries that contain store data 40. At this time, data buffer 18 is full, so store data 45 cannot be stored in data buffer 18, creating a bottleneck for the store operation.

[0036] FIG. 4C illustrates an approach according to the present technology. It can be determined that four portions of store data 40 specify the data value “a” (i.e., M=4). This can be performed using comparison circuit 22 as described above. Alternatively, or additionally, this determination can be performed based on the type of instruction that specified store data 40. As described above, when memory set instructions are executed, it is expected that repetitive patterns of data values ​​will occur. Therefore, decision circuit 24 can be provided to receive a signal from decoder circuit 16 when a memory set instruction is first encountered. Decision circuit 24 then controls allocation circuit 14 to allocate store data 40 in which “a” is identified as duplicate data to store buffer 16 without requiring a comparison between portions of store data 40. When allocating store data 40, allocation circuit 14 prevents two or more data entries from holding duplicate data value “a” as described above and sets all four data pointers associated with memory address 0x20 to point to the same data entry containing “a.” Thus, all four portions of store data 40 can be represented using only one data entry, thus leaving three entries available to hold further store data. The same determination can then be performed on store data 45, which also includes four portions that specify the data value "a." Thus, the same technique is applied to assign store data 45 to a store buffer so that all four data pointers associated with memory address 0x40 point to the same data entry containing "a."

[0037] 5 illustrates a series of steps that may be performed by allocation circuit 14 when allocating store data to a store buffer in accordance with the present technique. At step 50, store data is received for allocation to store buffer 16. At step 52, a determination is made to identify whether any two or more portions of the store data contain duplicate data. As discussed above, this may be performed using, for example, comparison circuit 22 or determination circuit 24. If two or more portions contain duplicate data, at step 54, allocation circuit 14 sets a corresponding number of indicators to identify the same data entries in data buffer 18. Thus, these two or more portions can be represented in data buffer 18 using only one data entry. If all portions of the store data contain unique data (i.e., there is no duplicate data), at step 56, corresponding indicators are set to identify different entries in the data buffer.

[0038] Apparatus incorporating the present technology may be combined with other methods of improving the performance of store buffer 16. FIG. 6 illustrates another example of load / store unit 12 that may include features similar to those of load / store unit 12 of FIG. 2. In this example, load / store unit 12 further includes merge circuitry 60 for supporting store buffer merging. In particular, merge circuitry 60 is configured to monitor memory addresses specified by store operations received by load / store unit 12 and respond to store operations that specify store data for memory addresses already pending in address buffer 20. In such a scenario, instead of writing first store data and then overwriting it with second store data, the store data can be merged such that the merged data can be written to the memory system in a single access.

[0039] FIG. 7 illustrates how a store buffer merge can be performed using first store data 70 and second store data 72, both of which are directed to the same memory address 0x20. The first store data 70 includes four portions, the first two of which contain duplicate data “a,” and the last two of which are null. The null portions can occur, for example, when the store data 70 corresponds to a cache line, but only a portion of the cache line has been updated with new data. Thus, the store data 70 is padded with null portions so that the store data 70 can still be processed with respect to the cache line, even though half of the cache line does not contain new data. The second store data includes a null portion, followed by data values ​​“c,” “d,” and “e.” Thus, it can be seen that merged store data 74 can be formed by overwriting portions of the first store data 70 with corresponding portions of the second store data 72. In particular, writing the merged store data 74 to memory is equivalent to writing the first store data 70 followed by the second store data 72, but with fewer memory accesses.

[0040] Because merging is based on identifying corresponding positions between individual portions of store data 70, 72, merging may be performed more efficiently when first store data 70 is held in different data entries in store buffer 18 (i.e., as described with reference to FIG. 3B or 4B ). Then, when second store data 72 is allocated to data buffer 18, it may overwrite portions of first store data 70, if necessary, to generate merged store data 74. Accordingly, merge circuit 60 is configured to generate an override signal to allocation circuit 14 to disable the compression techniques described with reference to FIG. 3C or 4C above in favor of improving performance for performing store buffer merging.

[0041] FIG. 8 illustrates a series of steps that may be performed by the allocation circuit 14 and the merge circuit 60. At step 80, store data is received for allocation within the store buffer. At step 82, it is determined, using, for example, the comparison circuit 22 or the decision circuit 24 described above, whether any two or more portions contain duplicate data. If each portion of the store data contains unique data (i.e., there is no duplicate data), at step 84, the allocation circuit 14 sets corresponding instructions to point to different data entries in the data buffer 18. However, if there is a portion of the store data that contains duplicate data, the merge circuit 60 determines, at step 86, whether the store data can be merged with further store data specified by another store operation. For example, the merge circuit 60 may monitor a queue of operations to be performed by the processing circuit 4 to identify any store operations directed to the same memory address as the store data received at step 80. If so, it is preferable to retain portions of the individual data entries within the data buffer 18 to enable store buffer merging. Accordingly, at step 84, the allocation circuit sets corresponding instructions as if that portion did not contain duplicate data. If the store data cannot be merged with further store data specified by another store operation, then in step 88 a corresponding instruction is set to identify the same data entry in data buffer 18. Thus, the store data can be represented using fewer entries in data buffer 18, as described in the previous example.

[0042] Returning to FIG. 6 , the load / store unit may also include forwarding circuitry 62 to support store-to-load forwarding. In particular, if a load operation is received while store data directed to the same memory address is held in store buffer 16, load / store unit 12 may reconstruct the store data returned in response to the load operation from the store buffer. Thus, the most current data is provided to the load operation faster than refetching the data from memory after it has been written. Therefore, forwarding circuitry 62 is configured to reconstruct store data distributed across one or more data entries in data buffer 18. In accordance with the present technique, for any portions represented by a single data entry in data buffer 18, forwarding circuitry 62 replicates those portions M times to reconstruct the original store data.

[0043] FIG. 9 illustrates a series of steps that may be performed by allocation circuit 14 and forwarding circuit 62. In step 90, allocation circuit 16 allocates a store buffer to store buffer 16, as described in the previous example. In step 92, while the store data is still in store buffer 16 (i.e., the store data has not yet been written to memory), a load operation is received that targets the same memory address of the store data. For example, forwarding circuit 62 may perform a lookup in address buffer 20 based on the memory address specified by the load operation. If there is a hit, forwarding circuit 62 may use the associated instruction (i.e., the data pointer of FIG. 6) to locate the corresponding data entry. In step 96, forwarding circuit 62 identifies whether any of the portions contained duplicate data by detecting that M instructions identified the same data entry in data buffer 18. If so, then in step 98, transfer circuitry 62 replicates the duplicated portion M times to reconstruct the original store before returning the reconstructed store data, e.g., to processing circuitry 4, in response to the load operation in step 100. If in step 96 no portion of the store data contained duplicate data, then the replication in step 98 is not necessary and in step 100 the reconstructed data can be returned immediately in response to the load operation.

[0044] 10 illustrates an example of the concepts described herein embodied in computer readable code 202 for fabricating an apparatus 204 that embodies the concepts described. For example, the computer readable code 202 may be used in one or more stages of a semiconductor design and fabrication process, including an Electronic Design Automation (EDA) stage, to fabricate an integrated circuit that includes an apparatus 204 that embodies the concepts. Such computer readable code may additionally or alternatively enable definition, modeling, simulation, verification, and / or testing of an apparatus 204 that embodies the concepts described herein.

[0045] For example, computer-readable code 202 for producing device 204 embodying the concepts described herein may be embodied in code defining a Hardware Description Language (HDL) representation of the concept. For example, code 202 may define a Register-Transfer-Level (RTL) abstraction of one or more logic circuits to define device 204 embodying the concept. Code 202 may define an HDL representation of one or more logic circuits embodying device 204 in intermediate representations such as Verilog, SystemVerilog, Chisel, or Very High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) and FIRRTL. Computer-readable code 202 may provide a definition embodying the concept using system-level modeling languages ​​such as SystemC and SystemVerilog or other behavioral representations of the concept that can be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concept.

[0046] Additionally or alternatively, computer readable code 202 may define a low-level description of integrated circuit components embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer readable representations of the integrated circuit components may be generated by applying one or more logic synthesis processes to the RTL representations to generate definitions used to fabricate devices embodying the invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from computer readable code 202 that is loaded into a Field Programmable Gate Array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for concept verification and testing purposes prior to fabrication in an integrated circuit, or the FPGA may be deployed directly into a product.

[0047] Computer readable code 202 may include a mixture of code representations for fabrication of device 204, including, for example, a mixture of one or more of an RTL representation, a netlist representation, or another computer readable definition used in a semiconductor design and fabrication process to fabricate device 204 (or indeed just any component of device 204) embodying the present invention. Alternatively or additionally, a concept may be defined in a combination of a computer readable definition used in a semiconductor design and fabrication process to fabricate device 204 and computer readable code 202 that defines instructions to be executed by the defined device once fabricated.

[0048] Such computer readable code may be disposed on any known transitory computer readable medium 200 (such as wired or wireless transmission of code over a network) or non-transitory computer readable medium 200, such as a semiconductor, magnetic disk, or optical disk. An integrated circuit fabricated using computer readable code 202 may include one or more components such as a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that individually or collectively embody concepts.

[0049] The concepts described herein may be embodied in a system comprising at least one packaged chip. The aforementioned devices are implemented within at least one packaged chip (either within one particular chip of the system or distributed across two or more packaged chips). At least one packaged chip is assembled on a substrate together with at least one system component. A chip-containing product may comprise a system assembled on a further substrate together with at least one other product component. The system or chip-containing product may be assembled within a housing or on a structural support (such as a frame or blade).

[0050] 11 , one or more packaged chips 400 having the above-described devices implemented on a single chip or distributed across two or more chips are manufactured by a semiconductor chip manufacturer. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer may be provided as a semiconductor package comprising a protective casing (e.g., made of metal, plastic, glass, or ceramic) that includes a semiconductor device implementing the above-described devices and connectors, such as lands, balls, or pins, for connecting the semiconductor device to the external environment. When two or more chips 400 are provided, they may be provided as separate integrated circuits (provided in separate packages) or may be packaged by a semiconductor provider into a multi-chip semiconductor package (e.g., by using an interposer or using three-dimensional integration to provide a multi-layer chip product with two or more vertically stacked integrated circuit layers).

[0051] In some examples, a collection of chiplets (i.e., small modular chips with a particular function) may itself be referred to as a chip. Chiplets may be individually packaged within a semiconductor package and / or packaged together with other chiplets into a multi-chiplet semiconductor package (e.g., using an interposer or using three-dimensional integration to provide a multi-layer chiplet product with two or more vertically stacked integrated circuit layers).

[0052] One or more packaged chips 400 are assembled on a substrate 402 along with at least one system component 404 to provide a system 406. For example, the substrate may include a printed circuit board. The substrate substrate may be made of any of a variety of materials, such as plastic, glass, ceramic, or a flexible substrate material such as paper, plastic, or a woven material. The at least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, the at least one system component 404 may include, for example, any one or more of the following: another packaged chip (e.g., provided by a different manufacturer or produced on a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0053] A chip-containing product 416 is produced that includes a system 406 (including a substrate 402, one or more chips 400, and at least one system component 404) and one or more product components 412. The product component 412 includes one or more additional components that are not part of the system 406. As a non-exhaustive list of examples, the one or more product components 412 may include user input / output devices such as keypads, touchscreens, microphones, loudspeakers, display screens, haptic devices, wireless communication transmitters / receivers, sensors, actuators for actuating mechanical movement, thermal control devices, additional packaged chips, interface modules, resistors, capacitors, inductors, transformers, diodes, and / or transistors. The system 406 and one or more product components 412 may be assembled on an additional substrate 414.

[0054] Substrate 402 or further substrate 414 may be provided on or within a device housing or other structural support (e.g., a frame or blade) to provide a product that can be handled by a user and / or is intended for operational use by a person or business.

[0055] System 406 or chip-containing product 416 may be at least one of an end-user product, a machine, a medical device, a computing or telecommunications infrastructure product, or an automation control system. For example, and this non-exhaustive list of examples, the chip-containing product may be any of the following: a telecommunications device, a mobile phone, a tablet, a laptop, a computer, a server (e.g., a rack server or a blade server), an infrastructure device, networking equipment, a vehicle or other automotive product, industrial machinery, a consumer device, a smart card, a credit card, smart glasses, an avionics device, a robotics device, a camera, a television, a smart television, a DVD player, a set-top box, a wearable device, a home appliance, a smart meter, a medical device, a heating / lighting control device, a sensor, and / or a control system for controlling public infrastructure equipment such as a smart highway or traffic light.

[0056] In a brief general overview, an apparatus, system, method, computer-readable medium, and computer code are disclosed. The apparatus includes an allocation circuit configured to allocate store data including N portions to a store buffer. The store buffer includes: a data buffer configured to hold data entries, each data entry configured to hold one of the N portions of the store data; and an address buffer configured to hold address entries, each address entry indicating a memory address where the store data should be stored and associated with N instructions identifying one or more of the data entries that include the store data. In response to determining that M of the N portions of the store data each include duplicate data, the allocation circuit sets M of the N instructions to identify the given data entry that holds the duplicate data.

[0057] In this application, the term "configured to" is used to mean that elements of a device have a configuration that allows them to perform a defined operation. In this context, "configuration" refers to the arrangement or interconnection of hardware or software. For example, a device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be modified in any way to provide the defined operation.

[0058] Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and that various changes, additions, and modifications can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, various combinations of the features of the following dependent claims can be made with the features of the independent claims without departing from the scope of the invention.

Claims

1. 1. An apparatus comprising: an allocation circuit configured to allocate store data in a store buffer, the store data comprising N portions, N>1; The store buffer a data buffer configured to hold data entries, each data entry configured to hold one of the N portions of the store data; an address buffer configured to hold address entries, a given address entry indicating a memory address where the store datum is to be stored, and associated with N instructions identifying one or more of the data entries containing the store datum; wherein the allocation circuitry, in response to determining that M of the N portions of the store data each include duplicate data, sets M of the N instructions to identify a given data entry that holds the duplicate data.

2. 2. The apparatus of claim 1, wherein in response to the determination that the M portions contain the duplicate data, the allocation circuitry is configured to prevent data entries other than the given data entry from holding the duplicate data.

3. 3. The apparatus of claim 1, further comprising a determination circuit configured to determine that each of the M portions includes the duplicate data in response to detecting that the store data is specified by a data processing instruction of a predetermined type.

4. 4. The apparatus of claim 3, wherein the predetermined type of instruction is a memory set instruction.

5. 5. The apparatus of claim 1, further comprising a comparison circuit configured to compare two or more of the N portions prior to allocation to identify whether the M portions contain the duplicate data.

6. 6. The apparatus of claim 1, wherein each of the N portions corresponds to a fixed amount of cache lines to be stored in a data cache.

7. 7. The apparatus of claim 6, wherein each of the N portions corresponds to 1 / N of the cache line.

8. a merging circuit configured to identify whether the M portions can be merged with further store data; 8. The apparatus of claim 1, wherein in response to identifying that the M portions can be merged with the further store data, the merging circuitry is configured to cause the allocating circuitry to set the M instructions to identify different data entries each storing one of the M portions.

9. a further address entry indicating a memory address where the further store data should be stored; 9. The apparatus of claim 8, wherein the merge circuitry is configured to identify that the M portions may be merged with further store data in response to the given address entry and the further address entry indicating the same memory address.

10. 10. The apparatus of claim 1, further comprising: a forwarding circuit configured to retrieve the N portions of store data based on the N instructions and to replicate the M portions to reconstruct the store data in response to a load operation specifying the memory address.

11. 11. The apparatus of claim 1, wherein M>1.

12. 1. A system comprising: The device according to any one of claims 1 to 11 implemented in at least one packaged chip; at least one system component; a substrate, The at least one packaged chip and the at least one system component are assembled on the substrate.

13. 13. A chip-containing product comprising the system of claim 12, the system assembled on a further substrate having at least one other product component.

14. 1. A method comprising: allocating store data in a store buffer, said store data comprising N portions, where N>1; maintaining data entries, each data entry configured to hold one of the N portions of the store data; maintaining address entries, where a given address entry indicates a memory address where the store data is to be stored, and associated with N instructions identifying one or more of the data entries containing the store data; and in response to determining that M of the N portions of the store data each contain duplicate data, setting M of the N instructions to identify a given data entry that holds the duplicate data.

15. 1. A non-transitory computer readable medium for storing computer readable code for fabricating an apparatus, comprising: an allocation circuit configured to allocate store data in a store buffer, the store data comprising N portions, N>1; The store buffer a data buffer configured to hold data entries, each data entry configured to hold one of the N portions of the store data; an address buffer configured to hold address entries, a given address entry indicating a memory address where the store datum is to be stored, and associated with N instructions identifying one or more of the data entries containing the store datum; the allocation circuit, in response to determining that M of the N portions of the store data each include duplicate data, sets M of the N instructions to identify a given data entry that holds the duplicate data.

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