Semiconductor device

Abstract

To provide a semiconductor device capable of transmitting data at high speed and having a reduced circuit area.SOLUTION: The semiconductor device includes a layer having two surfaces facing each other, a semiconductor chip, and an external terminal. The semiconductor chip is provided on one surface side of the layer, and the external terminal is provided in a region not overlapping at least the semiconductor chip on the other surface side of the layer. The semiconductor chip has a first circuit including a first transistor, and the layer has a second circuit including a second transistor. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the external terminal. The second transistor includes a metal oxide in a channel formation region. Note that the second circuit may be a CML circuit. An insulator may be provided above the one surface of the layer and on the side surface of the semiconductor chip.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] In recent years, the amount of data handled by electronic devices such as personal computers and display devices has been increasing. This is thought to be due to factors such as improved processing power of processors, increased storage capacity of storage devices, and the increasing resolution of display devices.

[0004] Furthermore, with improvements in processor processing power and increases in storage capacity of storage devices, there is a growing demand for faster data transmission. For example, even if a processor's processing power increases, if the amount of data transmitted is small, the overall processing time may increase. Furthermore, for example, if a storage device handles a large amount of data in a write or read operation, it may take a long time to transmit data input and output to the storage device. Patent Documents 1 and 2 disclose circuit configurations that use CML (current mode logic) circuits and enable high-speed data transmission. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-2408 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-50087 Summary of the Invention [Problem to be solved by the invention]

[0006] A CML circuit can be constructed using, for example, bipolar transistors or MOS transistors. However, for example, a CML circuit using bipolar transistors is difficult to form on the same substrate as a circuit using transistors other than bipolar transistors. Also, for example, a CML circuit using MOS transistors is difficult to form on the same substrate as a circuit using transistors other than MOS transistors.

[0007] Therefore, when the CML circuit and the other circuit are configured with different transistors, the CML circuit and the other circuit must be formed on different substrates. For example, when the CML circuit and the other circuit are mounted on a single printed circuit board, the area of ​​the printed circuit board increases, which may increase the manufacturing cost of the semiconductor device including the CML circuit and the other circuit.

[0008] Furthermore, even if the CML circuit and other circuits can be formed on the same substrate (e.g., a semiconductor wafer) using the same transistors, the circuit area may become large depending on the circuit scale. Even in this case, if the circuit area becomes large, the area required to form the circuit on the substrate increases, which may increase the manufacturing cost of a semiconductor device including the CML circuit and other circuits.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed data transmission.An object of one embodiment of the present invention is to provide a semiconductor device with a reduced circuit area.An object of one embodiment of the present invention is to provide a semiconductor device with reduced manufacturing costs.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0010] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0011] (1) One embodiment of the present invention is a semiconductor device including a layer having two surfaces, a semiconductor chip, and an external terminal. The semiconductor chip is provided on one surface of the layer, and the external terminal is provided on the other surface of the layer, at least in a region that does not overlap with the semiconductor chip. The semiconductor chip has a first circuit including a first transistor, and the layer has a second circuit including a second transistor. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the external terminal. The second transistor includes a metal oxide in a channel formation region.

[0012] (2) Alternatively, according to one embodiment of the present invention, in the above-described (1), the second circuit may be a CML circuit.

[0013] (3) Alternatively, in one embodiment of the present invention, in the above-described (1) or (2), an insulator may be provided above one surface of the layer and on a side surface of the semiconductor chip.

[0014] (4) Alternatively, in one aspect of the present invention, in any one of the above (1) to (3), the semiconductor chip may have connection terminals, and the first circuit and the second circuit may be electrically connected via the connection terminals. Also, it is preferable that the pitch width of the external terminals is larger than the pitch width of the connection terminals.

[0015] (5) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (4), the metal oxide may include indium, an element M (M is one or more elements selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0016] (6) Another embodiment of the present invention is an electronic device including the semiconductor device described in any one of (1) to (5) above and a housing.

[0017] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, an electronic component in which a chip is housed in a package, etc. are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0018] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0019] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0020] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0021] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0022] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0023] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0024] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, a "resistance element" is intended to include wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0025] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value greater than 0 F, a region of wiring having a capacitance value, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also a parasitic capacitance appearing between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0026] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0027] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0028] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0029] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0030] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0031] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0032] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0033] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0034] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0035] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" and / or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0036] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0037] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding hydrogen, and oxygen.

[0038] In this specification and the like, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0039] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0040] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0041] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0042] According to one embodiment of the present invention, a semiconductor device capable of high-speed data transmission can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a reduced circuit area can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced manufacturing costs can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0043] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0044] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 2] 2A and 2B are block diagrams showing configuration examples of a semiconductor device. [Figure 3] 3A to 3C are circuit diagrams showing examples of circuits included in a semiconductor device. [Figure 4] 4A to 4C are circuit diagrams showing examples of circuits included in a semiconductor device. [Figure 5] 5A to 5D are circuit diagrams showing examples of circuits included in a semiconductor device. [Figure 6] 6A to 6E are schematic cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 7] 7A to 7E are schematic cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 8] 8A to 8E are schematic cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 11] 11A to 11C are cross-sectional views showing examples of the structure of a transistor. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 13] FIG. 13A is a diagram illustrating the classification of IGZO crystal structures, FIG. 13B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 13C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 14] FIG. 14A is a perspective view showing an example of a semiconductor wafer, FIG. 14B is a perspective view showing an example of a die, FIGS. 14C and 14D are perspective views showing an example of a semiconductor device, and FIG. 14E is a perspective view showing an example of a mounting substrate. [Figure 15] FIG. 15 is a perspective view illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0045] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0046] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0047] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0048] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0049] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0050] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0051] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0052] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m,n]” may be added to the symbol.

[0053] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0054] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0055] <Configuration example of semiconductor device> 1 shows an example of a cross-sectional view of a semiconductor device having a Fan Out Wafer Level Package (FOWLP) configuration. The semiconductor device PSD includes, for example, a die SCD, a layer OSL, an insulator PR, and bumps HBL. The die SCD also includes a substrate BSA, a layer SIL, and connection terminals ET.

[0056] The die SCD may be a semiconductor chip cut out from a semiconductor wafer, as described in a fourth embodiment below. In this embodiment, in the die SCD, the layer SIL is formed on a substrate BSA. The layer SIL may include, for example, a switching circuit, a logic circuit, an analog circuit, etc. The analog circuit may include, for example, a signal conversion circuit, a potential level conversion circuit, an amplifier circuit, etc. The layer SIL may also include a memory device, an arithmetic circuit, etc.

[0057] The substrate BSA can be, for example, a semiconductor substrate made of silicon. By using a semiconductor substrate made of silicon as the substrate BSA, transistors containing silicon in their channel formation regions (hereinafter referred to as Si transistors) can be formed on the substrate BSA, and switching circuits, logic circuits, analog circuits, etc. included in the layer SIL can be configured with Si transistors.

[0058] The substrate BSA may be, for example, a semiconductor substrate made of germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. The substrate BSA may also be a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.

[0059] Alternatively, the substrate BSA may be, for example, an insulating substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Alternatively, the substrate BSA may be, for example, a conductive substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. However, when an insulating substrate or a conductive substrate is used as the substrate BSA, unlike a semiconductor substrate, a channel formation region cannot be formed on the insulating substrate or the conductive substrate, and therefore, a transistor cannot be formed directly on the insulating substrate or the conductive substrate. Therefore, to form a transistor on the insulating substrate or the conductive substrate, a separate semiconductor film must be provided above the insulating substrate or the conductive substrate.

[0060] The die SCD is provided so that the connection terminals ET are in contact with the layer OSL. The connection terminals ET function as terminals for electrically connecting the circuit included in the die SCD and the wiring included in the layer OSL.

[0061] Furthermore, a bump HBL is provided on the surface of the layer OSL opposite to the surface on which the die SCD is provided. The layer OSL is provided with wiring for electrically connecting the circuit included in the die SCD to the bump HBL. Therefore, the layer OSL functions as a rewiring layer in the FOWLP.

[0062] In FIG. 1, the bumps HBL are illustrated as balls as an example. The bumps HBL can be formed using solder. In this way, the semiconductor device PSD has terminals of a BGA (Ball Grid Array). The terminals of the semiconductor device PSD are not limited to BGA. For example, the semiconductor device PSD may have terminals of an LGA (Land Grid Array), a PGA (Pin Grid Array), or the like, instead of a BGA.

[0063] Furthermore, by providing the bumps HBL in a region of the layer OSL that does not overlap with the die SCD, the connection terminals ET can be extended to the outside of the die SCD. Therefore, it is preferable to provide the bumps HBL at least in a region of the layer OSL that does not overlap with the die SCD, and it is also preferable to provide the bumps HBL in a region of the layer OSL that overlaps with the die SCD. Furthermore, by providing the bumps HBL in a region of the layer OSL that does not overlap with the die SCD, the pitch width of the bumps HBL can be made larger than the pitch width of the connection terminals ET of the die SCD.

[0064] The layer OSL also includes a transistor OTr. The transistor OTr may be, for example, an OS transistor. The channel formation region of the OS transistor is preferably an oxide containing at least one of indium, gallium, and zinc. Alternatively, an oxide containing at least one of indium, an element M (e.g., aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) and zinc may be used instead of the oxide. The OS transistor more preferably has the structure of the transistor described in Embodiment 2.

[0065] Furthermore, by providing the transistor OTr in the layer OSL, which is a redistribution layer, a desired circuit can be configured in the redistribution layer. That is, for example, the layer OSL may have a circuit including the transistor OTr.

[0066] In the semiconductor device PSD of Fig. 1, the die SCD and the layer OSL are bonded together so as to be electrically connected to each other. Specifically, the die SCD and the layer OSL are bonded together so as to be in contact with each other. The electrical connection terminals included in the die SCD and the electrical connection terminals included in the layer OSL are, for example, conductors and wiring. A method for electrically connecting the circuit formed on the die SCD to the rewiring layer of the layer OSL will be described later.

[0067] An insulator PR is provided as a sealing material on the die SCD and the layer OSL. The insulator PR functions as a protective layer to prevent electrostatic breakdown of the die SCD and as a sealing material to prevent external components from entering the die SCD.

[0068] As the insulator PR, for example, an organic resin layer such as an epoxy resin can be used.

[0069] Here, as a specific example, a configuration example of a circuit included in the semiconductor device PSD of FIG. 1 is shown in the block diagram of FIG. 2A. In the semiconductor device PSD of FIG. 2A, as an example, the layer SIL has a circuit SIC, and the layer OSL has a circuit OSC. The circuit SIC or the circuit OSC may include, for example, a switching circuit, a logic circuit, an analog circuit, etc. Also, in the semiconductor device PSD of FIG. 2A, as an example, the circuit SIC is electrically connected to the circuit OSC, and the circuit OSC is electrically connected to an external terminal EXT1. Here, the external terminal EXT1 corresponds to, for example, the bump HBL shown in the semiconductor device PSD of FIG. 1. Note that, as shown in FIG. 2A, the circuit SIC may be electrically connected to the external terminal EXT2 without going through the circuit OSC. Here, the external terminal EXT2 corresponds to, for example, the bump HBL shown in the semiconductor device PSD of FIG. 1, similar to the external terminal EXT1.

[0070] In particular, in the semiconductor device PSD of FIG. 2A, as the circuit OSC, for example, a CML (Current Mode Logic) circuit may be included. The CML circuit is a signal transmission circuit using a small-amplitude differential transmission method utilizing a differential amplifier circuit, and realizes high-speed signal transmission. Further, the CML circuit has a function as an output buffer circuit in high-speed data communication, and can stabilize the level of the output signal via the CML circuit.

[0071] By providing a CML circuit in the layer OSL, signal transmission from the circuit SIC included in the layer SIL to the outside of the semiconductor device PSD1 and / or signal transmission from the outside of the semiconductor device PSD1 to the circuit SIC included in the layer SIL can be accelerated.

[0072] Incidentally, the semiconductor device of one aspect of the present invention is not limited to the configuration of the semiconductor device PSD shown in FIG. 2A. The semiconductor device of one aspect of the present invention may have, for example, a configuration shown in the block diagram of FIG. 2B. The semiconductor device PSD of FIG. 2B has the same circuit configuration as that of the semiconductor device PSD of FIG. 2A in that the layer SIL has the circuit SIC and the layer OSL has the circuit OSC, but is different from the circuit configuration of the semiconductor device PSD of FIG. 2A in that the circuit DEV is constituted by the circuit SIC and the circuit OSC. That is, the circuit OSC may be a part of the circuit that can constitute the circuit DEV in combination with the circuit SIC included in the layer SIL. Note that the circuit DEV can be, for example, a storage device, an arithmetic circuit, or the like. Further, as shown in FIG. 2B, similar to the semiconductor device PSD of FIG. 2A, the circuit SIC may be electrically connected to the external terminal EXT2 without passing through the circuit OSC.

[0073] <<Configuration Example of CML Circuit>> Here, a configuration example of the CML circuit that can be provided in the circuit OSC will be described.

[0074] [Oscillator] The circuit RGCM shown in FIG. 3A is a CML circuit that functions as an oscillator, and includes differential amplifier circuits CM[1] to CM[n+1] (where n is an even number equal to or greater than 4).

[0075] The circuit RGCM also has a terminal OCLN and a terminal OCLP, which function as output terminals of the circuit RGCM.

[0076] The inverting output terminal of the differential amplifier circuit CM[1] is electrically connected to the non-inverting input terminal of the differential amplifier circuit CM[2], and the non-inverting output terminal of the differential amplifier circuit CM[1] is electrically connected to the inverting input terminal of the differential amplifier circuit CM[2]. The inverting output terminal of the differential amplifier circuit CM[n-1] is electrically connected to the inverting input terminal of the differential amplifier circuit CM[n], and the non-inverting output terminal of the differential amplifier circuit CM[n-1] is electrically connected to the non-inverting input terminal of the differential amplifier circuit CM[2]. The inverting output terminal of the differential amplifier circuit CM[n] is electrically connected to the inverting input terminal of the differential amplifier circuit CM[n+1] and the non-inverting input terminal of the differential amplifier circuit CM1, and the non-inverting output terminal of the differential amplifier circuit CM[n] is electrically connected to the non-inverting input terminal of the differential amplifier circuit CM[n+1] and the inverting input terminal of the differential amplifier circuit CM[1]. Furthermore, the inverting input terminal of the differential amplifier circuit CM[n+1] is electrically connected to the terminal OCLN, and the non-inverting input terminal of the differential amplifier circuit CM[n+1] is electrically connected to the terminal OCLP.

[0077] 3A, an oscillator (ring oscillator) can be configured by coupling differential amplifier circuits CM[1] to CM[n] in a ring shape. Note that, in the configuration of this oscillator, between adjacent differential amplifier circuits, the non-inverting output terminal of one is electrically connected to the non-inverting input terminal of the other, and the inverting output terminal of one is electrically connected to the inverting input terminal of the other, and between the remaining adjacent differential amplifier circuits, the non-inverting output terminal of the preceding differential amplifier circuit is electrically connected to the inverting input terminal of the succeeding differential amplifier circuit, and the inverting output terminal of the preceding differential amplifier circuit is electrically connected to the non-inverting input terminal of the succeeding differential amplifier circuit.

[0078] 3A shows a configuration including the differential amplifier circuit CM[n+1], the circuit RGCM of Fig. 3A may be configured without the differential amplifier circuit CM[n+1]. For example, the circuit RGCM of Fig. 3A may be configured such that the inverting output terminal of the differential amplifier circuit CM[n] is electrically connected to the terminal OCLN, and the non-inverting output terminal of the differential amplifier circuit CM[n] is electrically connected to the terminal OCLP.

[0079] A differential amplifier circuit can operate at higher speeds than logic gates such as NAND circuits, AND circuits, and NOT circuits (inverter circuits). Furthermore, a differential amplifier circuit is also highly resistant to power supply noise. Therefore, the RGCM circuit shown in Figure 3A can be used as an oscillator, for example, in high-frequency circuits.

[0080] 3A, the number of differential amplifier circuits coupled in a ring shape is illustrated as an even number of four or more, but in some cases it may be two. Also, for example, when the number of differential amplifier circuits coupled in a ring shape is an odd number of three or more, the configuration of the circuit RGCM shown in FIG. 3B may be applied. The circuit RGCM in FIG. 3B is also a CML circuit that functions as an oscillator, and includes differential amplifier circuits CM[1] to CM[m+1] (where m is an odd number of three or more).

[0081] 3B shows a configuration including the differential amplifier circuit CM[m+1], the circuit RGCM of FIG. 3B may be configured without the differential amplifier circuit CM[m+1]. For example, the circuit RGCM of FIG. 3B may be configured such that the inverting output terminal of the differential amplifier circuit CM[m] is electrically connected to the terminal OCLN, and the non-inverting output terminal of the differential amplifier circuit CM[m] is electrically connected to the terminal OCLP.

[0082] [High-speed transmission circuit] The circuit HSTC shown in FIG. 3C is a CML circuit that functions as a high-speed transmission circuit, and includes a differential amplifier circuit CMA, a differential amplifier circuit CMB, a capacitance C1P, a capacitance C1N, a load LE2P, and a load LE2N.

[0083] The circuit HSTC also has terminals HIP, HIN, HON, and HOP. The terminals HIP and HIN function as input terminals of the circuit HSTC, and the terminals HON and HOP function as output terminals of the circuit HSTC.

[0084] The non-inverting input terminal of the differential amplifier circuit CMA is electrically connected to the terminal HIP, and the inverting input terminal of the differential amplifier circuit CMA is electrically connected to the terminal HIN. The inverting output terminal of the differential amplifier circuit CMA is electrically connected to the first terminal of the capacitor C1N, and the non-inverting output terminal of the differential amplifier circuit CMA is electrically connected to the first terminal of the capacitor C1P. The second terminal of the capacitor C1P is electrically connected to the first terminal of the load LE2P and the non-inverting input terminal of the differential amplifier circuit CMB, and the second terminal of the capacitor C1N is electrically connected to the first terminal of the load LE2N and the inverting input terminal of the differential amplifier circuit CMB. The inverting output terminal of the differential amplifier circuit CMB is electrically connected to the terminal HON, and the non-inverting output terminal of the differential amplifier circuit CMB is electrically connected to the terminal HOP. The second terminal of the load LE2P is electrically connected to the wiring VBL1, and the second terminal of the load LE2N is electrically connected to the wiring VBL2.

[0085] The wiring VBL1 and the wiring VBL2 function as wirings that apply a constant voltage. The constant voltage can be, for example, a positive potential, a negative potential, or a ground potential. The constant voltages applied by the wiring VBL1 and the wiring VBL2 may be equal to or different from each other.

[0086] The capacitors C1P and C1N function as DC blocking capacitors for AC coupling the differential amplifier circuits CMA and CMB.

[0087] The HSTC circuit shown in Figure 3C has a faster edge rate than the LVDS (Low Voltage Differential Signaling) circuit, which is also a high-speed transmission circuit. Also, the signal amplitude of the HSTC circuit can sometimes be higher than that of the LVDS circuit.

[0088] [Differential amplifier circuit] Next, a differential amplifier circuit applicable to the circuit RGCM and the circuit HSTC will be described. FIG. 4A shows a configuration example of a differential amplifier circuit applicable to the differential amplifier circuits CM[1] to CM[n+1] included in the circuit RGCM and the differential amplifier circuits CMA and CMB included in the circuit HSTC. The differential amplifier circuit CM shown in FIG. 4A includes, as an example, transistors DTrA and DTrB, loads LE1A and LE1B, and a current source CC. The differential amplifier circuit CM also includes terminals INP, INN, OUTP, and OUTN. In particular, the transistors DTrA and DTrB function as a differential pair.

[0089] In the differential amplifier circuit CM, the terminal INP corresponds to a non-inverting input terminal, the terminal INN corresponds to an inverting input terminal, the terminal OUTP corresponds to a non-inverting output terminal, and the terminal OUTN corresponds to an inverting output terminal.

[0090] The transistor DTrA and / or the transistor DTrB are provided as the above-mentioned transistor OTr, for example.

[0091] 4A includes a back gate, the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistors DTrA and DTrB shown in FIG. 4A may have a structure without a back gate, that is, single-gate transistors. Furthermore, some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0092] Furthermore, it is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors DTrA and DTrB are equal to each other. By making the transistor sizes equal to each other, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the sizes of the transistors DTrA and DTrB equal to each other, the transistors DTrA and DTrB can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the potentials of the source, drain, gate, etc. of the transistor DTrA and the potentials of the source, drain, gate, etc. of the transistor DTrB.

[0093] Unless otherwise specified, the on-state of each of the transistors DTrA and DTrB includes the case where they ultimately operate in the saturation region. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors include the case where they are appropriately biased to voltages within the range where they operate in the saturation region. However, one aspect of the present invention is not limited to this. For example, the on-state of the transistors DTrA and DTrB may operate in the linear region, or may operate in both the saturation region and the linear region.

[0094] The gate of the transistor DTrA is electrically connected to the terminal INP, and a first terminal of the transistor DTrA is electrically connected to a first terminal of the load LE1A and the terminal OUTP. The gate of the transistor DTrB is electrically connected to the terminal INN, and a first terminal of the transistor DTrB is electrically connected to a first terminal of the load LE1B and the terminal OUTN. The input terminal of the current source CC is electrically connected to the second terminal of the transistor DTrA and the second terminal of the transistor DTrB, and the output terminal of the current source CC is electrically connected to the wiring VSE. The second terminal of the load LE1A and the second terminal of the load LE1B are electrically connected to the wiring VDE.

[0095] The wiring VDE functions as, for example, a wiring that applies a constant voltage, which may be, for example, a high-level potential.

[0096] The wiring VSE functions as, for example, a wiring that applies a constant voltage, which may be, for example, a low-level potential or a ground potential (GND).

[0097] In FIG. 4A , the backgates of transistors DTrA and / or DTrB are illustrated, but the connection configuration of the backgates is not shown. However, the electrical connection of the backgates can be determined during the design stage. For example, in a transistor having a backgate, the gate and backgate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and backgate of transistor DTrA may be electrically connected, or the gate and backgate of transistor DTrB may be electrically connected. Furthermore, in a transistor having a backgate, for example, to change the threshold voltage of the transistor or reduce the off-state current of the transistor, wiring may be provided to electrically connect the backgate of the transistor to an external circuit or the like, and a potential may be applied to the backgate of the transistor from the external circuit or the like. Specifically, the differential amplifier circuit CM can be configured as shown in FIG. 4B . The differential amplifier circuit CM of FIG. 4B is configured such that wiring BGE1 is electrically connected to the backgates of transistors DTrA and DTrB included in the differential amplifier circuit CM of FIG. 4A. By applying a predetermined potential to the wiring BGE1, the threshold voltages of the transistors DTrA and DTrB can be varied.

[0098] In the differential amplifier circuit CM of Fig. 4B, a desired gain can be obtained by varying the threshold voltages of the transistors DTrA and DTrB. In addition, as shown in Fig. 1, the threshold voltages of the transistors DTrA and DTrB can be adjusted in a packaged semiconductor device PSD.

[0099] 4A illustrates n-channel transistors as the transistors DTrA and DTrB, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, some or all of the transistors DTrA and DTrB may be replaced with p-channel transistors.

[0100] The above-described modifications to the transistor structures and polarities are not limited to the transistors DTrA and DTrB. For example, the same modifications may be made to the structures and polarities of transistors described elsewhere in the specification or illustrated in other drawings.

[0101] The current source CC included in the differential amplifier circuit CM of Fig. 4A can have, for example, the circuit configuration shown in Fig. 4C. Note that Fig. 4C also illustrates the wiring VSE in order to show the connection configuration of the current source CC.

[0102] The current source CC shown in FIG. 4C includes, as an example, a transistor TrC.

[0103] The transistor TrC can be a transistor that can be used as the transistor DTrA or the transistor DTrB. For example, the transistor TrC can be an OS transistor that can be used as the transistor DTrA or the transistor DTrB.

[0104] Unless otherwise specified, the transistor TrC is considered to ultimately operate in the saturation region when it is on. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are considered to include a case where they are appropriately biased to voltages within the range in which they operate in the saturation region. For example, the transistor TrC may operate in the linear region when it is on, or may operate in both the saturation region and the linear region.

[0105] A first terminal of the transistor TrC is electrically connected to the input terminal of the current source CC, and a second terminal of the transistor TrC is electrically connected to the output terminal of the current source CC. In other words, when the current source CC of FIG. 4C is applied to the differential amplifier circuit CM of FIG. 4A, the first terminal of the transistor TrC is electrically connected to the second terminal of the transistor DTrA and the second terminal of the transistor DTrB. In addition, the gate of the transistor TrC is electrically connected to the wiring VAL.

[0106] The wiring VAL functions as, for example, a wiring that applies a constant voltage. In particular, the constant voltage may be set so that the gate-source voltage of the transistor TrC is higher than the threshold voltage of the transistor TrC.

[0107] The load LE1A and the load LE1B may be, for example, a resistor or a diode.

[0108] As an example, a circuit configuration in which the loads LE1A and LE1B are resistors is shown in Fig. 5A. The differential amplifier circuit CM1 shown in Fig. 5A has a circuit configuration in which resistors REA and REB are used as the loads LE1A and LE1B, respectively. A first terminal of the resistor REA is electrically connected to a first terminal of the transistor DTrA and the terminal OUTP, and a first terminal of the resistor REB is electrically connected to a first terminal of the transistor DTrB and the terminal OUTN. Furthermore, a second terminal of the resistor REA and a second terminal of the resistor REB are electrically connected to the wiring VDE.

[0109] As an example, FIG. 5B shows a circuit configuration in which the loads LE1A and LE1B are diodes. The differential amplifier circuit CM2 shown in FIG. 5B has a circuit configuration in which diodes DEA and DEB are used as the loads LE1A and LE1B, respectively. The output terminal of diode DEA is electrically connected to the first terminal of transistor DTrA and terminal OUTP, and the output terminal of diode DEB is electrically connected to the first terminal of transistor DTrB and terminal OUTN. The input terminal of diode DEA and the input terminal of diode DEB are electrically connected to wiring VDE.

[0110] The diodes DEA and DEB included in the differential amplifier circuit CM2 shown in FIG. 5B may be replaced with diode-connected transistors. The differential amplifier circuit CM2 shown in FIG. 5C has a circuit configuration in which transistors ITrA and ITrB are used as the diodes DEA and DEB, respectively. The first terminal of the transistor ITrA is electrically connected to the first terminal of the transistor DTrA and the terminal OUTP, and the first terminal of the transistor ITrB is electrically connected to the first terminal of the transistor DTrB and the terminal OUTN. The wiring VDE is electrically connected to the second terminal of the transistor ITrA, the gate of the transistor ITrA, the second terminal of the transistor ITrB, and the gate of the transistor ITrB.

[0111] The transistors ITrA and ITrB can be transistors applicable to the transistor DTrA or the transistor DTrB. For example, an OS transistor can be used as the transistor TrC.

[0112] Furthermore, as shown in FIG. 5C, transistors ITrA and ITrB may be transistors having back gates, similar to transistors DTrA and DTrB. Similarly to transistors DTrA and DTrB in the differential amplifier circuit CM of FIG. 4B, wiring for applying a potential may be electrically connected to the back gates of transistors ITrA and ITrB. Specifically, for example, the differential amplifier circuit CM2 of FIG. 5C may be configured, as in the differential amplifier circuit CM2 of FIG. 5D, with wiring BGE2 electrically connected to the back gates of transistors ITrA and ITrB. In FIG. 5D, applying a predetermined potential to wiring BGE2 can change the threshold voltages of transistors ITrA and ITrB. Note that the differential amplifier circuit CM2 of FIG. 5D has a configuration in which wiring BGE1 is electrically connected to the back gates of transistors DTrA and DTrB, similar to the configuration of the differential amplifier circuit CM of FIG. 4B.

[0113] In the differential amplifier circuit CM of Fig. 5D, a desired gain can be obtained by varying the threshold voltages of the transistors DTrA, DTrB, ITrA, and ITrB. In a packaged semiconductor device PSD, as shown in Fig. 1, the threshold voltages of the transistors DTrA, DTrB, ITrA, and ITrB can be adjusted.

[0114] <Semiconductor Device Fabrication Example 1> Next, an example of a method for manufacturing the semiconductor device PSD will be described.

[0115] 6A to 6D are cross-sectional views showing the semiconductor device PSD1 during the manufacturing process, and FIG. 6E is a cross-sectional view showing the semiconductor device PSD1 after the manufacturing process is completed. Note that this manufacturing method includes first to fifth steps.

[0116] <<First Step>> First, a die SCD is prepared. The die SCD can be obtained, for example, by undergoing a semiconductor process for forming a circuit on a wafer, a wafer polishing process, a dicing process, and the like.

[0117] In the die SCD shown in FIGS. 6A to 6E, the layer SIL is provided with electrical connection terminals ET.

[0118] Next, the die SCD is attached and fixed on the support SB having a release layer RL (see FIG. 6A). Specifically, the layer SIL and the connection terminals ET of the die SCD are attached to the release layer RL of the support SB so as to come into contact with each other.

[0119] Examples of the support SB include semiconductor substrates (e.g., single-crystal substrates or silicon substrates), SOI (Silicon-On-Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, and base films. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Other examples include synthetic resins such as acrylic. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper.

[0120] The release layer RL may be, for example, a laminated film having a tungsten film and a silicon oxide film, or an organic resin film such as polyimide, or may be a tape whose adhesive strength decreases when exposed to light such as ultraviolet light.

[0121] <<Second Step>> Next, an insulator PR is molded on the die SCD and on the release layer RL (see FIG. 6B).

[0122] Specifically, for example, the above-mentioned organic resin or the like is used as the material of the insulator PR, and the insulator PR is molded using a molding die or the like.

[0123] <<Third Step>> Next, the die SCD and the molded insulator PR are peeled off from the support SB and the release layer RL (see FIG. 6C). This step preferably exposes the connection terminals ET of the die SCD. Furthermore, after peeling off the support SB and the release layer RL, for example, the surface may be polished, or organic matter may be removed by irradiating ultraviolet light in an ozone atmosphere.

[0124] <<Fourth Step>> Next, a layer OSL is formed on the die SCD and the insulator PR (see FIG. 6D).

[0125] The die SCD and insulator PR shown in FIG. 6D are shown rotated 180 degrees from the die SCD and insulator PR in FIG. 6C.

[0126] The layer OSL can be formed by, for example, a semiconductor process. In particular, in the process of forming the layer OSL, wiring, terminals, pads, etc. (not shown) are formed on the connection terminals ET included in the die SCD. Furthermore, the layer OSL is formed so that the wiring, terminals, pads, etc. (not shown) are exposed on the surface opposite to the surface on which the die SCD is provided.

[0127] Furthermore, the semiconductor process can form a transistor OTr in the layer OSL.

[0128] By forming the layer OSL, it is possible to provide wiring electrically connected to the connection terminals ET of the die SCD and the transistor OTr in the layer OSL.

[0129] <<5th Step>> Next, bumps HBL are formed on the wiring, terminals, pads, etc. of the layer OSL that are exposed on the side opposite to the surface on which the die SCD is provided (see FIG. 6E). The bumps HBL are provided so as to be electrically connected to the wiring included in the layer OSL.

[0130] The bumps HBL may be formed using solder or the like.

[0131] By carrying out the above-described first to fifth manufacturing steps, a semiconductor device having a FOWLP structure can be manufactured.

[0132] <Semiconductor Device Fabrication Example 2> Here, an example of a method for manufacturing a semiconductor device having a different structure from the semiconductor device PSD of FIG. 1 will be described.

[0133] 7A to 7D are cross-sectional views showing the semiconductor device PSD2 during the manufacturing process, and FIG. 7E is a cross-sectional view showing the semiconductor device PSD2 after the manufacturing process is completed. Note that this manufacturing method includes first to fifth steps.

[0134] <<First Step>> First, a die SCD is prepared. For the die SCD, refer to the description of the die SCD explained in Example 1 of the semiconductor device fabrication.

[0135] Next, the die SCD is attached and fixed onto the substrate BSB (see FIG. 7A). Specifically, the substrate BSA of the die SCD and the substrate BSB are attached together so as to come into contact with each other.

[0136] The substrate BSB may be, for example, a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, etc. In particular, when a process of applying heat to the die SCD and the substrate BSB is performed in the second step or later, it is preferable that the substrate BSB be a heat-resistant substrate.

[0137] Furthermore, a die bonding film or the like may be used to bond the die SCD and the substrate BSB (not shown in FIGS. 7A to 7E).

[0138] <<Second Step>> Next, an insulator PR is molded on the die SCD and on the substrate BSB (see FIG. 7B).

[0139] Specifically, for example, the above-mentioned organic resin or the like is used as the material of the insulator PR, and the insulator PR is molded using a molding die or the like.

[0140] <<Third Step>> Next, the upper part of the molded insulator PR is removed until the connection terminals ET of the die SCD are exposed (see FIG. 7C). Methods for removing the upper part of the insulator PR include polishing, etching, ashing, etc. After polishing, etching, ashing, etc., organic matter (sometimes called organic residue) such as residues of chemicals and residues of the insulator PR that are unintentionally attached to the treated surface may be removed (e.g., a cleaning process using ultraviolet light in an ozone atmosphere).

[0141] <<Fourth Step>> Next, a layer OSL is formed on the die SCD and the insulator PR (see FIG. 7D).

[0142] For the formation of the layer OSL, the description of the fourth step explained in the first example of fabricating a semiconductor device can be referred to.

[0143] By forming the layer OSL, it is possible to provide wiring electrically connected to the connection terminals ET of the die SCD and the transistor OTr in the layer OSL.

[0144] <<5th Step>> Next, bumps HBL are formed on the wiring, terminals, pads, etc. (not shown in Figures 7A to 7E) of the layer OSL that are exposed on the side of the layer OSL opposite to the surface on which the die SCD is provided (see Figure 7E).

[0145] For the formation of the bumps HBL, please refer to the description of the fifth step explained in the first example of manufacturing a semiconductor device.

[0146] By the manufacturing process of the first to fifth steps described above, it is possible to manufacture a semiconductor device having a FOWLP configuration different from the semiconductor device PSD of FIG. 1 (the semiconductor device PSD1 of FIG. 6E).

[0147] <Semiconductor Device Fabrication Example 3> Next, an example of a manufacturing method of the semiconductor device PSD, which is different from the manufacturing steps shown in FIGS. 6A to 6E and the manufacturing steps shown in FIGS. 7A to 7E, will be described.

[0148] 8A to 8D are cross-sectional views showing the semiconductor device PSD3 during the manufacturing process, and Fig. 8E is a cross-sectional view showing the semiconductor device PSD3 after the manufacturing process is completed. Note that this manufacturing method includes first to fifth steps.

[0149] <<First Step>> First, a support SB having a release layer RL is prepared. Note that for the release layer RL or the support SB, the description of the release layer RL or the support SB in Fabrication Example 1 of the semiconductor device can be referred to.

[0150] Next, a layer OSL is formed on the release layer RL (see FIG. 8A). The layer OSL can be formed by a semiconductor process, similar to the above-described semiconductor device fabrication examples 1 and 2. In particular, in the process of forming the layer OSL, wiring, terminals, pads, etc. (not shown) for electrical connection with a bump HBL (described later) are formed on the side on which the release layer RL is provided, and wiring, terminals, pads, etc. (not shown) for electrical connection with a die SCD (described later) are formed on the side opposite to the side on which the release layer RL is provided. Furthermore, similar to the above-described semiconductor device fabrication examples 1 and 2, a transistor OTr can be formed in the layer OSL.

[0151] This allows the wiring and the transistor OTr to be formed in the layer OSL.

[0152] <<Second Step>> Next, a die SCD is prepared. For the die SCD, refer to the description of the die SCD explained in Example 1 of the semiconductor device fabrication.

[0153] Next, the die SCD is mounted on the layer OSL by flip-chip bonding (see FIG. 8B). Specifically, the connection terminals ET provided on the die SCD are electrically connected to the wiring, terminals, pads, etc. exposed on the upper surface of the layer OSL using solder or the like. In FIG. 8B, bumps BP are formed so as to contact the connection terminals ET of the die SCD.

[0154] Examples of flip-chip bonding include a method in which a resin containing anisotropic conductive particles is injected between the OSL layer and the SCD die, and a method in which SnAg solder is used for bonding. Alternatively, when the bumps and the conductors connected to the bumps are both made of gold, ultrasonic bonding can be used. In addition to the flip-chip bonding method, an underfill agent may be injected between the OSL layer and the SCD die to reduce physical stress such as impact and thermal stress.

[0155] 8B shows an example of a configuration in which the layer OSL and the die SCD are bonded together by an insulating resin IJ. The insulating resin IJ may be, for example, a resin containing anisotropic conductive particles or an underfill agent. Depending on the method for bonding the layer OSL and the die SCD, the insulating resin IJ may not be injected.

[0156] <<Third Step>> Next, an insulator PR is molded on the layer OSL and on the die SCD (see FIG. 8C).

[0157] Specifically, for example, the above-mentioned organic resin or the like is used as the material of the insulator PR, and the insulator PR is molded using a molding die or the like.

[0158] <<Fourth Step>> Next, the layer OSL, the die SCD, and the insulator PR are peeled off from the support SB and the release layer RL (see FIG. 8D). This step preferably exposes the wiring, terminals, pads, and the like (not shown in FIGS. 8A to 8E) of the layer OSL on the side of the layer OSL opposite to the side on which the die SCD is provided. Furthermore, for example, after peeling off the support SB and the release layer RL, the surface may be polished, or organic matter may be removed by irradiating ultraviolet light in an ozone atmosphere.

[0159] <<5th Step>> Next, bumps HBL are formed on the wiring, terminals, pads, etc. of the layer OSL that are exposed on the side opposite to the surface on which the die SCD is provided on the layer OSL (see FIG. 8E).

[0160] It should be noted that the layer OSL, die SCD, and insulator PR shown in FIG. 8E are shown rotated 180 degrees from the die SCD and insulator PR in FIG. 8D.

[0161] For the formation of the bumps HBL, please refer to the description of the fifth step explained in the first example of manufacturing a semiconductor device.

[0162] By performing the manufacturing process of the first to fifth steps described above, a semiconductor device having a FOWLP configuration different from the semiconductor device PSD of FIG. 1 (semiconductor device PSD1 of FIG. 6E) and the semiconductor device PSD2 of FIG. 7E can be manufactured.

[0163] When configuring a semiconductor device using FOWLP, it is difficult to form bipolar transistors or MOS transistors in the redistribution layer of the FOWLP (corresponding to the layer OSL in FIG. 1). For example, it is difficult to provide a CML circuit using bipolar transistors or a CML circuit using MOS transistors in the redistribution layer of the FOWLP. On the other hand, OS transistors can be formed in the redistribution layer of a FOWLP semiconductor device. As described above, therefore, a circuit using OS transistors can be provided in the redistribution layer of a FOWLP semiconductor device. Therefore, for example, by relocating a circuit formed on a conventional die as a circuit using OS transistors in the redistribution layer of a FOWLP semiconductor device, the mounting area of ​​the die in the redistribution layer can be reduced, thereby reducing the cost of the die.

[0164] In particular, since a CML circuit using an OS transistor can be provided in the redistribution layer of the FOWLP, a semiconductor device configured with the FOWLP can perform high-speed data transmission at the input and output of the semiconductor device.

[0165] In the present embodiment, a semiconductor device in a FOWLP package, which is a package in which the pitch of the die's connection terminals is expanded beyond the die's area by a redistribution layer, has been described. However, one embodiment of the present invention is not limited to this. For example, a semiconductor device in one embodiment of the present invention may be a semiconductor device PSD4 in the form of a wafer-level chip size package (sometimes referred to as WLCSP or FIWLP (Fan In Wafer Level Package)) as shown in FIG. 9. In the semiconductor device PSD4, the connection terminals ET of the die SCD are electrically connected to the bumps HBL via a layer OSL corresponding to the redistribution layer. Similar to the layer OSL of the semiconductor device PSD in FIG. 1, a circuit using OS transistors may be provided in the layer OSL of the semiconductor device PSD4 in FIG. 9. Alternatively, the circuit may be a CML circuit. The semiconductor device PSD4 may be fabricated by forming the layer OSL and the bumps HBL on a semiconductor wafer before cutting out the die SCDs, and then cutting the semiconductor wafer to a predetermined size. Alternatively, the semiconductor device PSD4 may be fabricated by forming the layer OSL on a semiconductor wafer, cutting the semiconductor wafer into a predetermined size, and then forming the bumps HBL.

[0166] Although the present embodiment has described a FOWLP semiconductor device using a die with connection terminals on the surface facing the semiconductor substrate, one aspect of the present invention is not limited to this. For example, one aspect of the present invention may be a semiconductor device in which connection terminals are provided on the semiconductor substrate side of the die using TSVs (Through Silicon Vias), and the semiconductor substrate and the rewiring layer are configured to face each other.

[0167] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0168] (Embodiment 2) In this embodiment, a structure example of a semiconductor device according to one embodiment of the present invention will be described.

[0169] <Configuration Example 1 of Semiconductor Device> Fig. 10 is a cross-sectional view schematically illustrating an example of the configuration of the semiconductor device PSD1 described in the first embodiment. Specifically, the semiconductor device PSD1 illustrated in Fig. 10 includes, as an example, a transistor 300 and a transistor 500. Fig. 11A illustrates a cross-sectional view of the transistor 500 in the channel length direction, Fig. 11B illustrates a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 11C illustrates a cross-sectional view of the transistor 300 in the channel width direction.

[0170] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has characteristics of a small off-state current and a field-effect mobility that does not change even at high temperatures. By using the transistor 500 as a transistor included in the semiconductor device PSD1 described in the above embodiment, for example, a semiconductor device whose operating capability does not deteriorate even at high temperatures can be realized. In particular, because an OS transistor has a small off-state current, by using an OS transistor as a transistor included in a memory cell, deterioration of the potential held in the memory cell due to current flowing through the transistor can be prevented. In other words, the potential held in the memory cell can be stored for a long time.

[0171] The transistor 300 includes a conductor 316, an isolation layer 312, an insulator 315, a semiconductor region 313 formed of a part of a substrate 310, and low-resistance regions 314a and 314b functioning as a source region or a drain region. Note that the transistor 300 can be applied to, for example, the transistor included in the layer SIL described in the above embodiment.

[0172] The substrate BSA included in the die SCD described in the above embodiment corresponds to the substrate 310 shown in FIG. 10. The layer OSL is provided above the die SCD. Therefore, the semiconductor device PSD1 in FIG. 10 has a configuration in which the transistor 500 is provided above the transistor 300.

[0173] 11C , the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0174] The transistor 300 may be either a p-channel type or an n-channel type.

[0175] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0176] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0177] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0178] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0179] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer 312 can be formed by, for example, a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa isolation method, or the like.

[0180] 10 and 11C is just an example, and the structure of the transistor 300 is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 shown in FIGS.

[0181] <<Die SCD configuration example>> Next, an example of the configuration of a die SCD will be described.

[0182] In the transistor 300 shown in FIG. 10, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0183] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0184] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0185] The insulator 322 may function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0186] The insulator 324 is preferably a film having a barrier property that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to a region where the transistor 500 is provided.

[0187] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, diffusion of hydrogen into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0188] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0189] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0190] Furthermore, conductors 328, 330, and the like are embedded in insulators 320, 322, 324, and 326. Note that conductors 328 and 330 function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connecting to the wiring may be integrated. In other words, there are cases where a portion of a conductor functions as wiring, and cases where a portion of a conductor functions as a plug.

[0191] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0192] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 10 , the insulator 350, the insulator 352, and the insulator 354 are stacked in this order over the insulator 326 and the conductor 330. The conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. For example, the conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0193] Note that, for example, the insulator 350 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably made of an insulator having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The conductor 356 preferably includes a conductor having barrier properties against water, hydrogen, and the like. In particular, a conductor having barrier properties against hydrogen is formed in the opening of the insulator 350 having barrier properties against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, thereby suppressing diffusion of hydrogen from the transistor 300 to the transistor 500.

[0194] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0195] In addition, an insulator 360, an insulator 362, and an insulator 370 are stacked in this order on the insulator 354 and the conductor 356.

[0196] The insulator 360 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0197] The insulator 362 functions as an interlayer insulating film and a planarizing film. As the insulator 362, an insulator having a barrier property against impurities such as water and hydrogen is preferably used, similar to the insulator 324. Therefore, the insulator 362 can be made of a material that can be used for the insulator 324.

[0198] As the insulator 370, it is preferable to use, for example, a film having barrier properties that prevent the diffusion of impurities such as water and hydrogen, similar to the insulator 324. That is, it is preferable to use, for the insulator 370, a material that can be used for the insulator 324. Alternatively, as the insulator 370, it is also possible to use, for example, an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance that occurs between wirings, similar to the insulator 326. That is, it is also possible to use, for the insulator 370, a material that can be used for the insulator 326.

[0199] Furthermore, openings are formed in the insulators 360, 362, and 370 in regions that overlap with a portion of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed on the insulator 362. Thereafter, the conductor 366 is patterned into the shape of a wiring, a terminal, a pad, or the like by etching or the like.

[0200] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, gold, etc. can be used as the conductor 366. Note that the conductor 366 is preferably made of the same components as the material used for the conductor 406 contained in the layer OSL, which will be described later.

[0201] Thereafter, a planarization process using a chemical mechanical polishing (CMP) method or the like is performed to improve the planarity of each of the insulator 370 and the conductor 366. This allows the conductor 366 to be formed on the die SCD as wiring, terminals, pads, etc. Note that the conductor 366 in FIG. 10 corresponds to the connection terminal ET of the die SCD of the semiconductor device PSD1 described in the above embodiment.

[0202] <<Example of layer OSL configuration>> Next, a configuration example of the layer OSL will be described.

[0203] In the semiconductor device fabrication example 1 described in the first embodiment, the semiconductor device PSD1 has a configuration in which a layer OSL is formed on a die SCD. Specifically, the connection terminals ET of the die SCD are electrically connected to the wiring included in the layer OSL. Therefore, a conductor 406 corresponding to the wiring, terminals, pads, etc. of the die SCD is formed on the conductor 366 of the die SCD. Furthermore, an insulator 402 for separating the multiple wirings, terminals, pads, etc. of the die SCD is formed on the insulator 370 of the die SCD.

[0204] In order to improve the planarity of the conductor 406 and the insulator 402, the conductor 406 and the insulator 402 are preferably subjected to planarization treatment using a chemical mechanical polishing method or the like.

[0205] The conductor 406 can be made of, for example, a material that can be used for the conductor 366. As described above, it is preferable to use the same material as the conductor 366 for the conductor 406.

[0206] Furthermore, for the insulator 402, for example, a material that can be used for the insulator 370 can be used.

[0207] In FIG. 10, an insulator 410, an insulator 412, and an insulator 414 are stacked in this order over the insulator 402 and the conductor 406.

[0208] As the insulator 410, it is preferable to use a film having barrier properties that prevent impurities such as water and hydrogen from diffusing into the region where the transistor 500 is provided, similar to the insulator 324. In other words, it is preferable to use a material that can be applied to the insulator 324 for the insulator 410. This allows the die SCD and the transistor 500 to be separated by a barrier layer, and it is possible to suppress the diffusion of hydrogen from the die SCD to the transistor 500.

[0209] For the insulators 412 and 414, it is preferable to use, for example, an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings, similar to the insulator 326. In other words, it is preferable to use, for the insulators 412 and 414, a material that can be used for the insulator 326.

[0210] 10, a conductor 416 functioning as a wiring is embedded in the insulators 410, 412, and 414. In this case, the conductor 416 functions as a wiring that connects a conductor 497, the transistor 300, the transistor 500, and the like, which will be described later. Therefore, the conductor 416 is formed to be in contact with the conductor 406. The conductor 416 can be formed using a material that can be used for the conductors 328, 330, and the like.

[0211] Wiring layers may also be provided over the insulator 414 and the conductor 416. For example, in FIG. 10 , the insulator 420, the insulator 422, and the insulator 424 are stacked in this order over the insulator 414 and the conductor 416. The conductor 426 is formed in the insulator 420, the insulator 422, and the insulator 424. The conductor 426 functions as a plug or wiring that connects, for example, a conductor 497, the transistor 300, the transistor 500, or the like, which will be described later. Therefore, the conductor 426 is formed to be in contact with the conductor 416. Note that the conductor 426 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0212] As the insulator 420, it is preferable to use an insulator that has barrier properties against impurities such as water and hydrogen, similar to the insulator 324. As the insulators 422 and 424, it is preferable to use an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings, similar to the insulator 326. As the conductor 426, it is preferable to include a conductor that has barrier properties against impurities such as water and hydrogen, similar to the conductor 356. As a result, a conductor that has barrier properties against impurities such as water and hydrogen is formed in the opening of the insulator 420 that has barrier properties against impurities such as water and hydrogen.

[0213] Further, wiring layers may be provided over the insulator 424 and the conductor 426. For example, in FIG. 10 , the insulator 430, the insulator 432, and the insulator 434 are stacked in this order over the insulator 424 and the conductor 426. The conductor 436 is formed in the insulator 430, the insulator 432, and the insulator 434. The conductor 436 functions as a plug or wiring that connects, for example, a conductor 497, the transistor 300, the transistor 500, or the like, which will be described later. Therefore, the conductor 436 is formed so as to be in contact with the conductor 426. Note that the conductor 436 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0214] The insulator 430 is preferably an insulator that has barrier properties against impurities such as water and hydrogen, similar to the insulators 324 and 420. The insulators 432 and 434 are preferably insulators with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings, similar to the insulator 326. The conductor 436 preferably includes, for example, a conductor that has barrier properties against impurities such as water and hydrogen, similar to the conductors 356 and 426.

[0215] An insulator 510, an insulator 512, an insulator 513, an insulator 514, and an insulator 516 are stacked in this order over the insulator 434 and the conductor 436. Any of the insulator 510, the insulator 512, the insulator 513, the insulator 514, and the insulator 516 is preferably formed using a substance that has a barrier property against oxygen and hydrogen.

[0216] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the like to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 or the like can be used.

[0217] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the substrate 310. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0218] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0219] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0220] For example, the insulator 513 is preferably a film having a barrier property that prevents diffusion of impurities such as water and hydrogen, similar to the insulators 510 and 514. In particular, in FIG. 10, the insulator 513 functions as a film that seals the transistor 500 together with the insulator 576 described later. For this reason, the insulator 513 is preferably made of a material that can be used for the insulator 576. The insulator 513 may also be made of a material that can be used for the insulator 510 or the insulator 514.

[0221] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320 or the insulator 326. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0222] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503 shown in FIGS. 11A and 11B), and the like are embedded in the insulators 510, 512, 513, 514, and 516. The conductor 518 functions as a plug or wiring that connects a conductor 497, which will be described later, the transistor 300, and the like. The conductor 518 can be formed using, for example, a material similar to that of the conductor 328 and the conductor 330.

[0223] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors that have barrier properties against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 500 can be separated by a layer that has barrier properties against oxygen, hydrogen, and water, and hydrogen diffusion from the die SCD to the transistor 500 can be suppressed.

[0224] Above the insulator 516 is the transistor 500 .

[0225] As shown in Figures 11A and 11B, the transistor 500 includes a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therein overlapping the conductors 542a and 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the surface on which the oxide 530c is formed, and a conductor 560 arranged on the surface on which the insulator 550 is formed. In this specification and the like, the conductor 542a and the conductor 542b are collectively referred to as the conductor 542.

[0226] 11A and 11B, it is preferable that an insulator 544 be disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 include a conductor 560a disposed inside the insulator 550 and a conductor 560b disposed so as to be embedded inside the conductor 560a. It is preferable that an insulator 574 be disposed on the insulator 580, the conductor 560, and the insulator 550, as shown in FIGS.

[0227] In the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530.

[0228] Although the transistor 500 has a three-layer structure of oxides 530a, 530b, and 530c in and around a channel formation region, one embodiment of the present invention is not limited to this structure. For example, the transistor may have a single layer of oxide 530b, a two-layer structure of oxides 530b and 530a, a two-layer structure of oxides 530b and 530c, or a stacked structure of four or more layers. Although the transistor 500 has a two-layer structure, one embodiment of the present invention is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 10, 11A, and 11B is merely an example, and the transistor is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0229] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0230] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0231] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to when a negative potential is not applied.

[0232] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0233] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0234] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0235] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0236] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, when the conductivity of the wiring can be maintained at a high level, the conductor 503a is not necessarily provided. While the conductor 503b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the above-mentioned conductive material.

[0237] The insulators 520, 522, and 524 function as a second gate insulating film.

[0238] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. In other words, the insulator 524 preferably has an excess oxygen region. By providing an insulator containing such excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced, improving the reliability of the transistor 500. Note that in this specification and elsewhere, oxygen vacancies in a metal oxide are referred to as V O This is sometimes called oxygen vacancy.

[0239] A transistor using a metal oxide has impurities or oxygen vacancies (V O ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0240] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0241] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V O H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO and be removed from the oxide 530 or the insulator near the oxide 530. Some of the hydrogen may also be diffused or captured (also called gettered) in the conductor 542a and the conductor 542b.

[0242] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0243] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0244] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0245] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0246] The insulator 522 preferably has a function of suppressing diffusion of oxygen, impurities, and the like, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 and the oxide 530 can be suppressed.

[0247] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film makes it possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0248] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen from the periphery of the transistor 500 into the oxide 530.

[0249] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0250] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0251] 11A and 11B, the second gate insulating film has a three-layer stack structure including the insulators 520, 522, and 524. However, the second gate insulating film may have a single-layer, two-layer, or four or more-layer stack structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0252] In the transistor 500, a metal oxide functioning as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used for the oxide 530. In particular, the In-M-Zn oxide that can be used for the oxide 530 is preferably a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) or a Cloud-Aligned Composite Oxide Semiconductor (CAC-OS). Alternatively, an In-Ga oxide, an In-Zn oxide, an In oxide, or the like may be used for the oxide 530.

[0253] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. To lower the carrier concentration of a metal oxide, the impurity concentration in the metal oxide should be lowered to lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0254] In particular, hydrogen contained in the metal oxide reacts with oxygen that bonds with the metal atom to form water, which can cause oxygen vacancies in the metal oxide. When hydrogen enters an oxygen vacancy in the oxide 530, the oxygen vacancy and hydrogen bond to form V. O May form H. V O H functions as a donor and may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen, which is bonded to a metal atom, to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, since hydrogen in a metal oxide is easily moved by stresses such as heat and an electric field, the reliability of the transistor may be reduced if the metal oxide contains a large amount of hydrogen. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain metal oxides with sufficiently reduced H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to compensate for oxygen deficiencies (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be achieved.

[0255] Defects in which hydrogen has entered oxygen vacancies can function as donors in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated using carrier concentration rather than donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of metal oxides, rather than donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as "donor concentration."

[0256] Therefore, when a metal oxide is used for the oxide 530, it is preferable that the hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is set to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0257] When a metal oxide is used for the oxide 530, the metal oxide has a wide band gap and is an intrinsic (also referred to as I-type) or substantially intrinsic semiconductor. The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is less than 1 x 10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0258] Furthermore, when a metal oxide is used for the oxide 530, contact between the conductors 542a and 542b and the oxide 530 may cause oxygen in the oxide 530 to diffuse into the conductors 542a and 542b, resulting in the oxidation of the conductors 542a and 542b. The oxidation of the conductors 542a and 542b is likely to result in a decrease in the conductivity of the conductors 542a and 542b. The diffusion of oxygen in the oxide 530 to the conductors 542a and 542b can be rephrased as the conductors 542a and 542b absorbing the oxygen in the oxide 530.

[0259] Furthermore, oxygen in the oxide 530 diffuses into the conductor 542a and the conductor 542b, which may form a heterogeneous layer between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. Since the heterogeneous layer contains more oxygen than the conductor 542a and the conductor 542b, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 542a or the conductor 542b, the heterogeneous layer, and the oxide 530b can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and may be referred to as a metal-insulator-semiconductor (MIS) structure or a diode junction structure based on the MIS structure.

[0260] Note that the above-mentioned different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b, and for example, the different layer may be formed between the conductor 542a and the conductor 542b and the oxide 530c.

[0261] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0262] The oxide 530 has the oxide 530a below the oxide 530b, which can prevent impurities from diffusing from structures formed below the oxide 530a to the oxide 530b. Also, the oxide 530 has the oxide 530c on the oxide 530b, which can prevent impurities from diffusing from structures formed above the oxide 530c to the oxide 530b.

[0263] The oxide 530 preferably has a stacked structure made up of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. The atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. The atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably greater than the atomic ratio of In to M in the metal oxide used for the oxide 530a. The oxide 530c can be made up of the same metal oxide as that used for the oxide 530a or the oxide 530b.

[0264] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or 1:1:0.5. Oxide 530b may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or 1:1:1. Oxide 530c may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 and an atomic ratio of Ga to Zn of Ga:Zn=2:1 or Ga:Zn=2:5. Specific examples of the oxide 530c having a layered structure include layered structures in which the atomic ratios of In, Ga, and Zn are In:Ga:Zn=4:2:3 and In:Ga:Zn=1:3:4, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:1 and In:Ga:Zn=4:2:3, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:5 and In:Ga:Zn=4:2:3, and layered structures in which gallium oxide and In, Ga, and Zn are In:Ga:Zn=4:2:3.

[0265] Furthermore, for example, when the atomic ratio of In to element M in the metal oxide used for oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for oxide 530b, an In-Ga-Zn oxide having a composition in which the atomic ratio of In to Ga to Zn is In:Ga:Zn=5:1:6 or thereabouts, In:Ga:Zn=5:1:3 or thereabouts, or In:Ga:Zn=10:1:3 or thereabouts, can be used as oxide 530b.

[0266] In addition to the compositions described above, oxide 530b may be made of a metal oxide having a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these.

[0267] It is preferable to combine these oxides 530a, 530b, and 530c so that the atomic ratios satisfy the above relationship. For example, it is preferable that oxides 530a and 530c are metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to that, and oxide 530b is a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition close to that. Note that the above compositions refer to the atomic ratios in the oxide formed on the substrate or in the sputtering target. Furthermore, increasing the In ratio in the composition of oxide 530b is preferable because it can increase the on-state current or field-effect mobility of the transistor.

[0268] The conduction band minimum energy of the oxide 530a and the oxide 530c is preferably higher than that of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than that of the oxide 530b.

[0269] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxides 530a, 530b, and 530c. In other words, the energy level of the conduction band minimum at the junction between the oxides 530a, 530b, and 530c changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the oxides 530a and 530b and at the interface between the oxides 530b and 530c.

[0270] Specifically, when the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and the oxide 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0271] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0272] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0273] 11A and 11B, the conductor 542a and the conductor 542b are shown as single-layer structures, but they may also have a stacked structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0274] Further, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0275] 11A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0276] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0277] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surfaces of the oxide 530 and the insulator 524 and to be in contact with the insulator 522.

[0278] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0279] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process. Note that the insulator 544 is not an essential component if the conductors 542a and 542b are made of oxidation-resistant materials or if their conductivity does not decrease significantly even when they absorb oxygen. The insulator 544 may be designed appropriately depending on the desired transistor characteristics.

[0280] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. The insulator 544 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0281] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably disposed in contact with the inside (top surface and side surface) of the oxide 530c. The insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0282] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0283] By providing the insulator 550, which releases oxygen upon heating, in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similar to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1 nm to 20 nm.

[0284] Furthermore, a metal oxide may be provided between the insulator 550 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0285] The insulator 550 may have a stacked structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a stacked structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a stacked structure that is thermally stable and has a high dielectric constant can be achieved.

[0286] The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 11A and 11B, but may have a single-layer structure or a stacked structure of three or more layers.

[0287] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used. The conductor 560a has the function of suppressing the diffusion of oxygen, which can suppress the oxidation of the conductor 560b due to oxygen contained in the insulator 550 and a decrease in conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, the conductor 560a can be made of an oxide semiconductor that can be used for the oxide 530. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be referred to as an OC (Oxide Conductor) electrode.

[0288] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0289] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of excess oxygen regions in a later step.

[0290] The insulator 580 has an excess oxygen region, and thus can release oxygen by heating the insulator 580. Therefore, by providing the insulator 580, from which oxygen is released by heating, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0291] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0292] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0293] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0294] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0295] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0296] Parts of the insulators 574, 580, 544, 522, 520, 516, and 514 are removed to form openings that surround the transistor 500 and expose the insulator 513, thereby forming an insulator 576 with high barrier properties against hydrogen or water. Therefore, the side surfaces of the insulators 574, 580, 544, 522, 520, 516, and 514 are in contact with the insulator 576. This prevents moisture and hydrogen from entering the transistor 500 from the outside.

[0297] As described above, the insulators 513 and 576 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom and a hydrogen molecule) or water molecules. For example, the insulator 513 and the insulator 576 are preferably made of silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties. This can suppress diffusion of hydrogen and other substances into the oxide 530, thereby preventing deterioration in the characteristics of the transistor 500. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0298] An insulator 581 functioning as an interlayer film or a planarizing film is preferably provided over the insulator 576. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0299] Furthermore, an insulator 552 is provided on the side surfaces of openings formed in insulators 581, 576, 574, 580, and 544. Then, conductors 540a and 540b are provided so as to contact the side surfaces of insulator 552 and the bottom surfaces of the openings. Note that in FIG. 11A , conductors 540a and 540b are provided opposite each other with conductor 560 interposed therebetween.

[0300] The insulator 552 is provided in contact with, for example, the insulator 581, the insulator 576, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably formed using an insulator with high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. Silicon nitride is particularly suitable for use as the insulator 552 because it has high hydrogen barrier properties. Using a material with high hydrogen barrier properties for the insulator 552 can suppress diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductors 540a and 540b. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b. Thus, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0301] The conductor 540a and the conductor 540b can be formed using, for example, the same material as the conductor 328, the conductor 330, the conductor 503, etc. In particular, it is preferable that each of the conductors 540a and 540b has a stacked structure of two or more layers, in which the first layer in contact with the insulator 552 is formed of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate), and the second and subsequent layers are formed of a conductive material with high conductivity that contains tungsten, copper, aluminum, or the like as a main component.

[0302] 10, an insulator 582 is provided over an insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen, hydrogen, and the like. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0303] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0304] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0305] 10 and 11A, conductors 540a, 540b, 546, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 576, 581, 582, and 586. Note that as conductor 546, for example, a material that can be used for conductors 540a and 540b can be used.

[0306] The conductor 540a, the conductor 540b, and the conductor 546 function as plugs or wirings that connect the transistor 500, the transistor 300, a conductor 497 (described later), and the like. The conductor 540a and the conductor 540b can be formed using the same material as the conductor 328 and the conductor 330. In particular, in FIG. 10, the conductor 546 is formed so as to be in contact with the conductor 518.

[0307] Furthermore, the conductor 450 may be provided over the conductor 540a, the conductor 540b, the conductor 546, and the insulator 586. The conductor 450 functions as a wiring that connects a conductor 497, the transistor 300, the transistor 500, and the like, which will be described later. In particular, in FIG. 10, the conductor 450 is formed so as to be in contact with the conductor 540a, the conductor 540b, the conductor 546, and the like.

[0308] For example, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 450. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be used.

[0309] 10, the conductor 450 has a single-layer structure, but is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0310] In addition, in the layer OSL of the semiconductor device PSD1 in FIG. 10, a wiring layer is also provided above the transistor 500, for example.

[0311] An insulator 451, an insulator 452, and an insulator 454 are stacked in this order over the insulator 586 and the conductor 450.

[0312] The insulator 451 is preferably a film having a barrier property that prevents impurities such as water and hydrogen from diffusing into a region where the transistor 500 is provided, similar to the insulator 324. That is, the insulator 451 is preferably a material that can be used for the insulator 324.

[0313] For the insulators 452 and 454, it is preferable to use, for example, an insulator with a relatively low relative dielectric constant, similar to the insulator 326. In other words, it is preferable to use, for the insulators 452 and 454, a material that can be used for the insulator 326.

[0314] A conductor 456 is embedded in the insulators 451, 452, and 454. The conductor 456 functions as a plug or a wiring that connects a conductor 497, the transistor 300, the transistor 500, or the like, which will be described later. The conductor 456 can be formed using, for example, a material that can be used for the conductor 328, the conductor 330, and the like.

[0315] 10, the insulator 460, the insulator 462, and the insulator 464 are stacked in this order over the insulator 454 and the conductor 456. The conductor 466 is formed in the insulator 460, the insulator 462, and the insulator 464. The conductor 466 functions as a plug or a wiring that connects, for example, a conductor 497, the transistor 300, the transistor 500, or the like, which will be described later. Note that the conductor 466 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0316] The insulator 460 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulators 324 and 420. Similarly to the insulator 326, the insulators 462 and 464 are preferably insulators having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. Similarly to the conductors 356 and 426, the conductor 466 preferably includes a conductor having barrier properties against impurities such as water and hydrogen. In particular, a conductor having barrier properties against impurities such as water and hydrogen is formed in an opening of the insulator 460 having barrier properties against impurities such as water and hydrogen. This allows the transistor 500 to be separated from the upper side of the layer OSL by the barrier layer, thereby suppressing diffusion of impurities such as water and hydrogen from the upper side of the layer OSL to the transistor 500.

[0317] In addition, an insulator 470 and an insulator 472 are stacked in this order on the insulator 464 and the conductor 466.

[0318] The insulator 470 is preferably an insulator that has barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 470 can be made of, for example, a material that can be used for the insulator 324.

[0319] The insulator 472 functions as a planarization film. Similarly to the insulator 324, the insulator 472 is preferably an insulator having a barrier property against impurities such as water and hydrogen. For this reason, the insulator 472 can be made of a material that can be used for the insulator 324.

[0320] Furthermore, openings are formed in the insulators 470 and 472 in regions that overlap with part of the conductor 466, and the conductor 493 is provided to fill the openings. The conductor 493 is also formed over the insulator 472. After that, the conductor 493 is patterned into the shape of a wiring, a terminal, a pad, or the like by etching or the like.

[0321] The conductor 493 can be made of, for example, copper, aluminum, tin, zinc, tungsten, silver, platinum, gold, or the like. The conductor 493 can be made of any material that can be used for the conductor 366 or the conductor 406.

[0322] Next, an insulator 492 is formed to cover the insulator 472 and the conductor 493, and then planarization treatment using a chemical mechanical polishing (CMP) method or the like is performed until the conductor 493 is exposed. This can improve the planarization of the insulator 492 and the conductor 493.

[0323] As the insulator 492, for example, an insulator that functions as a planarization film is preferably provided similarly to the insulator 362. Therefore, for example, the insulator 492 can be formed using a material that can be used for the insulator 362.

[0324] Next, an insulator 494 and an insulator 495 are deposited in this order over the insulator 492 and the conductor 493. After that, openings are formed in the insulator 494 and the insulator 495 so that the conductor 493 is exposed, and a conductor 496 is formed in the openings.

[0325] As the insulator 494, for example, an insulator that functions as a planarization film similar to the insulator 362 is preferably provided. Therefore, for example, the insulator 494 can be formed using a material that can be used for the insulator 362.

[0326] The insulator 495 is preferably an insulator that has barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 495 can be, for example, a material that can be used for the insulator 324.

[0327] The conductor 496 can be, for example, a material that can be used for the conductor 493. The conductor 496 is preferably a material that can form a conductor 497 over the conductor 496, which will be described later.

[0328] Conductor 497, which corresponds to bump HBL of semiconductor device PSD1 described in the first embodiment, is provided on conductor 496. Conductor 497 can be formed using, for example, solder. Alternatively, conductor 497 can be formed using an alloy of one or more elements selected from Sn, Cu, Ag, Au, Bi, etc. Note that while FIG. 10 illustrates conductor 497 as a ball-shaped bump as an example, cone-shaped bumps, pyramidal bumps such as square pyramids, mushroom-shaped bumps, columnar bumps, etc. may also be used. Conductor 497 can be formed by electroplating, electroless plating, printing, etc.

[0329] <Configuration Example 2 of Semiconductor Device> Next, a description will be given of a configuration example of the semiconductor device PSD3 described in the embodiment 1. Fig. 12 is a cross-sectional view schematically illustrating a configuration example of the semiconductor device PSD3, and the semiconductor device PSD3 includes, as an example, a transistor 300 and a transistor 500, similar to the semiconductor device PSD1.

[0330] The semiconductor device PSD3 has a configuration in which the layer OSL is formed and then the die SCD is mounted on the layer OSL, and therefore the up-down orientation of the transistor 500 included in the layer OSL is different from the up-down orientation of the transistor 300 included in the die SCD. This is because, in the layer OSL of the semiconductor device PSD3, wiring, insulators, and the like are formed from below the transistor 500, and wiring, terminals, pads, and the like for electrically connecting the transistor 500 to the die SCD are provided above the transistor 500.

[0331] In the semiconductor device PSD3 of FIG. 12, the description of the same parts as those in the configuration example of the semiconductor device PSD1 described above will be omitted.

[0332] The layer OSL of the semiconductor device PSD3 is formed in this order from the insulator 402 and the conductor 406 to the insulator 482 and the conductor 486, which will be described later. Note that in the layer OSL, the configurations and manufacturing methods of the insulator 402 and the conductor 406 to the insulator 472, the insulator 474, and the conductor 476 are to be taken into consideration in the configuration example of the layer OSL of the semiconductor device PSD1 described above.

[0333] A conductor 486 is formed on the insulator 474 and the conductor 476. The conductor 486 corresponds to a plurality of wirings, terminals, pads, etc. in the layer OSL for connection with the die SCD. Also, an insulator 482 is formed on the insulator 474 to separate the plurality of wirings, terminals, pads, etc. in the layer OSL.

[0334] The insulator 474 and the conductor 486 can be formed, for example, by first depositing the conductor 486 and then patterning the conductor 486 into the shape of a wiring, terminal, pad, etc. by etching or the like. Next, the insulator 482 is deposited so as to cover the insulator 474 and the conductor 486, and then a planarization process using a chemical mechanical polishing (CMP) method or the like is performed until the conductor 486 is exposed. This allows the conductor 486 to be formed in the layer OSL as a wiring, terminal, pad, etc.

[0335] Furthermore, in the die SCD of the semiconductor device PSD3, a transistor 300 is formed on a substrate 310, and an insulator 320, an insulator 332, and a conductor 328 are formed on the transistor 300. Furthermore, an insulator 324, an insulator 326, and a conductor 330 to an insulator 362, an insulator 370, and a conductor 366 are formed on the insulator 320, the insulator 332, and the conductor 328. Note that the configuration and manufacturing method of the die SCD of the semiconductor device PSD3 refer to the configuration example of the die SCD of the semiconductor device PSD1 described above.

[0336] In the semiconductor device PSD3, the conductor 366 of the die SCD is electrically connected to the conductor 486 of the layer OSL via the conductor 376. The conductor 376 corresponds to the bump BP of the semiconductor device PSD1 described in the first embodiment. The conductor 376 can be formed using, for example, solder. Alternatively, the conductor 376 can be formed using, for example, one or an alloy of two or more elements selected from Sn, Cu, Ag, Au, Bi, etc. Note that, in FIG. 12, the conductor 376 is illustrated as a ball-shaped bump as an example, but a cone-shaped bump, a pyramidal bump such as a square pyramid, a mushroom-shaped bump, a columnar bump, or the like may also be used. The conductor 486 can be formed by electroplating, electroless plating, printing, or the like.

[0337] In the semiconductor device PSD3, the layer OSL and the die SCD can be bonded by, for example, flip-chip bonding. In the semiconductor device PSD3 of Fig. 12, an insulator 380 is injected as an insulating resin between the layer OSL and the die SCD. The insulator 380 corresponds to the insulating resin IJ of the semiconductor device PSD3 described in the first embodiment.

[0338] Although not shown in FIGS. 10 and 12, the semiconductor device PSD1 and the semiconductor device PSD3 may have a capacitive element.

[0339] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0340] (Embodiment 3) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0341] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0342] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 13A. Fig. 13A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0343] As shown in FIG. 13A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0344] The structure within the bold frame shown in Figure 13A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0345] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 13B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." (The horizontal axis represents 2θ [deg.], and the vertical axis represents intensity in arbitrary units (au).) The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 13B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 13B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 13B is 500 nm.

[0346] As shown in Figure 13B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 13B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0347] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 13C. Figure 13C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 13C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0348] As shown in FIG. 13C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0349] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 13A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0350] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0351] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0352] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0353] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0354] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0355] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0356] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0357] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0358] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is unlikely to occur in CAAC-OS. Furthermore, since the crystallinity of oxide semiconductors can be reduced by the inclusion of impurities or the formation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using CAAC-OS for OS transistors enables greater flexibility in the manufacturing process.

[0359] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0360] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0361] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0362] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0363] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0364] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0365] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0366] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0367] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0368] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0369] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0370] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0371] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0372] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0373] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0374] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0375] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0376] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0377] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon, carbon, etc. in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 1017 atoms / cm 3 The following applies.

[0378] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0379] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0380] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0381] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0382] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0383] (Fourth embodiment) In this embodiment, a semiconductor wafer, a semiconductor chip obtained by cutting the semiconductor wafer, a semiconductor device incorporating the semiconductor chip by FOWLP, and the like will be described.

[0384] <Semiconductor wafers and semiconductor chips> First, an example of a semiconductor wafer on which circuits and the like are formed will be described with reference to FIG. 14A.

[0385] 14A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0386] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0387] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0388] By performing a dicing process, semiconductor chips 4800a as shown in FIG. 14B can be cut out from semiconductor wafer 4800. Semiconductor chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0389] Note that the shape of the element substrate of the semiconductor device of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 14A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the apparatus for manufacturing the element.

[0390] <Semiconductor device> Fig. 14C shows a perspective view of semiconductor device 4700. In semiconductor device 4700 shown in Fig. 14C, semiconductor chip 4800a is mounted above redistribution layer 4716, and sealing material 4711 is provided above redistribution layer 4716 so as to cover semiconductor chip 4800a. Note that Fig. 14C does not show a portion of sealing material 4711 in order to show the interior of semiconductor device 4700.

[0391] 14D is a perspective view of the underside of semiconductor device 4700. As an example, the underside of semiconductor device 4700 has a BGA (Ball Grid Array) with bumps 4717. Note that semiconductor device 4700 is not limited to a BGA, and may also have an LGA, PGA, or the like.

[0392] The semiconductor device 4700 may be mounted on other substrates using various mounting methods other than BGA, LGA, or PGA, such as a Staggered Pin Grid Array (SPGA), a Quad Flat Package (QFP), a Quad Flat J-leaded package (QFJ), or a Quad Flat Non-leaded package (QFN).

[0393] A heat sink (heat dissipation plate) may be provided so as to overlap the semiconductor device 4700, the semiconductor chip 4800a, and the like.

[0394] As described above, the semiconductor chip 4800a is packaged by FOWLP to manufacture the semiconductor device 4700. The semiconductor device 4700 may be, for example, a high bandwidth memory (HBM). The semiconductor device 4700 may be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a storage device.

[0395] By mounting semiconductor device 4700 on a printed circuit board or the like, it is possible to create a circuit board such as a main board or system board provided in an electronic device or the like. Fig. 14E shows, as an example, a perspective view of a board (mounting board 4704) on which semiconductor device 4700 is mounted. Also in Fig. 14E, semiconductor device 4700 is mounted on, for example, printed circuit board 4702. In this way, a plurality of semiconductor devices are combined and electrically connected on printed circuit board 4702, thereby completing mounting board 4704.

[0396] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0397] (Embodiment 5) In this embodiment, examples of electronic devices including the semiconductor device described in the above embodiment will be described. Note that, for example, a state in which a semiconductor device 4700 is included in each electronic device is illustrated in FIG.

[0398] [mobile phone] 15 is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0399] 15, the information terminal 5500 includes a semiconductor device such as a memory device, an imaging device, or a display device. For example, by applying a semiconductor device 4700 having a CML circuit provided in a redistribution layer to the information terminal 5500, signals can be transmitted at high speed between a circuit included in the semiconductor device 4700 and a circuit external to the semiconductor device 4700. This can increase the processing speed of the information terminal 5500.

[0400] [Wearable devices] 15 illustrates a wristwatch-type information terminal 5900 as an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, an operator 5904, a band 5905, and the like.

[0401] As with the information terminal 5500 described above, the processing speed of the wearable terminal can be increased by applying the semiconductor device 4700 in which a CML circuit is provided in the rewiring layer.

[0402] [Information terminal] 15 also shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0403] Like the information terminal 5500 described above, the desktop information terminal 5300 can reduce power consumption of the semiconductor device provided in the desktop information terminal 5300 by applying the semiconductor device described in the above embodiment.

[0404] In the above description, a smartphone, a desktop information terminal, and a wearable terminal are illustrated as examples of electronic devices in Fig. 15, but information terminals other than smartphones, desktop information terminals, and wearable terminals can also be applied. Examples of information terminals other than smartphones, desktop information terminals, and wearable terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0405] [electric appliances] 15 also illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0406] The electric refrigerator-freezer 5800 may be configured to include a communication device and be connectable to a network. That is, the electric refrigerator-freezer 5800 may be an electronic device compatible with IoT (Internet of Things). By applying the semiconductor device 4700 having a CML circuit provided in a rewiring layer to the electric refrigerator-freezer 5800, for example, the processing speed of the electric refrigerator-freezer 5800 related to IoT can be increased.

[0407] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction heating (IH) cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0408] [Game consoles] 15 also shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0409] FIG. 15 further illustrates a home video game console 7500, which is an example of a video game console. The home video game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 15, the controller 7522 can include a display unit that displays game images, a touch panel that serves as an input interface other than buttons, a stick, a rotary knob, a sliding knob, or the like. The shape of the controller 7522 is not limited to that shown in FIG. 15, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0410] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0411] By applying the semiconductor device 4700 in which a CML circuit is provided in the rewiring layer to the portable game machine 5200, the processing speed of the portable game machine 5200 can be increased.

[0412] 15 illustrates a portable game machine as an example of a game machine, but the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include a home-use stationary game machine, an arcade game machine installed in an entertainment facility (such as an arcade or amusement park), and a pitching machine for batting practice installed in a sports facility.

[0413] [Moving object] The semiconductor device described in the above embodiment mode can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.

[0414] FIG. 15 shows an automobile 5700 as an example of a moving object.

[0415] An instrument panel capable of displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device showing such information may also be provided around the driver's seat.

[0416] In particular, the display device can compensate for the view obstructed by pillars and the blind spot of the driver's seat by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby improving safety. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, it is possible to compensate for the blind spot and improve safety.

[0417] The semiconductor device described in the above embodiment can be applied to the above-mentioned instrument panel, imaging device, etc. In particular, by providing a CML circuit in the rewiring layer of the semiconductor device, the processing speed of the instrument panel, imaging device, etc. provided in the automobile 5700 can be increased.

[0418] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). The semiconductor device of one embodiment of the present invention can be applied to these moving objects to increase the processing speed.

[0419] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0420] 15 shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0421] By applying the semiconductor device 4700 in which a CML circuit is provided in the rewiring layer to the digital camera 6240, the processing speed of the digital camera 6240 can be increased.

[0422] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0423] 15 shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, and the like. The operation keys 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0424] As with the digital camera 6240 described above, by applying the semiconductor device 4700 in which a CML circuit is provided in the rewiring layer to the video camera 6300, the processing speed of the video camera 6300 can be increased.

[0425] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. [Explanation of symbols]

[0426] PSD: semiconductor device, SCD: die, PR: insulator, OSL: layer, HBL: bump, BSA: substrate, SIL: layer, ET: connection terminal, OTr: transistor, SIC: circuit, OSC: circuit, EXT1: external terminal, EXT2: external terminal, DEV: circuit, RGCM: circuit, HSTC: circuit, CM: differential amplifier circuit, CM1: differential amplifier circuit, CM2: differential amplifier circuit, CM[1]: differential amplifier circuit, CM[2]: differential amplifier circuit, CM[n-1]: differential amplifier circuit, CM[n]: differential amplifier circuit, CM[m]: differential amplifier circuit, CM[n+1]: differential amplifier circuit, CM[m+1] : Differential amplifier circuit, CMA: Differential amplifier circuit, CMB: Differential amplifier circuit, C1P: Capacitor, C1N: Capacitor, LE1A: Load, LE1B: Load, LE2P: Load, LE2N: Load, DTrA: Transistor, DTrB: Transistor, TrC: Transistor, ITrA: Transistor, ITrB: Transistor, DEA: Diode, DEB: Diode, CC: Current source, VBL1: Wiring, VBL2: Wiring, VDE: Wiring, VSE: Wiring, BGE1: Wiring, BGE2: Wiring, VAL: Wiring, OCLN: Terminal, OCLP: Terminal, HIP: Terminal, HIN: Terminal, HON: Terminal, HOP: terminal, INP: terminal, INN: terminal, OUTP: terminal, OUTN: terminal, PSD1: semiconductor device, PSD2: semiconductor device, PSD3: semiconductor device, PSD4: semiconductor device, BSB: substrate, SB: support, RL: release layer, BP: bump, IJ: insulating resin, SCL1: scribe line, SCL2: scribe line, 300: transistor, 310: substrate, 312: element isolation layer, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator , 326: insulator, 328: conductor, 330: conductor, 332: insulator, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 366: conductor, 370: insulator, 376: conductor, 380: insulator, 402: insulator, 406: conductor, 410: insulator, 412: insulator, 414: insulator, 416: conductor, 420: insulator, 422: insulator, 424: insulator, 426: conductor, 430: insulator, 432: insulator, 434: insulator, 436: conductor, 450: conductor, 451: insulator, 452: insulator,454: Insulator, 456: Conductor, 460: Insulator, 462: Insulator, 464: Insulator, 466: Conductor, 470: Insulator, 472: Insulator, 474: Insulator, 476: Conductor, 482: Insulator, 486: Conductor, 492: Insulator, 493: Conductor, 494: Insulator, 495: Insulator, 496: Conductor, 497: Conductor, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 513: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 522: Insulator , 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 530c: oxide, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 546: conductor, 550: insulator, 552: insulator, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 576: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 4700: semiconductor device, 4702: printed circuit board, 4704: mounting board, 47 11: sealing material, 4716: rewiring layer, 4717: bump, 4800: semiconductor wafer, 4800a: semiconductor chip, 4801: wafer, 4801a: wafer, 4802: circuit part, 4803: spacing, 4803a: spacing, 5200: portable game console, 5201: housing, 5202: display part, 5203: button, 5300: desktop information terminal, 5301: main body, 5302: display, 5303: keyboard, 5500: information terminal, 5510: housing, 5511: display part, 5700: automobile, 5800: electric refrigerator-freezer, 5801: Housing, 5802: refrigerator compartment door, 5803: freezer compartment door, 5900: information terminal, 5901: housing, 5902: display unit, 5903: operation button, 5904: operator, 5905: band, 6240: digital camera, 6241: housing, 6242: display unit, 6243: operation button, 6244: shutter button, 6246: lens, 6300: video camera, 6301: housing, 6302: housing, 6303: display unit, 6304: operation key, 6305: lens, 6306: connection unit, 7500: stationary game console, 7520: main unit, 7522: controller,

Claims

1. a wiring layer having two surfaces, a semiconductor chip, and external terminals; the semiconductor chip is provided on one surface side of the wiring layer, the external terminals are provided on the other surface of the wiring layer in an area that does not overlap with at least the semiconductor chip; the semiconductor chip has a first circuit; the wiring layer has a second circuit, the first circuit is electrically connected to the second circuit; the second circuit is electrically connected to the external terminal; the second circuit includes first to fourth transistors and a current source; one of a source and a drain of the first transistor is electrically connected to a first wiring; the other of the source and the drain of the first transistor is electrically connected to a first output wiring; a gate of the first transistor electrically connected to the first wiring; one of a source and a drain of the second transistor is electrically connected to the first wiring; the other of the source and the drain of the second transistor is electrically connected to a second output wiring; a gate of the second transistor electrically connected to the first wiring; one of the source and the drain of the third transistor is electrically connected to the first output wiring; the other of the source and the drain of the third transistor is electrically connected to the current source; a gate of the third transistor electrically connected to a second wiring; one of the source and the drain of the fourth transistor is electrically connected to the second output wiring; the other of the source and the drain of the fourth transistor is electrically connected to the current source; a gate of the fourth transistor electrically connected to a third wiring; At least one of the first to fourth transistors includes a metal oxide in a channel formation region. Semiconductor device.

2. In claim 1, the semiconductor chip has connection terminals, the first circuit and the second circuit are electrically connected via the connection terminal; The pitch width of the external terminals is larger than the pitch width of the connection terminals. Semiconductor device.

Images