Apparatus, synchronization maintaining method and system

Abstract

To provide a master device and a slave device for effectively synchronizing time.SOLUTION: In the synchronization system, the slave device receives the hardware time stamp from the master device through the communication unit, synchronizes its own time based on the hardware time stamp, calculates an error of its own time based on a timing at which the hardware time stamp is received, transmits weighting factor information indicating a weighting factor based on the error to another slave device through the communication unit, and receives the weighting factor information from another slave device through the communication unit. A synchronization pulse is transmitted to the other slave device through the communication unit, the synchronization pulse is received from the other slave device through the communication unit, the time of the other slave device is calculated based on the timing at which the synchronization pulse is received, and the own time is corrected based on the time of the other slave device and the weight coefficient information.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The embodiments of the present invention relate to a master device and a slave device. [Background technology]

[0002] A system is provided that includes a master that transmits a hardware timestamp and multiple slaves that receive the hardware timestamp from the master and synchronize their times. In such a system, the master transmits a hardware timestamp to each slave at a predetermined interval, such as 1 s.

[0003] Conventionally, systems have had the problem that when the master goes down, the time of each slave drifts. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6707209 Summary of the Invention [Problem to be solved by the invention]

[0005] In order to solve the above problem, a master device and a slave device capable of effectively synchronizing time are provided. [Means for solving the problem]

[0006] According to an embodiment, an information processing device includes a communication unit and a processor. The communication unit is connected to a first external device and a second external device. The processor receives a hardware timestamp from the first external device through the communication unit, synchronizes its own time based on the hardware timestamp, calculates an error in its own time based on the timing of receiving the hardware timestamp, transmits weighting coefficient information indicating a weighting coefficient based on the error to the second external device through the communication unit, receives the weighting coefficient information from the second external device through the communication unit, transmits a synchronization pulse to the second external device through the communication unit, receives the synchronization pulse from the second external device through the communication unit, calculates the time of the second external device based on the timing of receiving the synchronization pulse, and corrects its own time based on the time of the second external device and the weighting coefficient information. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a synchronization system according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of the master according to the first embodiment. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of a slave according to the first embodiment. [Figure 4] FIG. 4 is a timing chart showing an example of the operation of the synchronization system according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of a slave pulse table according to the first embodiment. [Figure 6] FIG. 6 is a timing chart showing an example of the operation of the synchronization system according to the first embodiment. [Figure 7] FIG. 7 is a flowchart showing an example of the operation of the slave according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing an example of the configuration of a master pulse table according to the second embodiment. [Figure 9]FIG. 9 is a timing chart showing an example of the operation of the synchronization system according to the second embodiment. [Figure 10] FIG. 10 is a timing chart showing an example of the operation of the synchronization system according to the third embodiment. [Figure 11] FIG. 11 is a block diagram showing an example of the configuration of a synchronization system according to the fourth embodiment. [Figure 12] FIG. 12 is a flowchart showing an example of the operation of the slave according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment will be described with reference to the drawings. (First embodiment) First, the first embodiment will be described. A synchronization system according to an embodiment synchronizes time among slaves. In the synchronization system, a master transmits a hardware timestamp to each slave. Each slave synchronizes time according to the hardware timestamp from the master.

[0009] Fig. 1 shows an example of the configuration of a synchronization system 1 according to an embodiment. As shown in Fig. 1, the synchronization system 1 includes a grandmaster 10 and a plurality of devices 11. The device 11 includes a master 20 (first external device, information processing device) and a plurality of slaves 30 (external devices, information processing devices).

[0010] The grandmaster 10 connects to the master 20 of each device 11. The master 20 connects to each slave 30. The synchronization system 1 may include other components as needed in addition to the components shown in FIG. 1, or certain components may be excluded from the synchronization system 1.

[0011] The grandmaster 10 transmits signals to each master 20 to synchronize the time. For example, the grandmaster 10 adjusts the time using GPS (Global Positioning System) signals from satellites. The grandmaster 10 transmits a software timestamp indicating the time to each master 20 via a network such as Ethernet (registered trademark). The grandmaster 10 also transmits a hardware timestamp to each master 20 at predetermined intervals. For example, the grandmaster 10 transmits a pulse every second (1 PPS) to each master 20 as a hardware timestamp.

[0012] The device 11 operates in synchronization with the time of the grandmaster 10. For example, the device 11 is a radar transmitter or receiver.

[0013] The synchronization system 1 includes devices 11 such as device 11a, device 11b, . Here, the device 11a will be described.

[0014] The device 11a includes a master 20 and slaves 30. The slaves 30 in the device 11a include a first slave 30a, a second slave 30b, . . . , an n-th slave 30n.

[0015] The master 20 synchronizes time with the grandmaster 10 based on software and hardware timestamps from the grandmaster 10 .

[0016] The master 20 also transmits a software timestamp indicating the time to each slave 30 via the network 40. The master 20 also transmits a hardware timestamp at predetermined intervals to each slave 30. For example, the master 20 transmits a pulse every second (1PPS) to each slave 30 as the hardware timestamp. The master 20 will be described in detail later.

[0017] The slave 30 synchronizes time with the master 20 based on the software timestamp and hardware timestamp from the master 20. The slave 30 executes predetermined processing according to the time. For example, the slave 30 serves as a radar transmitter and emits radio waves at a predetermined time. The slave 30 also serves as a radar receiver and receives reflected waves from an object to calculate the distance to the object. Note that the configuration of the operation of the slave 30 is not limited to a specific configuration. The slave 30 will be described in detail later.

[0018] The network 40 relays communication between the master 20 and the slaves 30. The network 40 implements a multi-drop connection. That is, the network 40 supplies signals from the master 20 to each slave 30. The network 40 also supplies signals from the slaves 30 to the master 20 and other slaves 30 (second external devices). For example, the network 40 supports Ethernet (e.g., a LAN (Local Area Network)).

[0019] Next, the master 20 will be described. Fig. 2 shows an example of the configuration of the master 20. As shown in Fig. 2, the master 20 includes a processor 21, a memory 22, a first communication unit 23, and a second communication unit 24. The processor 21 is connected to the memory 22, the first communication unit 23, and the second communication unit 24 via a data bus or a predetermined interface.

[0020] The master 20 may include other components as needed in addition to the components shown in FIG. 2, or certain components may be excluded from the master 20.

[0021] The processor 21 controls the overall operation of the master 20. For example, the processor 21 synchronizes the time according to information from the grandmaster 10. The processor 21 also transmits a software timestamp and a hardware timestamp to each slave 30.

[0022] For example, the processor 21 is configured from a CPU or the like. The processor 21 may also be configured from an ASIC (Application Specific Integrated Circuit) or the like. The processor 21 may also be configured from an FPGA (Field Programmable Gate Array) or the like.

[0023] The memory 22 stores various data. For example, the memory 22 functions as a ROM, a RAM, and an NVM. For example, the memory 22 stores a control program, control data, etc. The control program and control data are pre-installed according to the specifications of the master 20. For example, the control program is a program that supports functions realized by the master 20.

[0024] The memory 22 also temporarily stores data being processed by the processor 21. The memory 22 may also store data necessary for executing an application program, execution results of the application program, and the like.

[0025] The first communication unit 23 is an interface for transmitting and receiving data to and from the grandmaster 10, etc. For example, the first communication unit 23 is an interface that supports Ethernet.

[0026] The second communication unit 24 is an interface for transmitting and receiving data to and from each slave 30 via the network 40. The second communication unit 24 also transmits a hardware timestamp to each slave 30 under control of the processor 21. For example, the second communication unit 24 is an interface that supports Ethernet. The first communication unit 23 and the second communication unit 24 may be integrally formed.

[0027] Next, a description will be given of the slaves 30. The first slave 30a, the second slave 30b, ..., the n-th slave 30n have the same configuration, and therefore will be described as a single slave 30.

[0028] Fig. 3 shows an example of the configuration of the slave 30. As shown in Fig. 3, the slave 30 includes a processor 31, a memory 32, and a communication unit 33. The processor 31 is connected to the memory 32 and the communication unit 33 via a data bus or a predetermined interface.

[0029] The slave 30 may include other components as needed in addition to the components shown in FIG. 3, or certain components may be excluded from the slave 30.

[0030] The processor 31 controls the overall operation of the slave 30. For example, the processor 31 synchronizes the time according to information from the master 20.

[0031] For example, the processor 31 is configured from a CPU or the like. The processor 31 may also be configured from an ASIC or the like. The processor 31 may also be configured from an FPGA or the like.

[0032] The memory 32 stores various data. For example, the memory 32 functions as a ROM, a RAM, and an NVM. For example, the memory 32 stores a control program, control data, etc. The control program and control data are pre-installed according to the specifications of the slave 30. For example, the control program is a program that supports functions realized by the slave 30.

[0033] The memory 32 also temporarily stores data being processed by the processor 31. The memory 32 may also store data necessary for executing an application program, execution results of the application program, and the like.

[0034] The memory 32 also stores a slave pulse table in advance, which will be described later.

[0035] The communication unit 33 is an interface for transmitting and receiving data to and from the master 20, etc. For example, the communication unit 33 is an interface that supports Ethernet.

[0036] Next, a description will be given of functions realized by the master 20. The functions realized by the master 20 are realized by the processor 21 executing a program stored in the internal memory, the memory 22, or the like.

[0037] The processor 21 has a function of transmitting a software timestamp and a hardware timestamp to each slave 30 . Here, it is assumed that the processor 21 synchronizes the time with the grandmaster 10 using the software timestamp and hardware timestamp from the grandmaster 10.

[0038] At a predetermined timing, the processor 21 transmits a software timestamp indicating its own time (the current time measured by its own timer or the like) to each slave 30 via the second communication unit 24. The software timestamp includes the current hour, minute, second, etc. as the time. The software timestamp may also include a time less than a second (for example, milliseconds).

[0039] Furthermore, the processor 21 transmits a hardware timestamp to each slave 30 every second through the second communication unit 24. Here, the processor 21 transmits the hardware timestamp to each slave 30 through the second communication unit 24 at the timing when the second of the processor 21's own current time is "0". Here, the hardware timestamp is made up of one pulse having a predetermined width (here, pulse width A).

[0040] Next, we will explain the functions realized by the slave 30. The first slave 30a, the second slave 30b, ... the n-th slave 30n realize the same functions, so we will explain them as functions of the slave 30. The functions realized by the slave 30 are realized by the processor 31 executing a program stored in the internal memory or the memory 32, etc.

[0041] First, the processor 31 has a function of synchronizing the time with the master 20 based on the software timestamp and hardware timestamp from the master 20 .

[0042] The processor 31 receives the software timestamp from the master 20 via the communication unit 33. Upon receiving the software timestamp, the processor 31 synchronizes its own time (the current time measured by its own timer, etc.) with the time indicated by the software timestamp.

[0043] After synchronizing with the time indicated by the software timestamp, the processor 31 waits until it receives a hardware timestamp through the communication unit 33. Upon receiving the hardware timestamp, the processor 31 synchronizes its own time (time down to the second) with the time of the master 20 according to the time when the hardware timestamp was received. For example, the time when the hardware timestamp was received is collected by the physical layer.

[0044] Here, the processor 31 corrects the time so that the seconds of its own time are advanced to the timing (time) at which the hardware time stamp is received.

[0045] Fig. 4 is a timing chart showing an example of an operation for synchronizing time by the processor 31. Fig. 4 shows a software timestamp and a hardware timestamp transmitted by the processor 21. Fig. 4 also shows the time of the processor 31 (the corrected time).

[0046] 4, the processor 21 transmits a software timestamp at a predetermined timing. Here, the processor 21 of the master 20 transmits a software timestamp indicating xx hours, △△ minutes, 0 seconds, and 5 ms.

[0047] When the processor 31 of the slave 30 receives the software timestamp, it sets its own time to xx o'clock △△ minutes 0 seconds 5 ms. After setting its own time to xx o'clock △△ minutes 0 seconds 5 ms, the processor 31 waits for a hardware timestamp.

[0048] Here, the processor 21 of the master 20 transmits a hardware timestamp to the slave 30 . The processor 31 of the slave 30 receives the hardware timestamp through the communication unit 33. Upon receiving the hardware timestamp, the processor 31 corrects its own time so that the time becomes xx hours, △△ minutes, 1 second, and 0 ms at the time when the hardware timestamp is received.

[0049] The processor 31 also has a function of calculating a weighting factor related to the variation in its own time.

[0050] The processor 31 calculates the variance of the difference between its own time and the time of the master 20. That is, the processor 31 calculates the variance of the difference between its own time at the timing when the hardware timestamp is received and the time after correction by the hardware timestamp.

[0051] The processor 31 calculates the variance of the difference over a predetermined period of time. The processor 31 calculates the variance of the difference (time error) according to the following formula.

[0052]

number

[0053] where n is the number of times a hardware timestamp is received in a given period.

[0054]

number

[0055] indicates the fluctuation. yi indicates the corrected time.

[0056]

number

[0057] is the time before correction when the hardware timestamp is received.

[0058] The processor 31 calculates the variance based on the time error. After calculating the variance, the processor 31 calculates a weighting factor based on the variance. The weighting factor is a value that decreases as the variation increases.

[0059] For example, the processor 31 calculates the inverse of the variance as the weighting factor according to the following formula:

[0060]

number

[0061] where Wi is a weighting coefficient and σ is the standard deviation.

[0062] Alternatively, the processor 31 may calculate the reciprocal of the standard deviation as the weighting coefficient according to the following formula:

[0063]

number

[0064] The processor 31 may calculate the weighting coefficient based on the integrated value of the time error. The method by which the processor 31 calculates the weighting coefficient is not limited to a specific method.

[0065] After calculating the weighting coefficients, the processor 31 transmits weighting coefficient information indicating the calculated weighting coefficients to the other slaves 30 via the communication unit 33.

[0066] For example, the processor 31 transmits the weighting factor information every time a hardware time stamp is received. Alternatively, the processor 31 may transmit the weighting factor information when a predetermined period of time has elapsed.

[0067] The processor 31 also has the function of receiving weighting coefficient information from other slaves 30 . The processor 31 receives weighting coefficient information from other slaves via the communication unit 33. Upon receiving the weighting coefficient information, the processor 31 stores in the memory 32 information (such as an identifier) ​​that identifies the slave 30 and the weighting coefficient information in association with each other.

[0068] The processor 31 also has a function of transmitting a synchronization pulse to other slaves 30 via the communication unit 33 .

[0069] As described above, the memory 32 stores in advance a slave pulse table, which indicates the synchronization pulses that each slave 30 transmits.

[0070] Fig. 5 shows an example of the configuration of the slave pulse table. As shown in Fig. 5, the slave pulse table stores "slave name," "pulse width," "number of pulses," and "delay time" in association with each other.

[0071] The "slave name" is a name that identifies the slave 30. The slave pulse table may also indicate an identifier that identifies the slave 30 instead of the "slave name."

[0072] "Pulse width" indicates the width of the synchronization pulse.

[0073] "Number of pulses" indicates the number of pulses that the processor 31 outputs as synchronization pulses.

[0074] The "delay time" is the time from when the processor 31 receives the hardware timestamp from the master 20 until when it transmits the synchronization pulse.

[0075] The processor 31 transmits a synchronization pulse to each slave 30 through the communication unit 33 in accordance with the slave pulse table.

[0076] For example, the processor 31 of the first slave 30a acquires a pulse width B as the pulse width, a pulse count of 1, and a delay time T1 from the slave pulse table. After acquiring the pulse width, pulse count, and delay time, the processor 31 waits until T1 has elapsed since receiving the hardware timestamp.

[0077] When T1 has elapsed, the processor 31 transmits one pulse having a pulse width B to the other slaves 30 via the communication unit 33 as a synchronization pulse.

[0078] The processor 31 similarly transmits the next synchronization pulse to the other slaves 30. That is, the processor 31 transmits one pulse having a pulse width B to the other slaves 30 when T1 has elapsed since the reception of the next hardware timestamp.

[0079] The processor 31 transmits synchronization pulses to the other slaves 30 as described above until it receives a hardware timestamp from the master 20 .

[0080] Furthermore, the processor 31 has a function of synchronizing the time with other slaves 30 in accordance with a synchronization pulse from the other slaves 30 when the hardware time stamp stops.

[0081] The processor 31 determines whether the hardware time stamp from the master 20 has stopped. For example, if the processor 31 does not receive a hardware time stamp within a predetermined period of time since the processor 31 received the immediately preceding hardware time stamp, the processor 31 determines that the hardware time stamp has stopped.

[0082] The processor 31 receives a synchronization pulse from each of the other slaves 30 through the communication unit 33. For example, the processor 31 waits for a synchronization pulse until a predetermined time has elapsed from the time when it is predicted that a hardware timestamp will be received from the master 20 (predicted reception time). In this case, the predicted reception time is the point at which the seconds are advanced (00 ms).

[0083] Upon receiving a synchronization pulse, the processor 31 refers to the slave pulse table to identify the slave 30 that sent each synchronization pulse.

[0084] For example, the processor 31 refers to the slave pulse table to identify the slave 30 corresponding to the pulse width and number of each received synchronization pulse.

[0085] After identifying the slave 30 that is the source of each synchronization pulse, the processor 31 calculates the time of each slave 30 based on the slave pulse table.

[0086] For example, the processor 31 of the first slave 30a identifies the time when it received a synchronization pulse from the second slave 30b. After identifying the time, the processor 31 calculates the time of the second slave 30b (the time being measured by the second slave 30b) based on the identified time and T2, which is the standby time of the second slave. That is, the processor 31 calculates the time of the second slave 30b by assuming that the time when the synchronization pulse was received is the time T2 has elapsed since the predicted reception time.

[0087] The processor 31 calculates the time of the other slaves 30 in a similar manner.

[0088] After calculating the time of the other slaves 30, the processor 31 corrects its own time based on the time of each slave 30 and the weighting coefficient information of each slave 30. That is, the processor 31 corrects its own time so that the time of the slave 30 with the larger weighting coefficient is more strongly reflected.

[0089] The processor 31 corrects its own time according to the following formula:

[0090]

number

[0091] That is, the processor 31 calculates its own time by adding up the weighting coefficients of each slave 30 at the time of each slave 30 and dividing the sum by the sum of the weighting coefficients.

[0092] Here, TIMEi indicates the corrected time of the slave 30, and m is the number of slaves 30.

[0093] The processor 31 may correct its own time by including its own time and weighting coefficient in the above formula, or may correct its own time without including them.

[0094] Fig. 6 shows an example of an operation in which the processor 31 synchronizes time based on a synchronization pulse. Fig. 6 shows synchronization pulses output by the first slave 30a and the second slave 30b. Fig. 6 also shows synchronization pulses flowing through the network 40. Fig. 6 also shows the time of the processor 31 (corrected time).

[0095] 6, the first slave 30a transmits one pulse having a pulse width B as a synchronization pulse to the network 40 after T1 has elapsed from the predicted reception time, and the second slave 30b transmits two pulses having a pulse width B as synchronization pulses after T2 has elapsed from the predicted reception time.

[0096] Processor 31 waits for a synchronization pulse until a predetermined time has elapsed from the predicted reception time. Processor 31 calculates the time of each slave 30 according to the received synchronization pulse. After calculating the time of each slave 30, processor 31 corrects its own time based on the time of each slave 30 and each weighting coefficient.

[0097] Next, an example of the operation of the slave 30 will be described. FIG. 7 is a flowchart illustrating an example of the operation of the slave 30.

[0098] First, the processor 31 of the slave 30 receives a software timestamp from the master 20 via the communication unit 33 (S11). After receiving the software timestamp, the processor 31 receives a hardware timestamp from the master 20 via the communication unit 33 (S12).

[0099] Upon receiving the hardware timestamp, the processor 31 synchronizes its own time based on the hardware timestamp (S13). After synchronizing its own time, the processor 31 transmits a synchronization pulse to the other slaves 30 via the communication unit 33 (S15). After transmitting the synchronization pulse, the processor 31 calculates a weighting factor (S15). After calculating the weighting factor, the processor 31 transmits weighting factor information indicating the weighting factor to the other slaves 30 via the communication unit 33 (S16).

[0100] After transmitting the weighting factor information to the other slaves, the processor 31 receives the weighting factor information from the other slaves 30 through the communication unit 33 (S17). Upon receiving the weighting factor information, the processor 31 stores the received weighting factor information in the memory 32 (S18).

[0101] After storing the received weighting coefficient information in memory 32, processor 31 determines whether hardware time stamping has stopped (S19). If it determines that hardware time stamping has not stopped (S19, NO), processor 31 returns to S11.

[0102] When it is determined that the hardware time stamp has stopped (S19, YES), the processor 31 transmits a synchronization pulse to the other slave 30 through the communication unit 33 after a delay time has elapsed from the predicted reception time (S20). After transmitting the synchronization pulse, the processor 31 receives the synchronization pulse from the other slave 30 through the communication unit 33 (S21).

[0103] When a synchronization pulse is received from another slave 30, the processor 31 calculates the time of the other slave 30 (S22). After calculating the time of the other slave 30, the processor 31 corrects its own time based on the time of the other slave 30 and each weighting coefficient information (S23).

[0104] After correcting its own time, processor 31 returns to S19.

[0105] If the determination in S19 is that S12 has occurred, the processor 31 may set S18 to NO. Furthermore, the processor 31 may execute S20 and S21 simultaneously in parallel.

[0106] Furthermore, the processor 31 may correct its own time based on the synchronization pulse and weighting factor information from the other slaves 30 even if the hardware time stamp is not stopped.

[0107] The synchronization system configured as described above calculates a weighting factor based on the time dispersion of each slave before the hardware time stamp from the master stops. When the hardware time stamp from the master stops, the synchronization system synchronizes the time of the slave based on each time of the slave and the weighting factor. As a result, the synchronization system can synchronize the time between the slaves even if the hardware time stamp from the master stops. (Second embodiment) Next, a second embodiment will be described. The synchronization system according to the second embodiment differs from that according to the first embodiment in that the master handles leap seconds. Therefore, the other points are given the same reference numerals and detailed descriptions are omitted.

[0108] The configuration of the synchronization system 1 according to the second embodiment is similar to that according to the first embodiment, and therefore a description thereof will be omitted.

[0109] The memory 22 of the master 20 stores a master pulse table in advance. The master pulse table indicates the configuration of the hardware timestamp that the master 20 transmits.

[0110] Fig. 8 shows an example of the configuration of the master pulse table. As shown in Fig. 8, the master pulse table shows the configuration of hardware time stamps in normal operation, when leap seconds are added, and when leap seconds are subtracted.

[0111] The master pulse table shows one pulse with pulse width A as a hardware timestamp under normal circumstances. The master pulse table also shows one pulse with pulse width D as a hardware timestamp when leap seconds are added. The master pulse table also shows two pulses with a pulse width E as a hardware timestamp when leap seconds are subtracted.

[0112] Next, we will explain the functions realized by the master 20. The functions realized by the master 20 are realized by the processor 21 executing a program stored in the internal memory or the memory 22. The master 20 realizes the following functions in addition to the functions of the master 20 according to the first embodiment.

[0113] The processor 21 has a function of transmitting a hardware timestamp corresponding to the leap second addition or leap second subtraction when a leap second is added or subtracted.

[0114] When a leap second is added, the processor 21 references the master pulse table to obtain the configuration of the hardware timestamp corresponding to the leap second addition. Here, the processor 21 obtains a pulse width D as the pulse width and 1 as the number of pulses.

[0115] When the processor 21 acquires the pulse width D as the pulse width and the pulse number 1, the processor 21 transmits one pulse having the pulse width D as a hardware timestamp to each slave 30 via the second communication unit 24.

[0116] Furthermore, when leap seconds are subtracted, the processor 21 references the master pulse table to acquire the configuration of the hardware timestamp corresponding to the time of leap second subtraction. Here, the processor 21 acquires a pulse width E as the pulse width and 2 as the number of pulses.

[0117] When the processor 21 acquires the pulse width E as the pulse width and the number of pulses 2, the processor 21 transmits two pulses having the pulse width E as a hardware timestamp to each slave 30 via the second communication unit 24.

[0118] FIG. 9 shows an example of a hardware timestamp sent by the processor 21. As shown in FIG. 9, the processor 21 transmits one pulse having a pulse width D as a hardware timestamp to each slave 30 via the second communication unit 24 when leap seconds are added.

[0119] The processor 31 of the slave 30 also receives the hardware timestamp via the communication unit 33. The processor 31 performs a process of adding leap seconds based on the hardware timestamp. For example, the processor 31 may not change the system time, but may use the real time for processing that uses the time (distributed insertion method). The processor 31 may also use the system time for processing that uses the time (immediate adjustment).

[0120] Furthermore, the processor 21 transmits two pulses having a pulse width E as a hardware timestamp to each slave 30 via the second communication unit 24 when leap seconds are subtracted.

[0121] The processor 31 of the slave 30 also receives the hardware timestamp through the communication unit 33. The processor 31 performs a process of subtracting leap seconds based on the hardware timestamp. For example, the processor 31 may not change the system time, but may use the real time for time-based processing (distributed insertion method). The processor 31 may also use the system time for time-based processing (immediate adjustment).

[0122] The synchronization system configured as described above transmits a hardware timestamp indicating the leap second addition or subtraction to the slave when a leap second is added or subtracted, allowing the synchronization system to properly synchronize the time between slaves even when a leap second is added or subtracted. (Third embodiment) Next, a third embodiment will be described. The synchronization system according to the third embodiment differs from that according to the first embodiment in that the master intermittently transmits hardware timestamps. Therefore, the other features are denoted by the same reference numerals and detailed descriptions are omitted.

[0123] The configuration of the synchronization system 1 according to the third embodiment is similar to that according to the first embodiment, and therefore a description thereof will be omitted.

[0124] Next, we will explain the functions realized by the master 20. The functions realized by the master 20 are realized by the processor 21 executing a program stored in the internal memory or the memory 22. The master 20 realizes the following functions in addition to the functions of the master 20 according to the first embodiment.

[0125] The processor 21 has a function of transmitting a hardware timestamp based on the time accuracy of each slave 30 . As previously mentioned, each slave 30 transmits weighting factor information to the network 40 .

[0126] The processor 21 receives the weighting factor information of each slave 30 through the second communication unit 24. Upon receiving the weighting factor information, the processor 21 calculates an evaluation value indicating the accuracy of the time based on the weighting factor information.

[0127] For example, the processor 21 calculates the sum or moving average of the weighting coefficients indicated by the weighting coefficient information as the evaluation value. In this example, the evaluation value increases as the standard deviation of each slave 30 decreases. Therefore, the larger the evaluation value, the higher the accuracy of each slave 30.

[0128] The processor 21 transmits a hardware timestamp based on the evaluation value to each slave 30. For example, if the evaluation value is equal to or less than a predetermined threshold (if the accuracy is poor), the processor 21 transmits a hardware timestamp to each slave 30 via the second communication unit 24.

[0129] Furthermore, if the evaluation value is greater than a predetermined threshold (if the accuracy is high), the processor 21 does not transmit a hardware timestamp to each slave 30.

[0130] FIG. 10 shows an example of a hardware timestamp sent by the processor 21. As shown in FIG. 10, if the time accuracy of each slave 30 is poor, the processor 21 transmits a hardware time stamp to each slave 30 via the second communication unit 24 at the next timing (here, the timing when the seconds are advanced).

[0131] Furthermore, if the accuracy of the time of each slave 30 is good, the processor 21 will not transmit a hardware time stamp to each slave 30 at the next timing.

[0132] The processor 31 of the slave 30 may transmit a synchronization pulse if it does not receive a hardware timestamp. The processor 31 may also transmit a synchronization pulse if it does not receive a hardware timestamp for a predetermined period of time.

[0133] The processor 21 may also stop the hardware time stamp when the accuracy of the time of each slave 30 is acceptable for a predetermined number of consecutive times. The processor 21 may also resume transmission of the hardware time stamp when the accuracy of the time of each slave 30 is poor for a predetermined number of consecutive times.

[0134] The processor 31 may also implement the functions of the master 20 according to the second embodiment.

[0135] In the synchronization system configured as described above, the master does not transmit a hardware timestamp to each slave when the time of each slave is synchronized, which reduces the power consumption and EMI (Electromagnetic Interference) of the master. (Fourth embodiment) Next, a fourth embodiment will be described. The synchronization system according to the fourth embodiment differs from that according to the first embodiment in that it does not include the grandmaster 10 and the master 20. Therefore, the other components are given the same reference numerals and detailed description thereof will be omitted.

[0136] Fig. 11 shows an example of the configuration of a synchronization system 1' according to the fourth embodiment. As shown in Fig. 11, the synchronization system 1' includes a device 11. Note that the synchronization system 1' may include a plurality of devices 11.

[0137] The configuration of the device 11 is similar to that of the first embodiment.

[0138] Next, we will explain the functions realized by the slave 30. The functions realized by the slave 30 are realized by the processor 31 executing a program stored in the internal memory, the memory 32, or the like. The slave 30 realizes the following functions in addition to the functions of the slave 30 according to the first embodiment.

[0139] The processor 31 has a function of calculating a weighting factor based on the synchronization pulses from the other slaves 30 .

[0140] As described above, the processor 31 calculates the time of each slave 30 (here, the time that each slave 30 is measuring (for example, the system startup time)) based on the synchronization pulse of each slave 30. After calculating the time of each slave 30, the processor 31 calculates the difference between the time of each slave 30 and its own time over a predetermined period. After calculating the difference, the processor 31 calculates the dispersion of the difference (time error). The method by which the processor 31 calculates the variance is as described above.

[0141] After calculating the variance, the processor 31 calculates a weighting factor based on the variance. The method by which the processor 31 calculates the weighting coefficients is as described above.

[0142] After calculating the weighting coefficients, the processor 31 transmits weighting coefficient information indicating the calculated weighting coefficients to the other slaves 30 via the communication unit 33.

[0143] Next, an example of the operation of the slave 30 will be described. FIG. 12 is a flowchart for explaining an example of the operation of the slave 30.

[0144] First, the processor 31 of the slave 30 transmits a synchronization pulse to the other slave 30 through the communication unit 33 at a predetermined timing (S31). After transmitting the synchronization pulse to the other slave 30, the processor 31 receives the synchronization pulse from the other slave 30 through the communication unit 33 (S32).

[0145] When a synchronization pulse is received from another slave 30, the processor 31 calculates the time of the other slave 30 (S33). After calculating the time of the other slave 30, the processor 31 calculates a weighting coefficient (S34).

[0146] After calculating the weighting coefficients, the processor 31 transmits weighting coefficient information indicating the weighting coefficients to the other slaves 30 via the communication unit 33 (S35).

[0147] After transmitting the weighting factor information to the other slaves, the processor 31 receives the weighting factor information from the other slaves 30 through the communication unit 33 (S36). Upon receiving the weighting factor information, the processor 31 corrects its own time based on the time of the other slaves 30 and the weighting factor information (S37).

[0148] After correcting its own time, the processor 31 returns to S31. The processor 31 may execute S31 and S32 simultaneously in parallel.

[0149] The synchronization system configured as described above calculates a weighting factor for each slave according to the time variation among the slaves. The synchronization system synchronizes the time of each slave based on the weighting factor of each slave. As a result, the synchronization system can synchronize the time of each slave without having a master.

[0150] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. The inventions described in the original claims of this application are set forth below. [1] a communication unit that connects to a first external device and a second external device; receiving a hardware timestamp from the first external device through the communication unit; and synchronizing its own time based on the hardware timestamp; Calculating the error of its own time based on the timing of receiving the hardware timestamp; transmitting weighting coefficient information indicating a weighting coefficient based on the error to the second external device via the communication unit; receiving the weighting coefficient information from the second external device through the communication unit; transmitting a synchronization pulse to the second external device through the communication unit; receiving the synchronization pulse from the second external device through the communication unit; calculating the time of the second external device based on the timing of receiving the synchronization pulse; a processor that corrects its own time based on the time of the second external device and the weighting coefficient information; An information processing device comprising: [2] The processor: correcting its own time by multiplying the time of the second external device by the weighting coefficient indicated by the weighting coefficient information from the second external device; 2. The information processing device according to claim 1. [3] The processor: correcting its own time by dividing the sum of a value obtained by multiplying the time of the second external device and the weighting coefficient indicated by the weighting coefficient information from the second external device and a value obtained by multiplying its own time and its own weighting coefficient by the sum of the weighting coefficient of the second external device and its own weighting coefficient; 3. The information processing device according to claim 2. [4] The weighting factor is the inverse of the variance of the error. 4. An information processing device according to any one of claims 1 to 3. [5] The weighting factor is the inverse of the standard deviation of the error. 4. An information processing device according to any one of claims 1 to 3. [6] the processor transmits the synchronization pulse to the second external device after a predetermined delay time has elapsed from the time when the hardware timestamp is expected to be received through the communication unit; 6. An information processing device according to any one of appendices 1 to 5. [7] the processor identifies the second external device based on the width and number of pulses constituting the synchronization pulse from the second external device, and calculates the time of the identified second external device based on the delay time of the identified second external device; 7. The information processing device according to claim 6. [8] a communication unit for connecting to an external device; receiving a synchronization pulse from the external device through the communication unit; Calculating the error of its own time based on the timing of receiving the synchronization pulse, transmitting weighting coefficient information indicating a weighting coefficient based on the error to the external device via the communication unit; receiving the weighting coefficient information from the external device through the communication unit; receiving the synchronization pulse from the external device through the communication unit; calculating the time of the external device based on the timing of receiving the synchronization pulse; correcting its own time based on the time of the external device and the weighting coefficient information; a processor; An information processing device comprising: [9] a communication unit for connecting to an external device; When a leap second is added, a hardware timestamp indicating the leap second is transmitted to the external device via the communication unit; When a leap second is subtracted, a hardware timestamp indicating the leap second is transmitted to the external device via the communication unit. a processor; An information processing device comprising:

[10] a communication unit for connecting to an external device; receiving weighting factor information indicating a weighting factor related to a time variance of the external device via the communication unit; transmitting a hardware timestamp to the external device through the communication unit based on the weighting factor; a processor; An information processing device comprising: [Explanation of symbols]

[0151] 1...synchronization system, 1'...synchronization system, 10...grand master, 11...device, 20...master, 21...processor, 22...memory, 23...first communication unit, 24...second communication unit, 30...slave, 31...processor, 32...memory, 33...communication unit, 40...network.

Claims

1. a first communication unit connected to the grandmaster device; a second communication unit connected to the slave device; receiving a hardware timestamp from the grandmaster device through the first communication unit; synchronizing its own time based on said hardware timestamp; Calculating the error of its own time based on the timing of receiving the hardware timestamp; transmitting its own weighting coefficient information indicating a weighting coefficient based on the error to the slave device via the second communication unit; receiving weight coefficient information of the slave device from the slave device via the second communication unit; transmitting a hardware timestamp to the slave device through the second communication unit; receiving a synchronization pulse transmitted from the slave device via the second communication unit after waiting a predetermined delay time since the hardware time stamp was received by the slave device; calculating the time of the slave device based on the timing of receiving the synchronization pulse; and correcting the time of the slave device based on the time of the slave device and weighting coefficient information of the slave device. a processor; A master device comprising:

2. The processor: the slave device corrects its own time by integrating the time of the slave device with the weighting factor indicated by the weighting factor information from the slave device; The master device of claim 1 .

3. The processor: correcting its own time by dividing the sum of a value obtained by multiplying the time of the slave device and the weighting factor indicated by the weighting factor information from the slave device and a value obtained by multiplying its own time and its own weighting factor by the sum of the weighting factor of the slave device and its own weighting factor; The master device according to claim 2 .

4. The weighting factor is the inverse of the variance of the error.

4. The master device according to claim 1.

5. The weighting factor is the inverse of the standard deviation of the error.

4. The master device according to claim 1.

6. the processor transmits the synchronization pulse to the slave device after a predetermined delay time has elapsed from the time when the hardware timestamp is expected to be received through the first communication unit; 6. The master device according to claim 1.

7. the processor identifies the slave device based on the width and number of pulses constituting the synchronization pulse from the slave device, and calculates the time of the identified slave device based on the delay time of the identified slave device; The master device according to claim 6 .

8. The processor further comprises: When a leap second is added, a hardware timestamp indicating the leap second is transmitted to the slave device via the second communication unit; When a leap second is subtracted, a hardware timestamp indicating the leap second is transmitted to the slave device via the second communication unit.

8. The master device according to claim 1.

9. a communication unit connected to the master device according to any one of claims 1 to 8; receiving a synchronization pulse from the master device through the communication unit; Calculating the error of its own time based on the timing of receiving the synchronization pulse, transmitting weighting coefficient information indicating a weighting coefficient based on the error to the master device via the communication unit; receiving the weighting coefficient information from the master device through the communication unit; receiving the synchronization pulse from the master device through the communication unit; calculating the time of the master device based on the timing of receiving the synchronization pulse; and correcting its own time based on the time of the master device and the weighting coefficient information. a processor; A slave device comprising:

10. A device connectable to the master device according to any one of claims 1 to 8, a communication unit for connecting to other slave devices; receiving weighting coefficient information indicating a weighting coefficient related to a time variance of the other slave device via the communication unit; transmitting a hardware timestamp to the other slave device through the communication unit based on the weighting coefficient; a processor; A slave device comprising:

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