Image pickup device

Abstract

To provide an imaging element for adding and reading pixel signals of different columns.SOLUTION: The imaging device includes a first photoelectric conversion part and a second photoelectric conversion part provided in a row direction of the pixel part, a first signal line 25a2 for outputting first signals based on charges generated by the first photoelectric conversion part, second signal lines 25a1 and 25a3 for outputting second signals generated by the second photoelectric conversion part, a third 1AD conversion part 43a2 for converting at least one of the first signals and the second signals into digital signals, fourth 2AD conversion parts 43a1 and 43a3 for converting the second signals into digital signals, a first outputting part 1AD for outputting the signals converted into the digital signals by the third conversion part to a processing part for processing the signals, and a second outputting part for outputting the signals converted into the digital signals by the third conversion part to the processing part, a second output device, a third output device, and a fourth output device. 55c 60a 62c 62a 55b62b 55a 2AD.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] BACKGROUND ART Conventionally, imaging devices have been known in which a plurality of signal lines are arranged to output pixel signals (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2010 / 113393 Summary of the Invention

[0004] According to a first aspect of the invention, an imaging device includes a first photoelectric conversion unit and a second photoelectric conversion unit that generate charges by photoelectric conversion and are arranged in a row direction, a first signal line that outputs a first signal based on the charges generated by the first photoelectric conversion unit and is arranged in a column direction, a second signal line that outputs a second signal based on the charges generated by the second photoelectric conversion unit and is arranged in the column direction, a first AD conversion unit that converts at least one of the first signal and the second signal, which are analog signals, into a digital signal, and a second AD conversion unit that converts the second signal, which is analog, into a digital signal. a first output unit that outputs at least one of the first signal and the second signal converted into a digital signal by the first AD conversion unit to a processing unit that processes the signal; a second output unit that outputs the second signal converted into a digital signal by the second AD conversion unit to the processing unit; and a control unit that performs first control to output the first signal and the second signal to the processing unit by the first output unit, and second control to output the first signal to the processing unit by the first output unit and the second signal to the processing unit by the second output unit. [Brief explanation of the drawings]

[0005] [Figure 1]1 is a diagram illustrating an example of the configuration of an imaging device according to a first embodiment. [Figure 2] FIG. 1 is a diagram illustrating an example of the configuration of an imaging element according to a first embodiment. [Figure 3] 1 is a diagram illustrating an example of the configuration of a pixel of an imaging element according to a first embodiment. [Figure 4] 1 is a diagram illustrating an example of the configuration of a portion of an imaging element according to a first embodiment. [Figure 5] FIG. 2 is a diagram illustrating an example of the layout of a portion of an imaging element according to the first embodiment. [Figure 6] 4A and 4B are diagrams comparing read control according to the first embodiment with read control according to a comparative example. [Figure 7] FIG. 10 is a diagram illustrating an example of the configuration of a portion of an imaging element according to Modification 1. [Figure 8] FIG. 10 is a diagram illustrating an example of the configuration of a portion of an imaging element according to Modification 2. [Figure 9] FIG. 11 is a diagram illustrating an example of the configuration of a portion of an imaging element according to Modification 3. DETAILED DESCRIPTION OF THE INVENTION

[0006] (First embodiment) 1 is a diagram showing an example of the configuration of a camera 1, which is an example of an imaging device according to a first embodiment. The camera 1 includes a photographing optical system (imaging optical system) 2, an image sensor 3, a control unit 4, a memory 5, a display unit 6, and an operation unit 7. The photographing optical system 2 has multiple lenses, including a focus adjustment lens (focus lens), and an aperture stop, and forms a subject image on the image sensor 3. The photographing optical system 2 may be detachable from the camera 1.

[0007] The imaging element 3 is an imaging element such as a CMOS image sensor or a CCD image sensor. The imaging element 3 receives a light beam that has passed through the photographing optical system 2 and captures an image of a subject formed by the photographing optical system 2. The imaging element 3 has a plurality of pixels, each having a photoelectric conversion unit, arranged two-dimensionally (in the row and column directions). The photoelectric conversion element is composed of a photodiode (PD). The imaging element 3 photoelectrically converts the received light to generate a signal and outputs the generated signal to the control unit 4.

[0008] The memory 5 is a recording medium such as a memory card. Image data, control programs, etc. are recorded in the memory 5. Writing data to the memory 5 and reading data from the memory 5 are controlled by the control unit 4. The display unit 6 displays an image based on the image data, information related to shooting such as the shutter speed and aperture value, and a menu screen, etc. The operation unit 7 includes various setting switches such as a release button, a power switch, and switches for switching between various modes, and outputs signals to the control unit 4 based on the respective operations.

[0009] The control unit 4 is configured with a processor such as a CPU, FPGA, or ASIC, and memories such as ROM and RAM, and controls each unit of the camera 1 based on a control program. The control unit 4 supplies a signal that controls the image sensor 3 to the image sensor 3, thereby controlling the operation of the image sensor 3. The control unit 4 also performs various image processing on the signal output from the image sensor 3 to generate image data. The control unit 4 also functions as an image generation unit that generates image data, and generates still image data and moving image data based on the signal output from the image sensor 3. The image processing includes well-known image processing such as tone conversion processing and color interpolation processing.

[0010] The control unit 4 performs a process of individually reading out the signal from each pixel of the image sensor 3, and a process of adding and reading out the signals from multiple pixels. For example, the control unit 4 performs a process of adding and reading out the signals from multiple pixels when displaying a through image (live view image) of a subject on the display unit 6 or when shooting a video. The control unit 4 also performs a process of individually reading out the signals from each pixel when shooting a high-resolution still image.

[0011] 2 is a diagram showing an example of the configuration of an image sensor according to the first embodiment. The image sensor 3 includes a pixel section (pixel region) 20, a column circuit section 40 (column circuit section 40a, column circuit section 40b), a horizontal transfer section 50 (horizontal transfer section 50a, horizontal transfer section 50b), a processing section 60 (processing section 60a, processing section 60b), and a signal output section 70 (signal output section 70a, signal output section 70b). The image sensor 3 also includes a readout control section 100, a first supply section 110 (first supply section 110a, first supply section 110b), and a second supply section 120 (second supply section 120a, second supply section 120b). The number and arrangement of pixels arranged in the pixel section 20 are not limited to those shown in the figure.

[0012] Each pixel 10 is provided with one of three color filters 18 having different spectral characteristics of red (R), green (G), or blue (B). The pixels 10 include pixels (hereinafter referred to as R pixels) having color filters 18 with spectral characteristics that separate incident light into a first wavelength range (red (R) light), pixels (hereinafter referred to as G pixels) having color filters 18 with spectral characteristics that separate incident light into a second wavelength range (green (G) light), and pixels (hereinafter referred to as B pixels) having color filters 18 with spectral characteristics that separate incident light into a third wavelength range (blue (B) light).

[0013] 2, the image sensor 3 has a first pixel row in which R pixels 10 and G pixels 10 are alternately arranged in the left-right direction, i.e., the row direction (horizontal direction), and a second pixel row in which G pixels 10 and B pixels 10 are alternately arranged in the row direction. The first pixel row and the second pixel row are alternately arranged in the column direction. As such, in this embodiment, the R pixels 10, G pixels 10, and B pixels 10 are arranged according to a Bayer array.

[0014] The image sensor 3 is provided with vertical signal lines 25 (vertical signal lines 25a, 25b) for each pixel column, which is a column of pixels 10 arranged in the vertical direction, i.e., the column direction (vertical direction). In the example shown in Fig. 2, the vertical signal lines 25a are connected to the odd-numbered pixel columns, respectively. The vertical signal lines 25b are connected to the even-numbered pixel columns, respectively.

[0015] The readout control unit 100 is provided in common to multiple pixel columns. The readout control unit 100 is controlled by the control unit 4 of the camera 1, and supplies signals such as a signal TX, a signal RST, and a signal SEL, which will be described later, to each pixel 10 to control the operation of each pixel 10. The readout control unit 100 supplies signals to the gates of each transistor in the pixels 10 to turn the transistor on (connected state, conductive state, short-circuited state) or off (disconnected state, non-conductive state, open state, blocked state). The signal of a pixel in the pixel unit 20 selected by the readout control unit 100 is output to a vertical signal line 25 connected to that pixel 10.

[0016] A column circuit unit 40a is provided for odd-numbered pixel columns among the plurality of pixels 10 in the pixel unit 20. The column circuit unit 40a includes a plurality of current sources 41a, a horizontal adder 42a, and a plurality of analog-to-digital conversion units (AD conversion units) 43a. The current sources 41a and AD conversion units 43a in the column circuit unit 40a are provided for each vertical signal line 25a. The current sources 41a are connected to each pixel 10 via the vertical signal line 25a. The current sources 41a generate currents for reading out signals from the pixels 10 and supply the generated currents to the vertical signal lines 25a and each pixel 10.

[0017] As will be described later, the horizontal adder 42a is composed of multiple switches and performs addition of pixel signals output to the vertical signal line 25a. The readout control unit 100 controls the on / off of the multiple switches that make up the horizontal adder 42a to control the addition process of signals from multiple pixels arranged in the row direction (horizontal direction). The AD conversion unit 43a converts signals input from each pixel 10 via the horizontal adder 42a into digital signals and outputs the converted digital signals to the horizontal transfer unit 50a.

[0018] A column circuit unit 40b is provided for even-numbered pixel columns among the plurality of pixels 10 in the pixel unit 20. The column circuit unit 40b includes a plurality of current sources 41b, a horizontal adder 42b, and a plurality of AD conversion units 43b. The current sources 41b and AD conversion units 43b in the column circuit unit 40b are provided for each vertical signal line 25b. The current sources 41b are connected to each pixel 10 via the vertical signal lines 25b. The current sources 41b generate currents for reading signals from the pixels 10 and supply the generated currents to the vertical signal lines 25b and each pixel 10.

[0019] As will be described later, the horizontal adder 42b is composed of a plurality of switches and performs addition between pixel signals output to the vertical signal line 25b. The readout control unit 100 controls the on / off of the plurality of switches that make up the horizontal adder 42b to control the addition process of signals between a plurality of pixels arranged in the row direction (horizontal direction). The AD conversion unit 43b converts signals input from each pixel 10 via the horizontal adder 42b into digital signals and outputs the converted digital signals to the horizontal transfer unit 50b.

[0020] The horizontal transfer unit 50a is provided for the multiple AD conversion units 43a and sequentially outputs the signals converted into digital signals by each AD conversion unit 43a to the processing unit 60a. The horizontal transfer unit 50b is provided for the multiple AD conversion units 43b and sequentially outputs the signals converted into digital signals by each AD conversion unit 43b to the processing unit 60b. In this way, in the image sensor 3, signals from pixels in odd-numbered columns and signals from pixels in even-numbered columns are read out via separate paths.

[0021] The first supply unit 110a has a current source, generates a current for operating the AD conversion unit 43a, and supplies the generated current to the AD conversion unit 43a. The first supply unit 110b has a current source, generates a current for operating the AD conversion unit 43b, and supplies the generated current to the AD conversion unit 43b. The first supply unit 110a and the first supply unit 110b are each controlled by the read control unit 100.

[0022] The processing units 60a and 60b each include an amplifier circuit, a decoder circuit, and the like. The pixel signals converted into digital signals are input to the processing unit 60a from the horizontal transfer unit 50a. The processing unit 60a performs signal processing such as code conversion and correlated double sampling on the signals input from the horizontal transfer unit 50a, and outputs the resulting signals to the signal output unit 70a. The pixel signals converted into digital signals are input to the processing unit 60b from the horizontal transfer unit 50b. The processing unit 60b performs signal processing such as code conversion and correlated double sampling on the signals input from the horizontal transfer unit 50b, and outputs the resulting signals to the signal output unit 70b.

[0023] The second supply unit 120a generates a control signal for operating the processing unit 60a, which in this embodiment is a pulse signal (pulse), and supplies the generated pulse signal to the processing unit 60a. The second supply unit 120b generates a control signal for operating the processing unit 60b, which in this embodiment is a pulse signal, and supplies the generated pulse signal to the processing unit 60b. The second supply units 120a and 120b are each controlled by the read control unit 100. Note that these control signals may be signals of a constant potential (for example, a power supply potential).

[0024] The signal output units 70a and 70b each have an output circuit compatible with a high-speed interface such as SLVS or LVDS. The signal output unit 70a outputs (transmits) at high speed the signal input from the processing unit 60a to the control unit 4 of the camera 1. The signal output unit 70b outputs at high speed the signal input from the processing unit 60b to the control unit 4.

[0025] 3 is a diagram showing an example of the configuration of a pixel of the image sensor according to the first embodiment. A pixel 10 has a photoelectric conversion unit 11, a transfer unit 12, a reset unit 13, a floating diffusion (FD) 14, an amplifier unit 15, and a selection unit 16. The photoelectric conversion unit 11 is a photodiode PD, which converts incident light into electric charges and accumulates the photoelectrically converted electric charges.

[0026] The transfer unit 12 is composed of a transistor M1 controlled by a signal TX, and transfers the charges photoelectrically converted by the photoelectric conversion unit 11 to the FD 14. The transistor M1 is a transfer transistor. The capacitance C of the FD 14 accumulates (holds) the charges transferred to the FD 14 and converts them into a voltage.

[0027] The amplifier 15 is composed of a transistor M3 whose gate (terminal) is connected to the FD 14, and outputs a signal based on the voltage of the capacitance C of the FD 14. The amplifier 15 is connected to a vertical signal line 25 via a selection unit 16. The transistor M3 is an amplifying transistor. The amplifier 15 and selection unit 16 constitute an output unit that generates and outputs a signal based on the charge generated by the photoelectric conversion unit 11.

[0028] The reset unit 13 is composed of a transistor M2 controlled by a signal RST, and discharges the charge accumulated in the FD 14 and resets the voltage of the FD 14. The transistor M2 is a reset transistor. The selection unit 16 is composed of a transistor M4 controlled by a signal SEL, and electrically connects or disconnects the amplifier unit 15 and the vertical signal line 25. When the transistor M4 of the selection unit 16 is in the on state, it outputs a signal from the amplifier unit 15 to the vertical signal line 25. The transistor M4 is a selection transistor.

[0029] The pixels 10 sequentially output to the vertical signal lines 25 a signal (dark signal) when the voltage of the FD 14 is reset and a signal (photoelectric conversion signal) corresponding to the charge transferred from the photoelectric conversion unit 11 to the FD 14 by the transfer unit 12. The dark signal is an analog signal indicating a reference level for the photoelectric conversion signal. The photoelectric conversion signal is an analog signal generated based on the charge photoelectrically converted by the photoelectric conversion unit 11. The dark signal and photoelectric conversion signal sequentially output from the pixels 10 are input to the horizontal adder 42 via the vertical signal lines 25.

[0030] Fig. 4 is a diagram showing an example of the configuration of a portion of the image sensor according to the first embodiment. Fig. 4 shows some pixels 10 of the multiple pixels provided in the image sensor 3, a column circuit unit 40a, a horizontal transfer unit 50a, a processing unit 60a, and a signal output unit 70a. Furthermore, Fig. 4 illustrates 85 pixels 10, with 17 pixels in the row direction and 5 pixels in the column direction, with the pixel 10 in the upper left corner being pixel 10(1,1) in the first row and first column and the pixel 10 in the lower right corner being pixel 10(5,17) in the fifth row and 17th column.

[0031] The horizontal addition unit 42a has switches SW1 (SW1a to SW1i in FIG. 4) that connect or disconnect the vertical signal lines 25a (vertical signal lines 25a1 to 25a9 in FIG. 4) and the AD conversion units 43a (AD conversion units 43a1 to 43a9 in FIG. 4). The horizontal addition unit 42a also has switches SW2 (SW2a to SW2f in FIG. 4) that connect or disconnect adjacent vertical signal lines 25a. The switches SW2 are connectors that connect the vertical signal lines 25a together. The switches SW1 and SW2 are on / off controlled by the readout control unit 100 (see FIG. 2).

[0032] The AD conversion unit 43a includes a comparison unit 44 and a storage unit 45, and converts pixel signals input via the horizontal addition unit 42a into digital signals with a predetermined number of bits. The comparison unit 44 includes a comparator circuit. A current for operating the comparator circuit is supplied to the comparison unit 44 of the AD conversion unit 43a from a first supply unit 110a (see FIG. 2 ). The comparison unit 44 compares the signals output from the pixels 10 with a reference signal (ramp signal) that changes constantly over time, and outputs an output signal that is the comparison result to the storage unit 45.

[0033] The storage unit 45 is composed of a plurality of latch circuits corresponding to the number of bits of the digital signal to be stored. The storage unit 45 receives an output signal indicating the comparison result from the comparison unit 44 and a clock signal indicating a count value from a counter circuit (not shown). Based on the output signal from the comparison unit 44 and the clock signal from the counter circuit, the storage unit 45 stores, as a digital signal, a count value corresponding to the elapsed time from when the comparison by the comparison unit 44 starts until the comparison result is inverted. In other words, based on the signal output from the comparison unit 44, the storage unit 45 stores, as a digital signal, a count value corresponding to the time until the magnitude relationship between the level of the signal output from the pixel 10 and the level of the reference signal changes (is inverted).

[0034] When the dark signal of pixel 10 is input to the comparison unit 44 via the horizontal adder 42a, the comparison unit 44 compares the dark signal with the reference signal and outputs the comparison result to the storage unit 45. The storage unit 45 stores, based on the comparison result of the comparison unit 44 and the clock signal, a count value corresponding to the elapsed time from when the comparison unit 44 starts comparison to when the comparison result is inverted, as a digital signal corresponding to the dark signal. Furthermore, when the photoelectric conversion signal of pixel 10 is input to the comparison unit 44 via the horizontal adder 42a, the comparison unit 44 compares the photoelectric conversion signal with the reference signal and outputs the comparison result to the storage unit 45. Based on the comparison result of the comparison unit 44 and the clock signal, the storage unit 45 stores, as a digital signal corresponding to the photoelectric conversion signal, a count value corresponding to the elapsed time from when the comparison unit 44 starts comparison to when the comparison result is inverted.

[0035] In this way, the AD conversion unit 43a converts the photoelectric conversion signal, which is an analog signal, into a digital signal with a predetermined number of bits, and converts the dark signal, which is an analog signal, into a digital signal with a predetermined number of bits. The AD conversion unit 43a also has an output circuit (not shown) that operates with a current supplied from the first supply unit 110a, and outputs the digital signal stored in the memory unit 45 to the horizontal transfer unit 50a.

[0036] The horizontal transfer unit 50a includes a switch SW3 (SW3a to SW3i in FIG. 4), a data lane 55 (data lanes 55a to 55c), a sense amplifier 62 (sense amplifiers 62a to 62c), and an AND circuit 61. The switch SW3 is controlled to be turned on or off by the read control unit 100 (see FIG. 2), and connects or disconnects the AD conversion unit 43a and the data lane 55.

[0037] The data lanes 55 are provided for the plurality of AD conversion units 43a, and transfer (transmit) digital signals input from each AD conversion unit 43a via switch SW3 to the sense amplifier 62. The data lanes 55 are transmission paths for transmitting pixel signals converted into digital signals. In the example shown in FIG. 4, the horizontal transfer unit 50a has data lanes 55a, 55b, and 55c. Each of the data lanes 55a to 55c is configured with a plurality of signal lines corresponding to the number of bits of the digital signal to be transmitted.

[0038] The sense amplifier 62 is configured with a plurality of amplifier circuits corresponding to the number of bits of the input digital signal, and is provided for each data lane 55. Sense amplifier 62a is provided for data lane 55a, sense amplifier 62b is provided for data lane 55b, and sense amplifier 62c is provided for data lane 55c. A control signal for operating the amplifier circuit, which is a pulse signal in this embodiment, is supplied to each of the sense amplifiers 62a to 62c from a second supply unit 120a (see FIG. 2). The sense amplifiers 62a to 62c amplify and read out the signal input to the data lane 55 connected thereto. Thus, the digital signal stored in the memory unit 45 is sequentially output to the processing unit 60a via the data lane 55 and the sense amplifier 62. The control signal for operating the amplifier circuit may be a signal of a constant potential (for example, a power supply potential).

[0039] Signals V1 and V2 are input to the AND circuit 61. The signal V1 is also input to the sense amplifier 62b. The output signal of the AND circuit 61 is input to the sense amplifier 62a and the sense amplifier 62c, respectively. The signals V1 and V2 are signals used to control the sense amplifiers 62a to 62c. The read control unit 100 controls the operating states of the sense amplifiers 62a to 62c by controlling the signals V1 and V2. In this way, the horizontal transfer unit 50a sequentially outputs the signals converted into digital signals by the AD conversion units 43a to the processing unit 60a.

[0040] The processing unit 60a has signal processing units 64 (signal processing units 64a to 64c). A signal processing unit 64 is provided for each sense amplifier 62. The signal processing unit 64a is provided for the sense amplifier 62a, the signal processing unit 64b is provided for the sense amplifier 62b, and the signal processing unit 64c is provided for the sense amplifier 62c. The signal processing unit 64 is composed of a decoding circuit, a memory circuit, etc. The signal processing unit 64 performs signal processing such as code conversion and correlated double sampling on the signal input from the sense amplifier 62. The signal processing unit 64 outputs the processed signal to the signal output unit 70a.

[0041] The signal output unit 70a has output I / F units 71a to 71c. The output I / F units 71a to 71c are configured by output circuits compatible with high-speed interfaces such as SLVS. The output I / F unit 71a outputs a signal input from the signal processing unit 64a to the control unit 4 of the camera 1. The output I / F unit 71b outputs a signal input from the signal processing unit 64b to the control unit 4, and the output I / F unit 71c outputs a signal input from the signal processing unit 64c to the control unit 4. The column circuit unit 40b, horizontal transfer unit 50b, processing unit 60b, and signal output unit 70b are configured similarly to the column circuit unit 40a, horizontal transfer unit 50a, processing unit 60a, and signal output unit 70a described above, respectively.

[0042] The readout control unit 100 (see FIG. 2) controls each switch of the horizontal adder 42 and the horizontal transfer unit 50 to perform a process of individually reading out the signal of each pixel of the image sensor 3 (individual readout control) and a process of adding and reading out the signals of multiple pixels (addition readout control). The control unit 4 of the camera 1 controls the readout control unit 100 to switch the method of reading out the pixel signals.

[0043] In the individual readout control, the readout control unit 100 turns off the switch SW2 of the horizontal adder 42, sequentially selects a plurality of pixels of the image sensor 3 on a row-by-row basis, and causes the signals of the selected pixels to be output to the AD conversion unit 43. Furthermore, the readout control unit 100 causes the pixel signals converted into digital signals by each AD conversion unit 43 to be output sequentially to the processing unit 60 using the plurality of data lanes 55 of the horizontal transfer unit 50.

[0044] In the addition readout control, the readout control unit 100 turns on the switch SW2 of the horizontal adder 42, sequentially selects multiple pixels of the image sensor 3 row by row, and adds up the signals of the multiple pixels on the vertical signal line 25. The readout control unit 100 outputs the added pixel signals to some of the AD conversion units 43 among the multiple AD conversion units 43 arranged in the image sensor 3.

[0045] In this embodiment, as will be described later, some of the AD conversion units 43 to which the added pixel signals are input are connected to some of the multiple data lanes 55 of the horizontal transfer unit 50. Therefore, in the addition readout control, the readout control unit 100 can use only some of the multiple data lanes 55 to sequentially output the pixel signals converted into digital signals by each AD conversion unit 43 to the processing unit 60.

[0046] As described above, when performing additive readout control, the readout control unit 100 uses some of the AD conversion units 43 and some of the data lanes 55. The other AD conversion units 43 to which the added pixel signals are not input, the data lanes 55 to which those AD conversion units 43 are connected, and the sense amplifiers 62 connected to those data lanes 55 are not used in the additive readout control. Therefore, the readout control unit 100 controls the first supply unit 110 to stop the current supplied to the AD conversion units 43 that are not used in the additive readout control. The readout control unit 100 also stops the operation of the data lanes 55 that are not used in the additive readout control. Furthermore, the readout control unit 100 controls the second supply unit 120 to stop the operation of the sense amplifiers 62 that are not used in the additive readout control. This reduces the power consumption of the image sensor 3. Therefore, when capturing moving images at a high frame rate, it is possible to prevent an increase in power consumption due to additive readout control.

[0047] 4, the AD conversion units 43 used when performing accumulating readout control include, for example, AD conversion units 43a2, 43a5, and 43a8. The AD conversion units 43a2, 43a5, and 43a8 are connected to the same data lane 55b among the multiple data lanes 55a to 55c via switches SW3b, SW3e, and SW3h, respectively.

[0048] Some of the AD conversion units 43 (AD conversion units 43a2, 43a5, and 43a8 in FIG. 4), some of the data lanes 55 (data lane 55b in FIG. 4), and some of the sense amplifiers 62 (sense amplifier 62b in FIG. 4) of the image sensor 3 constitute a first output unit that outputs pixel signals output to the vertical signal lines 25 to the processing unit 60. When both individual readout control and additive readout control are performed, this first output unit is supplied with a current from the first supply unit 110 and a pulse signal from the second supply unit 120 and is put into an operating state.

[0049] The other AD conversion units 43 (AD conversion units 43a1, 43a3, 43a4, 43a6, 43a7, and 43a9 in FIG. 4), the other data lanes 55 (data lanes 55a and 55c in FIG. 4), and the other sense amplifiers 62 (sense amplifiers 62a and 62c in FIG. 4) of the image sensor 3 constitute a second output unit that outputs pixel signals output to the vertical signal lines 25 to the processing unit 60. When individual readout control is performed, this second output unit is supplied with current from the first supply unit 110 and with a pulse signal from the second supply unit 120, and is put into an operating state. When additive readout control is performed, pixel signals are not input to the second output unit. Therefore, when additive readout control is performed, the readout control unit 100 controls the first supply unit 110 to stop supplying current to the second output unit and the second supply unit 120 to stop supplying pulse signals to the second output unit. As a result, when performing addition readout control, the second output unit is not supplied with a current from the first supply unit 110 and a pulse signal from the second supply unit 120, and is in a stopped state.

[0050] As described above, the sense amplifiers 62 of the second output unit (sense amplifiers 62a and 62c in FIG. 4) are not used in the additive readout control. When the additive readout control is performed, the readout control unit 100 causes the second supply unit 120 to stop supplying pulse signals to the sense amplifiers 62a and 62c. As a result, when the additive readout control is performed, the sense amplifiers 62a and 62c are not supplied with pulse signals from the second supply unit 120 and are in a stopped (paused) state. When the additive readout control is performed, the second output unit is in a stopped state, and power consumption of the image sensor 3 is reduced. The individual read control and the additive read control will be described in more detail below.

[0051] When the control unit 4 selects (sets) individual readout control, the readout control unit 100 turns on the switches SW1a to SW1i of the horizontal adder 42 and turns off the switches SW2a to SW2f. The readout control unit 100 also sets both the signals V1 and V2 to high level. This enables the sense amplifiers 62a to 62c to amplify and read out the input signals.

[0052] The readout control unit 100 turns on the reset units 13 of the R pixels 10(1,1) to 10(1,17) in the first row. This resets the voltage of each FD 14 in the pixels 10 in the first row. The readout control unit 100 also turns on the selector units 16 of the pixels 10 in the first row. The readout control unit 100 turns off the selector units 16 of the pixels 10 in rows other than the first row. This causes the dark signals of the R pixels 10(1,1) to 10(1,17) in the first row to be output to the AD conversion units 43a1 to 43a9 via the selector units 16 of each pixel, the vertical signal lines 25a1 to 25a9 connected to each pixel, and the switches SW1a to SW1i.

[0053] The AD conversion units 43a1 to 43a9 convert the input dark signals into digital signals. The readout control unit 100 controls the switches SW3a to SW3i of the horizontal transfer unit 50a to sequentially output the dark signals converted into digital signals by the AD conversion units 43a to the processing unit 60a via the sense amplifier 62. The readout control unit 100 turns on only the switches SW3a to SW3c of the switches SW3a to SW3i to output the digital signals converted by the AD conversion units 43a1 to 43a3 to the processing unit 60a via the data lanes 55a to 55c, respectively. Thereafter, the readout control unit 100 turns on only the switches SW3d to SW3f of the switches SW3a to SW3i to output the digital signals converted by the AD conversion units 43a4 to 43a6 to the processing unit 60a via the data lanes 55a to 55c, respectively. Thereafter, the read control unit 100 turns on only the switches SW3g to SW3i among the switches SW3a to SW3i, and outputs the digital signals converted by the AD conversion units 43a7 to 43a9 to the processing unit 60a via the data lanes 55a to 55c, respectively.

[0054] The readout control unit 100 turns on the transfer units 12 of the R pixels 10(1,1) to 10(1,17) in the first row. This causes the charges photoelectrically converted by the PDs 11 in the pixels 10 in the first row to be transferred to the FDs 14. The photoelectric conversion signals of the R pixels 10(1,1) to 10(1,17) in the first row are output to the AD conversion units 43a1 to 43a9, respectively, via the selection units 16 of the pixels, the vertical signal lines 25 connected to the pixels, and the switch SW1.

[0055] The AD conversion units 43a1 to 43a9 convert the input photoelectric conversion signals into digital signals. The photoelectric conversion signals converted into digital signals by the AD conversion units 43a1 to 43a9 are sequentially output to the processing unit 60a via the data lanes 55a to 55c, respectively, in the same way as when the digitally converted dark signals are sequentially output to the processing unit 60a.

[0056] The readout control unit 100 reads out dark signals and photoelectric conversion signals from the pixels 10(2,1) to 10(2,17) in the second row in the same manner as when reading out signals from the pixels in the first row. Similarly, the readout control unit 100 sequentially selects the pixels in the third row and thereafter, row by row, in the order of the third row, fourth row, fifth row, and sixth row, and reads out signals from each selected pixel.

[0057] In this way, under individual readout control, the readout control unit 100 individually reads out signals from pixels of the image sensor 3. The dark signals and photoelectric conversion signals sequentially output to the data lanes 55a to 55c are subjected to signal processing such as correlated double sampling by the processing unit 60a. The signal output to the data lane 55a is input to the signal processing unit 64a via the sense amplifier 62a, and after being subjected to signal processing by the signal processing unit 64a, is output to the control unit 4 by the output I / F unit 71a. The signal output to the data lane 55b is input to the signal processing unit 64b via the sense amplifier 62b, and after being subjected to signal processing by the signal processing unit 64b, is output to the control unit 4 by the output I / F unit 71b. The signal output to the data lane 55c is input to the signal processing unit 64c via the sense amplifier 62c, and after being subjected to signal processing by the signal processing unit 64c, is output to the control unit 4 by the output I / F unit 71c. Next, as an example of additive readout control, a case where signals of pixels of the same color are added together and read out for every three pixels in the row direction will be described.

[0058] When addition readout control is selected by the control unit 4, the readout control unit 100 turns on switches SW1b, SW1e, and SW1h of the horizontal adder 42. The readout control unit 100 turns off switches SW1a, SW1c, SW1d, SW1f, SW1g, and SW1i. The readout control unit 100 also turns on switches SW2a to SW2f. The readout control unit 100 controls the first supply unit 110a to stop supplying current to the AD conversion units 43a1, 43a3, 43a4, 43a6, 43a7, and 43a9. The readout control unit 100 also sets signal V1 to a high level to enable sense amplifier 62b, and sets signal V2 to a low level to disable sense amplifiers 62a and 62c.

[0059] The readout control unit 100 turns on the reset units 13 of the R pixels 10(1,1) to 10(1,17), which are the pixels in the first row. The readout control unit 100 also turns on the selector units 16 of the pixels in the first row. The readout control unit 100 also turns off the selector units 16 of the pixels in rows other than the first row. Because the switches SW2a and SW2b are both on, the amplifier units 15 of the R pixels 10(1,1), 10(1,3), and 10(1,5) are electrically connected via the vertical signal lines 25a1 to 25a3. As a result, the dark signal of the R pixel 10(1,1), the dark signal of the R pixel 10(1,3), and the dark signal of the R pixel 10(1,5) are averaged. Because the switch SW1b is on, the averaged dark signal is output to the AD conversion unit 43a2.

[0060] Similarly, the dark signal of the R pixel 10(1,7), the dark signal of the R pixel 10(1,9), and the dark signal of the R pixel 10(1,11) are averaged and output to the AD conversion unit 43a5 via the switch SW1e. Also, the dark signal of the R pixel 10(1,13), the dark signal of the R pixel 10(1,15), and the dark signal of the R pixel 10(1,17) are averaged and output to the AD conversion unit 43a8 via the switch SW1h.

[0061] The AD conversion units 43a2, 43a5, and 43a8 each convert the added dark signal into a digital signal. The readout control unit 100 sequentially turns on the switches SW3b, SW3e, and SW3h of the horizontal transfer unit 50a, causing the digital signals converted by each AD conversion unit 43a to be sequentially output to the processing unit 60a via the sense amplifier 62. The readout control unit 100 turns on only the switch SW3b of the switches SW3a to SW3i, causing the digital signal converted by the AD conversion unit 43a2 to be output to the processing unit 60a via the data lane 55b. Thereafter, the readout control unit 100 turns on only the switch SW3e of the switches SW3a to SW3i, causing the digital signal converted by the AD conversion unit 43a5 to be output to the processing unit 60a via the data lane 55b. Thereafter, the read control unit 100 turns on only the switch SW3h among the switches SW3a to SW3i, and outputs the digital signal converted by the AD conversion unit 43a8 to the processing unit 60a via the data lane 55b.

[0062] The readout control unit 100 turns on the transfer units 12 of the R pixels 10(1,1) to 10(1,17) in the first row. This causes the charges photoelectrically converted by the PDs 11 in the first row of pixels 10 to be transferred to the FDs 14. Because the switches SW2a and SW2b are both on, the amplifier units 15 of the R pixels 10(1,1), 10(1,3), and 10(1,5) are electrically connected via the vertical signal lines 25a1 to 25a3. This causes the photoelectric conversion signal of the R pixel 10(1,1), the photoelectric conversion signal of the R pixel 10(1,3), and the photoelectric conversion signal of the R pixel 10(1,5) to be averaged. Because the switch SW1b is on, the averaged photoelectric conversion signal is output to the AD conversion unit 43a2.

[0063] Similarly, the photoelectric conversion signal of the R pixel 10(1,7), the photoelectric conversion signal of the R pixel 10(1,9), and the photoelectric conversion signal of the R pixel 10(1,11) are averaged and output to the AD conversion unit 43a5 via the switch SW1e. Also, the photoelectric conversion signal of the R pixel 10(1,13), the photoelectric conversion signal of the R pixel 10(1,15), and the photoelectric conversion signal of the R pixel 10(1,17) are averaged and output to the AD conversion unit 43a8 via the switch SW1h.

[0064] The AD conversion units 43a2, 43a5, and 43a8 each convert the added photoelectric conversion signal into a digital signal. The readout control unit 100 sequentially turns on the switches SW3b, SW3e, and SW3h of the horizontal transfer unit 50a, causing the digital signals converted by each AD conversion unit 43a to be sequentially output to the processing unit 60a via the sense amplifier 62. The readout control unit 100 turns on only the switch SW3b of the switches SW3a to SW3i, causing the digital signal converted by the AD conversion unit 43a2 to be output to the processing unit 60a via the data lane 55b. Thereafter, the readout control unit 100 turns on only the switch SW3e of the switches SW3a to SW3i, causing the digital signal converted by the AD conversion unit 43a5 to be output to the processing unit 60a via the data lane 55b. Thereafter, the read control unit 100 turns on only the switch SW3h among the switches SW3a to SW3i, and outputs the digital signal converted by the AD conversion unit 43a8 to the processing unit 60a via the data lane 55b.

[0065] The readout control unit 100 reads out the dark signals and photoelectric conversion signals added up from the pixels 10(2,1) to 10(2,17) in the second row in the same manner as when reading out the signals added up from the pixels in the first row. Similarly, the readout control unit 100 sequentially selects the pixels in the third row and thereafter, row by row, in the order of the third row, fourth row, fifth row, and sixth row, and reads out signals from each selected pixel.

[0066] In this way, in the additive readout control, the readout control unit 100 adds and reads out signals from multiple pixels of the image sensor 3. The added dark signals and photoelectrically converted signals are converted into digital signals by the AD conversion unit 43 and then output sequentially to the data lane 55b. The dark signals and photoelectrically converted signals output sequentially to the data lane 55b are input to the signal processing unit 64b via the sense amplifier 62b, and after signal processing such as correlated double sampling is performed by the signal processing unit 64b, they are output to the control unit 4 by the output I / F unit 71b.

[0067] 5 is a diagram showing an example layout of a portion of the image sensor according to the first embodiment. The image sensor 3 is configured using a semiconductor substrate having p-wells 201 and 202. The p-well 201 is provided with a region 210 and a region 211 formed to surround the region 210. The p-well 202 is provided with a region 220 and a region 221 formed to surround the region 220.

[0068] A region 210 in the p-well 201 is a region (analog circuit region) in which elements constituting an analog circuit are formed. The comparator 44 of the AD conversion unit 43 is provided in the analog circuit region 210. A region 220 in the p-well 202 is a region (digital circuit region) in which elements constituting a digital circuit are formed. The memory unit 45 and the horizontal transfer unit 50 are provided in the digital circuit region 220. Regions 211 and 221 are p+ regions formed using p-type impurities. Regions 211 and 221 each function as a guard ring to prevent charge from leaking to adjacent regions.

[0069] The analog circuit area 210 and the digital circuit area 220 are arranged close to each other, forming a parasitic capacitance 90 between them. Furthermore, because the comparator 44 in the analog circuit area 210 and the horizontal transfer unit 50 in the digital circuit area 220 are arranged relatively close to each other, they may interfere with each other via the parasitic capacitance 90, generating noise. If the operating state of the horizontal transfer unit 50 changes while the AD conversion unit 43 is performing AD conversion, the state of noise interference may change midway through the AD conversion, potentially resulting in variations in the AD conversion results. The accuracy of the AD conversion may be reduced due to changes in the magnitude of the noise that the horizontal transfer unit 50 exerts on the AD conversion unit 43.

[0070] In this embodiment, as described above, when performing addition readout control in which signals from three horizontal pixels are added and read out, digital signals are transferred using only one of the three data lanes 55. During a period in which signals are read out from pixels in one row, that one data lane 55 is in a state in which it repeatedly transfers digital signals, while the other two data lanes 55 are in a stopped state in which they do not transfer digital signals. This makes it possible to prevent changes in the operating state of the data lanes 55 when performing addition readout control. As a result, changes in the noise received by the AD conversion unit 43 are suppressed, and variations in the AD conversion results can be prevented. Below, the suppression of changes in the noise received by the AD conversion unit 43 is described in comparison with a comparative example.

[0071] In the comparative example, AD conversion units 43 used in addition read control are connected to different data lanes 55. AD conversion unit 43a2 is connected to data lane 55a, AD conversion unit 43a5 is connected to data lane 55b, and AD conversion unit 43a8 is connected to data lane 55c. In the comparative example, when addition read control is performed, the read control unit 100 simultaneously performs an operation of outputting a digital signal converted by AD conversion unit 43a2 to data lane 55a, an operation of outputting a digital signal converted by AD conversion unit 43a5 to data lane 55b, and an operation of outputting a digital signal converted by AD conversion unit 43a8 to data lane 55c.

[0072] FIG. 6 is a diagram comparing readout control according to the first embodiment with readout control according to a comparative example. FIG. 6(a) shows the operating states of the AD conversion unit 43 and data lanes 55a to 55c when the image sensor according to the present embodiment performs individual readout control. FIG. 6(b) shows the operating states of the AD conversion unit 43 and data lanes 55a to 55c when the image sensor according to the comparative example performs additive readout control. FIG. 6(c) shows the operating states of the AD conversion unit 43 and data lanes 55a to 55c when the image sensor according to the present embodiment performs additive readout control. Note that FIGS. 6(a) to 6(c) illustrate, on the same time axis, the case where signals of pixels in the Nth row are read out by the horizontal transfer unit 50. Note that, in FIGS. 6(a) to 6(c), the AD conversion process for signals of pixels in the (N+1)th row and the transfer process for signals of pixels in the Nth row are shown side by side to compare the operating states of the data lanes 55a to 55c during the AD conversion process by the AD conversion unit 43.

[0073] In the case of individual readout control, as described above, the readout control unit 100 uses the three data lanes 55a to 55c of the horizontal transfer unit 50 to sequentially output the pixel signals converted into digital signals to the processing unit 60. In the example shown in FIG. 6(a), during the period from time t1 to time t4, the data lanes 55a to 55c sequentially output the pixel signals of the Nth row to the processing unit 60. The period from time t1 to time t4 is the period during which the pixel signals of the Nth row are read out to the processing unit 60 (read period).

[0074] During the period from time t1 to time t4, the AD conversion units 43a1 to 43a9 sequentially convert the photoelectric conversion signals and dark signals output from the pixels in the (N+1)th row into digital signals. The period from time t1 to time t4 is the period during which the signals from the pixels in the (N+1)th row are converted into digital signals. The individual readout control in the comparative example is also the same as that in FIG. 6(a).

[0075] When additive readout control is performed in the comparative example, the readout control unit 100 uses three data lanes 55a to 55c to sequentially output pixel signals to the processing unit 60. Because pixel signals are added and read out for every three pixels in the horizontal direction, the number of signals (amount of data) transferred by the horizontal transfer unit 50 to the processing unit 60 is one-third of that in the case of individual readout control. Furthermore, because one-third of the pixel signals are read out to the processing unit 60 using the three data lanes 55a to 55c, as in the case of individual readout control, the read period in the additive readout control according to the comparative example is approximately one-third of that in the case of individual readout control.

[0076] In the case of the additive readout control according to the comparative example shown in FIG. 6(b), during the period from time t1 to time t2, the data lanes 55a to 55c sequentially output the pixel signals of the Nth row input from the AD conversion units 43a2, 43a5, and 43a8 to the processing unit 60. At time t2, the readout of the pixel signals of the Nth row to the processing unit 60 is completed. During the period from time t2 to time t4, the data lanes 55a to 55c do not receive pixel signals from the AD conversion unit 43 and are not used for data transfer. Furthermore, during the period from time t1 to time t4, the AD conversion units 43a2, 43a5, and 43a8 sequentially convert the added photoelectric conversion signals and dark signals of the pixels of the (N+1)th row into digital signals. As with the case of individual readout control, the period from time t1 to time t4 is the period during which the pixel signals of the (N+1)th row are converted into digital signals.

[0077] As described above, in the comparative example, the data lanes 55a to 55c change from an operating state to a stopped state during the period in which AD conversion processing is performed on the signals of the pixels in the (N+1)th row. Therefore, in the comparative example, when accumulating readout control is performed, the noise received by the AD conversion unit 43 changes during the period in which AD conversion processing is performed by the AD conversion unit 43. As a result, the accuracy of AD conversion decreases in the comparative example. It is conceivable to prevent changes in the noise received by the AD conversion unit 43 by causing the data lanes 55a to 55c to transfer signals during the period from time t2 to time t4, but this would increase power consumption.

[0078] When performing additive readout control, the readout control unit 100 according to this embodiment uses one data lane 55b to sequentially output pixel signals to the processing unit 60. The data lanes 55 used for additive readout control are aggregated into one data lane 55b. In the example shown in FIG. 6(c), during the period from time t1 to time t4, the data lane 55b outputs pixel signals sequentially input from the AD conversion units 43a2, 43a5, and 43a8 to the processing unit 60. During the period from time t1 to time t4, the data lane 55b is in an operating state, and the data lanes 55a and 55c are in a stopped state. In this embodiment, when additive readout control is performed, the period from time t1 to time t4 is the period during which pixel signals from the Nth row are read out to the processing unit 60, just as in the case of individual readout control.

[0079] As described above, in this embodiment, during the period in which AD conversion processing is performed on the signals of the pixels in the (N+1)th row, data lane 55b remains in an operating state, and data lanes 55a and 55c remain in a stopped state. This prevents the noise received by AD conversion unit 43 from changing during the period in which AD conversion processing is performed by AD conversion unit 43. As a result, in this embodiment, it is possible to prevent a decrease in the accuracy of AD conversion. Furthermore, in this embodiment, the number of data lanes 55 used for accumulating and reading control is limited, thereby making it possible to reduce power consumption.

[0080] According to the above-described embodiment, the following effects can be obtained. (1) The image sensor 3 has a photoelectric conversion unit 11 that generates electric charges by photoelectric conversion, and includes a first pixel and a second pixel (pixel 10) that output a signal based on the electric charges generated by the photoelectric conversion unit 11, a first signal line (for example, vertical signal line 25a2) that outputs the signal of the first pixel, a second signal line (for example, vertical signal line 25a3) that outputs the signal of the second pixel, and a first output unit (for example, AD conversion unit 43a2) that outputs at least one of the signals output to the first signal line and the second signal line to a processing unit 60 that performs signal processing. , data lane 55b, and sense amplifier 62b), a second output unit (e.g., AD conversion unit 43a3, data lane 55c, and sense amplifier 62c) that outputs a signal output to the second signal line to the processing unit 60, and a control unit (readout control unit 100) that performs first control to cause the first output unit to output the signal of the first pixel and the signal of the second pixel to the processing unit 60, and second control to output the signal of the first pixel to the processing unit 60 by the first output unit and the signal of the second pixel to the processing unit 60 by the second output unit. In this embodiment, the image sensor 3 performs addition readout control to operate the first output unit of the first and second output units and output the added pixel signal to the processing unit 60. Therefore, when addition readout control is performed, the second output unit is stopped, thereby reducing power consumption of the image sensor 3.

[0081] (2) In this embodiment, when the image sensor 3 performs binning and reading control in which pixel signals are binned and read out in groups of three pixels in the horizontal direction, the image sensor 3 uses data lane 55b of data lanes 55a to 55c to sequentially output the binned pixel signals to the processing unit 60. In this case, data lane 55b remains in an operating state, while data lanes 55a and 55c remain in a stopped state. This prevents the operating state of data lane 55 from changing during the period in which AD conversion processing is being performed by the AD conversion unit 43, thereby preventing changes in the noise received by the AD conversion unit 43. As a result, it is possible to prevent a decrease in the accuracy of AD conversion.

[0082] The following modifications are also within the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiment.

[0083] (Variation 1) 7 is a diagram showing an example of the configuration of a portion of an image sensor according to Modification 1. The image sensor 3 according to Modification 1 includes an AND circuit 63. A clock signal CLK and a signal V3 are input to the AND circuit 63. The clock signal CLK is also input to a signal processing unit 64b. An output signal from the AND circuit 63 is input to each of signal processing units 64a and 64c. The read control unit 100 controls the operation states of the signal processing units 64a and 64c by controlling the signal V3.

[0084] When the control unit 4 selects individual read control, the read control unit 100 sets the signal V3 to a high level. As a result, the clock signal CLK is input to the signal processing units 64a and 64c via the AND circuit 63. The clock signal CLK is also input to the signal processing unit 64b, so that the signal processing units 64a to 64c are able to perform signal processing on the signal output from the sense amplifier 62 based on the clock signal CLK.

[0085] When the control unit 4 selects the addition read control, the read control unit 100 sets the signal V3 to a low level. As a result, the signal processing units 64a and 64c are not input with a clock signal and are in a stopped state. Note that the signal processing unit 64b is input with a clock signal CLK and is therefore in an operable state.

[0086] As described above, the read control unit 100 controls the operation states of the signal processing units 64a and 64c by controlling the signal V3 input to the AND circuit 63. Therefore, when performing addition read control, the read control unit 100 can stop the signal processing units 64a and 64c to reduce the power consumption of the image sensor 3.

[0087] (Variation 2) 8 is a diagram showing an example of the configuration of a portion of an image sensor according to Modification 2. The image sensor 3 according to Modification 2 includes a conversion unit 65 and multiplexers 66a to 66c. The conversion unit 65 is connected to a signal processing unit 64b, and divides and outputs signals input from the signal processing unit 64b to the multiplexers 66a to 66c.

[0088] The multiplexer 66a is controlled by the read control unit 100 and selects the signal to be output to the output I / F unit 71a from the signal output by the signal processing unit 64a and the signal output by the conversion unit 65. The multiplexer 66b is controlled by the read control unit 100 and selects the signal to be output to the output I / F unit 71b from the signal output by the signal processing unit 64b and the signal output by the conversion unit 65. The multiplexer 66c is controlled by the read control unit 100 and selects the signal to be output to the output I / F unit 71c from the signal output by the signal processing unit 64c and the signal output by the conversion unit 65.

[0089] In the individual readout control, the multiplexer 66a outputs pixel signals input from the signal processing unit 64a to the output I / F unit 71a. The multiplexer 66b outputs pixel signals input from the signal processing unit 64b to the output I / F unit 71b. The multiplexer 66c outputs pixel signals input from the signal processing unit 64c to the output I / F unit 71c. The output I / F units 71a, 71b, and 71c output signals input from the signal processing units 64a, 64b, and 64c, respectively, to the control unit 4.

[0090] In the addition readout control, the signal processing unit 64b performs signal processing on pixel signals sequentially input via the data lane 55b and the sense amplifier 62b, and sequentially outputs the signals to the conversion unit 65. The conversion unit 65 divides the signals sequentially input from the signal processing unit 64b and outputs them to multiplexers 66a to 66c. The multiplexer 66a outputs the pixel signal input from the conversion unit 65 to the output I / F unit 71a, and the multiplexer 66b outputs the pixel signal input from the conversion unit 65 to the output I / F unit 71b. In addition, the multiplexer 66c outputs the pixel signal input from the conversion unit 65 to the output I / F unit 71c. The output I / F units 71a, 71b, and 71c each output the signal input from the conversion unit 65 to the control unit 4.

[0091] In the above-described embodiment, when additive readout control is performed, pixel signals are output to the control unit 4 by one output I / F unit 71b of the three output I / F units 71a to 71c. In this modified example, when additive readout control is performed, pixel signals are output to the control unit 4 by the output I / F units 71a to 71c. In both the case of individual readout control and the case of additive readout control, signals can be output to the control unit 4 from the three output I / F units 71a to 71c. The number of output I / F units 71 used in the case of individual readout control can be the same as the number of output I / F units 71 used in the case of additive readout control. Therefore, pixel signals can be communicated between the image sensor 3 and the control unit 4 in the same way when additive readout control and when individual readout control are performed.

[0092] (Variation 3) In the above-described embodiment, an example has been described in which the image sensor 3 has three data lanes 55 per horizontal transfer unit 50. However, the image sensor may have a configuration in which three or more data lanes per horizontal transfer unit are provided.

[0093] 9 is a diagram showing an example of the configuration of a portion of an image sensor according to Modification 3. In this modification, the horizontal transfer unit 50 (horizontal transfer unit 50a in FIG. 9) has four data lanes 55: data lane 55a, data lane 55b, data lane 55c, and data lane 55d. The horizontal transfer unit 50 also has a sense amplifier 62d. The processing unit 60 (processing unit 60a in FIG. 9) also has a signal processing unit 64d and a multiplexer 66d. The signal output unit 70 (signal output unit 70a in FIG. 9) also has an output I / F unit 71d.

[0094] In this modification, the AD conversion units 43 (AD conversion units 43a2, 43a5, and 43a8 in FIG. 9) used in the addition read control are connected to one of two data lanes 55 (data lanes 55a and 55b in FIG. 9). The AD conversion unit 43a2 is connected to data lane 55b, the AD conversion unit 43a5 is connected to data lane 55a, and the AD conversion unit 43a8 is connected to data lane 55b.

[0095] In the case of individual readout control, pixel signals of each row are output to AD conversion units 43a1-43a9 via the selector 16 of each pixel, vertical signal lines 25a1-25a9 connected to each pixel, and switches SW1a-SW1i, respectively. The AD conversion units 43a1-43a9 convert the input pixel signals into digital signals. The readout control unit 100 controls switches SW3a-SW3i of the horizontal transfer unit 50a to sequentially output the digital signals converted by the AD conversion units 43a1-43a9 to the processing unit 60a via data lanes 55a-55d. The signals output to the data lanes 55a-55d are input to signal processing units 64a-64d via sense amplifiers 62a-62d, respectively, and are then processed by the signal processing units 64a-64d before being output to the control unit 4 via output I / F units 71a-71d.

[0096] In the case of additive readout control, the readout control unit 100 sequentially outputs pixel signals to the processing unit 60 using two data lanes 55a and 55b. The readout control unit 100 simultaneously performs an operation of outputting a digital signal converted by one AD conversion unit 43a (e.g., AD conversion unit 43a2) to the data lane 55b and an operation of outputting a digital signal converted by another AD conversion unit 43a (e.g., AD conversion unit 43a5) to the data lane 55a. The signal output to the data lane 55a is input to the signal processing unit 64a via the sense amplifier 62a, and after signal processing by the signal processing unit 64a, is output to the control unit 4 by the output I / F unit 71a. The signal output to the data lane 55b is input to the signal processing unit 64b via the sense amplifier 62b, and after signal processing by the signal processing unit 64b, is output to the control unit 4 by the output I / F unit 71b. In the addition readout control of this modified example, the data lanes 55c and 55d are not used for data transfer because pixel signals are not input from the AD conversion unit 43. Therefore, the AD conversion unit 43, the sense amplifiers 62c and 62d, and the signal processing units 64c and 64d connected to the data lanes 55c and 55d are stopped, thereby reducing the power consumption of the image sensor 3.

[0097] (Variation 4) An amplifier unit may be provided between the switch SW1 connected to the vertical signal line 25 and the AD conversion unit 43. The amplifier unit is provided for each vertical signal line 25, amplifies pixel signals input via the vertical signal line 25 at a predetermined gain (amplification factor), and outputs the amplified pixel signals to the AD conversion unit 43. A current for operating the amplifier unit is supplied to the amplifier unit from a first supply unit 110. The AD conversion unit 43 converts the amplified pixel signals into digital signals and outputs them to the horizontal transfer unit 50.

[0098] Some of the AD conversion units 43 (AD conversion units 43a2, 43a5, and 43a8 in FIG. 4) of the image sensor 3, amplifier units connected to these AD conversion units 43, some of the data lanes 55 (data lane 55b in FIG. 4), and some of the sense amplifiers 62 (sense amplifier 62b in FIG. 4) constitute a first output unit that outputs pixel signals output to the vertical signal lines 25 to the processing unit 60. Other AD conversion units 43 (AD conversion units 43a1, 43a3, 43a4, 43a6, 43a7, and 43a9 in FIG. 4) of the image sensor 3, amplifier units connected to these other AD conversion units 43, other data lanes 55 (data lanes 55a and 55c in FIG. 4), and other sense amplifiers 62 (sense amplifiers 62a and 62c in FIG. 4) constitute a second output unit that outputs pixel signals output to the vertical signal lines 25 to the processing unit 60.

[0099] When additive readout control is performed, pixel signals are not input to the second output unit. Therefore, when additive readout control is performed, the readout control unit 100 causes the first supply unit 110 to stop supplying current to the second output unit and the second supply unit 120 to stop supplying pulse signals to the second output unit. As a result, when additive readout control is performed, the second output unit is in a stopped state, and power consumption of the image sensor 3 can be reduced.

[0100] (Variation 5) When performing additive readout control, the readout control unit 100 may turn on the switches SW1a to SW1i of the horizontal adder 42, just as when performing individual readout control. The added pixel signals are also input to the AD conversion unit 43 of the second output unit. In this case, the readout control unit 100 may control the second output unit not to output the pixel signals from the second output unit to the processing unit 60.

[0101] The readout control unit 100 may stop the first supply unit 110 from supplying a current to the second output unit, thereby preventing the pixel signal from being output from the second output unit to the processing unit 60. The readout control unit 100 may stop the second supply unit 120 from supplying a pulse signal to the sense amplifier 62 of the second output unit (sense amplifiers 62a and 62c in FIG. 4 ), thereby preventing the pixel signal from being output from the second output unit to the processing unit 60. At this time, the readout control unit 100 may stop the sense amplifier 62 of the second output unit by supplying a signal of a constant potential (for example, 0 V or ground potential) to the sense amplifier 62 of the second output unit for a predetermined time period using the second supply unit 120.

[0102] Furthermore, when performing additive readout control, the readout control unit 100 may control the signal processing unit 64 connected to the second output unit (signal processing units 64a and 64c in FIG. 4) so ​​that the signal processing unit 64 connected to the second output unit does not process pixel signals. In this case, as in the example shown in FIG. 7, the readout control unit 100 may stop the supply of a clock signal to the signal processing unit 64 connected to the second output unit, thereby preventing the signal processing unit 64 connected to the second output unit from processing pixel signals.

[0103] (Variation 6) The imaging elements and imaging devices described in the above-mentioned embodiments and variations may be applied to cameras, smartphones, tablets, cameras built into PCs, in-vehicle cameras, cameras mounted on unmanned aerial vehicles (drones, radio-controlled aircraft, etc.), etc.

[0104] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments that are conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0105] The disclosures of the following priority applications are incorporated herein by reference: Japanese Patent Application No. 2019-69146 (filed March 29, 2019) [Explanation of symbols]

[0106] 1...imaging device, 3...imaging element, 4...control unit, 10...pixel, 11...photoelectric conversion unit, 25...vertical signal line, 40...column circuit unit, 43...AD conversion unit, 50...horizontal transfer unit, 60...processing unit, 65...conversion unit, 70...signal output unit, 71...output I / F unit, 100...readout control unit, 110...first supply unit, 120...second supply unit

Claims

[Claim 1] a first photoelectric conversion unit and a second photoelectric conversion unit that generate electric charges by photoelectric conversion and are arranged in the row direction; a first signal line that outputs a first signal based on the charge generated by the first photoelectric conversion unit and is wired in a column direction; a second signal line that outputs a second signal based on the charge generated by the second photoelectric conversion unit and is wired in the column direction; a first AD conversion unit that converts at least one of the first signal and the second signal, which are analog signals, into a digital signal; a second AD conversion unit that converts the second signal, which is an analog signal, into a digital signal; a first output unit that outputs at least one of the first signal and the second signal converted into a digital signal by the first AD conversion unit to a processing unit that performs signal processing; a second output unit that outputs the second signal converted into a digital signal by the second AD conversion unit to the processing unit; a control unit that performs first control to cause the first output unit to output the first signal and the second signal to the processing unit, and second control to cause the first output unit to output the first signal to the processing unit and the second output unit to output the second signal to the processing unit; An imaging element comprising:

Images