Software development apparatus, software development program, and software development method

Abstract

To provide a new software development technique considering both an instruction set architecture of a processor and an instruction code to be given to the processor.SOLUTION: A software development apparatus for generating software to be executed by a reconfigurable processor includes an analysis module for analyzing a source code, a first generation module for generating an object code including an instruction code to be provided to the processor, a second generation module for generating an instruction set architecture setting code defining an instruction set architecture of the processor, and an optimization module for determining contents of the object code and the instruction set architecture setting code based on an analysis result.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a software development device and a software development program. [Background technology]

[0002] Reconfigurable computers or processors have been put to practical use for some time. Techniques for generating software for such computers or processors have been proposed. For example, Japanese Patent Laid-Open Publication No. 2006-155632 (Patent Document 1) discloses a system for compiling source code written in, for example, C or Pascal to generate an executable file for use in a dynamically reconfigurable processing unit having a selectively replaceable internal hardware structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-155632 Summary of the Invention [Problem to be solved by the invention]

[0004] In the configuration disclosed in the aforementioned Patent Document 1, in order to generate an object file for use in a dynamically reconfigurable processing unit, it is necessary to input a source file containing multiple instruction statements and reconfiguration instructions that specify one of the hardware structures for a subset of the instruction statements. As a result, only a predetermined hardware structure can be used, and the entire process is not necessarily optimized.

[0005] An object of the present disclosure is to provide a new software development technique that takes into consideration both the instruction set architecture of a processor and the instruction code to be given to the processor. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, there is provided a software development apparatus for generating software to be executed by a reconfigurable processor, the software development apparatus including: an analysis module for analyzing source code; a first generation module for generating object code including instruction codes to be provided to the processor; a second generation module for generating instruction set architecture setting code that defines the instruction set architecture of the processor; and an optimization module that determines the contents of the object code and the instruction set architecture setting code based on the analysis results.

[0007] The instruction set architecture configuration code may include a definition that maps multiple operations using wired logic implemented in the processor to a single instruction code.

[0008] The instruction set architecture configuration code may include a definition of the hardwired logic to be implemented in the processor.

[0009] The optimization module may determine the contents of the object code and the instruction set architecture setting code according to the number of repetitions of a particular process included in the source code and the complexity of the process.

[0010] According to another aspect of the present disclosure, there is provided a software development program for generating software to be executed on a reconfigurable processor. The computer executes the steps of analyzing the source code, generating object code including instruction codes to be given to the processor, generating instruction set architecture setting code that defines the instruction set architecture of the processor, and determining the contents of the object code and the instruction set architecture setting code based on the analysis results. [Effects of the Invention]

[0011] According to the present disclosure, a new software development technology that takes into account both the instruction set architecture of a processor and the instruction code given to the processor can be realized.

Brief Description of the Drawings

[0012] [Figure 1] It is a diagram for explaining a software development apparatus according to the related art. [Figure 2] It is a diagram for explaining a software development apparatus according to the present embodiment. [Figure 3] It is a schematic diagram showing an example of the hardware configuration of a software development apparatus according to the present embodiment. [Figure 4] It is a schematic diagram showing an example of the functional configuration of a software development apparatus according to the present embodiment. [Figure 5] It is a diagram showing an example of a process in which a software development apparatus according to the present embodiment generates circuit design code including a microprogram. [Figure 6] It is a diagram showing an example of a process in which a software development apparatus according to the present embodiment generates circuit design code including a configuration. [Figure 7] It is a schematic diagram showing an example of a process of source code by a software development apparatus according to the present embodiment. [[ID=二十七]] [Figure 8] It is a schematic diagram showing an example of a code generation process in a software development apparatus according to the present embodiment. [Figure 9] It is a flowchart showing an example of a processing procedure executed by a software development apparatus according to the present embodiment.

Embodiments for Carrying Out the Invention

[0013] Embodiments according to the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and their description will not be repeated.

[0014] <A. Overview> First, an overview of the present disclosure will be described. The present disclosure is directed to a software development apparatus that generates software to be executed on a reconfigurable processor.

[0015] 1 is a diagram for explaining a software development device according to the related art, which shows an example in which a general-purpose processor 20 executes a program.

[0016] More specifically, source code 10 describing a target program is converted by a compiler 12 into object code 14. When the program is executed, instruction codes 16 (written in machine language) contained in the object code 14 are sequentially provided to a processor 20.

[0017] The processor 20 is made up of a large number of logic circuits, and activates the target logic circuits according to the input instruction code 16, and sequentially executes the processing corresponding to the instruction code 16. Each instruction code 16 is made up of an opcode for issuing an instruction and (if necessary) an operand for specifying a target.

[0018] The processor 20 has a pre-designed instruction set architecture 22. In order to cause a processor 20 to execute processing according to the program described in the source code 10, a compiler 12 generates an object code 14 that is compatible with an instruction set architecture 22.

[0019] That is, the instruction code 16 included in the object code 14 is generated in accordance with rules set for the processor 20 (instruction set architecture 22).

[0020] There are two instruction set architectures: CISC (Complex Instruction Set Computer) and RISC (Reduce Instruction Set Computer). Each method has its advantages and disadvantages, but once the execution environment is fixed, the user cannot freely choose the instruction set architecture.

[0021] The inventors of the present application have discovered a new technical concept that processing performance can be further improved by optimizing the combination of instruction set architecture and instruction code according to the content of the program written in the source code.

[0022] Fig. 2 is a diagram for explaining a software development apparatus according to the present embodiment. Referring to Fig. 2, this embodiment uses a reconfigurable processor 40. Processor 40 can arbitrarily configure an instruction set architecture.

[0023] Examples of mechanisms for arbitrarily configuring the instruction set architecture include (1) arbitrarily setting the microprograms implemented in the processor 40, (2) arbitrarily setting the wired logic (logic circuits), and (3) a combination of (1) and (2).

[0024] (1) When the microprogram implemented in the processor 40 is arbitrarily set, an interface for updating the microprogram stored in the processor 40 is provided in the processor 40. The microprogram interprets the instruction code and determines which wired logics configured in the processor are to be used and in what order.

[0025] (2) To set wired logic arbitrarily, use FPGA (Field-Programmable Gate Array). Gate Array) or known reconfigurable devices can be used.

[0026] In this embodiment, the code generation module 32 has a function corresponding to a compiler, and generates an object code 34 and an instruction set architecture setting code 38 from the source code 10. When the program is executed, instruction codes 36 (written in machine language) included in the object code 34 are sequentially provided to the processor 40.

[0027] The instruction set architecture setting code 38 includes information for setting the instruction set architecture 42 in the processor 40. As described above, (1) in the case where a microprogram to be implemented in the processor 40 is arbitrarily set, the instruction set architecture setting code 38 includes the microprogram. In this way, the instruction set architecture setting code 38 includes a definition that associates multiple processes using wired logic implemented in the processor 40 with a single instruction code.

[0028] Also, (2) when the wired logic is arbitrarily set, the instruction set architecture setting code 38 stores information for configuring the wired logic (hereinafter referred to as "configuration Thus, the instruction set architecture configuration code 38 includes a definition of the hardwired logic to be implemented in the processor 40.

[0029] Note that in the case of a combination of (3) (1) and (2), the instruction set architecture setting code 38 may include both a microprogram and a configuration.

[0030] The code generation module 32 generates optimized object code 34 and instruction set architecture setting code 38 in accordance with the program described in the source code 10 .

[0031] As described above, according to the software development apparatus according to the present embodiment, in accordance with the program described in the source code 10, it is possible to optimize in consideration of both the instruction set architecture 42 of the processor 40 and the instruction code 36 output to the processor 40 comprehensively.

[0032] <B. Hardware Configuration Example> Next, a hardware configuration example of the software development apparatus according to the present embodiment will be described.

[0033] FIG. 3 is a schematic diagram showing a hardware configuration example of a software development apparatus 100 according to the present embodiment. The software development apparatus 100 is typically realized by a general-purpose computer.

[0034] Referring to FIG. 3, the software development apparatus 100 includes, as main components, a processor 102, a main memory 104, an input unit 106, a display 108, a hard disk 110, and a communication interface 112. These components are connected via an internal bus 114.

[0035] The processor 102 is composed of, for example, a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). A plurality of processors 102 may be arranged, or a processor 102 having a plurality of cores may be employed.

[0036] The main memory 104 is composed of a volatile storage device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). The hard disk 110 holds various programs and various data executed by the processor 102. Instead of the hard disk 110, a non-volatile storage device such as an SSD (Solid State Drive) or a flash memory may be used. A volatile storage device may also be used. A designated program from among the programs stored on the hard disk 110 is loaded onto the main memory 104, and the processor 102 sequentially executes computer-readable instructions contained in the program loaded onto the main memory 104, thereby realizing various functions as will be described later.

[0037] Typically, the hard disk 110 stores a software development program 120 for realizing an integrated development environment, source code 10 created arbitrarily by the user, and object code 34 and instruction set architecture setting code 38 generated from the source code 10. The software development program 120 generates the object code 34 and instruction set architecture setting code 38 from the source code 10 created arbitrarily by the user, and includes a module that provides a program development environment.

[0038] The input unit 106 receives input operations from a user who operates the software development device 100. The input unit 106 includes, for example, a keyboard, a mouse, and a touch panel arranged on a display device. It may be a panel, an operation button arranged on the housing of the software development device 100, or the like.

[0039] The display 108 displays the processing results of the processor 102. The display 108 may be, for example, an LCD (Liquid Crystal Display) or an organic EL (Electro-Luminescence) display.

[0040] The communication interface 112 is responsible for exchanging data with the device 200 including the processor 40. The communication interface 112 includes, for example, a wired connection terminal such as a Universal Serial Bus (USB) port, a serial port such as IEEE 1394, or a legacy parallel port. Alternatively, the communication interface 112 may include an Ethernet (registered trademark) port.

[0041] In addition, the communication interface 112 may have a function of writing a microprogram and / or a function of writing a configuration to the processor 40.

[0042] The software development apparatus 100 may further include a component for reading the stored program and the like from a non-transitory medium storing a software development program 120 including computer-readable instructions. The medium may be, for example, an optical medium such as a DVD (Digital Versatile Disc), a semiconductor medium such as a USB memory, or the like.

[0043] Note that the software development program 120 may not only be installed in the software development apparatus 100 via the medium, but may also be provided from a distribution server on the network.

[0044] <C. Functional Configuration Example> Next, a functional configuration example of the software development apparatus 100 according to the present embodiment will be described.

[0045] FIG. 4 is a schematic diagram showing a functional configuration example of the software development apparatus 100 according to the present embodiment. Each module shown in FIG. 4 may typically be realized by the processor 102 of the software development apparatus 100 executing the software development program 120.

[0046] Referring to FIG. 4, the software development apparatus 100 includes, as a functional configuration constituting the code generation module 32, a lexical analysis module 121, a syntax analysis module 122, an intermediate code generation module 123, an optimization module 124, an object code generation module 125, and a processor configuration code generation module 126.

[0047] The lexical analysis module 121 and the syntactic analysis module 122 analyze the source code 10 .

[0048] More specifically, the lexical analysis module 121 analyzes keywords, identifiers, operators, delimiters, etc. included in the source code 10. The syntax analysis module 122 determines the syntax structure included in the source code 10 based on the lexical elements analyzed by the lexical analysis module 121.

[0049] The intermediate code generation module 123 generates intermediate code in an arbitrary expression format based on the syntactic structure determined by the syntactic analysis module 122 .

[0050] The optimization module 124 determines a combination of instruction set architecture and instruction code for the processor 40 to perform processing, based on the syntactic structure determined by the syntax analysis module 122 and the intermediate code generated by the intermediate code generation module 123. In this way, the optimization module 124 determines the contents of the object code 34 and the instruction set architecture setting code 38 based on the analysis results.

[0051] The object code generation module 125 generates the object code 34 that can output the instruction code determined from the intermediate code according to the combination determined by the optimization module 124. In this way, the object code generation module 125 generates the object code 34 that includes the instruction code to be provided to the processor 40.

[0052] The processor configuration code generation module 126 generates the instruction set architecture setting code 38 that can realize the determined instruction set architecture according to the instruction set architecture determined by the optimization module 124. In this way, the processor configuration code generation module 126 generates the instruction set architecture setting code 38 that defines the instruction set architecture of the processor 40.

[0053] With the functional configuration as described above, the code generation module 32 (software development program 120) generates object code 34 and instruction set architecture setting code 38 from source code 10.

[0054] <D. Processing Example> Next, an example of code generation processing by the software development apparatus 100 according to the present embodiment will be described.

[0055] (d1: Processing Example 1) FIG. 5 is a diagram showing an example of processing for the software development apparatus 100 according to the present embodiment to generate instruction set architecture setting code 38 including a microprogram 48. FIG. 5 shows, as an example, an example of transmitting a packet from a communication module.

[0056] More specifically, an example is shown in which data to be transmitted is sequentially written into the register 46 of the communication module. In the memory 44, an area to which addresses 001 to 004 are assigned is formed, and data 1 to data 4 are respectively stored. Data 1 to data 4 stored in the memory 44 are sequentially transmitted to the register 46. Through such a series of processes, a packet is transmitted from the communication module.

[0057] Referring to FIG. 5(A), the object code 34A (for convenience of explanation, using a similar expression of mnemonic (the same applies hereinafter)) includes an instruction group 341 for sequentially storing data in the memory 44 and an instruction group 342 for sequentially storing the data stored in the memory 44 in the register 46. As shown in FIG. 5(A), without including substantial information in the instruction set architecture setting code 38, the object code 34A may be generated according to the instruction set architecture 42 of the processor 40.

[0058] 5(B), when it is necessary to repeat the same process multiple times, any process may be defined in microprogram 48. For example, object code 34B includes a data store instruction 343 and a data move instruction 344.

[0059] The data store instruction 343 is written with an instruction code such as "BST Data Addr 4." Here, the meaning of the opcode "BST" and the format of the operand are as follows: , are written in the microprogram 48. Therefore, the data store instruction 343 is interpreted with reference to the microprogram 48.

[0060] Similarly, data movement instruction 344 is written with an instruction code such as "BMV Addr 4 Reg." Here, the meaning of the opcode "BMV" and the format of the operand are written in microprogram 48. Therefore, data movement instruction 344 is interpreted with reference to microprogram 48.

[0061] That is, the software development device 100 generates a microprogram that describes the meaning of an arbitrary opcode and the format of the corresponding operand, and also generates an object code 34 that uses the opcode described in the generated microprogram.

[0062] 6 is a diagram showing an example of processing in which software development device 100 according to the present embodiment generates instruction set architecture setting code 38 including configuration 50. FIG. 6 also shows, as an example, an example in which a packet is transmitted from a communication module.

[0063] FIG. 6(A) shows a configuration similar to FIG. 5(A). For the configuration shown in FIG. 6(A), wired logic suitable for transmitting packets from the communication module may be adopted, as shown in FIG. 6(B). More specifically, memories 441 to 444 may be cascade-connected, and input paths may be provided for storing data 1 to data 4 in memories 441 to 444, respectively. A circuit may also be provided for sequentially moving data stored in memories 441 to 444 to adjacent memories. By configuring wired logic suitable for processing to transmit packets from the communication module in this way, efficient processing can be achieved. Note that configuration 50 includes information for configuring wired logic such as that shown in FIG. 6(B).

[0064] 6B, the object code 34C generated at the same time can be a simple code including a transmission command 345 for transmitting a packet from the communication module. The transmission command 345 includes an opcode corresponding to the wired logic configured according to the configuration 50.

[0065] In this way, the wired logic and object code can be totally optimized, thereby further improving processing performance.

[0066] Here, as an example of a method for optimizing the combination of the instruction set architecture and the instruction code, the combination of the instruction set architecture and the instruction code may be determined depending on the number of repetitions and complexity of a specific process included in the source code 10. In other words, as an optimization method, the contents of the object code and the instruction set architecture setting code may be determined depending on the number of repetitions and complexity of a specific process included in the source code 10.

[0067] Alternatively, descriptions that match predetermined rules may be extracted from the descriptions contained in the source code 10, and a corresponding instruction set architecture may be assigned to the extracted descriptions, and an instruction code 36 (written in machine language) consisting of an opcode and operands that refer to the assigned instruction set architecture may be generated.

[0068] (d2: Processing example 2) FIG. 7 is a schematic diagram showing an example of processing of source code 10 by software development device 100 according to this embodiment. The source code 10 shown in FIG. 7 includes, for example, input processing code, arithmetic processing code, encryption processing code, and communication processing code. In the source code 10, each processing code may not be clearly distinguished.

[0069] The software development device 100 identifies the processes contained in the source code 10 through lexical analysis and syntactic analysis, and determines whether to use the object code 34 or the instruction set architecture setting code 38 (wired logic realized in the processor 40) to implement each process based on the number of repetitions of the identified process and the complexity of the process.

[0070] 7(A) shows an example in which all of the processes described in source code 10 are implemented in object code 14. For the sake of convenience, an example is shown in which the instructions for realizing each process are arranged individually, but in reality, optimized object format data is generated.

[0071] 7(B) shows an example in which the processes described in the source code 10, excluding the encryption process, are implemented in the object code 14. The instruction set architecture setting code 38 includes encryption processing logic for realizing the encryption process, and the object code 14 is configured to refer to the encryption processing logic defined by the instruction set architecture setting code 38. In other words, the instruction set architecture setting code 38 configures wired logic for executing the encryption process in the processor 40. The object code 14 is capable of executing the wired logic configured in the processor 40.

[0072] In this way, the software development device 100 optimizes the contents of the object code 14 and the instruction set architecture setting code 38 according to the contents of the source code 10 .

[0073] (d3: Processing example 3) Fig. 8 is a schematic diagram showing an example of code generation processing in software development device 100 according to the present embodiment. Fig. 8 is a graph of a portion of intermediate code generated from source code 10. That is, Fig. 8 shows an example of intermediate representation (IR) corresponding to the intermediate code.

[0074] The intermediate representation represents the contents of the source code 10 in a format independent of the object code 34 and instruction set architecture setting code 38 that are ultimately generated. For example, the intermediate representation may be represented in a tree structure as shown in FIG. 8, or may be represented as a combination of instruction sequences.

[0075] For example, by using pattern matching, etc., the software development device 100 extracts the same or similar parts (hereinafter also referred to as "common structures") from the structures included in the intermediate representation.

[0076] When the software development apparatus 100 determines that it is more advantageous to configure the wire logic in the processor 40 according to the processing content and complexity of the searched common structure, etc., it determines the dedicated logic corresponding to the common description and adds it as a part of the instruction set architecture 42 (see FIG. 2).

[0077] Note that the method for extracting the common structure included in the intermediate representation is not limited to pattern matching, and a method using known AI (artificial intelligence) may also be used. Also, any algorithm can be adopted for pattern matching.

[0078] As described above, by extracting the same or similar parts on the intermediate code (intermediate representation), even when there are fluctuations in the description of the source code 10 or differences in the descriptions among program creators, etc., optimization can be surely performed. Thereby, the object code 34 and the instruction set architecture setting code 38 can be generated more efficiently.

[0079] <E. Processing Procedure> Next, an example of the processing procedure executed by the software development apparatus 100 according to the present embodiment will be described.

[0080] FIG. 9 is a flowchart showing an example of the processing procedure executed by the software development apparatus 100 according to the present embodiment. Each step shown in FIG. 9 may typically be realized by the processor 102 of the software development apparatus 100 executing the software development program 120.

[0081] Referring to FIG. 9, the software development apparatus 100 reads the source code 10 (step S2) in response to a user operation, and performs lexical analysis of the source code 10 (step S4). Subsequently, the software development apparatus 100 determines the syntax structure included in the source code 10 based on the result of the lexical analysis (step S6), and generates an intermediate code based on the determined syntax structure (step S8).

[0082] The software development device 100 determines a combination of an instruction set architecture and instruction codes based on the results of lexical analysis and the generated intermediate codes (step S10). Then, the software development device 100 generates an object code 34 that can output the instruction codes determined from the intermediate codes according to the determined combination (step S12). Also, the software development device 100 generates an instruction set architecture setting code 38 that can implement the determined instruction set architecture according to the determined combination (step S14).

[0083] Thus, the process related to code generation from the source code 10 ends.

[0084] Finally, the software development device 100 transmits the generated object code 34 and instruction set architecture setting code 38 to the target device 200 according to a user operation (step S16).

[0085] <F. Advantages> According to the present embodiment, based on the analysis results of the source code, after optimizing the contents of the object code and the instruction set architecture setting code, an object code including instruction codes given to the processor, and an instruction set architecture setting code that defines the instruction set architecture of the processor are generated. By adopting such a configuration, a new software development technology that takes into account both the instruction set architecture of the processor and the instruction codes given to the processor can be realized.

[0086] It should be considered that all aspects of the embodiments disclosed this time are illustrative and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Explanation of Reference Numerals

[0087] 10 Source code, 12 Compiler, 14, 34, 34A, 34B, 34C Object code, 16, 36 Instruction code, 20, 40 Processor, 22, 42 Instruction set architecture, 32 Code generation module, 38 Instruction set architecture Configuration code, 44, 441-444 Memory, 46 Register, 48 Microprogram, 50 Configuration, 100 Software development equipment, 102 Processor, 104 Main memory, 106 Input section, 108 Display, 110 Hard disk, 112 Communication interface, 114 Internal bus, 120 Software development program, 121 Lexical analysis module, 122 Syntax analysis module, 123 Intermediate code generation module, 124 Optimization module, 125 Object code generation module, 126 Processor configuration code generation module, 200 Device, 341, 342 Instruction group, 343 Data storage instruction, 344 Data movement instruction, 345 Transmission instruction.

Claims

1. A software development apparatus that generates software to run on a reconfigurable processor, A means for analyzing source code and generating an intermediate representation that shows the contents of the source code in a tree structure, Means for extracting common structures that are identical or similar in the aforementioned intermediate representation, Means for determining the logic corresponding to the aforementioned common structure, Means for generating instruction set architecture configuration code that defines the instruction set architecture of the processor, including the determined logic, A software development apparatus comprising means for generating object code including instruction code for the processor whose logic is configured according to the instruction set architecture configuration code.

2. The software development apparatus according to claim 1, wherein the common structure is extracted using pattern matching or AI (artificial intelligence).

3. The software development apparatus according to claim 1 or 2, wherein the common structure is a portion that repeatedly appears in the intermediate expression.

4. The means for generating a microprogram that includes, as part of the instruction set architecture configuration code, the definition of an opcode for referencing the instruction set architecture configured on the processor, The software development apparatus according to any one of claims 1 to 3, wherein the means for generating the object code generates the instruction code corresponding to the definition of the opcode included in the microprogram.

5. The software development apparatus according to claim 4, wherein the definition of the opcode includes a definition that associates a plurality of processes using wired logic implemented in the processor with a single instruction code.

6. The software development apparatus according to any one of claims 1 to 5, further comprising means for generating instruction set architecture configuration code such that logic corresponding to a specific process described in the source code is set in the processor.

7. The software development apparatus according to any one of claims 1 to 6, wherein the object code is executed with wired logic configured in the processor according to the instruction set architecture configuration code.

8. A software development program for generating software that runs on a reconfigurable processor, for a computer, The steps include: analyzing the source code and generating an intermediate representation that shows the contents of the source code as a tree structure; The steps include extracting common structures that are identical or similar in the aforementioned intermediate representation, The steps include determining the logic corresponding to the aforementioned common structure, The steps include generating instruction set architecture configuration code that defines the instruction set architecture of the processor, including the determined logic, A software development program that causes a step of generating object code including instruction code for the processor, in which the logic is configured according to the instruction set architecture configuration code.

9. A computer-based software development method for generating software that runs on a reconfigurable processor, The steps include: analyzing the source code and generating an intermediate representation that shows the contents of the source code as a tree structure; The steps include extracting common structures that are identical or similar in the aforementioned intermediate representation, The steps include determining the logic corresponding to the aforementioned common structure, The steps include generating instruction set architecture configuration code that defines the instruction set architecture of the processor, including the determined logic, A software development method comprising the steps of generating object code including instruction code for the processor, in which the logic is configured according to the instruction set architecture configuration code.

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