In-vehicle control device and stack area allocation method

Abstract

To provide a technique for allocating a stack area capable of improving the use efficiency of a storage area.SOLUTION: The in-vehicle control device includes a CPU, a storage device connected to the CPU, a peripheral device connected to the CPU, and a cache memory provided in the CPU, and includes a reserved area, which is an address area to which an address of an existing resource including the storage device and the peripheral device is not allocated, in an addressable memory address space for storing and reading information from the CPU. An area having the same size as an address area in the reserved area is fixedly associated with a predetermined area of the cache memory, and the address area is set as a stack area.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an in-vehicle control device and a stack area allocation method, and more particularly to an in-vehicle control device that allocates a stack area to a cache memory. [Background technology]

[0002] The stack area (normally used area of ​​the stack) and the variable area (data area) exist in consecutive areas within the storage device (RAM), and a gap area (fail-safe area) is provided between the stack area and the variable area.This prevents the variable area outside the stack area from being overwritten even if the nesting level becomes deep due to function calls and the storage location of the stack data deviates from the stack area, causing a stuff overflow.When the gap area is accessed, a stuff overflow (a signal indicating an impending overflow) is notified. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-036261 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when a gap area is added between the stack area and the variable area in a storage device, the memory area available for the stack area and the variable area becomes smaller, resulting in poor utilization efficiency of the memory area.

[0005] The present disclosure can provide a stack area allocation technique that can improve the utilization efficiency of the storage area of ​​a storage device. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] The vehicle control device of the present disclosure has a CPU, a storage device connected to the CPU, a peripheral device connected to the CPU, and a cache memory provided in the CPU, and includes a reserved area, which is an address area to which addresses of existing resources including the storage device and the peripheral device are not assigned, in an addressable memory address space for saving and reading information from the CPU.An address of the same size as an address area in the reserved area is fixedly associated with a predetermined area of ​​the cache memory, and the address area is set as a stack area, and the cache memory is used to save stack data.

[0007] Furthermore, the stack area allocation method according to the present disclosure includes an on-board control device having a CPU, a storage device connected to the CPU, a peripheral device connected to the CPU, and a cache memory provided in the CPU, and includes a reserved area, which is an address area to which addresses of existing resources including the storage device and the peripheral device are not assigned, in an addressable memory address space for saving and reading information from the CPU.The method fixedly associates an area of ​​the same size as an address area within the reserved area with a predetermined area of ​​the cache memory, and sets the address area as a stack area. [Effects of the Invention]

[0008] According to the present disclosure, by allocating a predetermined area of ​​a cache memory that does not have an address to an address in a reserved area and further using that area as a stack area, it is possible to prevent variables outside the stack area from being overwritten in the event of a stack overflow. Furthermore, since a stack area and a gap area are not required within the storage device, it is possible to improve the utilization efficiency of the storage area of ​​the storage device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an overall configuration of an on-vehicle control device according to a first embodiment. [Figure 2]FIG. 10 is a diagram illustrating a processing flow of a stack area in a reserved area when a function is executed according to the first embodiment. [Figure 3] FIG. 10 is a diagram illustrating a processing flow when a stack overflow occurs according to the first embodiment. [Figure 4] FIG. 10 is a diagram illustrating a configuration of a stack area when the on-board control device according to the second embodiment has a plurality of CPUs. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, with reference to the accompanying drawings, embodiments for carrying out the present disclosure will be described in detail. However, in the following description, the same components will be designated by the same reference numerals, and repeated explanations may be omitted. Note that the drawings may be more schematic than the actual embodiment for the purpose of clarifying the description, but they are merely examples and do not limit the interpretation of the present invention. [Example]

[0011] Fig. 1 is a diagram showing the overall configuration of an on-board control device according to Example 1. As shown in Fig. 1, an arithmetic device 120 serving as an on-board control device includes a CPU 100 which is a central processing unit (referred to as CPU1), a storage device 101 connected to the CPU 100, a peripheral device 108 connected to the CPU 100, and a cache memory 103 provided in the CPU 100. The storage device 101 can be, for example, a volatile static random access memory or a dynamic random access memory.

[0012] The arithmetic device 120 includes an addressable memory address space 130 for storing and reading information from the CPU 100. In this example, the memory address space 130 is provided between the hexadecimal address 0x0000_0000 and the hexadecimal address 0xFFFF_FFFF. The memory address space 130 is configured to include address areas to which addresses of existing resources including the storage device 101 and the peripheral device 108 are assigned (address area 106 of the storage device 101, address area 109 of the peripheral device 108), and a reserved area 102 which is an address area to which addresses of existing resources including the storage device 101 and the peripheral device 108 are not assigned.

[0013] The computing device 120 has a locking function (also called locking processing) that enables a predetermined area (here, 104) of the cache memory 103 to be allocated to a predetermined area (here, 102) of the memory address space 130.

[0014] The arithmetic unit 120 is set using this lock function. That is, a part of the address area 105 in the reserved area 102 is fixedly assigned to a predetermined part of the area 104 of the cache memory 103 using a lock process at the time of startup, such as when the arithmetic unit 120 is powered on (power ON). That is, an address of the same size as the part of the address area 105 in the reserved area 102 is fixedly associated with the predetermined part of the area 104 of the cache memory 103. Then, the part of the address area 105 is set as a stack area, and the predetermined part of the area 104 of the cache memory 103 is used to store stack data.

[0015] This stack area allocation method allows access to a predetermined area 104 in the cache memory 103 using an address in the address area 105, and the address area 105 can be used as a stack area (a stack data storage area). The address area 105 may also be referred to as the stack area 105 or the stack data storage area 105.

[0016] The address of the address area 105 is set so as to be arranged to include another address area 107 of the reserved area 102, which has the characteristic of being a gap area that prevents the address area 106 of the storage device 101 from being overwritten, between a portion of the address area 105 in the reserved area 102 and the address area 106 allocated to the storage device 101. In this example, the other address area 107 is contiguous with the portion of the address area 105 above the memory address space 130. As a result, even if the nesting level due to a function call becomes deep and the storage location of the stack data deviates from the stack area 105, causing a stack overflow, since the address area 107 is an address area that has the characteristic of being a gap area 107 that prevents the address area 106 of the storage device 101 from being overwritten, it is possible to prevent the variables (variable data) of the address area 106 from being overwritten by accesses from outside the stack area 105.

[0017] In the above example, the increased stack data is stored in the stack area 105 starting from the boundary with a larger address in the direction of smaller addresses. However, the increased stack data may also be stored starting from the boundary with a smaller address in the direction of larger addresses. In this case, it is preferable to place a reserved area 110 between the stack area 105 and the address area 109 of the peripheral device 108. The reserved area 110 can be referred to as a gap area.

[0018] According to the present disclosure, a predetermined area 104 of a cache memory 103 that does not have an address is allocated to an address in an address area 105 in a reserved area 102, and furthermore, the address area 105 is used as a stack area. This makes it possible to prevent variables in an address area 106 outside the stack area 105 from being overwritten when a stack overflow occurs. Furthermore, since a stack area and a gap area are not required within the storage device 101, the utilization efficiency of the storage area of ​​the storage device 101 can be improved.

[0019] 2 is a diagram showing the flow of processing in the stack area within the reserved area when a function is executed. Steps S1 to S3 will be explained below. Step S1 (before executing the function): Before the CPU 100 executes a function, that is, before the CPU 100 executes a function, the stack area 105, which is a stack data storage area, is still unused.

[0020] Step S2 (function execution): While CPU 100 is executing a function, that is, while CPU 100 is executing the function, addresses in reserved area 102 are allocated to secure addresses for a first area (variable storage area) 200 used for the internal variables of the function, a second area (return address storage area) 201 for saving the address to return to when function execution ends (return address), and a third area (argument storage area) 202 used for arguments of the function. That is, three different addresses (AAD1, AAD2, AAD3) in stack area 105 are allocated to first area 200 to third area 202, respectively. For example, if the three addresses are AAD1, AAD2, and AAD3, address AAD1 is allocated to first area 200, address AAD2 is allocated to second area 201, and address AAD3 is allocated to third area 202.

[0021] Step S3 (end of function execution): When CPU 100 finishes executing a function, that is, when CPU 100 finishes executing the function, it releases or frees three different addresses in stack area 105 allocated to first area 200 used for the function's internal variables, second area 201 for saving the return address when function execution ends, and third area 202 used for the function's arguments. For example, three addresses (AAD1, AAD2, AAD3) are released: address AAD1 allocated to first area 200, address AAD2 allocated to second area 201, and address AAD3 allocated to third area 202. This makes it possible to use stack area 105 for the next function processing.

[0022] FIG. 3 shows the processing flow when a stack overflow occurs. When a stack overflow occurs, stack data storage area 105 is already occupied by stack data, so CPU 100 attempts to save stack data to address area 107 outside stack area 105 in reserved area 102 adjacent to stack data storage area 105. However, address area 107 is characterized as a gap area that prevents address area 106 of storage device 101 from being overwritten. Therefore, CPU 100 detects or senses a memory access error during the stack data save process and generates exception interrupt 300 to notify the user of calculation device 120 of the abnormal state. After notifying the user of the abnormal state, calculation device 120 is reset 301. This notifies the user that a stack overflow has occurred, and allows the state in which calculation device 120 is unable to execute normal functions to be resolved quickly. [Example]

[0023] FIG. 4 is a diagram illustrating a configuration of a stack area when an on-board control device according to a second embodiment of the present disclosure has multiple CPUs.

[0024] The arithmetic device 400 as an on-board control device includes multiple CPUs, a first CPU 100 and a second CPU 401, a first cache memory 103 of the CPU 100, a second cache memory 402 of the CPU 401, a storage device 101 connected to the CPUs 100 and 401, and a peripheral device 108 connected to the CPUs 100 and 401.

[0025] When the arithmetic device 400 is started up, addresses are fixedly assigned to a predetermined area 104 of the cache memory 103 of the CPU 100 to a first address area 105 in the reserved area 102, and to a predetermined area 403 of the cache memory 402 of the CPU 401 to a second address area 404 in the reserved area 102.

[0026] The cap area 107 is provided between the address area 106 of the memory device 101 and the first address area 105, between the first address area 105 and the second address area 404, and between the second address area 404 and the address area 109 of the peripheral device 108, respectively.

[0027] The processing flow of the stack area in the reserved area when a function is executed can be explained using Figure 2 for each CPU 101, 401, so duplicated explanations will be omitted. Also, the processing flow when a stack overflow occurs can be explained using Figure 3 for each CPU 101, 401, so duplicated explanations will be omitted.

[0028] This allows area 104 of cache memory 103 to be accessed using an address in first address area 105. Also, area 403 of cache memory 402 can be accessed using an address in second address area 404. The first address area 105 can be used as a stack area for CPU 100, and the second address area 404 can be used as a stack area for CPU 401.

[0029] By dividing the addresses of the stack areas 105, 404 in the reserved area 102 for the CPU 100 and the CPU 401, it is possible to prevent overlapping of the stack areas 105, 402 in the reserved area 102. Furthermore, it is possible to obtain the same effects as in the first embodiment.

[0030] The disclosure made by the present inventor has been specifically described above based on examples, but it goes without saying that the present disclosure is not limited to the above-described embodiments and examples, and various modifications are possible. [Explanation of symbols]

[0031] 100:CPU1 101: Storage device 102: Reserved area 103: Cache memory in CPU1 104: Part of the cache memory in CPU1 105: Part of the cache memory in CPU1 allocated to an address in the reserved area (part of the address area) 106: Address area of ​​storage device 107: Other reserved areas (gap areas, other address areas) between the storage device and the stack area in the reserved area 108: Peripheral devices 109: Peripheral device address area 110: Another reserved area between the peripheral device and the stack area in the reserved area 120: Calculation device (on-board control device) 130: Addressable memory address space for storing and retrieving information from the CPU 200: Address of the internal variable area in the stack in the reserved area 201: Address of the function return address area in the stack in the reserved area 202: Address of the function argument area in the stack in the reserved area 300: Exception interrupt notification on stack overflow 400: Calculation device including multiple CPUs (vehicle control device) 401:CPU2 402: Cache memory in CPU2 403: Part of the cache memory in CPU2 404: Part of the cache memory in CPU2 allocated to an address in the reserved area

Claims

1. A CPU and a storage device connected to the CPU; a peripheral device connected to the CPU; a cache memory provided in the CPU; An in-vehicle control device including a reserved area, which is an address area to which addresses of existing resources including the storage device and the peripheral device are not assigned, in an addressable memory address space for storing and reading information from the CPU, The in-vehicle control device fixedly associates an area of ​​the same size as a part of the address area in the reserved area with a predetermined area of ​​the cache memory, and sets the part of the address area as a stack area.

2. The reserved area includes: In the address space, the address area is continuous with the part of the address area, The on-vehicle control device according to claim 1 , further comprising another address area located between the partial address area and the address area allocated to the storage device.

3. 2. The in-vehicle control device according to claim 1, wherein, when the CPU executes a function, addresses of the reserved area are respectively assigned within the stack area as an address for an area used for internal variables, an address for an area for saving a return address at the end of function execution, and an address for an area used for arguments of the function in order to process internal variables of the function.

4. 4. The in-vehicle control device according to claim 3, wherein, when the CPU completes execution of a function, the addresses of the reserved area allocated to the area used for the internal variables, the area for saving the address to return to when the function execution completes, and the area used for arguments of the function are released.

5. 2. The in-vehicle control device according to claim 1, wherein, when an access outside the stack area occurs due to a stack overflow, the CPU generates an exception interrupt, and the in-vehicle control device notifies the occurrence of the stack overflow.

6. The on-board control device according to claim 5 , wherein the on-board control device is reset after the CPU generates the exception interrupt.

7. the CPUs include a first CPU including a first cache memory and a second CPU including a second cache memory; a first address area and a second address area are included within the reserved area; When the on-board control device is started, a first predetermined area in the first cache memory is assigned to the first address area, and a second predetermined area in the second cache memory is assigned to the second address area; 2. The on-board control device according to claim 1, wherein the first address area is used as a stack area for the first CPU, and the second address area is used as a stack area for the second CPU.

8. A stack area allocation method for an on-board control device having a CPU, a storage device connected to the CPU, a peripheral device connected to the CPU, and a cache memory provided in the CPU, wherein the on-board control device includes a reserved area, which is an address area to which addresses of existing resources including the storage device and the peripheral device are not assigned, in an addressable memory address space for saving and reading information from the CPU, and the method fixedly associates an area of ​​the same size as an address area within the reserved area with a predetermined area of ​​the cache memory, and sets the address area as a stack area.

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