Display device and mother substrate

Abstract

To provide a display device and a mother substrate capable of shortening a measurement time.SOLUTION: A display device according to an embodiment includes a substrate, a display region configured to display an image, a peripheral region outside the display region, a partition wall located above the substrate and including a lower portion disposed in the peripheral region and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion, and a vernier disposed in the peripheral region and between the substrate and the partition wall. The vernier includes a plurality of scale lines extending in the first direction and arranged at an equal pitch in a second direction intersecting the first direction, and at least a part of the plurality of scale lines is located between the first partition wall and the second partition wall in the first direction.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device and a motherboard. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. This type of display device requires high-level quality control. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a motherboard that can reduce the measurement time. [Means for solving the problem]

[0005] A display device according to one embodiment includes a substrate, a display region for displaying an image, a peripheral region outside the display region, a partition wall located above the substrate and including a lower portion disposed in the peripheral region and an upper portion disposed on top of the lower portion and protruding from a side surface of the lower portion, and a vernier located in the peripheral region and between the substrate and the partition wall, wherein the partition wall includes a first partition wall and a second partition wall adjacent to each other in a first direction, and the vernier has a plurality of scale lines extending in the first direction and arranged at equal intervals in a second direction intersecting the first direction, and at least some of the plurality of scale lines are located between the first partition wall and the second partition wall in the first direction.

[0006] A motherboard according to one embodiment includes a substrate; a plurality of panel portions each including a display area, a peripheral area outside the display area, and a margin area surrounding the peripheral area; a partition wall located above the substrate and including a lower portion disposed in the peripheral area and an upper portion disposed on top of the lower portion and protruding from a side surface of the lower portion; and a vernier disposed across the peripheral area and between the substrate and the partition wall, wherein the partition wall includes a first partition wall and a second partition wall adjacent to each other in a first direction, and the vernier has a plurality of scale lines extending in the first direction and arranged at equal intervals in a second direction intersecting the first direction, and at least some of the plurality of scale lines are located between the first partition wall and the second partition wall in the first direction. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to this embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is an enlarged view of the area enclosed by the dashed line frame IV in FIG. [Figure 5]FIG. 5 is a schematic cross-sectional view of the display device taken along line VV in FIG. [Figure 6] FIG. 6 is a schematic plan view of the motherboard according to this embodiment. [Figure 7] FIG. 7 is a schematic plan view of the panel section. [Figure 8] FIG. 8 is an enlarged view of the area enclosed by the dashed line frame VIII in FIG. [Figure 9] FIG. 9 is a plan view of the peripheral region of the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the disclosure are naturally included within the scope of the present disclosure. Furthermore, in the drawings, the width, thickness, shape, etc. of each part may be schematically depicted compared to the actual embodiment for clarity of explanation, but these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with respect to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X-, Y-, and Z-axes are shown as necessary to facilitate understanding. The direction along the X-axis is referred to as the X-direction (second direction), the direction along the Y-axis is referred to as the Y-direction (first direction), and the direction along the Z-axis is referred to as the Z-direction. Viewing various elements parallel to the Z-direction is referred to as a planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] FIG. 1 is a diagram showing an example of the configuration of a display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film. The substrate 10 has an outline 10E surrounding the substrate 10 and corresponding to the outline of the substrate 10.

[0012] In this embodiment, the shape of the substrate 10 in plan view is substantially circular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as rectangular, square, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a green subpixel SP1, a red subpixel SP2, and a blue subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the drive transistor 3 and the capacitor 4. The source electrode of the drive transistor 3 is connected to the power line PL and the capacitor 4. The drain electrode of the drive transistor 3 is connected to the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP1 and SP2 are aligned with subpixel SP3 in the X direction. Furthermore, subpixels SP1 and SP2 are aligned with each other in the Y direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP2 are alternately arranged in the Y direction and columns in which multiple subpixels SP3 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel openings AP1 and AP2 are quadrilaterals with the same area. On the other hand, the pixel opening AP3 is a rectangle that is longer in the Y direction than the pixel openings AP1 and AP2. Note that the sizes and shapes of the pixel openings AP1, AP2, and AP3 are not limited to this example.

[0022] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0023] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] Conductive partition walls 6A are arranged in the display area DA. The partition walls 6A are located above the rib layer 5 and entirely overlap the rib layer 5. In the example of FIG. 2, the partition walls 6A have the same planar shape as the rib layer 5. That is, the partition walls 6A have openings in the subpixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition walls 6A have a lattice shape in a planar view and surround the display elements DE1, DE2, and DE3, respectively. The partition walls 6A serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0025] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0026] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 (the drain electrode of the drive transistor 3 shown in FIG. 1) through a contact hole provided in the organic insulating layer 12.

[0027] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. This shape of the partition wall 6A is called an overhanging shape.

[0028] In the example of FIG. 3, the lower part 61 has a bottom layer 63 arranged on the rib layer 5 and a shaft layer 64 arranged on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In the example of FIG. 3, both end parts of the bottom layer 63 protrude from the side surfaces of the shaft layer 64. In addition, the end parts of the bottom layer 63 are located between the end parts of the upper part 62 and the side surfaces of the shaft layer 64 in a plan view. The upper part 62 is arranged on the shaft layer 64.

[0029] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6A.

[0030] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0031] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0032] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively, to cover the stacked films FL1, FL2, and FL3. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6A around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6A around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6A around it.

[0033] 3, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6A. Also, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6A. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6A.

[0034] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6A. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0035] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0036] A polarizing plate 15 is disposed above the resin layer RS2. In the example shown in Fig. 3, the polarizing plate 15 is adhered to the upper surface of the resin layer RS2 via an adhesive layer 14. The polarizing plate 15 covers the entire display area DA. The adhesive layer 14 may be made of an adhesive such as OCA (Optical Clear Adhesive).

[0037] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0038] The lower electrodes LE1, LE2, and LE3 each include a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. The reflective layer can be made of a metal material with excellent light reflectivity, such as silver. Each conductive oxide layer can be made of a transparent conductive oxide, such as ITO (indium tin oxide), IZO (indium zinc oxide), or IGZO (indium gallium zinc oxide).

[0039] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0040] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emitting layers.

[0041] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0042] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of, for example, a metal material. Examples of the metal material for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum (Al), an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a laminated structure of multiple layers. The shaft layer 64 may also include a layer formed of an insulating material.

[0043] For example, the upper portion 62 of the partition wall 6A has a laminated structure of a lower layer made of a metal material and an upper layer made of a conductive oxide. Examples of the metal material that can be used to form the lower layer include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the upper layer include ITO and IZO. The upper portion 62 may also have a single-layer structure made of a metal material. Furthermore, the upper portion 62 may also include a layer made of an insulating material.

[0044] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0045] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the red wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the blue wavelength range.

[0046] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0047] Fig. 4 is an enlarged view of the area surrounded by the dashed line frame IV in Fig. 1. A plurality of partition walls 6B and a vernier VE are arranged in the peripheral area SA. In one example, the plurality of partition walls 6B are spaced apart from one another and extend longitudinally along the outline 10E. In the example shown in Fig. 4, the plurality of partition walls 6B (first partition walls and second partition walls) extend in the Y direction and are adjacent to one another in the Y direction.

[0048] The vernier VE is located between the partition walls 6B adjacent to each other in the Y direction. The vernier VE has a plurality of scale lines SC. In the example shown in FIG. 4, the plurality of scale lines SC include scale lines S1, S2, S3, S4, and S5. At least a portion of the plurality of scale lines SC is located between the partition walls 6B adjacent to each other in the Y direction. In the example shown in FIG. 4, the scale line S3 is located between the partition walls 6B adjacent to each other in the Y direction. The scale lines S1 to S5 extend in the Y direction and are formed in the shape of a rectangle that is elongated in the Y direction. The scale line S1 has an end S1Y that is located on the display area DA side among the ends parallel to the Y direction. The scale line S3 has an end S3Y that is located on the outline 10E side among the ends parallel to the Y direction.

[0049] In the example shown in Fig. 4, the scale lines S1 to S4 all have the same width in the X direction. Furthermore, the width of the scale line S5 in the X direction is approximately half of the width of each of the scale lines S1 to S4 in the X direction. As will be described in detail later, depending on the cutting position when cutting out the substrate 10 from the mother substrate for a display device (mother substrate MB shown in Fig. 6) along the outline 10E, the width of the scale line S5 in the X direction differs from that in the example shown in Fig. 4. Furthermore, depending on the cutting position, the number of scale lines on the vernier VE changes. Therefore, although the number of scale lines included in the scale lines SC is five in the example shown in Fig. 4, it may be four or less, or six or more.

[0050] The multiple scale lines SC are arranged at equal pitches in the X direction. Specifically, the scale lines S1 to S5 each have the same pitch P. In one example, the pitch P is about 25 μm.

[0051] In the example shown in FIG. 4, the scale lines S1, S2, and S3 have the same length in the Y direction, and the scale lines S4 and S5 have the same length in the Y direction. If the length of the scale lines S1, S2, and S3 (first scale lines) in the Y direction is defined as length L1 (first length) and the length of the scale lines S4 and S5 (second scale lines) in the Y direction is defined as length L2 (second length), then length L1 is greater than length L2 (L1 > L2). The relationship between the lengths of the scale lines S1 to S5 in the Y direction is not limited to this example. For example, the lengths of the scale lines S1 to S5 in the Y direction may all be the same. That is, length L1 may be equal to length L2 (L1 = L2). Alternatively, the lengths of the scale lines S1 to S5 in the Y direction may all be different. In one example, length L1 is approximately 220 to 240 μm, and length L2 is approximately 90 to 110 μm.

[0052] The distance between adjacent partition walls 6B in the Y direction is defined as distance D6B. In the example shown in FIG. 4, distance D6B is smaller than length L1 and larger than length L2 (L1>D6B>L2). Therefore, both end portions S3E of the scale mark S3 in the Y direction overlap with the partition walls 6B adjacent to each other in the Y direction in plan view. Note that only one of the end portions S3E may overlap with the partition wall 6B in plan view. Furthermore, distance D6B may be larger than length L1. In other words, the partition walls 6B and the scale lines S1 to S5 may not overlap with each other in plan view. Center portions C1 (areas surrounded by chain lines) of the multiple scale lines SC do not overlap with the partition walls 6B in plan view. Center portions C1 are portions that include the centers of the multiple scale lines SC in the Y direction.

[0053] An end 15E of the polarizing plate 15 is located in the peripheral area SA. In the example shown in Fig. 4, the end 15E is located between the display area DA and the vernier VE in a plan view.

[0054] The vernier VE is arranged not only in the area surrounded by the chain-line frame IV shown in Fig. 1, but also in multiple areas of the peripheral area SA. In one example, the vernier VE is arranged in an area on the opposite side of the chain-line frame IV across the display area DA, or in an area on the opposite side of the terminal section T across the display area DA. When the vernier VE is arranged in an area on the opposite side of the terminal section T across the display area DA, the multiple scale lines SC included in the vernier VE in that area extend in the X direction and are formed into a rectangular shape that is elongated in the X direction.

[0055] The vernier VE is used to check how much the actual cutting position deviates from the target cutting position when the panel portion PP of the motherboard MB (described later) is cut along the cutting line CL2. Specifically, it measures the distance between the scale line SC and the outline 10E. In the example shown in FIG. 4, it is possible to measure the distance M3 in the X direction between the end S3Y of the scale line S3 and the outline 10E. If the actual cutting position deviates to the right of the target cutting position in the figure, the distance M3 will be greater than the target value. On the other hand, if the actual cutting position deviates to the left of the target cutting position in the figure, the distance M3 will be smaller than the target value. By measuring in this way, it is possible to measure the amount of deviation between the actual cutting position and the target cutting position.

[0056] The vernier VE can also be used to check the amount of deviation in the attachment position of the polarizing plate 15. Specifically, by measuring the distance M1 in the X direction between the edge 15E of the polarizing plate 15 and the edge S1Y of the scale line S1, the amount of deviation between the actual attachment position of the polarizing plate 15 and the target attachment position can be checked. In addition to the above example, the vernier VE can be used for various other measurements.

[0057] 5 is a schematic cross-sectional view of the display device DSP taken along line VV in FIG. 4. The circuit layer 11 described above has inorganic insulating layers 31 and 32 arranged in this order on the substrate 10. The inorganic insulating layers 31 and 32 are formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. Note that the circuit layer 11 may further have a plurality of inorganic insulating layers and organic insulating layers in addition to the inorganic insulating layers 31 and 32. The inorganic insulating layer 32 is covered with a rib layer 5.

[0058] The partition wall 6B is disposed on the rib layer 5. Like the partition wall 6A, the partition wall 6B includes a lower portion 61 including a bottom layer 63 and a shaft layer 64, and an upper portion 62. In the partition wall 6B, both end portions of the upper portion 62 also protrude from the side surfaces of the lower portion 61. The bottom layer 63 and the shaft layer 64 of the partition wall 6B are formed of, for example, a metal material. The upper portion 62 of the partition wall 6B has a laminated structure of, for example, a lower layer formed of a metal material and an upper layer formed of a conductive oxide.

[0059] The vernier VE is disposed between the substrate 10 and the partition wall 6B in the Z direction. Specifically, the plurality of scale lines SC of the vernier VE are disposed between the inorganic insulating layers 31 and 32.

[0060] The width of the partition wall 6B (upper portion 62) in the X direction is defined as width W1, and the width of each of the multiple scale lines SC in the X direction is defined as width W2. Width W2 is smaller than width W1 (W1>W2).

[0061] The scale lines SC are made of a metal material such as titanium, aluminum, molybdenum, tungsten, or a molybdenum-tungsten alloy. In the example shown in Fig. 5, the scale lines SC are made of a molybdenum-tungsten alloy. The scale lines SC may be formed as a single layer, or as a laminate of different metal layers.

[0062] The multiple scale lines SC are arranged in the same layer as the scanning lines GL shown in Fig. 1 and are made of the same material as the scanning lines GL. In other words, the multiple scale lines SC are formed simultaneously with the scanning lines GL in the process of forming the scanning lines GL.

[0063] When manufacturing the display device DSP, a large motherboard is fabricated on which a plurality of regions (panel sections) each corresponding to a display device DSP are formed. The following describes a configuration that can be applied to this motherboard.

[0064] 6 is a schematic plan view of the mother substrate MB according to this embodiment. The mother substrate MB is rectangular as shown in the figure, but may be circular or have other shapes.

[0065] The motherboard MB has a plurality of panel units PP arranged in a matrix, with blank areas BA1 surrounding the panel units PP. In the example of Fig. 6, the panel units PP are arranged in the X and Y directions with blank areas BA1 between them. However, the arrangement of the panel units PP on the motherboard MB is not limited to this example. As another example, some panel units PP may be arranged without blank areas BA1 between them.

[0066] 7 is a schematic plan view of the panel portion PP. The outer shape of the panel portion PP corresponds to the cutting lines CL1 along which each panel portion PP is cut out from the motherboard MB.

[0067] The panel unit PP has the above-mentioned display area DA and peripheral area SA, and a blank area BA2 surrounding the peripheral area SA. A cut line CL2, which defines the outline of the substrate 10 of the display device DSP, is arranged between the peripheral area SA and the blank area BA2. The cut line CL2 corresponds to the outline 10E shown in FIG. 1. The blank area BA2 corresponds to the area between the cut lines CL1 and CL2. The peripheral area SA corresponds to the area between the display area DA and the cut line CL2.

[0068] The blank area BA2 includes an inspection area TA between the cut lines CL1 and CL2. A plurality of inspection pads TD for inspecting the operation of the display panel PNL are arranged in the inspection area TA. Each inspection pad TD is connected to a terminal portion T via a wiring WL.

[0069] The cut line CL2 passes between the terminal portion T and each test pad TD near the terminal portion T. That is, the cut line CL2 crosses each wiring WL.

[0070] When manufacturing the display device DSP, the panel portion PP is cut out from the mother substrate MB along the cut line CL1. Further, the cut-out panel portion PP is inspected using the inspection pads TD. After this inspection, the blank area BA2 is cut out from the panel portion PP along the cut line CL2.

[0071] Fig. 8 is an enlarged view of the area surrounded by the dashed line frame VIII in Fig. 7. Similar to the peripheral area SA, a plurality of partitions 6B are also arranged in the marginal area BA2. In the example shown in Fig. 8, the partitions 6B in the peripheral area SA and the partitions 6B in the marginal area BA2 have different lengths in the Y direction, but they may also be the same. A vernier VE is arranged across the peripheral area SA and the marginal area BA2.

[0072] The plurality of scale lines SC includes scale lines S1 to S9. The scale lines S1 to S9 extend in the Y direction and are formed in the shape of a rectangle that is elongated in the Y direction. The number of scale lines included in the plurality of scale lines SC is not limited to the example shown in Fig. 8. A central portion C1 of the plurality of scale lines SC in the Y direction does not overlap with the partition wall 6B in plan view.

[0073] The scale lines S1 to S9 all have the same width in the X direction. The scale lines S1 to S9 are arranged at equal pitches in the X direction. Specifically, the pitch P of each of the scale lines S1 to S9 is equal.

[0074] In the example shown in FIG. 8, the scale lines S1, S2, and S3 have the same length in the Y direction, the scale lines S4, S5, and S6 have the same length in the Y direction, and the scale lines S7, S8, and S9 have the same length in the Y direction. The length of the scale lines S1, S2, and S3 in the Y direction is defined as length L1, the length of the scale lines S4, S5, and S6 in the Y direction is defined as length L2, and the length of the scale lines S7, S8, and S9 in the Y direction is defined as length L3. In this case, length L3 is greater than length L2 and less than length L1 (L1 > L3 > L2). However, the relationship between the lengths of the scale lines S1 to S9 in the Y direction is not limited to this. For example, the lengths of the scale lines S1 to S9 in the Y direction may all be the same. In other words, lengths L1, L2, and L3 may all be equal (L1 = L2 = L3). Furthermore, the scale lines S1 to S9 may all have different lengths in the Y direction. In one example, the length L3 is about 150 to 170 μm.

[0075] The cut line CL2 overlaps with the vernier VE. In the example shown in Fig. 8, the cut line CL2 overlaps with the scale line S5. The blank area BA2 is removed by cutting the panel portion PP along the cut line CL2. The peripheral area SA remains after cutting the panel portion PP, resulting in a configuration similar to that shown in Fig. 4.

[0076] The position of the cut line CL2 varies depending on the cutting accuracy, positioning accuracy, etc., so the cut line CL2 does not necessarily have to overlap with the scale line S5. For example, the cut line CL2 may overlap with a scale line other than the scale line S5, or may be located between adjacent scale lines SC.

[0077] 9 is a plan view of the peripheral area SA of a comparative example. In the example of FIG. 9, the partition walls 6B and the scale lines S3 overlap, and most of the scale lines S3 overlap with the partition walls 6B. In particular, the central portions C1 overlap with the partition walls 6B. Because the partition walls 6B include a layer formed of a metal material and are positioned above the scale lines SC, it is difficult to visually recognize the scale lines S3 that overlap with the partition walls 6B in a plan view. Therefore, when trying to measure the distance between the scale lines S3 and the outline 10E, it may take a long time to measure the distance.

[0078] In this embodiment, the vernier VE is located between the partition walls 6B adjacent in the Y direction. Therefore, most of the scale lines SC do not overlap with the partition walls 6B. In particular, the central portion C1 does not overlap with the partition walls 6B. This improves the visibility of the scale lines SC and makes it easier to measure distances. As a result, measurement time is shortened, and production efficiency can be improved.

[0079] 4 and 8, both end portions S3E of the scale lines S3 overlap the partition wall 6B. Even in such a case, most of the scale lines S3 do not overlap the partition wall 6B, and the center portion C1 does not overlap the partition wall 6B. Therefore, there is almost no effect on distance measurement. In other words, some of the scale lines SC may overlap the partition wall 6B as long as the visibility of the scale lines SC is not impaired. This allows for a wider range of design options for the partition wall 6B and the vernier VE.

[0080] Additionally, the length L1 of the scale lines S1 to S3, the length L2 of the scale lines S4 to S6, and the length L3 of the scale lines S7 to S9 are all different. This makes it possible to immediately determine which of the multiple scale lines SC is the scale line of interest during measurement. As a result, measurement time is shortened and production efficiency is improved.

[0081] Furthermore, the vernier VE is located in the same layer as the scanning lines GL, and is formed in the same process as the process of forming the scanning lines GL. Therefore, there is no need to provide a separate process for forming the vernier VE, and the manufacturing cycle can be shortened. Furthermore, the thickness of the scanning lines GL is relatively thin compared to the thickness of other metal layers located between the substrate 10 and the partition wall 6B. Therefore, even if the vernier VE is formed in the peripheral region SA, the thickness of the vernier VE has little effect on other layers.

[0082] All display devices and motherboards that can be implemented by a person skilled in the art by making appropriate design modifications based on the display devices and motherboards described above as embodiments of the present disclosure also fall within the scope of the present disclosure as long as they include the gist of the present disclosure.

[0083] Within the scope of the concept of the present disclosure, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present disclosure. For example, modifications in which a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiments, or adds or omits steps or modifies conditions, are also included within the scope of the present disclosure as long as they include the gist of the present disclosure.

[0084] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present disclosure. [Explanation of symbols]

[0085] MB...motherboard, DSP...display device, DE1, DE2, DE3...display element, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, 5...rib layer, 6A, 6B...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, VE...vernier, SC, S1 to S9...scale lines.

Claims

1. A substrate; a display area for displaying an image; a peripheral area outside the display area; a partition wall including a lower portion disposed above the substrate in the peripheral region and an upper portion disposed above the lower portion and protruding from a side surface of the lower portion; a vernier disposed in the peripheral region and between the substrate and the partition wall; the partition walls include a first partition wall and a second partition wall adjacent to each other in a first direction, the vernier has a plurality of scale lines extending in the first direction and arranged at equal intervals in a second direction intersecting the first direction, At least some of the plurality of scale lines are located between the first partition wall and the second partition wall in the first direction. Display device.

2. central portions of the plurality of scale lines in the first direction do not overlap with the partition wall in a plan view; The display device according to claim 1 .

3. a width of each of the plurality of scale lines in the second direction being smaller than a width of the partition wall in the second direction; The display device according to claim 1 .

4. the plurality of scale lines include a first scale line having a first length in the first direction and a second scale line having a second length in the first direction that is shorter than the first length; The display device according to claim 1 .

5. a distance between the first partition wall and the second partition wall in the first direction is smaller than the first length and larger than the second length; The display device according to claim 4 .

6. a distance between the first partition wall and the second partition wall in the first direction is smaller than a length in the first direction of some of the plurality of scale lines; The display device according to claim 1 .

7. one end of some of the plurality of scale lines overlaps with the first partition wall in a plan view; The display device according to claim 1 .

8. a polarizing plate positioned above the substrate and covering the display area; an end of the polarizing plate is located between the display area and the vernier in a plan view; The display device according to claim 1 .

9. the plurality of scale lines are formed of a metal material; The display device according to claim 1 .

10. a plurality of scanning lines extending in the second direction in the display area; the plurality of scale lines are formed of the same material as the scanning lines; The display device according to claim 1 .

11. the upper portion includes a layer formed of a metal material; The display device according to claim 1 .

12. A substrate; a plurality of panel sections each including a display area, a peripheral area outside the display area, and a blank area surrounding the peripheral area; a partition wall including a lower portion disposed above the substrate in the peripheral region and an upper portion disposed above the lower portion and protruding from a side surface of the lower portion; a vernier disposed across the peripheral region and the margin region and between the substrate and the partition wall, the partition walls include a first partition wall and a second partition wall adjacent to each other in a first direction, the vernier has a plurality of scale lines extending in the first direction and arranged at equal intervals in a second direction intersecting the first direction, At least some of the plurality of scale lines are located between the first partition wall and the second partition wall in the first direction. Motherboard.

13. central portions of the plurality of scale lines in the first direction do not overlap with the partition wall in a plan view; The motherboard according to claim 12.

14. a width of each of the plurality of scale lines in the second direction being smaller than a width of the partition wall in the second direction; The motherboard according to claim 12.

15. the plurality of scale lines include a first scale line having a first length in the first direction and a second scale line having a second length in the first direction that is shorter than the first length; The motherboard according to claim 12.

16. a distance between the first partition wall and the second partition wall in the first direction is smaller than a length in the first direction of some of the plurality of scale lines; The motherboard according to claim 12.

17. one end of some of the plurality of scale lines overlaps with the first partition wall in a plan view; The motherboard according to claim 12.

18. the plurality of scale lines are formed of a metal material; The motherboard according to claim 12.

19. a plurality of scanning lines extending in the second direction in the display area; the plurality of scale lines are formed of the same material as the scanning lines; The motherboard according to claim 12.

20. the upper portion includes a layer formed of a metal material; The motherboard according to claim 12.

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