Filter circuit, diplexer, and radio-frequency front-end circuit and communication device including the same

Abstract

To suppress the deterioration of filter characteristics accompanying the approach of an external shield electrode in a filter circuit.SOLUTION: The filter circuit 251 is a filter device that is disposed in the dielectric substrate 110 in which a plurality of dielectric layers are laminated and has a pass band in a region higher than a predetermined frequency. The dielectric substrate has main surfaces 111112 and opposite to each other. External terminals TA, T1, and T2 for connection to an external device are disposed on the main surface 112. The filter device includes terminals Tin1 and Tout1, and resonant circuits RC1 and RC2. The resonance circuit RC1 is connected between the terminals Tin1 and Tout1. The resonance circuit RC2 is connected between the resonance circuit RC1 and the ground potential GND. Each of the resonant circuits RC1 and RC2 constitutes an LC resonant circuit including a capacitor and an inductor. A portion of the inductor RC2 included in the resonance circuit L13 is disposed on a dielectric layer between the inductors L11 and L12 included in the resonance circuit RC1 and the main surface 111 in the dielectric substrate.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a filter circuit, a diplexer, and a high-frequency front-end circuit and a communication device incorporating the same, and more particularly to a technique for suppressing degradation of filter characteristics due to a shield electrode of an external device. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2017-92546 (Patent Document 1) discloses a diplexer having a low-pass filter (LPF) and a band-pass filter (BPF) with a passband that is higher than the frequency band of the low-pass filter within a multilayer substrate. The low-pass filter and band-pass filter that make up such a diplexer generally include a resonant circuit including an inductor and a capacitor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-92546 Summary of the Invention [Problem to be solved by the invention]

[0004] Such diplexers are sometimes used in mobile terminals, such as mobile phones and smartphones. In such cases, if a shield electrode included in another device or element installed inside the device's housing approaches the diplexer, parasitic capacitance is generated between the shield electrode and an inductor included in the filter circuit of the diplexer. This can cause the frequency of the attenuation pole generated by the resonant circuit including the inductor to fluctuate. This can result in the desired filter characteristics being lost and can adversely affect the characteristics of the diplexer.

[0005] The present disclosure has been made to solve such problems, and its purpose is to suppress the degradation of filter characteristics in a filter circuit that accompanies the proximity of an external shield electrode. [Means for solving the problem]

[0006] A filter circuit according to one aspect of the present disclosure is a filter device disposed within a dielectric substrate having a plurality of laminated dielectric layers, and having a passband in a range higher than a predetermined frequency. The dielectric substrate has a first main surface and a second main surface facing each other. An external terminal for connecting to an external device is disposed on the second main surface. The filter circuit includes a first terminal, a second terminal, a first resonant circuit, and a second resonant circuit. The first resonant circuit is connected between the first terminal and the second terminal. The second resonant circuit is connected between the first resonant circuit and ground potential. Each of the first resonant circuit and the second resonant circuit forms an LC resonant circuit including a capacitor and an inductor. A portion of the inductor included in the second resonant circuit is disposed in a dielectric layer of the dielectric substrate between the inductor included in the first resonant circuit and the first main surface.

[0007] A diplexer according to another aspect of the present disclosure includes a dielectric substrate, an input terminal, a first output terminal, a second output terminal, a first filter device, and a second filter device. The dielectric substrate has a first main surface and a second main surface facing each other, and a plurality of dielectric layers are stacked on top of each other. The input terminal, the first output terminal, and the second output terminal are arranged on the second main surface. The first filter device is connected between the input terminal and the first output terminal. The second filter device is connected between the input terminal and the second output terminal. The first filter device has a pass band in a range lower than a first frequency. The second filter device includes a first filter circuit having a pass band in a range higher than the first frequency. The first filter circuit includes a first resonant circuit and a second resonant circuit. The first resonant circuit is connected between the input terminal and the second output terminal. The second resonant circuit is connected between the first resonant circuit and ground potential. Each of the first resonant circuit and the second resonant circuit forms an LC resonant circuit including a capacitor and an inductor. A part of the inductor included in the second resonant circuit is disposed on a dielectric layer between the inductor included in the first resonant circuit and the first main surface of the dielectric substrate. [Effects of the Invention]

[0008] The filter circuit according to the present disclosure is a high-pass filter having two resonant circuits disposed within a dielectric substrate. The inductor included in the resonant circuit (second resonant circuit) connected to the ground electrode is positioned closer to the upper main surface of the dielectric substrate than the inductor included in the resonant circuit (first resonant circuit) positioned between the first input terminal and the second output terminal. In such a high-pass filter, the attenuation pole due to the first resonant circuit occurs closer to the passband than the attenuation pole due to the second resonant circuit. Therefore, by positioning the inductor of the first resonant circuit away from the upper main surface of the dielectric substrate, coupling between the shield electrode of an external device and the inductor of the first resonant circuit can be suppressed even when the shield electrode is close to the upper surface of the dielectric substrate. This suppresses degradation of filter characteristics due to the proximity of the external shield electrode. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram of a communication device equipped with a diplexer including a filter circuit according to an embodiment. [Figure 2] 2 is an example of an equivalent circuit diagram of the diplexer in FIG. 1. [Figure 3] FIG. 2 is an external perspective view of the diplexer in FIG. [Figure 4] FIG. 4 is an exploded perspective view showing an example of a laminated structure of the diplexer of FIG. 3. [Figure 5] 10A and 10B are diagrams for explaining filter characteristics of a filter circuit included in a diplexer according to an embodiment and a filter circuit of a comparative example. [Figure 6] 10 is a diagram for explaining an inductor arrangement in a filter circuit according to a first modification. FIG. [Figure 7] 10 is a diagram for explaining an inductor arrangement in a filter circuit according to a second modification. FIG. [Figure 8] 10 is a diagram for explaining an inductor arrangement in a filter circuit according to a third modification. FIG. [Figure 9] FIG. 10 is a diagram for explaining an inductor arrangement in a filter circuit according to a fourth modification. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0011] [Basic configuration of communication equipment] 1 is a block diagram of a communication device 10 equipped with a diplexer 100 including a filter circuit according to an embodiment. Referring to FIG. 1, the communication device 10 includes a high-frequency front-end circuit 20 including the diplexer 100, and an RF signal processing circuit (hereinafter also referred to as "RFIC") 30.

[0012] The high-frequency front-end circuit 20 demultiplexes a high-frequency signal received by the antenna device ANT into multiple predetermined frequency bands and transmits the demultiplexed signals to a subsequent processing circuit. The high-frequency front-end circuit 20 is used in, for example, mobile terminals such as mobile phones, smartphones, and tablets, and communication devices such as personal computers with communication functions. The high-frequency front-end circuit 20 shown in FIG. 1 is a receiving system front-end circuit. The high-frequency front-end circuit 20 includes a diplexer 100 and amplifier circuits LNA1 and LNA2.

[0013] The diplexer 100 includes an input terminal TA which is a common terminal, output terminals T1 and T2, and filter devices 200 and 250. The diplexer 100 includes a filter device 200 (first filter device) and a filter device 250 (second filter device) which have passbands in different frequency ranges.

[0014] The filter device 200 is connected between the input terminal TA and the output terminal T1. The filter device 200 is a low-band filter having a passband that is the frequency range of a low-band (LB) group and a non-passband that is the frequency range of a high-band (HB) group. The filter device 250 is connected between the input terminal TA and the output terminal T2. The filter device 250 is a high-band filter having a passband that is the frequency range of a high-band group and a non-passband that is the frequency range of a low-band group. In this embodiment, the filter device 200 is a low-pass filter, and the filter device 250 is a band-pass filter.

[0015] Each of the filter devices 200 and 250 passes a high-frequency signal that corresponds to the pass band of the corresponding filter among the high-frequency signals received by the antenna device ANT, thereby separating the high-frequency signal received by the antenna device ANT into signals of a plurality of predetermined frequency bands.

[0016] Each of the amplifier circuits LNA1 and LNA2 is a so-called low noise amplifier. The amplifier circuits LNA1 and LNA2 amplify the high frequency signal that has passed through the diplexer 100 with low noise and transmit the amplified signal to the RFIC 30.

[0017] The RFIC 30 is an RF signal processing circuit that processes high-frequency signals transmitted and received by the antenna device ANT. Specifically, the RFIC 30 processes the high-frequency signals input from the antenna device ANT via the receiving-side signal path of the high-frequency front-end circuit 20 by down-conversion or the like, and outputs the received signals generated by the signal processing to a baseband signal processing circuit (not shown).

[0018] 1, when the high-frequency front-end circuit 20 is a receiving system front-end circuit, in the diplexer 100, the terminal TA to which the antenna device ANT is connected serves as an input terminal, and the terminals T1 and T2 serve as output terminals. On the other hand, the high-frequency front-end circuit can also be used as a transmitting system front-end circuit. In this case, the terminals T1 and T2 of the diplexer 100 serve as input terminals, and the terminal TA serves as a common output terminal. In this case, a power amplifier is used instead of a low-noise amplifier as the amplifier included in the amplification circuit.

[0019] [Diplexer configuration] Next, the detailed configuration of the diplexer 100 will be described with reference to Figures 2 to 4. Figure 2 is an example of an equivalent circuit diagram of the diplexer 100 in Figure 1. Figure 3 is an external perspective view of the diplexer 100, and Figure 4 is an exploded perspective view showing an example of the layered structure of the diplexer 100.

[0020] 2, as described above, filter device 200 is connected between input terminal TA and output terminal T1, and filter device 250 is connected between input terminal TA and output terminal T2.

[0021] The filter device 200 is a low-pass filter including inductors L1 and L2 and capacitors C1 and C2. One end of the inductor L1 is connected to an input terminal TA. The inductor L2 is connected between the other end of the inductor L1 and an output terminal T1. That is, the inductors L1 and L2 are connected in series between the input terminal TA and the output terminal T1.

[0022] The capacitor C1 is connected between the output terminal T1 and a connection node N1 between the inductors L1 and L2. In other words, the capacitor C1 is connected in parallel with the inductor L2. The capacitor C2 is connected between the connection node N1 and the ground potential GND.

[0023] The filter device 250 includes filter circuits 251 and 252 connected in series between the input terminal TA and the output terminal T2. The filter circuit 251 is a high-pass filter, and the filter circuit 252 is a low-pass filter. The cutoff frequency of the filter circuit 252 is higher than the cutoff frequency of the filter circuit 251. Therefore, the filter device 250 functions as a band-pass filter by the filter circuits 251 and 252.

[0024] The filter circuit 251 includes a terminal Tin1 connected to the input terminal TA, a terminal Tout1, inductors L11, L12, and L13, and capacitors C10, C11, C12, and C13.

[0025] The capacitor C10, the inductors L11 and L12, and the capacitor C13 are connected in series in this order between the terminal Tin1 and the terminal Tout1. The capacitor C11 is connected between the connection node between the capacitor C10 and the inductor L11 and the connection node between the inductor L12 and the capacitor C13. In other words, the capacitor C11 is connected in parallel to the series-connected inductors L11 and L12. That is, the capacitor C11 and the inductors L11 and L12 form an LC parallel resonant circuit (resonant circuit RC1).

[0026] One end of inductor L13 is connected to a connection node N2 between inductors L11 and L12. The other end of inductor L13 is connected to ground potential GND via capacitor C12. That is, inductor L13 and capacitor C12 form an LC series resonant circuit (resonant circuit RC2).

[0027] In the filter circuit 251, each of the resonant circuits RC1 and RC2 generates an attenuation pole on the lower frequency side of the pass band. More specifically, the attenuation pole generated by the resonant circuit RC1 occurs in a region closer to the pass band than the attenuation pole generated by the resonant circuit RC2. In other words, the frequency of the attenuation pole generated by the resonant circuit RC1 is higher than the frequency of the attenuation pole generated by the resonant circuit RC2. Therefore, the influence of fluctuations in the resonant frequency of the resonant circuit RC1 on the filter characteristics (bandwidth, attenuation steepness) is greater than the influence of fluctuations in the resonant frequency of the resonant circuit RC2.

[0028] The filter circuit 252 includes a terminal Tin2 connected to the terminal Tout1 of the filter circuit 251, a terminal Tout2 connected to the output terminal T2, inductors L21 and L22, and capacitors C21 to C23.

[0029] Inductors L21 and L22 are connected in series between terminal Tin2 and terminal Tout2. Capacitor C21 is connected in parallel to inductor L21. Capacitor C22 is connected in parallel to inductor L22. Capacitor C23 is connected between a connection node N3 between inductors L21 and L22 and ground potential GND.

[0030] In the diplexer 100 according to the above embodiment, the high-band side filter device 250 is a band-pass filter, but the high-band side filter device 250 may be a high-pass filter including only the filter circuit 251 .

[0031] 3 and 4, the diplexer 100 includes a rectangular or approximately rectangular parallelepiped dielectric substrate 110 in which a plurality of dielectric layers LY1 to LY10 are stacked in a predetermined direction. Each dielectric layer of the dielectric substrate 110 is formed of ceramic, such as low-temperature co-fired ceramics (LTCC), or resin. Inside the dielectric substrate 110, inductors and capacitors included in the filter devices 200 and 250 are configured by a plurality of electrodes provided on each dielectric layer and a plurality of vias arranged between the dielectric layers. In the following description, for ease of explanation, the dielectric substrate 110 will be described as being a multilayer substrate as described above, but the dielectric substrate 110 may also be a single-layer substrate.

[0032] In this specification, the term "via" refers to a conductor provided in a dielectric layer to connect electrodes provided on different dielectric layers. The via is formed, for example, by conductive paste, plating, and / or a metal pin. In the following description, the direction in which the dielectric layers LY1 to LY10 in the dielectric substrate 110 are stacked is referred to as the "Z-axis direction," the direction perpendicular to the Z-axis direction and along the long side of the dielectric substrate 110 is referred to as the "X-axis direction," and the direction along the short side of the dielectric substrate 110 is referred to as the "Y-axis direction." In the following, the positive direction of the Z-axis in each drawing may be referred to as the upper side, and the negative direction may be referred to as the lower side.

[0033] The dielectric substrate 110 includes an upper surface 111, a lower surface 112, and side surfaces 113 to 116. A direction mark DM for specifying the direction of the diplexer 100 is arranged on the upper surface 111 (first dielectric layer LY1) of the dielectric substrate 110. As shown in Fig. 3, external terminals (input terminal TA, output terminals T1 and T2, and ground terminal GND) for connecting the diplexer 100 to external devices are arranged on the lower surface 112 (tenth dielectric layer LY10) of the dielectric substrate 110. That is, the input terminal TA, output terminals T1 and T2, and ground terminal GND form an LGA (Land Grid Array).

[0034] In FIG. 4, filter device 200 is provided on the left side (negative side of the X-axis) of dielectric substrate 110, and filter device 250 is provided on the right side (positive side of the X-axis).

[0035] First, the details of the filter device 200 will be described. Referring to Fig. 4, the input terminal TA arranged on the lower surface 112 (tenth dielectric layer LY10) of the dielectric substrate 110 is connected by a via V1 to a substantially rectangular capacitor electrode PC1 arranged on the eighth dielectric layer LY8. Furthermore, the capacitor electrode PC1 is connected by a via V10 to a plate electrode PL10 arranged on the second dielectric layer LY2.

[0036] The plate electrode PL10 is a strip-shaped electrode having a substantially U-shape or a substantially O-shape, and one end of the plate electrode PL10 is connected to a via V10. The other end of the plate electrode PL10 is connected to a via V11, which is connected to a plate electrode PL11 disposed on the third dielectric layer LY3.

[0037] The plate electrode PL11 is a strip-shaped electrode having a substantially U-shape or a substantially O-shape, and one end of the plate electrode PL11 is connected to a via V11. The other end of the plate electrode PL11 is connected to a via V12, which is connected to a capacitor electrode PC10 arranged on the seventh dielectric layer LY7. The vias V10 to V12 and the plate electrodes PL10 and PL11 form the inductor L1 in FIG. 2.

[0038] The capacitor electrode PC10 has a substantially rectangular shape. When the dielectric substrate 110 is viewed in a plan view from the Z-axis direction, the capacitor electrode PC10 partially overlaps with the capacitor electrodes PC11 and PC20 arranged on the eighth dielectric layer LY8. The capacitor electrode PC11 is connected to the ground terminal GND arranged on the tenth dielectric layer LY10 by a via VG1. The capacitor electrodes PC10 and PC11 form the capacitor C2 in FIG. 2.

[0039] The capacitor electrode PC20 is a strip-shaped electrode extending in the Y-axis direction. Although it is somewhat obscured by the back surfaces of the other vias in Fig. 4, the capacitor electrode PC20 is connected to the output terminal T1 arranged on the tenth dielectric layer LY10 by a via V2.

[0040] The capacitor electrode PC11 is connected to a capacitor electrode PC12 disposed on the seventh dielectric layer LY7 by a via VG3. The capacitor electrode PC12 is a strip-shaped electrode extending in the X-axis direction. When the dielectric substrate 110 is viewed in a plan view from the Z-axis direction, the capacitor electrode PC12 partially overlaps with the capacitor electrode PC20. The capacitor electrode PC12 and the capacitor electrode PC20 form the capacitor C1 in FIG. 2.

[0041] The capacitor electrode PC10 is further connected by a via V20 to a plate electrode PL20 arranged on the fourth dielectric layer LY4. The plate electrode PL20 is a strip-shaped electrode having a substantially J-shape, and the via V20 is connected to one end of the plate electrode PL20. The other end of the plate electrode PL20 is connected by a via V21 to a plate electrode PL21 arranged on the fifth dielectric layer LY5.

[0042] The plate electrode PL21 is a strip-shaped electrode having a substantially U-shape or a substantially O-shape, and one end of the plate electrode PL21 is connected to a via V21. The other end of the plate electrode PL21 is connected to a capacitor electrode PC20 arranged on the eighth dielectric layer LY8 by a via V22. The vias V20, V21, and V22 and the plate electrodes PL20 and PL21 form the inductor L2 in FIG. 2.

[0043] Next, the filter device 250 will be described in detail. When the dielectric substrate 110 is viewed in a plan view from the Z-axis direction, the capacitor electrode PC1 on the eighth dielectric layer LY8 partially overlaps with the substantially rectangular capacitor electrode PC30 disposed on the seventh dielectric layer LY7. The capacitor electrode PC1 and the capacitor electrode PC30 form the capacitor C10 in FIG. 2.

[0044] The capacitor electrode PC30 is connected by a via V30 to a plate electrode PL30 disposed on the fourth dielectric layer LY4. The plate electrode PL30 is a strip-shaped electrode having a substantially U-shape or a substantially O-shape, and the via V30 is connected to one end of the plate electrode PL30. The other end of the plate electrode PL30 is connected by a via V40 to a substantially rectangular capacitor electrode PC40 disposed on the sixth dielectric layer LY6.

[0045] A via V31 is connected to the middle portion of the plate electrode PL30. The via V31 is connected to the plate electrode PL31 arranged on the second dielectric layer LY2. The plate electrode PL31 is a strip-shaped electrode having a substantially U-shape or a substantially O-shape, and the via V31 is connected to one end of the plate electrode PL31. The other end of the plate electrode PL31 is connected by a via V32 to a substantially rectangular capacitor electrode PC35 arranged on the seventh dielectric layer LY7.

[0046] When the dielectric substrate 110 is viewed in plan from the Z-axis direction, at least a portion of the capacitor electrode PC35 overlaps with a substantially rectangular capacitor electrode PC52 disposed on the eighth dielectric layer LY8. The capacitor electrode PC52 is connected to the ground terminal GND on the tenth dielectric layer LY10 by a via VG2.

[0047] The capacitor electrode PC52 is connected to a substantially rectangular capacitor electrode PC53 disposed on the sixth dielectric layer LY6 by vias VG4 and VG5. When the dielectric substrate 110 is viewed in a plan view from the Z-axis direction, at least a portion of the capacitor electrode PC53 overlaps with the capacitor electrode PC35 disposed on the seventh dielectric layer LY7.

[0048] The portion of the plate electrode PL30 extending from the connection point of the via V31 to the capacitor electrode PC30 via the via V30 constitutes the inductor L11 in Fig. 2. The portion of the plate electrode PL30 extending from the connection point of the via V31 to the capacitor electrode PC40 via the via V40 constitutes the inductor L12 in Fig. 2.

[0049] The vias V31 and V32 and the plate electrode PL31 form the inductor L13 in Fig. 2. The capacitor electrodes PC35, PC52, and PC53 form the capacitor C12 in Fig. 2.

[0050] The capacitor electrode PC40 is connected by two vias V41 to a substantially rectangular capacitor electrode PC31 disposed on the eighth dielectric layer LY8. When the dielectric substrate 110 is viewed in a plan view from the Z-axis direction, the capacitor electrode PC30 partially overlaps with the capacitor electrode PC40 disposed on the sixth dielectric layer LY6 and the capacitor electrode PC31 disposed on the eighth dielectric layer LY8. The capacitor electrode PC30, the capacitor electrode PC31, and the capacitor electrode PC40 form the capacitor C11 in FIG. 2.

[0051] At least one of the vias V41 is also connected to a capacitor electrode PC36 arranged on the seventh dielectric layer LY7. The capacitor electrode PC36 is a substantially rectangular electrode extending in the Y-axis direction. When the dielectric substrate 110 is viewed in a plan view from the Z-axis direction, the capacitor electrode PC36 partially overlaps with the capacitor electrode PC34 arranged on the sixth dielectric layer LY6 and the capacitor electrode PC32 arranged on the eighth dielectric layer LY8. The capacitor electrodes PC32, PC34, and PC36 form the capacitor C13 in FIG. 2.

[0052] The capacitor electrode PC32 is connected by a via V50 to a plate electrode PL52 arranged on the second dielectric layer LY2 and to a capacitor electrode PC34 arranged on the sixth dielectric layer LY6. The plate electrode PL52 is a strip-shaped electrode extending in the X-axis direction, and one end of the plate electrode PL52 is connected to the via V50. The other end of the plate electrode PL52 is connected by a via V51 to a plate electrode PL53 arranged on the fourth dielectric layer LY4.

[0053] The plate electrode PL53 is a strip-like electrode having a substantially J-shape, and one end of the plate electrode PL53 is connected to a via V51. The other end of the plate electrode PL53 is connected by a via V52 to a substantially rectangular capacitor electrode PC50 disposed on the eighth dielectric layer LY8. The vias V50, V51, and V52 and the plate electrodes PL52 and PL53 form the inductor L21 in FIG. 2.

[0054] The capacitor electrode PC50 is also connected to a plate electrode PL54 arranged on the fourth dielectric layer LY4 by a via V53. The plate electrode PL54 is a strip-shaped electrode having a substantially L-shape, and one end of the plate electrode PL54 is connected to the via V53. The other end of the plate electrode PL54 is connected to a plate electrode PL55 arranged on the fifth dielectric layer LY5 by a via V54.

[0055] The plate electrode PL55 is a generally U-shaped electrode, one end of which is connected to the via V54. The other end of the plate electrode PL55 is connected to the output terminal T2 on the tenth dielectric layer LY10 by the via V55, a capacitor electrode PC60 arranged on the eighth dielectric layer LY8, and a via V3. The vias V3, V53, V54, V55, the plate electrodes PL54, PL55, and the capacitor electrode PC60 form the inductor L22 in FIG. 2.

[0056] When the dielectric substrate 110 is viewed in plan from the Z-axis direction, the capacitor electrodes PC50 and PC60 partially overlap with the capacitor electrode PC41 disposed on the sixth dielectric layer LY6. The capacitor electrodes PC41, PC50, and PC60 form the capacitor C22 in FIG.

[0057] When the dielectric substrate 110 is viewed in plan from the Z-axis direction, the capacitor electrodes PC50 and PC52 partially overlap with the capacitor electrode PC51 disposed on the ninth dielectric layer LY9. The capacitor electrodes PC50, PC51, and PC52 form the capacitor C23 in FIG.

[0058] Furthermore, when the dielectric substrate 110 is viewed in plan from the Z-axis direction, the capacitor electrodes PC50 and PC32 partially overlap with the capacitor electrode PC33 disposed on the seventh dielectric layer LY7. The capacitor electrodes PC32, PC33, and PC50 form the capacitor C21 in FIG.

[0059] 4, the capacitor electrodes constituting the capacitors included in each filter device are arranged on a dielectric layer from the middle to the bottom surface 112 side of the dielectric substrate 110. In other words, the electrodes constituting each capacitor are arranged on a dielectric layer between the inductor and the bottom surface 112.

[0060] In the filter circuit 251, when viewed from above in the normal direction of the dielectric substrate 110, at least a portion of the plate electrode PL30 included in the inductors L11 and L12 overlaps with the plate electrode PL31 included in the inductor L13.

[0061] [Effect of external shield electrode] The diplexer described above may be used in mobile terminals, such as mobile phones and smartphones. In this case, if a shield electrode included in another device or element installed inside the device's housing approaches the diplexer, the magnetic flux generated by an inductor included in the filter circuit within the diplexer is blocked by the shield, causing a change in the inductance of the inductor. This causes the frequency of the attenuation pole generated by the resonant circuit including the inductor to fluctuate, making it impossible to obtain the desired filter characteristics, which may affect the characteristics of the diplexer.

[0062] Generally, when the magnetic flux generated by an inductor is obstructed, the inductance of the inductor decreases, and the resonant frequency of the resonant circuit formed by the inductor increases. In other words, the frequency of the attenuation pole generated by the resonant circuit increases. In this case, the pass characteristics of the high-pass filter, especially on the high-band side, are significantly affected, resulting in a narrower passband bandwidth of the high-pass filter.

[0063] Generally, the closer the distance between the inductor and the external shield electrode, the more magnetic flux is blocked by the external shield electrode. Therefore, in the diplexer according to this embodiment, in the high-band high-pass filter, the inductor included in the resonant circuit that generates the attenuation pole closest to the pass band is positioned at a location where the magnetic flux is least likely to be blocked by the external shield electrode, thereby suppressing the degradation of filter characteristics due to the proximity of the external shield electrode.

[0064] 3, the mounting surface is the bottom surface 112 of the dielectric substrate 110, and the external shield electrode is therefore located close to the top surface 111 of the dielectric substrate 110. Therefore, the inductor included in the resonant circuit that generates the attenuation pole closest to the pass band in the high-pass filter is located as far away as possible from the top surface 111 of the dielectric substrate 110. This prevents the external shield electrode from interfering with the magnetic flux of the inductor, which is likely to affect the filter characteristics, and as a result, it is possible to prevent degradation of the filter characteristics due to the proximity of the external shield electrode.

[0065] [Filter circuit pass characteristics] 5 is a diagram illustrating the filter characteristics of filter circuit 251 included in diplexer 100 of the embodiment and filter circuit 251X of the comparative example. In Fig. 5, the upper part shows a perspective view illustrating the inductor arrangements in the filter circuits of the embodiment and the comparative example, and the lower part shows a graph illustrating the pass characteristics of each filter circuit.

[0066] In the upper diagram of the inductor arrangement, only the structure of the inductor portion included in the high-pass filter in the high-band filter device is highlighted. Also, in the plate electrode PL30, the portion included in inductor L11 is referred to as plate electrode PL301, and the portion included in inductor L12 is referred to as plate electrode PL302.

[0067] In the lower graph, the horizontal axis represents frequency, and the vertical axis represents insertion loss from terminal Tin1 to terminal Tout1. The dashed lines LN11 and LN21 represent the insertion loss of each filter alone, and the solid lines LN10 and LN20 represent the insertion loss when an external shield electrode is placed close to the top surface 111 of the dielectric substrate 110.

[0068] In filter circuit 251 of the embodiment, plate electrode PL31 included in inductor L13 that configures resonant circuit RC2 is arranged closer to upper surface 111 of dielectric substrate 110 than plate electrode PL30 included in inductors L11 and L12 that configure resonant circuit RC1. That is, in filter circuit 251, plate electrode PL31 is arranged on the dielectric layer between upper surface 111 of dielectric substrate 110 and plate electrode PL30.

[0069] On the other hand, in filter circuit 251X of the comparative example, plate electrode PL30 for resonant circuit RC1 is arranged closer to upper surface 111 than plate electrode PL31 for resonant circuit RC2. That is, in filter circuit 251X, plate electrode PL30 is arranged on the dielectric layer between upper surface 111 of dielectric substrate 110 and plate electrode PL31.

[0070] 2, the attenuation pole generated by the resonant circuit RC1 is closer to the passband than the attenuation pole generated by the resonant circuit RC2. Therefore, in the comparative example in which the plate electrode PL30 included in the resonant circuit RC1 is arranged closer to the upper surface 111, when the external shield electrode approaches the upper surface 111 of the dielectric substrate 110, the attenuation pole near 2.65 GHz (dashed line LN21) shifts to the high-frequency side near 2.75 GHz (solid line LN20). In other words, the passband region narrows.

[0071] On the other hand, in the embodiment, the plate electrode PL30 included in the resonant circuit RC1 is located farther from the top surface 111 than in the comparative example, thereby reducing coupling with the external shield electrode. Therefore, as shown in the graph, the frequency of the attenuation pole hardly changes even when the external shield electrode approaches the top surface 111. As a result, the attenuation curve near the low-frequency side of the passband has approximately the same shape, regardless of whether or not an external shield electrode is present. In other words, in the filter circuit 251 of the embodiment, degradation of the filter characteristics due to the proximity of the external shield electrode is suppressed.

[0072] As described above, in a high-pass filter including a parallel resonant circuit provided between the input terminal and the output terminal within a dielectric substrate, and a series resonant circuit provided between the parallel resonant circuit and ground potential, by locating the inductor included in the parallel resonant circuit farther from the top surface of the dielectric substrate than the inductor included in the series resonant circuit, it is possible to suppress degradation of the filter characteristics when an external shield electrode approaches the top surface of the dielectric substrate.

[0073] Furthermore, in a diplexer including such a high-pass filter, and in a high-frequency front-end circuit and a communication device incorporating such a diplexer, it is possible to suppress degradation of the filter characteristics when an external shield electrode is brought close.

[0074] The "filter circuit 251" and the "filter circuit 252" in the embodiments correspond to the "first filter circuit" and the "second filter circuit" in the present disclosure, respectively. The "output terminal T1" and the "output terminal T2" in the embodiments correspond to the "first output terminal" and the "second output terminal" in the present disclosure, respectively. The "terminal Tin1" and the "terminal Tout1" in the embodiments correspond to the "first terminal" and the "second terminal" in the present disclosure, respectively. The "principal surface 111" and the "principal surface 112" in the embodiments correspond to the "first principal surface" and the "second principal surface" in the present disclosure, respectively. The "resonant circuit RC1" and the "resonant circuit RC2" in the embodiments correspond to the "first resonant circuit" and the "second resonant circuit" in the present disclosure, respectively. The "inductor L11," "inductor L12," and "inductor L13" in the embodiments correspond to the "first inductor," "second inductor," and "third inductor," respectively. "Capacitor C11," "capacitor C12," and "capacitor C10" in the embodiments correspond to "first capacitor," "second capacitor," and "third capacitor," respectively, in the present disclosure.

[0075] [Variations] In the embodiment, the plate electrodes PL301 and PL302 included in the plate electrode PL30 are arranged on the same dielectric layer. In the following modified example, a configuration in which the plate electrodes PL301 and PL302 are arranged on different dielectric layers will be described.

[0076] In the first and second modifications, the plate electrode included in inductor L11 is arranged closer to the top surface 111 of the dielectric substrate 110 than the plate electrode included in inductor L13. In the third and fourth modifications, the plate electrode included in inductor L13 is arranged closer to the top surface 111 of the dielectric substrate 110 than the plate electrode included in inductor L11.

[0077] (Variation 1) Fig. 6 is a diagram illustrating the arrangement of inductors in filter circuit 251A of modification 1. In filter circuit 251A of modification 1, plate electrode PL302 in filter circuit 251 shown in Fig. 5 is arranged closer to lower surface 112 of dielectric substrate 110 than plate electrode PL301. Via V31 connecting plate electrode PL30 and plate electrode PL31 extends from plate electrode PL31 to plate electrode PL302 via plate electrode PL301.

[0078] In other words, the plate electrode PL301 is disposed on the dielectric layer between the plate electrodes PL31 and PL302.

[0079] In filter circuit 251A, plate electrodes PL301 and PL302 included in inductors L11 and L12 are also disposed farther from top surface 111 of dielectric substrate 110 than plate electrode PL31 included in inductor L13. Therefore, even if an external shield electrode approaches top surface 111 of dielectric substrate 110, degradation of filter characteristics can be suppressed.

[0080] (Variation 2) Fig. 7 is a diagram illustrating the arrangement of inductors in a filter circuit 251B of Modification 2. In filter circuit 251B of Modification 3, the plate electrodes PL30 and PL31 in filter circuit 251 shown in Fig. 5 are replaced with plate electrodes PL30A and PL31A, respectively.

[0081] In the filter circuit 251B, the plate electrodes PL30A and PL31A are helical coils in which lines are wound across multiple dielectric layers. In the example of Fig. 7, the plate electrodes PL30A and PL31A have lines wound across two dielectric layers.

[0082] For the plate electrode PL30A, the line arranged on one dielectric layer is the plate electrode PL301A included in the inductor L11, and the line arranged on the other dielectric layer is the plate electrode PL302A included in the inductor L12. In the filter circuit 251B, the plate electrode PL302A is arranged closer to the lower surface 112 of the dielectric substrate 110 than the plate electrode PL301A. The via V31 connecting the plate electrodes PL30A and PL31A extends from the plate electrode PL31A to the plate electrode PL302A by way of the plate electrode PL301A.

[0083] In other words, the plate electrode PL301A is disposed on the dielectric layer between the plate electrodes PL31A and PL302A.

[0084] In the filter circuit 251B, when viewed from above in the normal direction of the dielectric substrate 110, at least a portion of the plate electrode PL31A overlaps with the plate electrode PL30A.

[0085] In filter circuit 251B, too, plate electrodes PL301A and PL302A included in inductors L11 and L12 are disposed farther from top surface 111 of dielectric substrate 110 than plate electrode PL31A included in inductor L13. Therefore, even if an external shield electrode approaches top surface 111 of dielectric substrate 110, degradation of filter characteristics can be suppressed.

[0086] (Variation 3) Fig. 8 is a diagram illustrating the arrangement of inductors in a filter circuit 251C of Modification 3. In filter circuit 251C of Modification 3, plate electrode PL301 in filter circuit 251 shown in Fig. 5 is arranged closer to the lower surface 112 of dielectric substrate 110 than plate electrode PL302. A via V31 connecting plate electrodes PL30 and PL31 extends from plate electrode PL31 to plate electrode PL301 via plate electrode PL302.

[0087] In other words, the plate electrode PL302 is disposed on the dielectric layer between the plate electrodes PL31 and PL301.

[0088] In filter circuit 251C, plate electrodes PL301 and PL302 included in inductors L11 and L12 are also disposed farther from top surface 111 of dielectric substrate 110 than plate electrode PL31 included in inductor L13. Therefore, even if an external shield electrode approaches top surface 111 of dielectric substrate 110, degradation of filter characteristics can be suppressed.

[0089] (Variation 4) 9 is a diagram illustrating the arrangement of inductors in a filter circuit 251D of Modification 4. In filter circuit 251D of Modification 4, similar to filter circuit 251B of Modification 2 shown in FIG. 7, plate electrodes PL30A and PL31A are provided instead of plate electrodes PL30 and PL31 of filter circuit 251.

[0090] However, in the filter circuit 251D, the plate electrode PL301A of the plate electrode PL30A is located closer to the lower surface 112 of the dielectric substrate 110 than the plate electrode PL302A. The via V31 connecting the plate electrodes PL30A and PL31A extends from the plate electrode PL31A to the plate electrode PL301A via the plate electrode PL302A. In other words, the plate electrode PL302A is located on the dielectric layer between the plate electrodes PL31A and PL301A.

[0091] In filter circuit 251D, plate electrodes PL301A and PL302A included in inductors L11 and L12 are also disposed farther from top surface 111 of dielectric substrate 110 than plate electrode PL31A included in inductor L13. Therefore, even if an external shield electrode approaches top surface 111 of dielectric substrate 110, degradation of filter characteristics can be suppressed.

[0092] [Aspect] It will be appreciated by those skilled in the art that the exemplary embodiments described above are examples of the following aspects.

[0093] (Item 1) A filter circuit according to one aspect is disposed within a dielectric substrate having a plurality of laminated dielectric layers, and has a passband in a region higher than a predetermined frequency. The dielectric substrate has a first main surface and a second main surface facing each other. An external terminal for connecting to an external device is disposed on the second main surface. The filter circuit includes a first terminal, a second terminal, a first resonant circuit, and a second resonant circuit. The first resonant circuit is connected between the first terminal and the second terminal. The second resonant circuit is connected between the first resonant circuit and ground potential. Each of the first resonant circuit and the second resonant circuit forms an LC resonant circuit including a capacitor and an inductor. A portion of the inductor included in the second resonant circuit is disposed in a dielectric layer of the dielectric substrate between the inductor included in the first resonant circuit and the first main surface.

[0094] (Item 2) In the filter circuit described in item 1, the first resonant circuit includes a first inductor, a second inductor, and a first capacitor. A first end of the first inductor is connected to the first terminal. The second inductor is connected between a second end of the first inductor and the second terminal. The first capacitor is connected in parallel with the first inductor and the second inductor, which are connected in series.

[0095] (Item 3) In the filter circuit described in item 2, the second resonant circuit includes a third inductor and a second capacitor connected in series between a connection node of the first inductor and the second inductor and a ground potential.

[0096] (Item 4) In the filter circuit described in item 3, the electrodes constituting the first capacitor and the second capacitor are arranged on a dielectric layer between the third inductor and the second main surface of the dielectric substrate.

[0097] (Item 5) In the filter circuit described in item 3 or 4, when the dielectric substrate is viewed in a plan view from the normal direction of the first main surface, at least a portion of the coil formed by the first inductor and the second inductor overlaps with the coil formed by the third inductor.

[0098] (Item 6) In the filter circuit according to any one of Items 2 to 5, the first inductor and the second inductor are configured by plate electrodes and vias arranged in a dielectric substrate, and at least a portion of the plate electrode of the first inductor is arranged on the same dielectric layer as the plate electrode of the second inductor.

[0099] (Item 7) In the filter circuit according to any one of items 1 to 5, the frequency of the attenuation pole formed by the first resonant circuit is closer to the pass band than the frequency of the attenuation pole formed by the second resonant circuit.

[0100] (Item 8) The filter circuit according to any one of items 1 to 7 further includes a third capacitor connected between the first terminal and the first resonant circuit.

[0101] (Item 9) A diplexer according to one aspect includes a dielectric substrate, an input terminal, a first output terminal, a second output terminal, a first filter device, and a second filter device. The dielectric substrate has a first main surface and a second main surface facing each other, and a plurality of dielectric layers are laminated on the dielectric substrate. The input terminal, the first output terminal, and the second output terminal are arranged on the second main surface. The first filter device is connected between the input terminal and the first output terminal. The second filter device is connected between the input terminal and the second output terminal. The first filter device has a pass band in a range lower than a first frequency. The second filter device includes a first filter circuit having a pass band in a range higher than the first frequency. The first filter circuit includes a first resonant circuit and a second resonant circuit. The first resonant circuit is connected between the input terminal and the second output terminal. The second resonant circuit is connected between the first resonant circuit and ground potential. Each of the first resonant circuit and the second resonant circuit forms an LC resonant circuit including a capacitor and an inductor. A part of the inductor included in the second resonant circuit is disposed on a dielectric layer between the inductor included in the first resonant circuit and the first main surface of the dielectric substrate.

[0102] (Item 10) In the diplexer described in item 9, the second filter device further includes a second filter circuit connected between the first filter circuit and the second output terminal. The second filter circuit has a passband in a region lower than a second frequency. The second frequency is higher than the first frequency. The second filter device functions as a bandpass filter by the first filter circuit and the second filter circuit.

[0103] (Item 11) A high-frequency front-end circuit comprising the diplexer according to item 9 or 10.

[0104] (Item 12) A communication device equipped with the high-frequency front-end circuit described in item 11.

[0105] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the description of the above embodiments, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0106] 10 communication device, 20 high frequency front-end circuit, 30 RFIC, 100 diplexer, 110 dielectric substrate, 111, 112 main surface, 113 to 116 side surface, 200, 250 filter device, 250 to 252, 251A to 251D, 251X filter circuit, ANT antenna device, C1, C2, C10 to C13, C21 to C23 capacitor, DM direction mark, GND ground terminal, L1, L2, L11 to L13, L21, L22 inductor, LNA1, LNA2 amplifier circuit, LY1 to LY10 dielectric layer, N1 to N3 connection node, PC1, PC10 to PC12, PC20, PC30 to PC36, PC40, PC41, PC50 to PC53, PC60 Capacitor electrodes, PL10, PL11, PL20, PL21, PL30, PL31, PL30A, PL31A, PL52 to PL55, PL301, PL302, PL301A, PL302A plate electrodes, RC1, RC2 resonant circuit, T1, T2, TA, Tin1, Tin2, Tout1, Tout2 terminals, V1 to V3, V10 to V12, V20 to V22, V30 to V32, V40, V41, V50 to V55, VG1 to VG5 vias.

Claims

1. A filter circuit disposed in a dielectric substrate having a plurality of laminated dielectric layers, the filter circuit having a passband in a region higher than a predetermined frequency, the dielectric substrate has a first main surface and a second main surface facing each other, an external terminal for connecting to an external device is disposed on the second main surface; The filter circuit comprises: A first terminal; A second terminal; a first resonant circuit connected between the first terminal and the second terminal; a second resonant circuit connected between the first resonant circuit and a ground potential; each of the first resonant circuit and the second resonant circuit constitutes an LC resonant circuit including a capacitor and an inductor; A filter circuit, wherein a portion of the inductor included in the second resonant circuit is disposed on a dielectric layer of the dielectric substrate between the inductor included in the first resonant circuit and the first main surface.

2. The first resonant circuit comprises: a first inductor having a first end connected to the first terminal; a second inductor connected between the second end of the first inductor and the second terminal; 2. The filter circuit of claim 1, further comprising: a first capacitor connected in parallel to the first inductor and the second inductor connected in series.

3. 3. The filter circuit according to claim 2, wherein the second resonant circuit includes a third inductor and a second capacitor connected in series between a connection node of the first inductor and the second inductor and the ground potential.

4. 4. The filter circuit according to claim 3, wherein in the dielectric substrate, electrodes constituting the first capacitor and the second capacitor are disposed on a dielectric layer between the third inductor and the second main surface.

5. 4. The filter circuit according to claim 3, wherein, when the dielectric substrate is viewed in a plan view from a direction normal to the first main surface, at least a portion of a coil formed by the first inductor and the second inductor overlaps with a coil formed by the third inductor.

6. the first inductor and the second inductor are configured by plate electrodes and vias disposed in the dielectric substrate, 3. The filter circuit according to claim 2, wherein at least a portion of a plate electrode of the first inductor is disposed on the same dielectric layer as a plate electrode of the second inductor.

7. 6. The filter circuit according to claim 1, wherein the frequency of the attenuation pole formed by the first resonant circuit is closer to the pass band than the frequency of the attenuation pole formed by the second resonant circuit.

8. 6. The filter circuit according to claim 1, further comprising a third capacitor connected between the first terminal and the first resonant circuit.

9. a dielectric substrate having a first main surface and a second main surface facing each other and having a plurality of dielectric layers stacked thereon; an input terminal, a first output terminal, and a second output terminal arranged on the second main surface; a first filter device connected between the input terminal and the first output terminal; a second filter device connected between the input terminal and the second output terminal; the first filter device has a passband in a region lower than a first frequency; the second filter device includes a first filter circuit having a passband in a region higher than the first frequency; The first filter circuit a first resonant circuit connected between the input terminal and the second output terminal; a second resonant circuit connected between the first resonant circuit and a ground potential; each of the first resonant circuit and the second resonant circuit constitutes an LC resonant circuit including a capacitor and an inductor; A diplexer, wherein a portion of the inductor included in the second resonant circuit is disposed on a dielectric layer of the dielectric substrate between the inductor included in the first resonant circuit and the first main surface.

10. the second filter device further includes a second filter circuit connected between the first filter circuit and the second output terminal; the second filter circuit has a pass band in a region lower than a second frequency, the second frequency is higher than the first frequency; 10. The diplexer of claim 9, wherein the second filter device functions as a bandpass filter by means of the first filter circuit and the second filter circuit.

11. A high frequency front-end circuit comprising the diplexer according to claim 9 or 10.

12. A communication device equipped with the high-frequency front-end circuit according to claim 11.

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