Electro-optical device and electronic apparatus

Abstract

To prevent noise caused by potential variation of a selection signal from being superimposed on a constant potential line.SOLUTION: The electro-optical device includes data lines 14 grouped every three lines, data signal lines 13 to which data signals corresponding to the gray scales of pixels are supplied in a time division manner corresponding to the three data lines 14, selection signal lines 180 to which selection signals SEL (1) to SEL (3) are supplied, inverted selection signal lines 181 to which inverted selection signals / SEL (1) to / SEL (3) of the selection signals are supplied in pairs with the selection signal lines 180, a transistor N1 which is turned on or off according to a selection signal supplied to one selection signal line 181, and a light-shielding film 160 which overlaps the selection signal lines 180 and the inverted selection signal lines 181 and is maintained at a predetermined potential.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] In a demultiplexer-type electro-optical device, data lines are grouped into groups of several lines. Data signals are supplied to data signal lines provided corresponding to each group. The data signals are distributed to each data line by switching elements whose on or off state is determined by a selection signal (see, for example, Patent Document 1). In such an electro-optical device, a selection signal is supplied via a selection signal line extending in a direction intersecting the data line. A constant potential wiring may be provided so as to overlap the selection signal line and the data signal line in a plan view. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-240830 Summary of the Invention [Problem to be solved by the invention]

[0004] However, noise caused by potential fluctuations in the selection signal can be superimposed on the constant potential wiring. Since the potential of the constant potential wiring is often shared with other elements, there is a problem in that if noise is superimposed on the constant potential wiring and the potential fluctuates, adverse effects such as a decrease in display quality occur. [Means for solving the problem]

[0005] In order to solve the above problem, an electro-optical device according to one embodiment of the present disclosure includes a plurality of data lines including k (k is an integer of 2 or more) data lines that are grouped together, data signal lines to which data signals corresponding to the gradations of pixels are supplied in a time-division manner corresponding to the k data lines, k selection signal lines to which selection signals are respectively supplied, k inverted selection signal lines that are paired with the k selection signal lines and to which inverted selection signals of the selection signals are respectively supplied, first switching elements that are provided in one-to-one correspondence with the plurality of data lines and are located between the data signal lines and one of the data lines and are turned on or off in response to a selection signal supplied to one of the k selection signal lines, and constant potential wiring that overlaps the k selection signal lines and the k inverted selection signal lines in a planar view and is maintained at a predetermined potential. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective view showing an electro-optical device according to a first embodiment. [Figure 2] FIG. 1 is a block diagram showing a configuration of an electro-optical device. [Figure 3] FIG. 2 is a diagram illustrating a configuration of a pixel circuit in an electro-optical device. [Figure 4] FIG. 2 is a diagram showing the arrangement of each part in the electro-optical device. [Figure 5] FIG. 2 is a diagram showing the arrangement of a light-shielding film in an electro-optical device. [Figure 6] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 7] FIG. 10 is a diagram illustrating a configuration of a demultiplexer of an electro-optical device according to a comparative example. [Figure 8] FIG. 10 is a diagram for explaining a problem in the comparative example. [Figure 9] 2 is a diagram showing the configuration of a demultiplexer and the like of the electro-optical device according to the first embodiment. FIG. [Figure 10] FIG. 2 is a diagram illustrating noise cancellation in the first embodiment. [Figure 11] FIG. 2 is a diagram illustrating a wiring layer in the first embodiment. [Figure 12] FIG. 4 is a diagram showing another example of the wiring layer in the first embodiment. [Figure 13] 10 is a diagram showing the configuration of a demultiplexer and the like of an electro-optical device according to a second embodiment. FIG. [Figure 14] FIG. 10 is a plan view showing a main part of an electro-optical device according to a second embodiment. [Figure 15] FIG. 10 is a diagram showing a wiring layer of an electro-optical device according to a second embodiment. [Figure 16] FIG. 10 is a plan view showing another example of the main part of the electro-optical device according to the second embodiment. [Figure 17] 10A and 10B are diagrams illustrating another example of the wiring layer of the electro-optical device according to the second embodiment. [Figure 18] FIG. 10 is a diagram showing the configuration of a demultiplexer of an electro-optical device according to a third embodiment. [Figure 19] 1 is a diagram showing a projection display device to which an electro-optical device according to an embodiment is applied; DETAILED DESCRIPTION OF THE INVENTION

[0007] Projection display devices according to embodiments will be described below with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from those of the actual device. The embodiments described below are preferred examples, and therefore various technically preferable limitations are applied. However, the scope of the present disclosure is not limited to these embodiments unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0008] FIG. 1 is a perspective view showing the configuration of a module 1 including an electro-optical device 100 according to the first embodiment. The electro-optical device 100 is a transmissive liquid crystal panel used, for example, as a light valve in a projection display device. The electro-optical device 100 is housed in a frame-shaped case 72 that opens in a rectangular display area 10. One end of an FPC board 74 is connected to the electro-optical device 100. FPC is an abbreviation for Flexible Printed Circuits. A plurality of terminals 76 are provided on the other end of the FPC board 74, and are connected to a higher-level circuit (not shown).

[0009] The display control circuit 30, which is a semiconductor chip, is mounted on the FPC board 74 by face-down bonding, and video data is supplied from a higher-level circuit in synchronization with a synchronization signal via multiple terminals 76. The video data defines the gradation of pixels in the image to be displayed, for example, in 8 bits.

[0010] In the drawing, the X direction is the longitudinal direction of the display area 10, that is, the direction in which the scanning lines extend, and the Y direction is the lateral direction of the display area 10, that is, the direction in which the data lines extend. When the electro-optical device 100 is used as a light valve in a projection display device, transmitted images from three electro-optical devices 100 corresponding to the primary colors R (red), G (green), and B (blue) are synthesized to display a color image, as will be described later. Therefore, a pixel, which is the smallest unit of a color image, is expressed by additive color mixing of a red subpixel formed by an electro-optical device corresponding to R, a green subpixel formed by an electro-optical device corresponding to G, and a blue subpixel formed by an electro-optical device corresponding to B. However, when it is not necessary to specify the color of the red, green, and blue subpixels or when only brightness is an issue, there is no need to refer to them as subpixels. Therefore, in this explanation, the red, green, and blue subpixels will also be referred to simply as "pixels."

[0011] The synchronization signals include a vertical synchronization signal that instructs the pixels arranged in the display area 10 to start vertical scanning, a horizontal synchronization signal that instructs the pixels to start horizontal scanning, and a clock signal that indicates the timing of one pixel of video data. The display control circuit 30 processes the video data and synchronization signals, and outputs data signals and control signals necessary for driving the electro-optical device 100. The data signals are analog signals obtained by converting the video data, and the control signals are signals for controlling vertical scanning and horizontal scanning in the electro-optical device 100. The display control circuit 30 may be provided in a higher-level circuit, rather than being mounted on the FPC board 74, and may receive video signals and control signals via terminals .

[0012] 2 is a block diagram showing the electrical configuration of the module 1. The module 1 includes the above-described electro-optical device 100 and a display control circuit 30. A scanning line driving circuit 130 and a peripheral circuit 150 are provided on the periphery of the display area 10 of the electro-optical device 100. The electro-optical device 100 is configured by sealing liquid crystal between an element substrate on which thin film transistors and the like are formed and an opposing substrate on which a common electrode is formed, and a scanning line driving circuit 130 and a peripheral circuit 150 are formed on the element substrate.

[0013] In the display region 10 of the electro-optical device 100, pixel circuits 110 corresponding to the pixels of the image to be displayed are arranged in a matrix. More specifically, in the display region 10, m scanning lines 12 are provided extending horizontally in the figure, and a total of (3n) data lines 14, each grouped into three lines, extend vertically in the figure and are provided electrically insulated from the scanning lines 12. The pixel circuits 110 are provided at intersections of the m scanning lines 12 and the (3n) data lines 14. Therefore, in this embodiment, the pixel circuits 110 are arranged in a matrix of m rows and (3n) columns.

[0014] Here, m is an integer equal to or greater than 2. n is an integer equal to or greater than 2. In this embodiment, m<(3n). An integer i between 1 and m is used to generally describe the rows of the scanning lines 12 and the rows in the matrix-arranged pixel circuits 110. For example, the scanning lines 12 may be referred to as rows 1, 2, 3, ..., (i-1), i, ..., (m-1), and m from top to bottom in the figure. Similarly, an integer j between 1 and n is used to generalize and describe the columns of data lines 14 and the columns of matrix-arranged pixel circuits 110. For example, to distinguish the data lines 14, they may be referred to as columns 1, 2, 3, ..., (3j-2), (3j-1), (3j), ..., (3n-2), (3n-1), and (3n) from left to right in the drawing. For convenience of explanation, the configuration of the pixel circuit 110 will be described with reference to FIG.

[0015] FIG. 3 is a diagram showing an equivalent circuit of four pixel circuits 110 (2×2) corresponding to the intersections of two adjacent scanning lines 12 and two adjacent data lines 14. As shown in the figure, the pixel circuit 110 includes a transistor 116 and a liquid crystal element 120. The transistor 116 is, for example, an N-channel thin film transistor. In the pixel circuit 110, the gate node of the transistor 116 is connected to the scan line 12, the source node is connected to the data line 14, and the drain node is connected to the pixel electrode 118 and one end of the storage capacitor 109.

[0016] In this description, "connection" means a direct or indirect connection or coupling between two or more elements, and includes, for example, coupling between two or more elements in a semiconductor substrate through different wiring layers and contact holes, even if the elements are not directly connected to each other.

[0017] A common electrode 108 is provided on the opposing substrate in common to all pixel circuits 110 so as to face the pixel electrodes 118. The common electrode 108 is maintained at a substantially constant potential Ccom over time. A liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108. Therefore, for each pixel circuit 110, a liquid crystal element 120 is formed by the pixel electrode 118, the common electrode 108, and the liquid crystal 105. The storage capacitor 109 is electrically connected in parallel to the liquid crystal element 120, and the other end is connected to a capacitor wiring 140. The capacitor wiring 140 is maintained at a constant potential over time, for example, the same potential Ccom as the common electrode .

[0018] 2, in this embodiment, the (3n) data lines 14 are grouped into groups of 3. The j-th group counting from the left corresponds to the three data lines 14 in the (3j-2)th, (3j-2)th, and (3j)th columns. Furthermore, the data lines 14 or columns may be described as, for example, the (3j-2)th column in the jth group being the first series, the (3j-1)th column being the second series, and the (3j)th column being the third series. In other words, in the jth group, the data line 14 of the first series is the (3j-2)th column, the data line 14 of the second series is the (3j-1)th column, and the data line 14 of the third series is the (3j)th column.

[0019] The display control circuit 30 processes the video data and synchronization signals supplied from the higher-level circuit, and outputs control signals to the scanning line driving circuit 130 as well as data signals Vid(1), Vid(2), Vid(3), ..., Vid(n) and selection signals Sel(1) to Sel(3). Data signals Vid(1), Vid(2), Vid(3), ..., Vid(n) are supplied to the electro-optical device 100 via n data signal lines 13. The data signals Vid(1), Vid(2), Vid(3), ..., Vid(n) will be generally described below. Data signal Vid(j) is a signal whose potential corresponds to the grayscale levels of three pixels corresponding to the intersections of three data lines 14 belonging to the j-th group and horizontally scanned scanning lines 12. In detail, the potential of data signal Vid(j) changes in a time-division manner during the horizontal scanning period according to the grayscale levels of the three pixels.

[0020] The selection signal Sel(1) is a signal for selecting the first series of data lines 14. Similarly, the selection signal Sel(2) is a signal for selecting the second series of data lines 14, and the selection signal Sel(3) is a signal for selecting the third series of data lines 14. The logic levels of the selection signals Sel(1) to Sel(3) are inverted by the NOT circuit Iv11 and output in order as inverted selection signals / Sel(1) to / Sel(3). The selection signals Sel(1) to Sel(3) are individually supplied to selection signal lines extending in the X direction, and inverted signals of the inverted selection signals / Sel(1) to / Sel(3) are individually supplied to inverted selection signal lines also extending in the X direction. Inversion refers to the inversion of the logical levels of the paired logic signals, and an inverted select signal has a logical level that is the inverse of that of the select signal. When an inverted select signal is generated by inverting a select signal using a NOT circuit, there is a time delay between the inverted select signal and the select signal. However, as will be described later, if the noise caused by the select signal can be offset by the noise caused by the inverted select signal, the time delay will not be a problem.

[0021] The scanning line driving circuit 130 supplies scanning signals individually to m rows of scanning lines 12 under the control of the display control circuit 30. Here, the scanning signal supplied to the first scanning line 12 is denoted as Gwr(1), and similarly, the scanning signals supplied to the second, third, ..., (i-1), i, ..., (m-1), and m-th scanning lines 12 are denoted as Gwr(2), Gwr(3), ..., Gwr(i-1), Gwr(i), ..., Gwr(m-1), and Gwr(m), respectively.

[0022] The display control circuit 30 outputs various control signals for controlling the scanning line driving circuit 130, but since the control signals to the scanning line driving circuit 130 are not important in this case, only the signal paths are illustrated and detailed descriptions of the control signals are omitted.

[0023] The peripheral circuit 150 is a circuit (demultiplexer) that distributes data signals supplied to the data signal lines 13 to each of the data lines 14 in accordance with selection signals Sel(1) to Sel(3). In detail, the peripheral circuit 150 has a transistor N1 and a NOT circuit Iv1 for each column of the data lines 14.

[0024] The transistor N1 is an N-channel thin film transistor similar to the transistor 116 in the pixel circuit 110. The transistor N1 and the NOT circuit Iv1 will be described with a focus on the j-th group.

[0025] A data signal Vid(j) is supplied to the data signal line 13 corresponding to the j-th group. The data signal line 13 branches into three data signal lines 13_1, 13_2, and 13_3 in this order. In the j-th group, the input terminal of the first series transistor N1 is connected to the data signal line 13_1, and the output terminal is connected to the j-th data line 14 of the first series. In the j-th group, the NOT circuit Iv1 of the first series re-inverts the logic level of the inverted selection signal / Sel(1) and outputs it. The selection signal Sel(1) and the inverted signal of the inverted selection signal / Sel(1) are joined and supplied to the gate node of the j-th transistor N1 of the first series.

[0026] In the j-th group, the input terminal of the second series transistor N2 is connected to the data signal line 13_2, and the output terminal is connected to the j-th data line 14 of the second series. In the j-th group, the second-series NOT circuit Iv1 re-inverts the logic level of the inverted selection signal / Sel(2) and outputs it. The selection signal Sel(2) and the inverted signal of the inverted selection signal / Sel(2) are joined and supplied to the gate node of the j-th second-series transistor N1. Similarly, in the j-th group, the input terminal of the third series transistor N3 is connected to the data signal line 13_3, and the output terminal is connected to the j-th data line 14 of the third series. In the j-th group, the NOT circuit Iv1 of the third series re-inverts the logic level of the inverted selection signal / Sel(3) and outputs it. The selection signal Sel(3) and the inverted signal of the inverted selection signal / Sel(3) are joined and supplied to the gate node of the j-th transistor N1 of the third series. 2 is a diagram for easily explaining the electrical configuration of the electro-optical device 100. Next, the actual arrangement of each element in the electro-optical device 100 will be described.

[0027] FIG. 4 is a plan view showing the arrangement of each element in the electro-optical device 100, particularly the arrangement on the element substrate. As described above, one end of the FPC board 74 is connected to one longitudinal side of the electro-optical device 100. Between the one end of the FPC board 74 and the display area 10, the peripheral circuit 150 is provided.

[0028] A scanning line driving circuit 130 is provided on each of the two sides of the display area 10 along the Y direction. That is, two scanning line driving circuits 130 are provided, and scanning signals are supplied to the scanning lines 12 from both ends. The reason for this configuration is that the effect of delay in the scanning signal on the display can be reduced compared to when the scanning signal is supplied from only one end. The two scanning line driving circuits 130 are supplied with the same control signal from the display control circuit 30. Although the selection signals Sel(1) to Sel(3) are supplied from the left end in FIG. 2, they are supplied from both the left and right ends, as shown in FIG. 4, in the same way as the scanning signals, in order to suppress the effects of delay. The NOT circuit Iv11 is also provided at both the left and right ends. Therefore, the inverted selection signals / Sel(1) to / Sel(3) are also supplied from both the left and right ends.

[0029] FIG. 5 is a plan view showing the arrangement of the light-shielding film 160 in the electro-optical device 100. As shown in FIG. The light-shielding film 160 is provided to partition the display area 10 and surround the display area 10 in a planar view to prevent light from entering the scanning line driving circuit 130, the peripheral circuit 150, etc. Surrounding in a planar view means blocking the outer area of ​​the display area 10, which is the object to be surrounded, like a picture frame in a planar view. Furthermore, a constant potential is applied to the light-shielding film 160 in order to shield the data signal lines 13 before branching and the data signal lines 13_1, 13_2, and 13_3 after branching. That is, the light-shielding film 160 overlaps the data signal lines 13, 13_1, 13_2, and 13_3 in plan view in order to shield these signal lines. In this description, the term "planar view" refers to a view from one of the element substrate and the opposing substrate toward the other substrate.

[0030] In this embodiment, the light-shielding film 160 is electrically connected to the capacitance wiring 140 that commonly connects the other ends of the storage capacitors 109, and is maintained at a potential Com. Note that the wiring layer that forms the capacitance wiring 140 in the display region 10 and the wiring layer that forms the light-shielding film 160 outside the display region 10 may be different or the same. In any case, it is preferable that the light-shielding film 160 be made of a wiring layer that is not optically transparent and has conductivity, specifically aluminum, titanium nitride, or the like.

[0031] FIG. 6 is a timing chart showing the operation of the electro-optical device 100. As shown in FIG. In the electro-optical device 100, m scanning lines 12 are scanned one by one during a frame (V) period in the order of 1st, 2nd, 3rd, ..., mth rows. In detail, as shown in the figure, the scanning signals Gwr(1), Gwr(2), ..., Gwr(i-1), Gwr(i), ..., Gwr(m-1), Gwr(m) are sequentially and exclusively set to H level by the scanning line driving circuit 130 for each horizontal scanning period (H). In this embodiment, the periods during which adjacent scanning signals Gwr(1) to Gwr(m) are at H level are separated in time. Specifically, after scanning signal Gwr(i-1) changes from H level to L level, the next scanning signal Gwr(i) becomes H level after a period. This period corresponds to the horizontal blanking period.

[0032] In this description, the period of one frame (V) refers to the period required to display one frame of an image specified by video data supplied from a higher-level circuit. If the length of one frame (V) is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal. Furthermore, the horizontal scanning period (H) is the time interval during which the scanning signals Gwr(1) to Gwr(m) sequentially go to H level, but for convenience in the figure, the start timing of the horizontal scanning period (H) is shown approximately in the center of the horizontal blanking period.

[0033] When one of the scanning signals Gwr(1) to Gwr(m), for example the scanning signal Gwr(i) for the ith row, goes high, the transistor 121 of the pixel circuit 110 located in the ith row is turned on. As a result, in the pixel circuit 110, one end of the liquid crystal element 120 and one end of the storage capacitor 109 are electrically connected to the corresponding data line 14. In the case of the pixel circuit 110 in the ith row and (3j-2)th column, one end of the liquid crystal element 120 and one end of the storage capacitor 109 in the pixel circuit 110 are electrically connected to the (3j-2)th column data line 14.

[0034] In this description, the "on state" of a transistor means that the source node and drain node of the transistor are electrically closed, resulting in a low impedance state, and the "off state" of a transistor means that the source node and drain node are electrically open, resulting in a high impedance state.

[0035] During the period in which the scanning signal Gwr(i) is at H level, the selection signals Sel(1), Sel(2), and Sel(3) successively and exclusively become H level. When the selection signal Sel(1) goes high, the inverted selection signal / Sel(1) goes low, and the output of the NOT circuit Iv1 in the first series goes high, turning on the transistor N1 in the first series. The display control circuit 30 outputs the potentials of the data signals Vid(1), Vid(2), ..., Vid(j), ..., Vid(n) in order according to the gradation of the pixels in the i-th row and the 1st, 4th, ..., (3j-2), ..., (3n-2)th columns, and according to the write polarity.

[0036] Therefore, the data signal Vid(j) is applied to one end of the liquid crystal element 120 and one end of the storage capacitor 109 in the pixel circuit 110 in the i-th row and (3j-2)th column via the data line 14 in the (3j-2)th column. The potential of the data signal Vid(j) applied to one end of the liquid crystal element 120 is maintained by the capacitive nature of the liquid crystal element 120 and the storage capacitance 109 even when the transistor N1 in the (3j-2) column is turned off and the horizontal scanning period for the i-th row ends and the scanning signal Gwr(i) becomes L level.

[0037] As is well known, in the liquid crystal element 120, the orientation of the liquid crystal molecules changes in response to the electric field generated by the pixel electrode 118 and the common electrode 108. Therefore, the liquid crystal element 120 has a transmittance that corresponds to the effective value of the applied voltage. In this embodiment, the transmittance is minimum when the voltage applied to the liquid crystal element 120 is zero, and the transmittance increases as the applied voltage increases, in a normally black mode.

[0038] The data signal Vid(j) is a potential corresponding to the gradation of the pixel in the i-th row (3j-2) column, and is a potential corresponding to the write polarity. When driving the liquid crystal element 120, AC driving is required to prevent deterioration of the liquid crystal 105. For this reason, a positive potential on the higher side and a negative potential on the lower side relative to the amplitude center potential Vcen are alternately applied to the pixel electrode 118, for example, every one frame (V). The potential Vcen can be considered to be approximately the same potential as the potential LCcom applied to the common electrode 108.

[0039] The range that the positive polarity potential can take is indicated by Rng(+). The range Rng(+) is, for example, from the potential Vwt(+) when the gradation is at its highest value to the potential Vbk(+) when the gradation is at its lowest value. The range that the negative polarity potential can take is indicated by Rng(-). The range Rng(-) is, for example, from the potential Vwt(-) when the gradation is at its highest value to the potential Vbk(-) when the gradation is at its lowest value. Here, the (3j-2)th column of the horizontal scanning of the ith row has been described, but the same operation is similarly performed in the first series of 1st, 4th, 7th, . . . , (3n-2)th columns. The selection signal Sel(1) goes to L level, and then the selection signal Sel(2) goes to H level.

[0040] When the selection signal Sel(2) goes high, the second-series transistor N1 is turned on. The display control circuit 30 outputs the data signals Vid(1), Vid(2), ..., Vid(j), ..., Vid(n) in order at potentials corresponding to the grayscales and write polarities of the pixels in the i-th row and the 2nd, 5th, ..., (3j-1), ..., (3n-1)th columns. As a result, the liquid crystal element 120 of the pixel circuit 110 corresponding to the intersection of the i-th row scanning line and the second-series data line 14 exhibits a transmittance corresponding to the grayscale. The selection signal Sel(2) goes to L level, and then the selection signal Sel(3) goes to H level.

[0041] When the selection signal Sel(3) goes high, the third-series transistor N1 is turned on. The display control circuit 30 outputs the data signals Vid(1), Vid(2), ..., Vid(j), ..., Vid(n) in order at potentials corresponding to the grayscales of the pixels in the i-th row and the 3rd, 6th, ..., (3j), ..., (3n) columns, and at potentials corresponding to the write polarity. As a result, the liquid crystal element 120 of the pixel circuit 110 corresponding to the intersection of the i-th row scanning line and the third-series data line 14 exhibits a transmittance corresponding to the grayscale. After this, the selection signal Sel(3) goes low, and horizontal scanning of the i-th row ends.

[0042] Here, horizontal scanning of the i-th row has been described, but similar operations are performed sequentially for horizontal scanning of the 1st, 2nd, 3rd, . . . , mth rows. When horizontal scanning of the mth row is completed, the next frame period begins, and horizontal scanning starts again from row 1. During the next frame period, the display control circuit 30 inverts the potential polarity of the data signal.

[0043] Before describing the advantages of the electro-optical device 100 according to the first embodiment, an electro-optical device according to a comparative example will be described.

[0044] 7 is a diagram showing the configuration of the jth group of peripheral circuits 150 in an electro-optical device according to a comparative example. As shown in this diagram, in the comparative example, selection signals Sel(1) to Sel(3) are supplied via selection signal lines 180, but inverted selection signals / Sel(1) to / Sel(3) are not supplied. Furthermore, a NOT circuit Iv1 is not provided for each data line 14. In the comparative example, the light-shielding film 160 overlaps in plan view with three selection signal lines 180 to which selection signals Sel(1) to Sel(3) are respectively supplied, as indicated by hatching. In reality, the light-shielding film 160 also overlaps with the transistor N1 in plan view, but the hatching is not superimposed on the transistor N1 because it would overlap with the symbol and be difficult to see. The light-shielding film 160 and the selection signal line 180 are electrically insulated from each other by an insulating layer, but a parasitic capacitance occurs between them with the insulating layer acting as a dielectric.

[0045] FIG. 8 is a diagram for explaining noise superimposed on the light-shielding film 160 in the comparative example. The selection signals Sel(1), Sel(2), and Sel(3) become H level exclusively in this order during the horizontal scanning period (H). When the logic level of the selection signal Sel(1) changes, noise Ns1a corresponding to the change in logic level is superimposed on the light-shielding film 160 via the parasitic capacitance. Similarly, when the logic levels of the selection signals Sel(2) and Sel(3) change, noise corresponding to the change in logic level is superimposed on the light-shielding film 160 via the parasitic capacitance. In detail, noise Ns2a corresponding to the change in the logic level of the selection signal Sel(2) is superimposed on the light-shielding film 160 via parasitic capacitance, and noise Ns3a corresponding to the change in the logic level of the selection signal Sel(3) is superimposed on the light-shielding film 160 via parasitic capacitance.

[0046] The light-shielding film 160 is electrically connected to the capacitance wiring 140, which is maintained at a potential Com, but when noise is superimposed on the light-shielding film 160, the potential fluctuates from the potential Com, causing an unstable state. Fluctuations in the potential of the light-shielding film 160 and the capacitance wiring 140 can cause degradation of display quality, such as display unevenness.

[0047] FIG. 9 is a diagram showing the configuration of the j-th group of the peripheral circuits 150 in the electro-optical device 100 according to the first embodiment. As described above, in the embodiment, not only are the selection signals Sel(1) to Sel(3) supplied individually via the selection signal line 180, but the inverted selection signals / Sel(1) to / Sel(3) are also supplied individually via the inverted selection signal line 181. Furthermore, in the first embodiment, the light-shielding film 160 overlaps not only the three selection signal lines 180 but also the three inverted selection signal lines 181 in plan view. The light-shielding film 160 and the inverted selection signal lines 181 are electrically insulated from each other via an insulating layer, but like the selection signal lines 180, a parasitic capacitance occurs with the insulating layer as a dielectric.

[0048] The inverted selection signals / Sel(1) to / Sel(3) are signals obtained by inverting the logic levels of the selection signals Sel(1) to Sel(3), respectively. Therefore, the change in the logic level of the selection signal Sel(1) and the change in the logic level of the inverted selection signal / Sel(1) are in opposite directions to each other, but the magnitudes of the changes are approximately the same. Similarly, the change in the logic level of the selection signal Sel(2) and the logic level of the inverted selection signal / Sel(2), and the change in the logic level of the selection signal Sel(3) and the logic level of the inverted selection signal / Sel(3) are in opposite directions to each other, but the magnitudes of the changes are approximately the same.

[0049] FIG. 10 is a diagram for explaining cancellation of noise superimposed on the light-shielding film 160 in the first embodiment. When the logic level of the selection signal Sel(1) changes, noise Ns1a corresponding to the change in logic level is superimposed on the light-shielding film 160 via parasitic capacitance. However, at the same time, noise Ns1b of approximately the same magnitude and in the opposite direction to the noise Ns1a, specifically noise Ns1b corresponding to the change in logic level of the inverted selection signal / Sel(1), is superimposed on the light-shielding film 160 via parasitic capacitance.

[0050] Therefore, noise Ns1a superimposed on the light-shielding film 160 in accordance with a change in the logic level of the selection signal Sel(1) is cancelled out by noise Ns1b superimposed in accordance with a change in the logic level of the inverted selection signal / Sel(1). Similarly, noise Ns2a superimposed on the light-shielding film 160 in accordance with a change in the logic level of the selection signal Sel(2) is cancelled out by noise Ns2b superimposed in accordance with a change in the logic level of the inverted selection signal / Sel(2). The noise Ns3a superimposed on the light-shielding film 160 in accordance with the change in the logic level of the selection signal Sel(3) is cancelled out by the noise Ns3b superimposed in accordance with the change in the logic level of the inverted selection signal / Sel(3). Here, "a certain "noise" being cancelled out by another "noise"" means that another "noise" in the opposite direction to the certain "noise" is propagated through parasitic capacitance or the like, thereby canceling out and reducing the "noise" of the certain "noise."

[0051] In this way, in the first embodiment, noises Ns1a to Ns3a that occur in accordance with changes in the logic levels of the selection signals Sel(1) to Sel(3) are cancelled out by noises Ns1b to Ns3b that occur in accordance with changes in the logic levels of the inverted selection signals / Sel(1) to / Sel(3). Therefore, in the first embodiment, fluctuations in the potential in the light-shielding film 160 are suppressed, and degradation of display quality, such as display unevenness, caused by fluctuations in the potential of the capacitance wiring 140 connected to the light-shielding film 160 can be avoided.

[0052] In the first embodiment, it is preferable that the parasitic capacitance generated between the light-shielding film 160 and the selection signal line 180 is the same as or close to the parasitic capacitance generated between the light-shielding film 160 and the inverted selection signal line 181. To achieve this, the wiring layer that forms the light-shielding film 160, the wiring layer that forms the selection signal line 180, and the wiring layer that forms the inverted selection signal line 181 may be configured as follows.

[0053] For example, as shown in the cross-sectional view of FIG. 11, the selection signal line 180 and the inverted selection signal line 181 may be formed by patterning the first wiring layer Mt1, and the light-shielding film 160 may be formed by patterning the second wiring layer Mt2. In practice, gate electrodes, semiconductor layers, etc. are provided below the first wiring layer Mt1, while wiring layers such as pixel electrodes 118 are provided above the second wiring layer Mt2. In addition, an interlayer insulating film is provided between the wiring layers. According to this configuration, the selection signal line 180 or the inverted selection signal line 181 and the light-shielding film 160 sandwich a common insulating film, so it is easy to align the parasitic capacitance between the selection signal line 180 and the light-shielding film 160 and the parasitic capacitance between the inverted selection signal line 181 and the light-shielding film 160. Alternatively, the light-shielding film 160 may be formed by patterning the first wiring layer Mt1, and the selection signal line 180 and the inverted selection signal line 181 may be formed by patterning the second wiring layer Mt2.

[0054] 12, for example, a configuration may be adopted in which the selection signal line 180 is formed by patterning the first wiring layer Mt1, the light-shielding film 160 is formed by patterning the second wiring layer Mt2, and the inverted selection signal line 181 is formed by patterning the third wiring layer Mt3. In other words, a configuration may be adopted in which the light-shielding film 160 is sandwiched between the selection signal line 180 and the inverted selection signal line 181. According to this configuration, the selection signal line 180 and the inverted selection signal line 181 overlap in a planar view, so that the area in a planar view can be reduced. Alternatively, the inverted selection signal line 181 may be formed by patterning the first wiring layer Mt1, and the selection signal line 180 may be formed by patterning the third wiring layer Mt3.

[0055] In the first embodiment, the switching element that distributes the data signal supplied to the data signal line 13 to each data line 14 is configured as an N-channel transistor N1, but it may also be configured as a P-channel transistor. However, the resistance of one channel type transistor in the on state is relatively high, so as resolution increases and the period during which the transistor is in the on state becomes shorter, there is a possibility that the data signal supplied to the data signal line 13 will not be able to be written (propagated) sufficiently to each data line 14. Therefore, a second embodiment will be described, which reduces such a possibility. Note that the electro-optical device 100 according to the second embodiment differs from the first embodiment only in the demultiplexer and its periphery, and is otherwise the same as the first embodiment. Therefore, the differences from the second embodiment will be mainly described.

[0056] FIG. 13 is a diagram showing the configuration of the j-th group of the peripheral circuits 150 in the electro-optical device 100 according to the second embodiment. In the second embodiment, each data line 14 has a transmission gate Trs. The transmission gate Trs is an analog switch in which a P-channel transistor P1 and an N-channel transistor N1 are connected in parallel. The transistors P1 and N1 are both thin-film transistors similar to the transistor 116 in the pixel circuit 110. In the second embodiment, each data line 14 does not have a NOT circuit Iv1.

[0057] In the second embodiment, similarly to the first embodiment, three inverted selection signal lines 181 are provided extending in the same X direction as the selection signal line 180. Inverted selection signals / Sel(1) to / Sel(3) are supplied to the three inverted selection signal lines 181 in order by NOT circuits Iv11 provided corresponding to each of them.

[0058] In the j-th group, the input terminal of the first series transmission gate Trs is connected to the data signal line 13_1 branched in the j-th group corresponding to the first series, and the output terminal is connected to the first series data line 14 in the j-th group. In the j-th group, of the transistors P1 and N1 constituting the first-series transmission gate Trs, a selection signal Sel(1) is supplied to the gate node of the transistor N1, and an inverted selection signal / Sel(1) is supplied to the gate node of the transistor P1 constituting the transmission gate Trs.

[0059] In the j-th group, the second series of transmission gates Trs is the same as the first series. That is, in the j-th group, the input terminal of the second-series transmission gate Trs is connected to the data signal line 13_2 branched off corresponding to the second series in the j-th group, and the output terminal is connected to the second-series data line 14 in the j-th group. In the j-th group, the selection signal Sel(2) is supplied to the gate node of the transistor N1 constituting the second-series transmission gate Trs, and the inverted selection signal / Sel(2) is supplied to the gate node of the transistor P.

[0060] In the j-th group, the third-system transmission gate Trs is the same as the first-system. That is, in the j-th group, the input terminal of the third-series transmission gate Trs is connected to the data signal line 13_3 branched off corresponding to the third series in the j-th group, and the output terminal is connected to the third-series data line 14 in the j-th group. In the j-th group, a selection signal Sel(3) is supplied to the gate node of the transistor N1 constituting the third-series transmission gate Trs, and an inverted selection signal / Sel(3) is supplied to the gate node of the transistor P.

[0061] Also in the second embodiment, noises Ns1a to Ns3a generated in accordance with changes in the logic levels of the selection signals Sel(1) to Sel(3) are cancelled out by noises Ns1b to Ns3b generated in accordance with changes in the logic levels of the inverted selection signals / Sel(1) to / Sel(3). Therefore, also in the second embodiment, fluctuations in the potential in the light-shielding film 160 are suppressed, and degradation of display quality such as display unevenness caused by fluctuations in the potential of the capacitance wiring 140 connected to the light-shielding film 160 can be avoided.

[0062] In the second embodiment, the ON state of the transmission gate Trs means that the transistors N1 and P1 are simultaneously turned ON in parallel, and the resistance value is approximately half of that when only one of the channel type transistors is turned ON. When the potential of the data signal is high in positive write, the P-channel transistor compensates for the insufficient write of the N-channel transistor. Conversely, when the potential of the data signal is low in negative write, the N-channel transistor compensates for the insufficient write of the P-channel transistor. Therefore, according to the second embodiment, even if resolution continues to increase, the data signals supplied to the data signal lines 13 can be sufficiently written to each data line 14, and display unevenness caused by differences in write polarity can be suppressed.

[0063] Next, an example of branch wiring from the selection signal line 180 and the inverted selection signal line 181 to the gate node of the transistor P1 and the gate node of the transistor N1 that configure the transmission gate Trs in the second embodiment will be described.

[0064] FIG. 14 is a plan view showing the main parts of an electro-optical device 100 according to a second embodiment. Specifically, the main parts are a selection signal line 180, an inverted selection signal line 181, and branch wiring to the gate node of the transistor that constitutes the transmission gate Trs. Note that in FIG. 14, the wiring lines are shifted to make the layer structure easier to understand, but in reality, they overlap in a planar view. FIG. 15 is a cross-sectional view simply showing the configuration of the wiring layer when broken along line Aa in FIG. 14.

[0065] In the second embodiment, as shown in the cross-sectional view of Figure 15, selection signal lines 180 etc. are formed by patterning the first wiring layer Mt1, a light-shielding film 160 is formed by patterning the second wiring layer Mt2, inverted selection signal lines 181 etc. are formed by patterning the third wiring layer Mt3, and data signal lines 13_1 etc. are formed by patterning the fourth wiring layer Mt4. In FIG. 14, the light-shielding film 160 is omitted to avoid complication.

[0066] 14, the selection signal lines 180 and the inverted selection signal lines 181 each extend in the X direction and are arranged, for example, in the following order: In detail, arranged in the Y direction are the selection signal line 180 supplied with the selection signal Sel(1), the inverted selection signal line 181 supplied with the inverted selection signal / Sel(1), the selection signal line 180 supplied with the selection signal Sel(2), the inverted selection signal line 181 supplied with the inverted selection signal / Sel(2), the selection signal line 180 supplied with the selection signal Sel(3), and the inverted selection signal line 181 supplied with the inverted selection signal / Sel(3).

[0067] In the first system, the selection signal line 180, to which the selection signal Sel(1) is supplied, branches into lines Mw11 and Mw12 at a point where it intersects with the data signal line 13_1 in a plan view. In detail, the line Mw11 branches in the opposite Y direction from the selection signal line 180 to which the selection signal Sel(1) is supplied, and extends to the gate node of the transistor N1 that constitutes the transmission gate Trs of the first system, which is omitted in FIG. 14. Furthermore, the line Mw12 extends in the Y direction in a plan view to a point where it intersects with the inverted selection signal line 181 to which the inverted selection signal / Sel(1) is supplied.

[0068] In plan view, the wiring Mw13 branches off from the inverted selection signal line 181, to which the inverted selection signal / Sel(1) is supplied, at the point where it intersects with the data signal line 13_1. In detail, the wiring Mw13 branches off in the opposite Y direction from the inverted selection signal line 181, to which the inverted selection signal / Sel(1) is supplied, and extends to the gate node of the transistor P1 that configures the first-system transmission gate Trs, which is omitted in FIG. Therefore, the light-shielding film 160 made of the second wiring layer Mt2 is sandwiched in the first series by the wirings Mw11 and Mw12 of the first wiring layer Mt1 and the wiring Mw13 of the third wiring layer Mt3 over approximately the same distance in the Y direction.

[0069] In the second group, the selection signal line 180 supplied with the selection signal Sel(2) branches into wires Mw21 and Mw22 at a point where the selection signal line 180 intersects with the data signal line 13_2 in a plan view. In detail, the wire Mw21 branches in the opposite Y direction from the selection signal line 180 supplied with the selection signal Sel(2), passes through an inverted selection signal line 181 supplied with an inverted selection signal / Sel(1), and bends in the opposite X direction just before the selection signal line 180 supplied with the selection signal Sel(1). The wiring Mw21 and the selection signal line 180 are patterned on the same first wiring layer Mt1, and therefore cannot intersect in a planar view. Therefore, the wiring Mw21 is connected to the wiring Mw24 via the relay wiring Mw23, straddling the selection signal line 180 to which the selection signal Sel(1) is supplied. Note that the wiring Mw23 is patterned on, for example, the third wiring layer Mt3 other than the first wiring layer Mt1 and the second wiring layer Mt2, and is connected to the wirings Mw21 and Mw24 via contact holes indicated by x marks in the figure. In this way, the selection signal line 180 to which the selection signal Sel(2) is supplied is connected to the wiring Mw24 via the wirings Mw21 and Mw23 in this order. The wiring Mw24 overlaps with the data signal line 13_2 in plan view, and extends in the opposite Y direction up to the gate node of the transistor N1 constituting the second-series transmission gate Trs, which is omitted in FIG. Furthermore, the wiring Mw22 extends in the Y direction in plan view up to a point where it intersects with the inverted selection signal line 181 to which the inverted selection signal / Sel(2) is supplied.

[0070] The wiring Mw25 branches off from the inverted selection signal line 181, to which the inverted selection signal / Sel(2) is supplied, at a point where it intersects with the data signal line 13_2 in a plan view. In detail, the wiring Mw25 branches off in the opposite Y direction from the inverted selection signal line 181, to which the inverted selection signal / Sel(2) is supplied, straddles the selection signal line 180, to which the selection signal Sel(1) is supplied, and the wiring Mw22, and bends in the X direction just before the inverted selection signal line 181, to which the inverted selection signal / Sel(1) is supplied. The wiring Mw25 and the inverted selection signal line 181 are patterned on the same third wiring layer Mt3, and therefore cannot intersect in a planar view. Therefore, the wiring Mw25 is connected to the wiring Mw27 via the relay wiring Mw26, passing under the inverted selection signal line 181 to which the inverted selection signal / Sel(1) is supplied. Note that the wiring Mw26 is patterned on a wiring layer other than the second wiring layer Mt2 and the third wiring layer Mt3, for example, the first wiring layer Mt1, and is connected to the wirings Mw25 and Mw27 via contact holes indicated by x marks in the figure. In this way, the inverted selection signal line 181 to which the inverted selection signal / Sel(2) is supplied is connected to the wiring Mw27 via the wirings Mw25 and Mw26 in this order. The wiring Mw27 overlaps with the data signal line 13_2 in plan view, and extends in the opposite Y direction up to the gate node of the transistor P1 constituting the second-system transmission gate Trs, which is omitted in FIG. Therefore, in the second series, the light-shielding film 160 made of the second wiring layer Mt2 is sandwiched over approximately the same distance in the Y direction between the wirings Mw21, Mw22, and Mw24 of the first wiring layer Mt1 and the wirings Mw25 and Mw27 of the third wiring layer Mt3. The light-shielding film 160 made of the second wiring layer Mt2 is patterned so as not to come into contact with the metal or the like filled in the contact holes.

[0071] The third series overlaps with the second series, so details will be omitted, but the selection signal line 180 to which the selection signal Sel(3) is supplied is connected to a wiring Mw36 via wirings Mw31, Mw33, Mw34, and Mw35 in this order. The wiring Mw36 overlaps with the data signal line 13_3 in plan view, and extends in the opposite Y direction up to the gate node of the transistor N1 that configures the transmission gate Trs of the third series, which is omitted in FIG. Furthermore, the wiring Mw32 extends in the Y direction in plan view up to a point where it intersects with the inverted selection signal line 181 to which the inverted selection signal / Sel(3) is supplied. The selection signal line 180, to which the inverted selection signal / Sel(3) is supplied, is connected to a wiring Mw41 via wirings Mw37, Mw38, Mw39, and Mw40 in this order. The wiring Mw41 overlaps the data signal line 13_3 in plan view, and extends in the opposite Y direction up to the gate node of a transistor P1 constituting a third-system transmission gate Trs, which is omitted in FIG. Therefore, in the third series, the light-shielding film 160 made of the second wiring layer Mt2 is sandwiched over approximately the same distance along the Y direction between the wirings Mw31, Mw32, Mw34 and Mw36 of the first wiring layer Mt1 and the wirings Mw37, Mw39 and Mw41 of the third wiring layer Mt3.

[0072] As described above, in the second embodiment, not only are the selection signal lines 180 and the inverted selection signal lines 181 sandwiched between each series by the light-shielding film 160, but also the wiring branching from the selection signal line 180 and the wiring branching from the inverted selection signal line 181 are sandwiched at approximately the same distance by the light-shielding film 160. Therefore, in the second embodiment, in addition to the effect of using the transmission gate Trs, noise generated in the light-shielding film 160 due to level changes in the selection signals Sel(1) to Sel(3) can be accurately canceled out by noise due to level changes in the inverted selection signals / Sel(1)) to / Sel(3).

[0073] In the second embodiment, the selection signal line 180 and the inverted selection signal line 181, and the branch wiring from these signal lines to the gate node of the transistor P1 and the gate node of the transistor N1 that constitute the transmission gate Trs, are not limited to the structures shown in FIGS. 14 and 15.

[0074] FIG. 16 is a plan view showing another example of the main part of the electro-optical device 100 according to the second embodiment, and FIG. 17 is a cross-sectional view showing a simplified configuration of the wiring layer when cut along line Bb in FIG. In this alternative example, for example, odd-numbered inverted selection signal lines 181 and even-numbered selection signal lines 180 are formed by patterning the first wiring layer Mt1, wires Mw51 to Mw56 are formed by patterning the second wiring layer Mt2, odd-numbered selection signal lines 180 and even-numbered inverted selection signal lines 181 are formed by patterning the third wiring layer Mt3, and a light-shielding film 160 is formed by patterning the fourth wiring layer Mt4. In FIG. 16, the light-shielding film 160 and the data signal lines 13_1 to 13_3 are omitted to avoid complication.

[0075] As shown in FIG. 16, the selection signal lines 180 and the inverted selection signal lines 181 are arranged in the same order as in FIG. On the other hand, the wirings Mw51 to Mw56 extend along the Y direction and are arranged at approximately equal intervals. Of these, the wiring Mw51 is connected via a contact hole to a selection signal line 180 to which a selection signal Sel(1) is supplied. Furthermore, the wiring Mw51 extends, on the Y direction side, to a point where it intersects with an inverted selection signal line 181 to which an inverted selection signal / Sel(3) is supplied, and on the opposite side in the Y direction, it extends to a gate node of a transistor N1 that constitutes a first-series transmission gate Trs, which is omitted in FIG. Similarly, the wiring Mw52 is connected via a contact hole to an inverted selection signal line 181 to which an inverted selection signal / Sel(1) is supplied. Furthermore, the wiring Mw52 extends, on the Y direction side, to a point where it intersects with the inverted selection signal line 181 to which an inverted selection signal / Sel(3) is supplied, and on the opposite side in the Y direction, extends to a gate node of a transistor P1 that constitutes a first-system transmission gate Trs (omitted in FIG. 16).

[0076] The wirings Mw53 and Mw54 are connected, via contact holes, in order to a selection signal line 180 to which a selection signal Sel(2) is supplied and an inverted selection signal line 181 to which an inverted selection signal / Sel(2) is supplied. On the Y-direction side, the wirings Mw53 and Mw54 both extend to a point where they intersect with the inverted selection signal line 181 to which an inverted selection signal / Sel(3) is supplied, and on the opposite side in the Y-direction, they extend in order to the gate nodes of the transistors N1 and P1 that constitute the second-system transmission gate Trs.

[0077] The wirings Mw55 and Mw56 are connected, via contact holes, in order to a selection signal line 180 to which a selection signal Sel(3) is supplied and an inverted selection signal line 181 to which an inverted selection signal / Sel(3) is supplied. On the Y-direction side, the wirings Mw55 and Mw56 both extend to a point where they intersect with the inverted selection signal line 181 to which the inverted selection signal / Sel(3) is supplied, and on the opposite side in the Y-direction, they extend in order to the gate nodes of the transistors N1 and P1 that constitute the third-system transmission gate Trs.

[0078] As described above, according to another example of the second embodiment, the light-shielding film 160 is arranged such that the selection signal lines 180 and the inverted selection signal lines 181 face each other in each series, and therefore noise generated in the light-shielding film 160 due to level changes in the selection signals Sel(1)) to Sel(3) can be offset by noise due to level changes in the inverted selection signals / Sel(1)) to / Sel(3). Furthermore, the wirings Mw51 to Mw56 all have the same area where they intersect with the selection signal line 180 and the inverted selection signal line 181 in plan view, so that the parasitic capacitances can be equalized.

[0079] FIG. 18 is a diagram showing a main part of a peripheral circuit 150 in an electro-optical device 100 according to a third embodiment. In the third embodiment, each data line 14 has a transmission gate Trs and a NOT circuit Iv5. As in the second embodiment, the transmission gate Trs is an analog switch in which a P-channel transistor P1 and an N-channel transistor N1 are connected in parallel.

[0080] In the j-th group, the input terminals of the transmission gates Trs of the first, second and third series are connected to the data signal lines 13_1, 13_2 and 13_3 corresponding to the series, respectively, and the output terminals are connected to the data line 14 corresponding to the series.

[0081] In the j-th group, a selection signal Sel(1) is supplied to the gate node of the transistor N1 that constitutes the transmission gate Trs of the first system via a line branching from the selection signal line 180. The gate node of transistor P1 constituting the first series transmission gate Trs is supplied with a signal inverted by NOT circuit Iv5 from the logic level of selection signal Sel(1) supplied via a wiring branched from selection signal line 180. In the third embodiment, three inverted selection signal lines 181 are provided, extending in the same X direction as the selection signal lines 180 and separated into groups. The signal inverted by the first NOT circuit Iv5 is connected to one of the three inverted selection signal lines 181 via a signal line extending in the Y direction.

[0082] In the j-th group, the transmission gate Trs and the NOT circuit Iv5 of the second series are the same as those of the first series. That is, in the j-th group, the selection signal Sel(2) is supplied to the gate node of the transistor N1 that constitutes the second-system transmission gate Trs via a line branching from the selection signal line 180. The gate node of transistor P1 constituting the second series transmission gate Trs is supplied with a signal inverted by NOT circuit Iv5 from the logic level of selection signal Sel(2) supplied via a wiring branched from selection signal line 180. The signal inverted by the second NOT circuit Iv5 is connected to another one of the three inverted selection signal lines 181 via a signal line extending along the Y direction.

[0083] In the j-th group, the transmission gate Trs and the NOT circuit Iv5 of the third system are similar to those of the first and second systems. That is, in the j-th group, the selection signal Sel(3) is supplied to the gate node of the transistor N1 that constitutes the transmission gate Trs of the third series via a line branching from the selection signal line 180. The gate node of transistor P1 constituting the third series transmission gate Trs is supplied with a signal inverted by NOT circuit Iv5 from the logic level of selection signal Sel(3) supplied via a wiring branched from selection signal line 180. The signal inverted by the third NOT circuit Iv5 is connected to the remaining one of the three inverted selection signal lines 181 via a signal line extending along the Y direction.

[0084] The three inverted selection signal lines 181 are individually supplied with the inverted selection signals / Sel(1) to / Sel(3) in the first embodiment. Therefore, similar to the first and second embodiments, the light-shielding film 160 intersects with three selection signal lines 180 to which selection signals Sel(1) to Sel(3) are supplied and three inverted selection signal lines 181 to which inverted selection signals / Sel(1) to / Sel(3) are supplied. In the third embodiment, a layout is preferred in which the overlapping area between the light-shielding film 160 and the selection signal line 180 in each series is approximately the same as the overlapping area between the light-shielding film 160 and the inverted selection signal line 181 in plan view. The reason for this is that, as seen from the light-shielding film 160, the parasitic capacitance generated between the light-shielding film 160 and the selection signal line 180 is approximately the same as the parasitic capacitance generated between the light-shielding film 160 and the inverted selection signal line 181, so that noise can be canceled out with high precision.

[0085] In the third embodiment as well, noise occurring in association with changes in the logic levels of the selection signals Sel(1) to Sel(3) is cancelled out by noise occurring in association with changes in the logic levels of the inverted selection signals / Sel(1) to / Sel(3). Therefore, in the third embodiment as well, it is possible to avoid degradation of display quality, such as display unevenness, caused by potential fluctuations in the light-shielding film 160 and the capacitance wiring 140.

[0086] In the third embodiment shown in FIG. 18, the NOT circuit Iv5 inverts the selection signal supplied to the selection signal line 180 and supplies the inverted signal to the gate node of the transistor P1 in the transmission gate Trs and the inverted selection signal line 181, but the present invention is not limited to this configuration. Although not specifically shown, the NOT circuit Iv5 may be configured to invert the inverted selection signal supplied to the inverted selection signal line 181 and supply the inverted signal to the gate node of the transistor N1 in the transmission gate Trs and to the selection signal line 180.

[0087] In the first, second and third embodiments (hereinafter referred to as "embodiments, etc."), the number k of data lines 14 constituting one group is described as "3", but it may also be "2" or an integer greater than or equal to "4".

[0088] Next, a projection display device will be described as an example of an electronic device to which the electro-optical device 100 according to the embodiment and the like is applied.

[0089] 19 is a diagram showing the optical configuration of a projection display device 200. As shown in the figure, the projection display device 200 includes electro-optical devices 100R, 100G, and 100B.

[0090] A lamp unit 2102 consisting of a white light source such as a halogen lamp or an LED is provided inside the projection display device 200. Light emitted from the lamp unit 2102 is separated into three primary colors, red (R), green (G), and blue (B), by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Of these, the R light enters the electro-optical device 100R, the G light enters the electro-optical device 100G, and the B light enters the electro-optical device 100B. Since the optical path of B is longer than the optical paths of R and G, it is necessary to prevent loss in the optical path of B. For this reason, a relay lens system 2121 consisting of an input lens 2122, a relay lens 2123, and an output lens 2124 is provided in the optical path of B.

[0091] The electro-optical devices 100R, 100G, and 100B are common to the electro-optical device 100 according to the embodiment, but because the colors of the incident light are different, they are distinguished by symbols for convenience. The liquid crystal elements of the electro-optical device 100R are driven based on a data signal corresponding to R supplied from a higher-level circuit, and have a transmittance that corresponds to the voltage of the data signal. Therefore, in the electro-optical device 100R, an R transmission image is generated by individually controlling the transmittance of the liquid crystal elements. Similarly, in the electro-optical device 100G, a G transmission image is generated based on a data signal corresponding to G, and in the electro-optical device 100B, a B transmission image is generated based on a data signal corresponding to B.

[0092] The transmitted images of each color generated by the electro-optical devices 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light are refracted at 90 degrees, while the G light travels straight. Therefore, the dichroic prism 2112 combines the images of each color. The combined image formed by the dichroic prism 2112 is incident on the projection lens 2114. The projection lens 2114 enlarges and projects the combined image onto the screen Scr.

[0093] The transmission images of the electro-optical devices 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmission image of the electro-optical device 100G is projected in a straight line. Therefore, the transmission images of the electro-optical devices 100R and 100B are left-right inverted relative to the transmission image of the electro-optical device 100G.

[0094] Furthermore, although a projection display device 200 has been used as an example of an electronic device here, the present invention is not limited to this and can also be applied to, for example, the display panel of a head-mounted display, an electronic viewfinder in a video camera or a digital camera with interchangeable lenses, a personal digital assistant, a display part of a wristwatch, and the like.

[0095] From the above-described exemplary embodiments, the following aspects can be understood, for example.

[0096] In order to solve the above problem, an electro-optical device according to one embodiment of the present disclosure includes a plurality of data lines including k (k is an integer of 2 or more) data lines that are grouped together, data signal lines to which data signals corresponding to the gradations of pixels are supplied in a time-division manner corresponding to the k data lines, k selection signal lines to which selection signals are respectively supplied, k inverted selection signal lines that are paired with the k selection signal lines and to which inverted selection signals of the selection signals are respectively supplied, first switching elements that are provided in one-to-one correspondence with the plurality of data lines and are located between the data signal lines and one of the data lines and are turned on or off in response to a selection signal supplied to one of the k selection signal lines, and constant potential wiring that overlaps the k selection signal lines and the k inverted selection signal lines in a planar view and is maintained at a predetermined potential.

[0097] In the electro-optical device according to aspect 1, noise superimposed on the constant potential wiring due to potential fluctuations on the selection signal line is canceled out by noise due to potential fluctuations on the inverted selection signal line, thereby suppressing potential fluctuations on the constant potential wiring. Note that "one noise is canceled out by another noise" refers to the occurrence of a noise in the opposite direction to the one noise, thereby canceling out the one noise. The light-shielding film 160 is an example of a "constant potential wiring," and the transistor N1 is an example of a "first switching element."

[0098] In an electro-optical device according to a specific aspect 2 of aspect 1, the constant potential wiring has a light-shielding property and surrounds, in a plan view, a display area in which a plurality of pixel circuits are arranged. The electro-optical device according to aspect 2 prevents stray light and the like from entering the display area.

[0099] An electro-optical device according to a specific aspect 3 of aspect 2 further has a scanning line, and the pixel circuit includes a second switching element, an electro-optical element, and a storage capacitor, and the second switching element is turned on or off between the data line and one end of the electro-optical element depending on the potential of the scanning line, the electro-optical element has optical characteristics depending on the voltage at the one end and the other end, the storage capacitor holds the voltage at the one end of the electro-optical element, and the constant potential wiring and the other end of the storage capacitor are electrically connected. According to the electro-optical device of aspect 3, the potential applied to the constant potential wiring can be the same as the potential applied to the other end of the storage capacitor, and potential fluctuations in the constant potential wiring and the other end of the storage capacitor are suppressed, thereby suppressing degradation of display quality caused by such potential fluctuations. The liquid crystal element 120 is an example of an "electro-optical element," the transistor 116 is an example of a "second switching element," and the capacitor wiring 140 is an example of the "other end of the storage capacitor."

[0100] In an electro-optical device according to a fourth aspect, which is a specific example of the first aspect, the first switching element is a P-channel transistor or an N-channel transistor. The electro-optical device according to the fourth aspect can have a simplified configuration.

[0101] An electro-optical device according to a specific aspect 5 of aspect 4 further includes NOT circuits arranged in one-to-one correspondence with the plurality of data lines, the first switching element being the N-channel transistor, the NOT circuit corresponding to one of the plurality of data lines inverts the logic level of an inverted selection signal supplied to one of the k inverted selection signal lines, and a gate node of the N-channel transistor is supplied with a merged signal of the inverted signal supplied to one selection signal line paired with the one inverted selection signal line and the output signal of the NOT circuit corresponding to the one data line. The first switching element may be a P-channel transistor. Specifically, the electro-optical device further includes NOT circuits provided in one-to-one correspondence with the plurality of data lines, and the first switching element is The NOT circuit, which is a P-channel transistor and corresponds to one of the multiple data lines, inverts the logic level of a selection signal supplied to one of the k selection signal lines, and a gate node of the P-channel transistor is supplied with a merged signal of an inverted signal supplied to an inverted selection signal line that forms a pair with the one selection signal line and an output signal of the NOT circuit corresponding to the one data line.

[0102] In an electro-optical device according to a sixth aspect, which is a specific example of the first aspect, the first switching element is a transmission gate that combines a P-channel transistor and an N-channel transistor. The electro-optical device according to the sixth aspect can adequately write data signals supplied to data signal lines to the data lines, and can suppress display unevenness caused by differences in write polarity.

[0103] An electro-optical device according to a specific aspect 7 of aspect 6 further includes a NOT circuit arranged in one-to-one correspondence with the plurality of data lines, and a selection signal supplied to one of the k selection signal lines is supplied to a gate node of an N-channel transistor in the first switching element corresponding to one of the plurality of data lines, and the NOT circuit corresponding to the one data line inverts the logical level of the selection signal supplied to the one selection signal line and supplies it to the gate node of the P-channel transistor in the first switching element corresponding to the one data line and to an inverted selection signal line paired with the one selection signal line.

[0104] An electronic device according to an eighth aspect includes the electro-optical device according to any one of the first to seventh aspects. [Explanation of symbols]

[0105] 1...projection display device, 30...display control circuit, 100...electro-optical device, 110...pixel circuit, 118...pixel electrode, 120...liquid crystal element, 180...selection signal line, 181...inverted selection signal line, N1, P1...transistor, Trs...transmission gate, Iv1, Iv5, Iv11...NOT circuit, Mw11 to Nw13, Mw21 to N27, Nw31 to Nw41, Nw51 to Nw56...wiring.

Claims

1. a plurality of data lines including grouped k (k is an integer of 2 or more) data lines; data signal lines to which data signals corresponding to the gradations of pixels are supplied in a time-division manner in correspondence with the k data lines; k selection signal lines each supplied with a selection signal; k inverted selection signal lines that are paired with the k selection signal lines and that are supplied with inverted selection signals of the selection signals; a first switching element provided in one-to-one correspondence with the plurality of data lines, the first switching element being turned on or off in response to a selection signal supplied to one of the k selection signal lines between the data signal line and the one data line; a constant potential wiring that overlaps the k selection signal lines and the k inverted selection signal lines in a plan view and is maintained at a predetermined potential; An electro-optical device comprising:

2. The constant potential wiring is It has light-blocking properties, The display area where multiple pixel circuits are arranged is enclosed in a plan view. The electro-optical device according to claim 1 .

3. further having scan lines; The pixel circuit a second switching element, an electro-optical element, and a storage capacitor; The second switching element is Between the data line and one end of the electro-optical element, the state is turned on or off depending on the potential of the scanning line, The electro-optical element is The optical characteristics are determined according to the voltages at the one end and the other end, The storage capacity is maintaining a voltage at the one end of the electro-optical element; The constant potential wiring and the other end of the storage capacitor are electrically connected. The electro-optical device according to claim 2 .

4. The first switching element is It is a P-channel transistor or an N-channel transistor. The electro-optical device according to claim 1 .

5. further including NOT circuits provided in one-to-one correspondence with the plurality of data lines; The first switching element is The N-channel transistor, The NOT circuit corresponding to one of the plurality of data lines is inverting a logic level of an inverted selection signal supplied to one of the k inverted selection signal lines; The gate node of the N-channel transistor is A merged signal of the inverted signal supplied to one selection signal line paired with the one inverted selection signal line and the output signal of the NOT circuit corresponding to the one data line is supplied. The electro-optical device according to claim 1 .

6. The first switching element is It is a transmission gate that combines P-channel transistors and N-channel transistors. The electro-optical device according to claim 1 .

7. further including NOT circuits provided in one-to-one correspondence with the plurality of data lines; The gate node of the N-channel transistor of the first switching element corresponding to one of the plurality of data lines is A selection signal is supplied to one of the k selection signal lines, The NOT circuit corresponding to the one data line is a logic level of the selection signal supplied to the one selection signal line is inverted and supplied to a gate node of a P-channel transistor in the first switching element corresponding to the one data line and to an inverted selection signal line paired with the one selection signal line; 7. The electro-optical device according to claim 6.

8. 8. An electronic device comprising the electro-optical device according to claim 1.

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