Method of manufacturing semiconductor device and semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device capable of mixedly mounting one kind of LDMOS transistor and other transistors.SOLUTION: A method of manufacturing a semiconductor device includes a step of preparing a semiconductor substrate having an upper surface including a first portion and a second portion, a step of forming, on the upper surface, an insulating film having a thin film portion located on the first portion and a thick film portion located on the second portion and thicker than the thin film portion, and a step of patterning the insulating film to form a first gate insulating film of a first transistor including the thin film portion and the thick film portion and a second gate insulating film of a second transistor including the thick film portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] The semiconductor device described in JP 2022-186304 A (Patent Document 1) has a semiconductor substrate, a gate insulating film, and a gate electrode. The semiconductor substrate has an upper surface. A body layer, a source layer surrounded by the body layer, a drift layer in contact with the body layer, and a drain layer surrounded by the drift layer are formed within the semiconductor substrate. The gate insulating film has a thin film portion and a thick film portion. The thin film portion faces the body layer located between the source layer and the drift layer. The thick film portion faces the drift layer located between the body layer and the drain layer. The gate electrode is formed on the thin film portion and the thick film portion. The body layer, source layer, drift layer, drain layer, gate insulating film, and gate electrode constitute an LDMOS (Laterally Diffused Metal Oxide Transistor) transistor. The LDMOS transistor is turned on by applying a voltage to the gate electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-186304 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device, one type of LDMOS transistor may be mounted together with other types of transistors. The manufacturing process of the semiconductor device described in Patent Document 1 requires an additional manufacturing step for forming a field plate portion, which increases manufacturing costs. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of: preparing a semiconductor substrate having an upper surface including a first portion and a second portion; forming an insulating film on the upper surface, the insulating film having a thin film portion located on the first portion and a thick film portion located on the second portion and thicker than the thin film portion; and patterning the insulating film to form a first gate insulating film of a first transistor including the thin film portion and the thick film portion and a second gate insulating film of a second transistor including the thick film portion. The first transistor has a first body layer formed on the upper surface within the semiconductor substrate, a first source layer formed on the upper surface within the semiconductor substrate so as to be surrounded by the first body layer, a first drift layer formed on the upper surface within the semiconductor substrate so as to be in contact with the first body layer, and a first drain layer formed on the upper surface within the semiconductor substrate so as to be surrounded by the first drift layer. The thin film portion included in the first gate insulating film faces the first body layer located between the first source layer and the first drift layer. The thick film portion included in the first gate insulating film faces the first drift layer located between the first body layer and the first drain layer. [Effects of the Invention]

[0006] According to the method for manufacturing a semiconductor device of the present disclosure, it is possible to realize the mixed mounting of one type of LDMOS transistor and other transistors at low cost. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a cross-sectional view of the semiconductor device DEV1. [Figure 2]10A to 10C are manufacturing process diagrams of the semiconductor device DEV1. [Figure 3] FIG. 10 is a cross-sectional view illustrating an element isolation film forming step S2. [Figure 4] FIG. 10 is a cross-sectional view illustrating an ion implantation step S3. [Figure 5] FIG. 10 is a cross-sectional view illustrating a thermal oxidation step S41. [Figure 6] FIG. 10 is a cross-sectional view illustrating an insulating film removing step S42. [Figure 7] FIG. 10 is a cross-sectional view illustrating a thermal oxidation step S43. [Figure 8] FIG. 10 is a cross-sectional view illustrating a gate electrode forming step S5. [Figure 9] FIG. 10 is a cross-sectional view illustrating an ion implantation step S6. [Figure 10] FIG. 10 is a cross-sectional view illustrating a sidewall spacer forming step S7. [Figure 11] FIG. 10 is a cross-sectional view of a semiconductor device DEV1 according to a first modification. [Figure 12] 10A to 10C are diagrams illustrating the manufacturing process of the semiconductor device DEV1 according to the first modification. [Figure 13] FIG. 10 is a cross-sectional view illustrating an amorphous layer forming step S44. [Figure 14] FIG. 10 is a cross-sectional view illustrating a thermal oxidation step S45. [Figure 15] FIG. 2 is a cross-sectional view of the semiconductor device DEV2. DETAILED DESCRIPTION OF THE INVENTION

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0010] <Configuration of semiconductor device DEV1> As shown in FIG. 1, the semiconductor device DEV1 has a semiconductor substrate SUB, a gate insulating film GI1, a gate insulating film GI2, a gate electrode GE1, a gate electrode GE2, an element isolation film ISL, a sidewall spacer SWS1, and a sidewall spacer SWS2.

[0011] The semiconductor substrate SUB is made of, for example, single crystal silicon. The semiconductor substrate SUB has an upper surface F1 and a lower surface F2 located on the opposite side of the upper surface F1. The semiconductor substrate SUB has a body layer BL1, a source layer SL1, a drift layer DRL1, a drain layer DRA1, and a back gate layer BG1. The conductivity types of the body layer BL1 and the back gate layer BG1 are opposite to the conductivity types of the source layer SL1, the drift layer DRL1, and the drain layer DRA1.

[0012] The body layer BL1 is formed on the upper surface F1 in the semiconductor substrate SUB. The source layer SL1 is formed on the upper surface F1 in the semiconductor substrate SUB so as to be surrounded by the body layer BL1. The source layer SL1 has a first portion SL1a and a second portion SL1b. The first portion SL1a is located between the second portion SL1b and the drain layer DRA1. The dopant concentration in the first portion SL1a is lower than the dopant concentration in the second portion SL1b. That is, the source layer SL1 has an LDD (Lightly Doped Diffusion) structure. The drift layer DRL1 is formed on the upper surface F1 in the semiconductor substrate SUB so as to be in contact with the body layer BL1. The drain layer DRA1 is formed on the upper surface F1 in the semiconductor substrate SUB so as to be surrounded by the drift layer DRL1. The dopant concentration in the drift layer DRL1 is lower than the dopant concentrations in the source layer SL1 and the drain layer DRA1. The back gate layer BG1 is formed on the upper surface F1 so as to be surrounded by the body layer BL1.

[0013] The semiconductor substrate SUB also has a source layer SL2, a drain layer DRA2, and a well layer WE1. The conductivity types of the source layer SL2 and the drain layer DRA2 are opposite to the conductivity type of the well layer WE1.

[0014] The source layer SL2 and the drain layer DRA2 are formed on the upper surface F1 in the semiconductor substrate SUB. The drain layer DRA2 is spaced apart from the source layer SL2. The source layer SL2 has a first portion SL2a and a second portion SL2b. The first portion SL2a is located between the second portion SL2b and the drain layer DRA2. The dopant concentration in the first portion SL2a is lower than the dopant concentration in the second portion SL2b. That is, the source layer SL2 has an LDD structure. The drain layer DRA2 has a first portion DRA2a and a second portion DRA2b. The first portion DRA2a is located between the second portion DRA2b and the source layer SL2. The dopant concentration in the first portion DRA2a is lower than the dopant concentration in the second portion DRA2b. That is, the drain layer DRA2 has an LDD structure. The well layer WE1 is formed on the upper surface F1 in the semiconductor substrate SUB so as to surround the source layer SL2 and the drain layer DRA2.

[0015] The gate insulating film GI1 is formed on the upper surface F1. The gate insulating film GI1 is formed of, for example, silicon oxide. The gate insulating film GI1 has a thin film portion GI1a and a thick film portion GI1b. The thick film portion GI1b is thicker than the thin film portion GI1a. The thickness of the thick film portion GI1b is, for example, greater than the thickness of the thin film portion GI1a and equal to or less than twice the thickness of the thin film portion GI1a. The thin film portion GI1a faces the body layer BL1 located between the source layer SL1 and the drift layer DRL1. The thin film portion GI1a may further face the drift layer DRL1 located between the body layer BL1 and the drain layer DRA1. The thick film portion GI1b faces the drift layer DRL1 located between the body layer BL1 and the drain layer DRA1.

[0016] The gate electrode GE1 is disposed on the gate insulating film GI1. The gate electrode GE1 is formed of, for example, polycrystalline silicon containing a dopant. The body layer BL1, the source layer SL1, the drift layer DRL1, the drain layer DRA1, the gate insulating film GI1, and the gate electrode GE1 form a first transistor. The first transistor is an LDMOS transistor.

[0017] The gate insulating film GI2 is formed on the upper surface F1. The gate insulating film GI2 faces the well layer WE1 located between the source layer SL2 and the drain layer DRA2. The gate insulating film GI2 is formed of, for example, silicon oxide. The thickness of the gate insulating film GI2 is the same as the thickness of the thick film portion GI1b. Note that if the thickness of the gate insulating film GI2 is within a range of ±5 percent with respect to the thickness of the thick film portion GI1b, the thickness of the gate insulating film GI2 can be considered to be the same as the thickness of the thick film portion GI1b. The gate electrode GE2 is formed on the gate insulating film GI2. The gate electrode GE2 is formed of, for example, polycrystalline silicon containing a dopant. The source layer SL2, the drain layer DRA2, the well layer WE1, the gate insulating film GI2, and the gate electrode GE2 form a second transistor. The second transistor is an NMOS (N-type Metal Oxide Semiconductor) transistor or a PMOS (P-type Metal Oxide Semiconductor) transistor.

[0018] A trench TR is formed in the upper surface F1. The trench TR extends from the upper surface F1 toward the lower surface F2. An element isolation film ISL is formed in the trench TR. The element isolation film ISL is made of, for example, silicon oxide. The first transistor is surrounded by the element isolation film ISL in a plan view, and is thereby insulated and isolated from other elements. Similarly, the second transistor is surrounded by the element isolation film ISL in a plan view, and is thereby insulated and isolated from other elements.

[0019] The sidewall spacers SWS1 are formed on both side surfaces of the gate electrode GE1. More specifically, the sidewall spacers SWS1 are formed on the first portion SL1a and the drift layer DRI1. The sidewall spacers SWS1 are formed of, for example, silicon nitride. The sidewall spacers SWS2 are formed on both side surfaces of the gate electrode GE2. More specifically, the sidewall spacers SWS2 are formed on the first portion SL2a and the first portion DRA2a. The sidewall spacers SWS2 are formed of, for example, silicon nitride.

[0020] <Method of Manufacturing Semiconductor Device DEV1> As shown in FIG. 2, the manufacturing method of the semiconductor device DEV1 includes a preparation step S1, an element isolation film formation step S2, an ion implantation step S3, an insulating film formation step S4, a gate electrode formation step S5, an ion implantation step S6, a sidewall spacer formation step S7, and an ion implantation step S8.

[0021] In the preparation step S1, a semiconductor substrate SUB is prepared. After the preparation step S1, an element isolation film formation step S2 is performed.

[0022] As shown in FIG. 3, in the element isolation film forming step S2, the element isolation film ISL is formed. In the element isolation film forming step S2, first, a trench TR is formed in the upper surface F1. The trench TR is formed by dry etching the upper surface F1 using a hard mask formed on the upper surface F1 as a mask. Second, a constituent material of the element isolation film ISL is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method so as to fill the trench TR. Third, the constituent material of the element isolation film ISL formed outside the trench TR is removed by a CMP (Chemical Mechanical Polishing) method or etch-back. Through the above steps, the element isolation film ISL is formed in the trench TR. After the element isolation film forming step S2, an ion implantation step S3 is performed.

[0023] 4, in the ion implantation step S3, a body layer BL1 is formed in the first portion F1a and a drift layer DRL1 is formed in the second portion F1b in the semiconductor substrate SUB by ion implantation. However, the boundary between the body layer BL1 and the drift layer DRL1 is located in the first portion F1a. Furthermore, in the ion implantation step S3, a well layer WE1 is formed in the second portion F1b in the semiconductor substrate SUB by ion implantation. After the ion implantation step S3, an insulating film formation step S4 is performed.

[0024] In the insulating film forming step S4, an insulating film IF is formed. As shown in FIG. 2, the insulating film forming step S4 includes a thermal oxidation step S41, an insulating film removing step S42, and a thermal oxidation step S43. The upper surface F1 includes a first portion F1a and a second portion F1b. In the semiconductor substrate SUB, a body layer BL1 is formed in the first portion F1a, and a drift layer DRI1 and a well layer WE1 are formed in the second portion F1b. The boundary between the body layer BL1 and the drift layer DRI1 is located in the first portion F1a.

[0025] As shown in FIG. 5, in the thermal oxidation step S41, an insulating film IFab is formed on the upper surface F1 by thermal oxidation. After the thermal oxidation step S41, an insulating film removal step S42 is performed. As shown in FIG. 6, in the insulating film removal step S42, dry etching is performed using a resist pattern formed on the insulating film IFab and having an opening that exposes the first portion F1a as a mask, thereby removing the insulating film IFab located on the first portion F1a. As a result, the body layer BL1 and a portion of the drift layer DRI1 in contact with the body layer BL1 are exposed from the insulating film IFab. After the insulating film removal step S42, a thermal oxidation step S43 is performed. As shown in FIG. 7, in the thermal oxidation step S43, a thin film portion IFb is formed on the first portion F1a by thermal oxidation. Furthermore, in the thermal oxidation step S43, the insulating film IFab located on the second portion F1b grows by thermal oxidation, thereby forming a thick film portion IFc. In this way, in the insulating film forming step S4, an insulating film IF having a thin film portion IFb located on the first portion F1a and a thick film portion IFc located on the second portion F1b is formed. After the insulating film forming step S4, a gate electrode forming step S5 is performed.

[0026] As shown in FIG. 8, in the gate electrode formation process S5, gate electrodes GE1 and GE2 are formed on the insulating film IF. In the gate electrode formation process S5, first, the constituent materials of the gate electrodes GE1 and GE2 are deposited on the insulating film IF by, for example, CVD. Second, the constituent materials of the gate electrodes GE1 and GE2 are patterned by dry etching using a resist pattern formed on the constituent materials of the gate electrodes GE1 and GE2 as a mask. As a result, the gate electrode GE1 is formed on the thin film portion IFb and the thick film portion IFc, and the gate electrode GE2 is formed on the thick film portion IFc. During the dry etching, the insulating film IF located other than under the gate electrode GE1 and the gate electrode GE2 is also removed. Therefore, in the gate electrode formation process S5, the insulating film IF is patterned to form a gate insulating film GI1 including the thin film portion IFb and the thick film portion IFc and a gate insulating film GI2 including only the thick film portion IFc. After the insulating film formation process S4, an ion implantation process S6 is performed.

[0027] 9, in the ion implantation step S6, a first portion SL1a of the source layer SL1, a first portion SL2a of the source layer SL2, and a first portion DRA2a of the drain layer DRA2 are formed by ion implantation. After the ion implantation step S6, a sidewall spacer formation step S7 is performed.

[0028] 10, in the sidewall spacer formation step S7, sidewall spacers SWS1 are formed on both side surfaces of the gate electrode GE1, and sidewall spacers SWS2 are formed on both side surfaces of the gate electrode GE2. In the sidewall spacer formation step S7, first, the constituent material of the sidewall spacers SWS1 and SWS2 is deposited on the upper surface F1 so as to cover the gate electrode GE2, for example, by CVD. Second, the constituent material of the sidewall spacers SWS1 and SWS2 is etched back. Through the above steps, the sidewall spacers SWS1 and SWS2 are formed. After the sidewall spacer formation step S7, an ion implantation step S8 is performed.

[0029] In the ion implantation step S8, the second portion SL1b of the source layer SL1, the drain layer DRA1, the back gate layer BG1, the second portion SL2b of the source layer SL2, and the second portion DRA2b of the drain layer DRA2 are formed by ion implantation. In this way, the structure of the semiconductor device DEV1 shown in FIG. 1 is formed.

[0030] <Effects of semiconductor device DEV1> In the semiconductor device DEV1, the gate insulating film GI1 (thin film portion GI1a) facing the body layer BL1 located between the source layer SL1 and the drift layer DRL1 is thinner than the gate insulating film GI1 (thick film portion GI1b) facing the drift layer DRL1 located between the body layer BL1 and the drain layer DRA1, thereby reducing the on-resistance of the first transistor. Furthermore, the thick film portion GI1b is thicker than the thin film portion GI1a, and the gate electrode GE1 located on the thick film portion GI1b acts as a field plate, thereby improving the off-state breakdown voltage of the first transistor. In this way, the off-state breakdown voltage of the first transistor can be improved while reducing the on-state resistance of the first transistor.

[0031] The semiconductor device DEV1 includes a second transistor in addition to the first transistor. According to the manufacturing method of the semiconductor device DEV1, the thick film portion GI1b can be formed by utilizing the process for forming the gate insulating film GI2 of the second transistor, so there is no need to add a new process for forming the thick film portion GI1b, and the manufacturing process can be simplified.

[0032] <Variation 1> As shown in FIG. 11 , the second transistor does not have to be an NMOS transistor or a PMOS transistor, but may be an LDMOS transistor. More specifically, the semiconductor substrate SUB does not have a well layer WE1, but has a body layer BL2, a drift layer DRL2, and a back gate layer BG2. The body layer BL2 is formed on the upper surface F1 so as to surround the source layer SL2. The drift layer DRL2 is formed on the upper surface F1 in contact with the body layer BL2 and so as to surround the drain layer DRA2. The gate insulating film GI2 faces the body layer BL2 located between the source layer SL2 and the drift layer DRL2 and the drift layer DRL2 located between the body layer BL2 and the drain layer DRA2. The thickness of the gate insulating film GI2 located on the body layer BL2 is greater than the thickness of the gate insulating film GI1 located on the body layer BL1. Therefore, the semiconductor device DEV1 has multiple types of LDMOS transistors (first transistors and second transistors) whose gate insulating films located on the body layers have different thicknesses.

[0033] Since the gate insulating film GI2 is thicker than the thin film portion GI1a, the second transistor has a higher dielectric strength voltage than the first transistor. In this way, the semiconductor device DEV1 can incorporate multiple types of LDMOS transistors with different reliability characteristics. For example, the first transistor is used to reduce the on-resistance of the first transistor and reduce the device area. The second transistor is used to improve the life of the second transistor. In this case, the well layer WE1 is not formed in the ion implantation step S3, and a body layer BL2 and a drift layer DRL2 are formed in addition to the body layer BL1 and the drift layer DRL1.

[0034] <Variation 2> As shown in Fig. 12, the insulating film forming step S4 may include an amorphous layer forming step S44 and a thermal oxidation step S45. As shown in Fig. 13, in the amorphous layer forming step S44, ions are implanted into the second portion F1b to amorphize the second portion F1b, thereby forming an amorphous layer AMO in the semiconductor substrate SUB. The ion implantation may involve implanting, for example, silicon, argon, fluorine, or nitrogen. The amorphous layer forming step S44 is followed by a thermal oxidation step S45.

[0035] Because the amorphous layer AMO is formed, the crystal structure of the second portion F1b is disturbed. Therefore, as shown in FIG. 14 , thermal oxidation causes the insulating film IF to grow faster on the second portion F1b than on the first portion F1a, and an insulating film IF having a thin film portion IFb located on the first portion F1a and a thick film portion IFc located on the second portion F1b is formed on the upper surface F1. In this case, as a result of ion implantation into the second portion F1b, the thick film portion IFc (thick film portion GI1b and gate insulating film GI2) may contain argon, fluorine, or nitrogen. Furthermore, the ions implanted by the ion implantation remain in the semiconductor substrate SUB. If the ions implanted into the semiconductor substrate SUB are nitrogen or fluorine, the ions implanted into the semiconductor substrate SUB suppress the diffusion of dopants in the semiconductor substrate SUB, thereby improving the characteristics and reliability of the transistor.

[0036] (Second embodiment) A semiconductor device DEV2 according to the second embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV1, and overlapping descriptions will not be repeated.

[0037] <Configuration of semiconductor device DEV2> 15, in the semiconductor device DEV2, the semiconductor substrate SUB further includes a source layer SL3, a drain layer DRA3, and a well layer WE2. The source layer SL3 and the drain layer DRA3 are formed on an upper surface F1 in the semiconductor substrate SUB. The drain layer DRA3 is spaced apart from the source layer SL3.

[0038] The source layer SL3 has a first portion SL3a and a second portion SL3b. The first portion SL3a is located between the second portion SL3b and the drain layer DRA3. The dopant concentration in the first portion SL3a is lower than the dopant concentration in the second portion SL3b. That is, the source layer SL3 has an LDD structure. The drain layer DRA3 has a first portion DRA3a and a second portion DRA3b. The first portion DRA3a is located between the second portion DRA3b and the source layer SL3. The dopant concentration in the first portion DRA3a is lower than the dopant concentration in the second portion DRA3b. That is, the drain layer DRA3 has an LDD structure.

[0039] The well layer WE2 is formed on the upper surface F1 in the semiconductor substrate SUB so as to surround the source layer SL3 and the drain layer DRA3. The conductivity type of the well layer WE2 is opposite to that of the source layer SL3 and the drain layer DRA3.

[0040] The semiconductor device DEV2 further includes a gate insulating film GI3, a gate electrode GE3, and a sidewall spacer SWS3. The gate insulating film GI3 is formed on the upper surface F1. The gate insulating film GI3 faces the well layer WE2 located between the source layer SL3 and the drain layer DRA3. The gate insulating film GI3 is formed of, for example, silicon oxide. The thickness of the gate insulating film GI3 is the same as the thickness of the thin film portion GI1a. Note that if the thickness of the gate insulating film GI3 is within a range of ±5 percent with respect to the thickness of the thin film portion GI1a, the thickness of the gate insulating film GI3 can be considered to be the same as the thickness of the thin film portion GI1a.

[0041] The gate electrode GE3 is formed on the gate insulating film GI3. The gate electrode GE3 is formed of, for example, polycrystalline silicon containing a dopant. The source layer SL3, the drain layer DRA3, the well layer WE2, the gate insulating film GI3, and the gate electrode GE3 form a third transistor. The third transistor is an NMOS transistor or a PMOS transistor. Note that, since the gate insulating film GI3 is thinner than the gate insulating film GI2, the operating speed of the third transistor is faster than the operating speed of the second transistor.

[0042] The sidewall spacers SWS3 are formed on both side surfaces of the gate electrode GE3. More specifically, the sidewall spacers SWS3 are formed on the first portions SL3a and DRA3a. The sidewall spacers SWS2 are made of, for example, silicon nitride. Note that the third transistor is also surrounded by an element isolation film ISL in plan view, and is therefore insulated and isolated from other elements.

[0043] <Method of manufacturing semiconductor device DEV2> In the manufacturing method of the semiconductor device DEV2, in the ion implantation step S3, in addition to the source layer SL1, the drift layer DRL1, and the well layer WE1, a well layer WE2 is formed. In the manufacturing method of the semiconductor device DEV2, in the gate electrode formation step S5, in addition to the gate electrodes GE1 and GE2, a gate electrode GE3 is formed. In the gate electrode formation step S5, when the gate electrodes GE1, GE2, and GE3 are formed, the insulating film IF is patterned to form the gate insulating films GI1, GI2, and GI3.

[0044] In the manufacturing method of the semiconductor device DEV2, in the ion implantation step S6, in addition to the first portion SL1a of the source layer SL1, the first portion SL2a of the source layer SL2, and the first portion DRA2a of the drain layer DRA2, a first portion SL3a of the source layer SL3 and a first portion DRA3a of the drain layer DRA3 are formed. Also, in the manufacturing method of the semiconductor device DEV2, in the sidewall spacer formation step S7, in addition to the sidewall spacers SWS1 and SWS2, a sidewall spacer SWS3 is formed. In the manufacturing method of the semiconductor device DEV2, in the ion implantation step S8, in addition to the second portion SL1b of the source layer SL1, the drain layer DRA1, the back gate layer BG1, the second portion SL2b of the source layer SL2, and the second portion DRA2b of the drain layer DRA2, a second portion SL3b of the source layer SL3 and a second portion DRA3b of the drain layer DRA3 are formed.

[0045] <Effects of semiconductor device DEV2> The semiconductor device DEV2 includes a third transistor in addition to the first and second transistors. According to the manufacturing method of the semiconductor device DEV2, the gate insulating film GI3 can be formed by utilizing the process for forming the thin film portion GI1a, so there is no need to add a new process for forming the gate insulating film GI3, and the manufacturing process can be simplified.

[0046] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0047] AMO amorphous layer, BG1, BG2 back gate layers, BL1, BL2 body layers, DEV1, DEV2 semiconductor device, DRA1 drain layer, DRA2 drain layer, DRA2a first portion, DRA2b second portion, DRA2 drain layer, DRA3a first portion, DRA3b second portion, DRL1, DRL2 drift layers, F1 upper surface, F1a first portion, F1b second portion, F2 lower surface, GE1, GE2, GE3 gate electrode, GI1 gate insulating film, GI1a thin film portion, GI1b thick film portion, GI2, GI3 gate insulating film, IF, IFa insulating film, IFb thin film portion, IFc thick film portion, ISL element isolation film, S1 preparation step, S2 element isolation film formation step, S3 ion implantation step, S4 insulating film formation step, S41 thermal oxidation step, S42 insulating film removal step, S43 Thermal oxidation step, S44 amorphous layer formation step, S45 thermal oxidation step, S5 gate electrode formation step, S6 ion implantation step, S7 sidewall spacer formation step, S8 ion implantation step, SL1 source layer, SL1a first portion, SR1b second portion, SL2 source layer, SL2a first portion, SL2b second portion, SL3 source layer, SL3a first portion, SL3b second portion, SUB semiconductor substrate, SWS1, SWS2, SWS3 sidewall spacers, TR trench, WE1, WE2 well layer.

Claims

1. providing a semiconductor substrate having an upper surface including a first portion and a second portion; forming an insulating film on the upper surface, the insulating film having a thin film portion located on the first portion and a thick film portion located on the second portion and thicker than the thin film portion; and forming a first gate insulating film of a first transistor including the thin film portion and the thick film portion and a second gate insulating film of a second transistor including the thick film portion by patterning the insulating film, The first transistor is a first body layer formed on the upper surface within the semiconductor substrate; a first source layer formed on the upper surface of the semiconductor substrate and surrounded by the first body layer; a first drift layer formed on the upper surface of the semiconductor substrate so as to be in contact with the first body layer; a first drain layer formed on the upper surface of the semiconductor substrate so as to be surrounded by the first drift layer, the thin film portion included in the first gate insulating film faces the first body layer located between the first source layer and the first drift layer, the thick film portion included in the first gate insulating film faces the first drift layer located between the first body layer and the first drain layer.

2. The second transistor is a second source layer formed on the upper surface within the semiconductor substrate; a second drain layer formed on the upper surface of the semiconductor substrate so as to be spaced apart from the second source layer; a first well layer formed on the upper surface of the semiconductor substrate so as to surround the second source layer and the second drain layer; 2. The method for manufacturing a semiconductor device according to claim 1, wherein said second gate insulating film faces said first well layer located between said second source layer and said second drain layer.

3. The second transistor is a second body layer formed on the upper surface within the semiconductor substrate; a second source layer formed on the upper surface of the semiconductor substrate so as to be surrounded by the second body layer; a second drift layer formed on the upper surface of the semiconductor substrate so as to be in contact with the second body layer, and a second drain layer formed on the upper surface of the semiconductor substrate so as to be surrounded by the second drift layer, 2. The method for manufacturing a semiconductor device according to claim 1, wherein the second gate insulating film faces the second body layer located between the second source layer and the second drift layer and the second drift layer located between the second body layer and the second drain layer.

4. The step of forming the insulating film includes: forming a base insulating film on the upper surface; removing the base insulating film located on the first portion; 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming the thin film portion on the first portion and growing the underlying insulating film located on the second portion to form the thick film portion.

5. The formation of the base insulating film is carried out by thermal oxidation, 5. The method for manufacturing a semiconductor device according to claim 4, wherein the formation of the thin film portion on the first portion and the growth of the underlying insulating film on the second portion are performed by thermal oxidation.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed by making the growth rate of the insulating film on the second portion higher than the growth rate of the insulating film on the first portion.

7. The method further includes, before the step of forming the insulating film, forming an amorphous layer in the second portion in the semiconductor substrate; 7. The method for manufacturing a semiconductor device according to claim 6, wherein said insulating film is formed by thermal oxidation.

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the amorphous layer is formed by ion implantation.

9. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first gate insulating film, the second gate insulating film, and a third gate insulating film of a third transistor including the thin film portion are formed by patterning the insulating film.

10. The third transistor is a third source layer formed on the upper surface within the semiconductor substrate; a third drain layer formed on the upper surface of the semiconductor substrate so as to be spaced apart from the third source layer; a second well layer formed on the upper surface of the semiconductor substrate so as to surround the third source layer and the third drain layer, 10. The method for manufacturing a semiconductor device according to claim 9, wherein said third gate insulating film faces said second well layer located between said third source layer and said third drain layer.

11. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of said thick film portion is greater than the thickness of said thin film portion and is not more than twice the thickness of said thin film portion.

12. a semiconductor substrate having an upper surface; a first gate insulating film of a first transistor formed on the upper surface and having a thin film portion and a thick film portion thicker than the thin film portion; a second gate insulating film of a second transistor formed on the upper surface and having the same thickness as the thick film portion; The first transistor is a first body layer formed on the upper surface within the semiconductor substrate; a first source layer formed on the upper surface of the semiconductor substrate and surrounded by the first body layer; a first drift layer formed on the upper surface of the semiconductor substrate so as to be in contact with the first body layer; a first drain layer formed on the upper surface of the semiconductor substrate so as to be surrounded by the first drift layer, the thin film portion faces the first body layer located between the first source layer and the first drift layer; the thick film portion faces the first drift layer located between the first body layer and the first drain layer.

13. The second transistor is a second source layer formed on the upper surface within the semiconductor substrate; a second drain layer formed on the upper surface of the semiconductor substrate so as to be spaced apart from the second source layer; a first well layer formed on the upper surface of the semiconductor substrate so as to surround the second source layer and the second drain layer; 13. The semiconductor device according to claim 12, wherein said second gate insulating film faces said first well layer located between said second source layer and said second drain layer.

14. The second transistor is a second body layer formed on the upper surface within the semiconductor substrate; a second source layer formed on the upper surface of the semiconductor substrate so as to be surrounded by the second body layer; a second drift layer formed on the upper surface of the semiconductor substrate so as to be in contact with the second body layer; a second drain layer formed on the upper surface of the semiconductor substrate so as to be surrounded by the second drift layer, 13. The semiconductor device according to claim 12, wherein the second gate insulating film faces the second body layer located between the second source layer and the second drift layer and the second drift layer located between the second body layer and the second drain layer.

15. The semiconductor device according to claim 12 , further comprising a third gate insulating film of a third transistor formed on said upper surface and having the same thickness as said thin film portion.

16. The third transistor is a third source layer formed on the upper surface of the semiconductor substrate; and a third drain layer formed on the upper surface of the semiconductor substrate so as to be spaced apart from the third source layer; a second well layer formed on the upper surface of the semiconductor substrate so as to surround the third source layer and the third drain layer, 16. The semiconductor device according to claim 15, wherein said third gate insulating film faces said second well layer located between said third source layer and said third drain layer.

17. 13. The semiconductor device according to claim 12, wherein the thickness of said thick film portion is greater than the thickness of said thin film portion and is equal to or less than twice the thickness of said thin film portion.

18. 13. The semiconductor device according to claim 12, wherein said thick film portion and said second gate insulating film contain at least one of argon, fluorine, and nitrogen.

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