Semiconductor circuit and step-down dc / dc converter

Abstract

To provide a semiconductor circuit which is resistant to noise of a power supply voltage and can achieve more appropriate operation.SOLUTION: The circuit 10 has a low pass filter 100 for filtering a power source voltage and transistors MP1 and MP2. A voltage generated by filtering the power source voltage by the low pass filter 100 is supplied to the back gate terminals of the transistors MP1 and MP2. The voltage generated without being filtered by the low pass filter 100 is supplied to the source terminals of the transistors MP1 and MP2.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor circuit and a step-down DC / DC converter. [Background technology]

[0002] Metal oxide semiconductor (MOS) transistors are used in various electronic components such as operational amplifiers and comparators. Semiconductor circuits including such electronic components are used in, for example, DC / DC converters.

[0003] For example, Patent Document 1 discloses a step-down DC / DC converter that includes an error amplifier that generates an error signal corresponding to the error between the electrical state of the step-down DC / DC converter and its target state, a clamp circuit that clamps the error signal using a clamp voltage, and a pulse width modulation comparator (hereinafter simply referred to as "comparator") that compares the error signal clamped by the clamp circuit with a ramp voltage.

[0004] In the technology described in Patent Document 1, a logic circuit generates a pulse signal in response to a pulse width modulation signal generated by a comparator, and a driver uses the pulse signal to drive a high-side transistor and a low-side transistor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2024-53910

[0006] [overview] However, the present inventors have come to recognize the following problem. In the technology described in Patent Document 1, a common power supply voltage is supplied to the driver and the comparator. When the driver operates, noise may occur in the power supply voltage, and this noise affects the operation of the comparator. More specifically, noise occurs in the power supply voltage input to the back gate terminal of the P-channel MOS transistor inside the comparator, and this noise is transmitted to the gate terminal of the MOS transistor. As a result, malfunctions occur in the operation of the comparator.

[0007] One possible solution is to filter the power supply voltage with a low-pass filter and supply the resulting filtered voltage to the comparator. However, the filtered voltage is lower than the power supply voltage because it is the power supply voltage that is stepped down by the low-pass filter. Therefore, if only the filtered voltage is used, a sufficiently large current cannot be passed through the transistors in the comparator, making it difficult to achieve high-speed operation of the comparator.

[0008] The present disclosure has been made in light of these circumstances, and one of its exemplary purposes is to provide a semiconductor circuit that is resistant to noise in the power supply voltage and can achieve more appropriate operation.

[0009] A semiconductor circuit according to an embodiment of the present disclosure includes a low-pass filter that filters a power supply voltage and a MOS transistor. A voltage generated by filtering the power supply voltage through the low-pass filter is supplied to a back gate terminal of the MOS transistor. A voltage generated without being filtered by the low-pass filter is supplied to a source terminal of the MOS transistor.

[0010] Any combination of the above components and conversion of the expressions of the present disclosure into methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0011] [Figure 1]FIG. 1 is a block diagram of a DC / DC converter according to a first embodiment. [Figure 2] FIG. 2 is a block diagram of a comparator according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view illustrating an example of the layout of a P-channel MOS transistor and an N-channel MOS transistor according to the embodiment. [Figure 4] FIG. 4 is a top view of a semiconductor substrate showing an example of a layout of a transistor according to the embodiment. [Figure 5] FIG. 5 is a block diagram for explaining the influence of the power supply voltage on the DC / DC converter according to the first comparative technique. [Figure 6] FIG. 6 is a diagram for explaining the power supplied to the error amplifier and the comparator in the analog block according to the comparative technique 2. In FIG. [Figure 7] FIG. 7 is a diagram for explaining the influence of noise on the power supply voltage in the comparator according to the comparative technique 2. In FIG. [Figure 8] FIG. 8 is a cross-sectional view showing the layout of a transistor according to the second comparative technique. [Figure 9] FIG. 9 is a timing chart showing the results of simulating the ramp voltage, power supply voltage, and high-side gate signal in the DC / DC converter according to the second comparative technique. [Figure 10] FIG. 10 is a timing chart showing the simulation results of the gate signals generated by the drivers of the other channels, the power supply voltage, and the high-side gate signal of the DC / DC converter according to the comparative technique 2. In FIG. [Figure 11] FIG. 11 is a timing chart showing the results of simulating the ramp voltage, power supply voltage, voltage generated by filtering, and high-side gate signal in the DC / DC converter according to the first embodiment. [Figure 12] FIG. 12 is a circuit diagram of a delay circuit according to the second embodiment.

[0012] [Detailed explanation] (overview) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0013] A semiconductor circuit according to one embodiment includes a low-pass filter that filters a power supply voltage and a MOS transistor. A voltage generated by filtering the power supply voltage through the low-pass filter is supplied to a back gate terminal of the MOS transistor. A voltage generated without being filtered by the low-pass filter is supplied to a source terminal of the MOS transistor.

[0014] This configuration prevents power supply voltage noise from being transmitted from the back gate terminal of the MOS transistor to the gate terminal. Furthermore, since the source terminal of the MOS transistor receives a voltage generated without filtering, it is not necessary to use a voltage that has been dropped by filtering. This makes the semiconductor circuit more resistant to power supply voltage noise and allows for more appropriate operation.

[0015] In one embodiment, the MOS transistor may be constructed using a semiconductor substrate. The semiconductor substrate may include a P-type substrate region and an N-well region formed on the substrate region. A P-type source region, a P-type drain region, and an N-type back gate region of the MOS transistor may be formed in the N-well region. The back gate region may be connected to a back gate terminal. The source region may be connected to a source terminal. The substrate region and the N-well region may be configured to generate capacitance that contributes to a capacitor of the low pass filter.

[0016] In one embodiment, when the first transistor is a MOS transistor, the semiconductor circuit may further include a second transistor that is an N-channel MOS transistor. The first and second transistors may share an N-well region. The second transistor may be connected to a terminal that receives the filtered voltage, and may include an N-type region that is doped more heavily than the N-well region and formed within the N-well region.

[0017] In one embodiment, the semiconductor circuit may include a plurality of first transistors and a plurality of second transistors. The plurality of first transistors and the plurality of second transistors may share an N-well region. A voltage generated after filtering may be supplied to a back gate terminal of each of the plurality of first transistors. A voltage generated without being filtered by a low-pass filter may be supplied to a source terminal of each of the plurality of first transistors. A terminal connected to an N-type region of each of the plurality of second transistors may be supplied with the voltage generated after filtering.

[0018] In one embodiment, the semiconductor circuit may further include a second transistor that is an N-channel MOS transistor when the first transistor is a MOS transistor. The first transistor may be a P-channel MOS transistor. The first transistor and the second transistor may form a CMOS circuit.

[0019] In one embodiment, the semiconductor circuit may further include a first CMOS circuit, a second CMOS circuit configured with a third transistor that is a P-channel MOS transistor and a fourth transistor that is an N-channel MOS transistor, and an RC circuit including a resistor and a capacitor and provided between the first CMOS circuit and the second CMOS circuit. The first CMOS circuit, the second CMOS circuit, and the RC circuit may form a delay circuit that delays a signal input to the first CMOS circuit and outputs the delayed signal from the second CMOS circuit.

[0020] In one embodiment, the semiconductor circuit may further include a first input transistor, a second input transistor, a MOS transistor that forms an input differential pair with the first input transistor, a current source that receives a power supply voltage and supplies a tail current to the source of the input differential pair, a current mirror circuit provided as an active load of the input differential pair, and an output circuit. The first input transistor and the second input transistor may each be a P-channel MOS transistor. The current source, the input differential pair, the current mirror circuit, and the output circuit may form a comparator that compares two input voltages input to the input differential pair and outputs a comparison signal from the output circuit according to the result. A voltage generated by filtering may be supplied to each of the back gate terminals of the first input transistor and the second input transistor.

[0021] In one embodiment, the semiconductor circuit may be monolithically integrated on a single semiconductor chip.

[0022] In one embodiment, a step-down DC / DC converter may step down an input voltage to generate an output voltage. The step-down DC / DC converter may include: an error amplifier that generates an error signal by amplifying the error between a reference voltage and a feedback voltage corresponding to the output voltage of the step-down DC / DC converter; the semiconductor circuit; an output stage including a high-side transistor and a low-side transistor that generates the output voltage of the step-down DC / DC converter; a driver that drives the output stage; and a logic circuit that generates a pulse signal for controlling the operation of the driver. The two input voltages may be the error signal and a periodic ramp voltage. The logic circuit may generate a pulse signal that determines the duty ratio based on the comparison signal. The driver may control the driving of the high-side transistor and the low-side transistor based on the pulse signal.

[0023] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0024] In this specification, "component A is connected to component B" includes not only a case where component A and component B are directly physically connected, but also a case where component A and component B are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0025] Similarly, "component C is connected (provided) between component A and component B" includes not only a case where component A and component C, or component B and component C, are directly connected, but also a case where they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0026] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0027] In this specification, "mono-integrated" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are mono-integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate to adjust the circuit constants.

[0028] (First embodiment) FIG. 1 is a block diagram of a DC / DC converter 1 according to a first embodiment. The DC / DC converter 1 according to this embodiment operates in response to an input voltage V IN1 is stepped down to output voltage V OUT1 The DC / DC converter 1 according to this embodiment includes a semiconductor circuit 10 and a peripheral circuit 20.

[0029] The semiconductor circuit 10 according to this embodiment is a controller circuit that controls the operation of the DC / DC converter 1. The semiconductor circuit 10 according to this embodiment includes a low-pass filter 100, an analog block 120, a driver 160, a feedback terminal FB, a high-side terminal TH, and a low-side terminal TL. The semiconductor circuit 10 may be integrated into a single semiconductor chip.

[0030] The low-pass filter 100 is connected to the power supply voltage V DD1 is filtered to obtain the voltage V DD2 In this embodiment, the power supply voltage V DD1 is supplied from a single power supply circuit (not shown). The low-pass filter 100 includes a resistor R1 and a capacitor C1. The resistor R1 is connected to the power supply voltage V DD1 Node 102 supplied with voltage V DD2A capacitor C1 is provided between one end of the resistor R1 on the node 104 side and the ground. The capacitor C1 may be provided as an individual capacitor, or may be formed by the parasitic capacitance of a semiconductor substrate on which a transistor is formed, as will be described later.

[0031] The analog block 120 detects the feedback voltage V at the feedback terminal FB. FB The pulse signal S determines the duty ratio according to P The analog block 120 includes an error amplifier 130, a comparator 140, and a logic circuit 150. Note that the analog block 120 may further include an error amplifier, as necessary, that detects the current flowing through an inductor L1 (or the current flowing through the high-side transistor MH or the low-side transistor ML) and feeds back the detection result.

[0032] The error amplifier 130 detects the output voltage V of the DC / DC converter 1. OUT1 Feedback voltage V according to FB and the reference voltage V REF The error signal S ERR The error amplifier 130 generates a reference voltage V REF is input, and the feedback voltage V FB The error amplifier 130 according to this embodiment is provided so that it receives the power supply voltage V DD1 It operates using this as a power source.

[0033] The comparator 140 outputs the error signal S ERR and the periodic ramp voltage V RAMP A comparison signal S according to the result of the comparison COMP A comparison signal S COMP The duty ratio is controlled by the comparator 140. The comparator 140 receives an error signal S ERR is input, and the inverting input terminal is supplied with a ramp voltage V RAMP The lamp voltage S RAMPmay be, for example, a voltage in which a sawtooth wave or a triangular wave is periodically repeated. DD1 and voltage V DD2 It operates using this as a power source.

[0034] The logic circuit 150 outputs a comparison signal S COMP The duty ratio of the pulse signal S is determined based on P The logic circuit 150 includes a flip-flop circuit 152 and an oscillator 154 that generates a clock signal CLK. The flip-flop circuit 152 according to this embodiment is an RS type, and generates the clock signal CLK and the comparison signal S. COMP In response to P Generate.

[0035] The driver 160 generates a pulse signal S P Specifically, the driver 160 controls the driving of the high-side transistor MH and the low-side transistor ML, which will be described later, in response to the high-side gate signal S HG and the low-side gate signal S LG The driver 160 according to this embodiment generates a power supply voltage V DD1 It operates using this as a power source.

[0036] The peripheral circuit 20 includes a high-side transistor MH, a low-side transistor ML, an inductor L1, a capacitor C2, resistors R2 and R3, and an output terminal OUT1. OUT1 is output from the output terminal OUT1. Note that a portion of the configuration of the peripheral circuit 20 may be included in the semiconductor circuit 10. For example, the high-side transistor MH, the low-side transistor ML, and the resistors R2 and R3 may be included in the semiconductor circuit 10 as needed.

[0037] The high-side transistor MH and the low-side transistor ML according to this embodiment are connected to the output voltage V OUT1The high-side transistor MH and the low-side transistor ML according to this embodiment are each configured as an N-channel MOS transistor. The gate of the high-side transistor MH is connected to the high-side terminal TH, and the drain terminal of the high-side transistor MH is connected to the input voltage V IN1 The gate terminal of the low-side transistor ML is connected to the low-side terminal TL, and the source terminal of the low-side transistor ML is connected to ground.

[0038] The high-side transistor MH receives a high-side gate signal S supplied from the driver 160 via a high-side terminal TH. HG The low-side transistor ML is driven in response to a low-side gate signal S supplied from the driver 160 via a low-side terminal TL. LG Drives according to

[0039] One end of the inductor L1 is connected between the high-side transistor MH and the low-side transistor ML. The other end of the inductor L1 is connected to the output terminal VOUT1. The capacitor C2 is provided between the output terminal OUT1 and ground. The resistors R2 and R3 are connected in series and are connected to the output voltage V OUT1 The feedback voltage V FB Generate.

[0040] 2 is a block diagram of a comparator 140 according to this embodiment. The comparator 140 according to this embodiment includes a current source 142, an input differential pair 144, a current mirror circuit 146, an output circuit 148, a non-inverting input terminal INP, an inverting input terminal INN, and an output terminal OUT2. The current source 142, the input differential pair 144, the current mirror circuit 146, and the output circuit 148 generate a comparison signal S according to the result of comparing two input voltages input to the input differential pair 144. COMP is output from the output circuit 148.

[0041] The current source 142 is connected to the power supply voltage V DD1and supplies a tail current I1 to the sources of the input differential pair 144 (more specifically, the source terminals of transistors MP1 and MP2, which will be described later).

[0042] The input differential pair 144 is configured to generate differential currents I2 and I3 according to the difference between two input voltages. In this embodiment, the two input voltages are a periodic ramp voltage V RAMP and the error signal S input to the non-inverting input terminal INP. ERR is.

[0043] The input differential pair 144 includes a transistor MP1 (first input transistor) and a transistor MP2 (second input transistor), each configured as a P-channel MOS transistor. The gate terminal of the transistor MP1 is connected to the inverting input terminal INN, and the gate terminal of the transistor MP2 is connected to the non-inverting input terminal INP. A current I2 is the drain current of the transistor MP1, and a current I3 is the drain current of the transistor MP2.

[0044] A low-pass filter 100 is connected to each of the back gate terminals of the transistor MP1 and the transistor MP2, and the ...2 and the back gate terminals of the transistor MP1 and the transistor MP2. DD1 The voltage V generated by filtering DD2 This prevents noise from being propagated to the gate terminals of the transistors MP1 and MP2 via the back gate terminals of the transistors MP1 and MP2.

[0045] The source terminals of the transistors MP1 and MP2 are connected to the current source 142. Therefore, the power supply voltage V that has not been filtered by the low-pass filter 100 is applied to the source terminals of the transistors MP1 and MP2 (specifically, the current source 142). DD1 Therefore, the voltage V DD2As a result, a larger current can be passed through the input differential pair 144, and the operation speed of the comparator 140 can be increased.

[0046] The current mirror circuit 146 is provided as an active load of the input differential pair 144 and is connected to the output circuit 148. The current mirror circuit 146 according to this embodiment includes transistors ML1 and ML2, each configured as an N-channel MOS transistor. The gate terminal of the transistor ML1 is connected to the drain terminal of the transistor ML1 in common with the gate terminal of the transistor ML2. The source terminal of the transistor ML1 is connected to the ground in common with the source terminal of the transistor ML2. The drain terminal of the transistor ML1 is connected to the drain terminal of the transistor MP1. The drain terminal of the transistor ML2 is connected to the drain terminal of the transistor MP2 and the output circuit 148.

[0047] The output circuit 148 outputs a comparison signal S according to the differential currents I2 and I3. COMP The configuration of the output circuit 148 is not particularly limited, but may be configured by combining a current source and a common source circuit, for example. COMP is the lamp voltage V RAMP and the error signal S ERR The comparison signal S COMP is output from the output terminal OUT2.

[0048] 3 is a cross-sectional view illustrating an example of the layout of a P-channel MOS transistor 320 and an N-channel MOS transistor 340 according to this embodiment. For example, the transistors MP1 and MP2 of the comparator 140 may be configured similarly to the MOS transistor 320 shown in FIG. 3. Furthermore, the transistors ML1 and ML2 of the comparator 140 may be configured similarly to the MOS transistor 340 shown in FIG.

[0049] Each of the MOS transistors 320 and 340 is configured using a semiconductor substrate 300. The semiconductor substrate 300 includes a P-type substrate region 302 and an N-well region 304 formed on the substrate region 302. As shown in FIG. 3, in this embodiment, the MOS transistors 320 and 340 share the N-well region 304. The substrate region 302 is connected to ground GND.

[0050] A P-type source region 322, a P-type drain region 324, and an N-type back gate region 326 of the MOS transistor 320 are formed in the N-well region 304. The back gate region 326 is doped at a higher concentration than the N-well region 304. The source region 322, the drain region 324, and the back gate region 326 are connected to a source terminal SP, a drain terminal DP, and a back gate terminal BGP of the MOS transistor 320, respectively. The back gate terminal BGP is connected to a power supply voltage V DD1 The voltage V generated by filtering DD2 is supplied.

[0051] An insulating film 328 is provided on the N-well region 304 between the source region 322 and the drain region 324. An electrode 330 connected to the gate terminal GP of the MOS transistor 320 is provided on the insulating film 328.

[0052] An N-type region 342 that is doped at a higher concentration than the P-well region 344 and N-well region 304 of the MOS transistor 340 is formed in the N-well region 304. The N-type region 342 is connected to a voltage adjustment terminal BL. In this embodiment, a voltage higher than ground is supplied to the voltage adjustment terminal BL so that the potential of the back gate terminal BGN of the MOS transistor 340 does not become ground. In this embodiment, the voltage adjustment terminal BL is connected to a power supply voltage V DD1 The voltage V generated by filtering DD2 is supplied.

[0053] An N-type source region 346, an N-type drain region 348, and a P-type back gate region 350 are formed in the P-well region 344. The back gate region 350 is doped more heavily than the P-well region 344. The source region 346, the drain region 348, and the back gate region 350 are connected to the source terminal SN, the drain terminal DN, and the back gate terminal BGN of the MOS transistor 340, respectively.

[0054] An insulating film 352 is provided on the P-well region 344 between the source region 346 and the drain region 348. An electrode 354 connected to the gate terminal GN of the MOS transistor 340 is provided on the insulating film 352.

[0055] In this embodiment, the substrate region 302 and the N-well region 304 contribute a capacitance C P1 Specifically, as shown in FIG. 3, a capacitance C P1 In a large-scale circuit, when the back gate terminal BGP and the voltage adjustment terminal BL are provided in a common N-well region 304, the voltage V DD2 A large capacitance C P1 As a result, even if a capacitor is not provided to configure the low-pass filter 100, the capacitance C P1 By using the resistor R1, the low-pass filter 100 can be configured by simply providing the resistor R1. P1 The low-pass filter 100 can be configured as follows.

[0056] 4 is a top view of a semiconductor substrate 300 showing an example of the layout of transistors MP11-15 and MN11-MN14 according to this embodiment. The semiconductor circuit 10 according to this embodiment has transistors MP11-15 (first transistors) each composed of a plurality of P-channel MOS transistors, and transistors MN11-MN14 (second transistors) each composed of a plurality of N-channel MOS transistors.

[0057] 4 shows an example in which the number of transistors MP11-15 configured as P-channel MOS transistors is five, but the number of such transistors may be four or less, or six or more. Also, while Fig. 4 shows an example in which the number of transistors MN11-14 configured as N-channel MOS transistors is four, the number of such transistors may be three or less, or five or more.

[0058] The transistors MP11 to MP15 may each be configured similarly to the MOS transistor 320 shown in Fig. 3. The transistors MN11 to MN14 may each be configured similarly to the MOS transistor 340 shown in Fig. 3. The transistors MP11 to MP15 may correspond to the transistors MP1 and MP2 of the comparator 15, and the transistors MN11 to MN14 may correspond to the transistors ML1 and ML2 of the comparator 15.

[0059] 4, the plurality of transistors MP11 to MP15 and the plurality of transistors MN11 to MN14 according to this embodiment share an N-well region 304. In addition, the plurality of transistors MN11 to MN14 share a P-well region 344.

[0060] In this embodiment, the back gate terminals of the plurality of transistors MP11 to MP15 are connected to a power supply voltage V DD1 The voltage V generated by filtering DD2 The voltage adjustment terminals of the plurality of transistors MN11 to MN14 are supplied with the power supply voltage V DD1 The voltage V generated by filtering DD2 As a result, the semiconductor circuit 10 receives the power supply voltage V DD1 In the case of a large-scale circuit, there may be multiple noise sources, but even in such a case, the power supply voltage V DD1 The influence of noise can be suppressed.

[0061] Furthermore, the source terminals of the plurality of transistors MP11 to MP15 are connected to a voltage (power supply voltage V DD1 ) is supplied. DD2 A supply voltage greater than V DD1 to the source terminal side, a larger current can be made to flow.

[0062] In addition, for some of the P-channel transistors MP11 to MP15, the voltage generated by filtering is applied to the source terminal side in addition to the back gate terminal. VDD2 Specifically, a voltage may be supplied to the source terminal side. VDD2 For transistors that can supply sufficient current even when using VDD2 may be supplied.

[0063] The DC / DC converter 1 and its semiconductor circuit 10 according to this embodiment have been described above. The semiconductor circuit 10 according to this embodiment operates in response to a power supply voltage V DD1 The low-pass filter 100 filters the power supply voltage V DD1 The voltage V generated by filtering DD2 The source terminals of the transistors MP1 and MP2 are supplied with a voltage (power supply voltage V DD1 ) is supplied.

[0064] With this configuration, the power supply voltage V DD1 Furthermore, since the source terminals of the transistors MP1 and MP2 are supplied with a voltage generated without filtering, it is not necessary to use a voltage that has been dropped by filtering. Therefore, the semiconductor circuit 10 according to this embodiment can reduce the power supply voltage V DD1This makes it possible to achieve more appropriate operation and be more resistant to noise.

[0065] The advantages of the DC / DC converter 1 according to this embodiment become even clearer when compared with comparative techniques.

[0066] FIG. 5 shows the power supply voltage V DD1 FIG. 1 is a block diagram illustrating the influence of the power supply voltage V DD1 is supplied to a power supply terminal VDD from a power supply circuit (not shown) via an output capacitor C9. For example, a parasitic inductor L9 occurs in the path from the power supply circuit to the power supply terminal VDD.

[0067] When the driver 160 operates, a current I9 flows instantaneously from the power supply terminal VDD to the driver 160. At this time, the parasitic inductor L9 DD1 The error amplifier 930 and the comparator 940 included in the analog block 920 according to the first comparative technique generate noise N1. DD1 Therefore, the power supply voltage V DD1 When noise N1 occurs in the error amplifier 930, the error signal S ERR8 is affected by noise N1, or the comparison signal S COMP8 The pulse width of the input signal is affected by the noise N1. As a result, the DC / DC converter according to the first comparative technique is strongly affected by the noise N1.

[0068] 6 is a diagram illustrating the power supply to the error amplifier 932 and the comparator 950 in the analog block according to the comparative technique 2. The error amplifier 932 according to the comparative technique 2 is DD1 The voltage V generated by filtering with a low-pass filter DD2 Therefore, the power supply voltage V DD1 Even if noise occurs in the error amplifier 932, the error signal S ERR9 This can suppress the occurrence of noise.

[0069] However, in filtering, the supply voltage V DD1 The voltage V generated by filtering all the power supplies of the comparator 950 is DD2 In this case, a sufficiently large voltage cannot be supplied to the comparator 950 as a power supply. As a result, a sufficiently large current cannot flow, and the comparator 950 cannot achieve a high response speed. Therefore, in comparative technique 2, the power supply for the comparator 950 is an unfiltered power supply voltage V DD1 Only using.

[0070] FIG. 7 shows the power supply voltage V DD1 9 is a diagram for explaining the influence of noise N2 in the input differential pair 952 of the comparator 950 according to the comparative technique 2. The input differential pair 952 of the comparator 950 according to the comparative technique 2 includes transistors MP91 and MP92, each of which is configured as a P-channel MOS transistor. The back gate terminals of the transistors MP91 and MP92 are connected to the unfiltered power supply voltage V DD1 is supplied.

[0071] 8 is a cross-sectional view showing the layout of transistor MP91 according to comparative technique 2. Transistor MP91 is configured using a semiconductor substrate 900. The semiconductor substrate 900 includes a P-type substrate region 902 and an N-well region 904. The N-well region 904 is connected to a back gate terminal BG9. A source region 906 and a drain region 908 of transistor MP91 are formed within the N-well region 904. The source region 906 and the drain region 908 are connected to a source terminal S9 and a drain terminal D9, respectively.

[0072] An insulating film 910 is provided on the N-well region 904 between the source region 906 and the drain region 908. An electrode 912 connected to the gate terminal G9 is provided on the insulating film 910. A power supply voltage V DD1 When noise N2 occurs in the gate terminal G9, this noise N2 is transmitted through the parasitic capacitance CP9 , and is propagated to the gate terminal G9 through the noise N2. Therefore, the comparator 950 according to the second comparative technique is affected by the noise N2 and may not operate properly.

[0073] In the comparator 140 according to this embodiment, the back gate terminals of the transistors MP1 and MP2 are connected to the power supply voltage V DD1 The voltage V generated by filtering DD2 Therefore, the comparator 140 according to this embodiment is supplied with the power supply voltage V DD1 Therefore, the influence of noise is suppressed.

[0074] FIG. 9 shows the ramp voltage V RAMP , power supply voltage V DD1 and high-side gate signal S HG9 9 is a timing chart showing the results of a simulation of the high-side gate signal S HG9 At the rising or falling timings t91 to t94, the power supply voltage V DD1 As a result, noise propagates from the transistor MP91 of the comparator 950 to the gate terminal, causing the ramp voltage V RAMP Noise occurs.

[0075] The inventors have determined that the comparison signal S of the comparator 950 according to the second comparative technique COMP8 A simulation was conducted to examine the relationship between the parasitic inductor L9 and the duty ratio. As a result, it was confirmed that a low duty ratio can be achieved when there is no parasitic inductor L9, but that a duty ratio lower than a certain ratio cannot be achieved when there is parasitic inductor L9. Therefore, it was confirmed that the DC / DC converter according to Comparative Technology 2 may not operate properly due to noise caused by the parasitic inductor L9.

[0076] The above mainly focuses on the power supply voltage V due to the operation of the DC / DC converter driver. DD1In the example above, noise occurs in the power supply voltage V. If there is a dedicated power supply circuit for one DC / DC converter, only the power supply voltage noise from that DC / DC converter needs to be considered. However, if one power supply circuit is shared by drivers for multiple channels, the operation of the drivers for other channels (for example, the generation of transistor gate signals) can cause noise in the power supply voltage V. DD1 Noise occurs.

[0077] Figure 10 shows the gate signal S generated by the driver of the other channel. G , power supply voltage V DD1 and the high-side gate signal S of the DC / DC converter according to Comparative Technique 2 HG9 10 is a timing chart showing the simulation results of the above.

[0078] As shown in FIG. 10, the driver of another channel receives a rising gate signal S G In response, the power supply voltage V DD1 This noise affects the operation of the comparator 950 according to the second comparative technique, and as a result, at timing t96, the high-side gate signal S HG9 This can result in unintended on-time occurrences.

[0079] As described above, in the DC / DC converter according to Comparative Technique 2, the power supply voltage V DD1 When noise occurs, proper operation cannot be achieved.

[0080] FIG. 11 shows the ramp voltage V RAMP , power supply voltage V DD1 , the filtered voltage V DD2 and high-side gate signal S HG 11 is a timing chart showing the results of a simulation of the high-side gate signal S HGAt the rising and falling timings t1 to t4, the power supply voltage V DD1 However, this noise is generated at the voltage V DD2 As a result, the lamp voltage V RAMP This suppresses noise in the DC / DC converter 1, enabling it to operate properly.

[0081] The inventors also simulated the operation of the DC / DC converter 1 according to this embodiment when the driver of another channel generates a gate signal. DD2 The noise generated in the high-side gate signal S HG It was confirmed that no unintended on-time occurred and that DC / DC converter 1 could operate properly.

[0082] (Second embodiment) 12 is a circuit diagram of a delay circuit 40 according to the second embodiment. The delay circuit 40 is configured as a part of a semiconductor circuit. The semiconductor circuit according to the second embodiment may have a low-pass filter, similar to the first embodiment.

[0083] The delay circuit 40 according to the second embodiment includes a first CMOS (Complementary Metal Oxide Semiconductor) circuit 400, an RC circuit 420, a second CMOS circuit 440, an input terminal IN2, and an output terminal OUT2. The delay circuit 40 receives a signal (input voltage V IN2 ) and outputs the delayed signal (output voltage V OUT2 ) is configured to output the input voltage V IN2 is input to the input terminal IN2, and the output voltage V OUT2 is output from the output terminal OUT2. The first CMOS circuit 400 and the second CMOS circuit 440 each function as an inverter circuit.

[0084] The first CMOS circuit 400 receives an input voltage VIN2 Voltage V according to INV The first CMOS circuit 400 includes a transistor MP21 (first transistor) configured as a P-channel MOS transistor and a transistor MN21 (second transistor) configured as an N-channel MOS transistor. The gate terminal of the transistor MP21 and the gate terminal of the transistor MN21 are connected in common to the input terminal IN2. The source terminal of the transistor MN21 is connected to ground.

[0085] The source terminal of the transistor MP21 is connected to the power supply voltage V DD3 The back gate terminal of the transistor MP21 and the voltage adjustment terminal of the transistor MN21 are supplied with the power supply voltage V DD3 is filtered by a low-pass filter to generate the voltage V DD4 A voltage V is supplied between the transistors MP21 and MN21. INV is generated.

[0086] The RC circuit 420 converts the input voltage V INV Voltage V according to RC The RC circuit 420 includes a resistor R4 and a capacitor C3. One end of the resistor R4 is connected between the transistor MP21 and the transistor MN21, and the other end of the resistor R4 is connected to one end of the capacitor C3. The other end of the capacitor C3 is connected to ground, and a voltage V RC is generated.

[0087] The second CMOS circuit 440 is connected to a voltage V RC Output voltage V according to OUT2The second CMOS circuit 440 includes a transistor MP22 (third transistor) configured as a P-channel MOS transistor and a transistor MN22 (fourth transistor) configured as an N-channel MOS transistor. The gate terminal of the transistor MP22 is connected to one end of a capacitor C3 in common with the gate terminal of the transistor MN22. The source terminal of the transistor MN22 is connected to ground.

[0088] The source terminal of transistor MP22 is connected to the power supply voltage V DD3 The back gate terminal of the transistor MP22 and the voltage adjustment terminal of the transistor MN22 are supplied with the power supply voltage V DD3 is filtered by a low-pass filter to generate the voltage V DD4 The output voltage V is supplied between the transistor MP22 and the transistor MN22. OUT2 is generated.

[0089] An example of the operation of the delay circuit 40 will now be described. IN2 12, a voltage that falls from high to low at a certain timing is input to the first CMOS circuit 400. The first CMOS circuit 400 receives this input voltage V IN2 Inverts the voltage V that rises from low to high. INV The RC circuit 420 generates the voltage V INV The voltage V that falls slowly from high to low depending on RC The second CMOS circuit 440 generates the voltage V RC Depending on the input voltage V IN2 The output voltage V rises later than OUT2 Generate.

[0090] Here, the back gate terminals of the transistors MP21 and MP22 and the voltage adjustment terminals of the transistors MN21 and MN22 are supplied with a filtered voltage V IN4 Therefore, the delay circuit 40 is a circuit that is resistant to noise. Also, the second CMOS circuit 440 receives a voltage VRC At this time, the source terminal of the transistor MP22 receives the power supply voltage V that is not filtered by the low-pass filter. DD3 is supplied, so that the filtered voltage V DD4 This allows a larger current to flow through the transistor MP22 than when the second CMOS circuit 440 is supplied to the source terminal. As a result, the second CMOS circuit 440 can respond faster and provide a more appropriate output voltage V OUT2 It is possible to generate

[0091] The configuration of the DC / DC converter 1 according to the first embodiment can be applied to the delay circuit 40 according to the second embodiment as necessary. For example, the transistors MP21, MP22, MN21, and MN22 can have a layout configuration as described with reference to FIGS.

[0092] (supplement) Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. Furthermore, not only the embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention.

[0093] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0094] (Item 1) a low-pass filter for filtering the power supply voltage; a MOS transistor; a back gate terminal of the MOS transistor is supplied with a voltage generated by filtering a power supply voltage by the low-pass filter; A voltage generated without being filtered by the low-pass filter is supplied to the source terminal side of the MOS transistor. Semiconductor circuit.

[0095] (Item 2) the MOS transistor is configured using a semiconductor substrate, the semiconductor substrate includes a P-type substrate region and an N-well region formed on the substrate region; a P-type source region, a P-type drain region, and an N-type back gate region of the MOS transistor are formed in the N-well region; the back gate region is connected to the back gate terminal; the source region is connected to the source terminal; the substrate region and the N-well region are configured to generate a capacitance that contributes to a capacitor of the low pass filter. Item 1. The semiconductor circuit according to item 1.

[0096] (Item 3) When the MOS transistor is a first transistor, the semiconductor device further includes a second transistor that is an N-channel MOS transistor, the first transistor and the second transistor share the N-well region; the second transistor is connected to a terminal to which the voltage generated by filtering is supplied, and includes an N-type region doped at a higher concentration than the N-well region and formed within the N-well region; Item 2. The semiconductor circuit according to item 2.

[0097] (Item 4) the semiconductor circuit includes a plurality of the first transistors and a plurality of the second transistors; the plurality of first transistors and the plurality of second transistors share the N-well region; the filtered voltage is supplied to a back gate terminal of each of the plurality of first transistors; a voltage generated without being filtered by the low-pass filter is supplied to a source terminal side of each of the plurality of first transistors; the voltage generated by filtering is supplied to a terminal connected to the N-type region of each of the plurality of second transistors; Item 3. The semiconductor circuit according to item 3.

[0098] (Item 5) When the MOS transistor is a first transistor, the semiconductor device further includes a second transistor that is an N-channel MOS transistor, the first transistor is a P-channel MOS transistor, the first transistor and the second transistor constitute a CMOS circuit. 5. The semiconductor circuit according to any one of items 1 to 4.

[0099] (Item 6) a second CMOS circuit including the CMOS circuit as a first CMOS circuit, a third transistor being a P-channel MOS transistor, and a fourth transistor being an N-channel MOS transistor; an RC circuit including a resistor and a capacitor, the RC circuit being disposed between the first CMOS circuit and the second CMOS circuit; the first CMOS circuit, the second CMOS circuit, and the RC circuit constitute a delay circuit that delays a signal input to the first CMOS circuit and outputs the delayed signal from the second CMOS circuit. Item 6. The semiconductor circuit according to item 5.

[0100] (Item 7) a second input transistor which is a MOS transistor forming an input differential pair with the first input transistor, the second input transistor being a MOS transistor; a current source that receives the power supply voltage and supplies a tail current to the sources of the input differential pair; a current mirror circuit provided as an active load of the input differential pair; an output circuit, the first input transistor and the second input transistor are P-channel MOS transistors, the current source, the input differential pair, the current mirror circuit, and the output circuit constitute a comparator that compares two input voltages input to the input differential pair and outputs a comparison signal from the output circuit according to the result; the back gate terminal of the first input transistor and the back gate terminal of the second input transistor are each supplied with the voltage generated by filtering; 5. The semiconductor circuit according to any one of items 1 to 4.

[0101] (Item 8) Integrated on a single semiconductor chip 8. The semiconductor circuit according to any one of items 1 to 7.

[0102] (Item 9) A step-down DC / DC converter that steps down an input voltage to generate an output voltage, an error amplifier that generates an error signal by amplifying an error between a reference voltage and a feedback voltage corresponding to an output voltage of the step-down DC / DC converter; Item 7. The semiconductor circuit according to item 7, an output stage including a high-side transistor and a low-side transistor for generating an output voltage of the step-down DC / DC converter; a driver that drives the output stage; a logic circuit that generates a pulse signal for controlling the operation of the driver; the two input voltages being the error signal and a periodic ramp voltage; the logic circuit generates the pulse signal that determines a duty ratio based on the comparison signal; the driver controls driving of the high-side transistor and the low-side transistor based on the pulse signal. Step-down DC / DC converter. [Explanation of symbols]

[0103] 1 DC / DC converter, 10 semiconductor circuit, 20 peripheral circuit, 22 output stage, 100 low-pass filter, 40 delay circuit, 120 analog block, 130 error amplifier, 140 comparator, 142 current source, 144 input differential pair, 146 current mirror circuit, 148 output circuit, 150 logic circuit, 152 flip-flop circuit, 154 oscillator, 160 driver, 300 semiconductor substrate, 302 substrate region, 304 N-well region, 320, 340 MOS transistor, 322, 346 source region, 324, 348 drain region, 326, 350 backgate region, 328, 352 insulating film, 330, 354 electrode, 400 first CMOS circuit, 420 RC circuit, 440 second CMOS circuit, MH high-side transistor, ML Low-side transistors, MP1, MP2, MP11 to MP15, MP21, MP22, ML1, ML2, MN11 to MN14, MN21, MN22 transistors, L1 inductor, C1 to C3 capacitors, C P1 Capacitor, R1 to R4 resistors, SP, SN source terminals, DP, DN drain terminals, GP, GN gate terminals, BGP, BGN back gate terminals, BL voltage adjustment terminal.

Claims

1. a low-pass filter for filtering the power supply voltage; a MOS transistor; a back gate terminal of the MOS transistor is supplied with a voltage generated by filtering a power supply voltage by the low-pass filter; A voltage generated without being filtered by the low-pass filter is supplied to the source terminal side of the MOS transistor. Semiconductor circuit.

2. the MOS transistor is configured using a semiconductor substrate, the semiconductor substrate includes a P-type substrate region and an N-well region formed on the substrate region; a P-type source region, a P-type drain region, and an N-type back gate region of the MOS transistor are formed in the N-well region; the back gate region is connected to the back gate terminal; the source region is connected to the source terminal; the substrate region and the N-well region are configured to generate a capacitance that contributes to a capacitor of the low pass filter. The semiconductor circuit according to claim 1 .

3. When the MOS transistor is a first transistor, the semiconductor device further includes a second transistor which is an N-channel MOS transistor, the first transistor and the second transistor share the N-well region; the second transistor is connected to a terminal to which the voltage generated by filtering is supplied, and includes an N-type region doped at a higher concentration than the N-well region and formed within the N-well region; The semiconductor circuit according to claim 2 .

4. the semiconductor circuit includes a plurality of the first transistors and a plurality of the second transistors; the plurality of first transistors and the plurality of second transistors share the N-well region; the filtered voltage is supplied to a back gate terminal of each of the plurality of first transistors; a voltage generated without being filtered by the low-pass filter is supplied to a source terminal side of each of the plurality of first transistors; the filtered voltage is supplied to a terminal connected to the N-type region of each of the plurality of second transistors; 4. The semiconductor circuit according to claim 3.

5. When the MOS transistor is a first transistor, the semiconductor device further includes a second transistor which is an N-channel MOS transistor, the first transistor is a P-channel MOS transistor, the first transistor and the second transistor form a CMOS circuit. The semiconductor circuit according to claim 1 .

6. a second CMOS circuit including a third transistor that is a P-channel MOS transistor and a fourth transistor that is an N-channel MOS transistor, the second CMOS circuit being a first CMOS circuit; an RC circuit including a resistor and a capacitor, the RC circuit being disposed between the first CMOS circuit and the second CMOS circuit; the first CMOS circuit, the second CMOS circuit, and the RC circuit constitute a delay circuit that delays a signal input to the first CMOS circuit and outputs the delayed signal from the second CMOS circuit; 6. The semiconductor circuit according to claim 5.

7. a second input transistor which is a MOS transistor forming an input differential pair with the first input transistor, the second input transistor being a first input transistor; a current source that receives the power supply voltage and supplies a tail current to the sources of the input differential pair; a current mirror circuit provided as an active load of the input differential pair; an output circuit, the first input transistor and the second input transistor are P-channel MOS transistors, the current source, the input differential pair, the current mirror circuit, and the output circuit constitute a comparator that compares two input voltages input to the input differential pair and outputs a comparison signal from the output circuit according to the result; the back gate terminal of the first input transistor and the back gate terminal of the second input transistor are each supplied with the voltage generated by filtering; The semiconductor circuit according to claim 1 .

8. Integrated on a single semiconductor chip The semiconductor circuit according to any one of claims 1 to 7.

9. A step-down DC / DC converter that steps down an input voltage to generate an output voltage, an error amplifier that generates an error signal by amplifying an error between a feedback voltage corresponding to an output voltage of the step-down DC / DC converter and a reference voltage; a semiconductor circuit according to claim 7; an output stage including a high-side transistor and a low-side transistor for generating an output voltage of the step-down DC / DC converter; a driver that drives the output stage; a logic circuit that generates a pulse signal for controlling the operation of the driver; the two input voltages being the error signal and a periodic ramp voltage; the logic circuit generates the pulse signal that determines a duty ratio based on the comparison signal; the driver controls driving of the high-side transistor and the low-side transistor based on the pulse signal. Step-down DC / DC converter.

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