Current generation circuit and dc / dc converter

Abstract

To provide a current generation circuit capable of generating a sense current corresponding to voltages at both ends of a sense element by using a voltage at one end of the sense element in a wider range.SOLUTION: The current generation circuit 140 includes a first transistor MN1, a second transistor MN2, a first current source 142, a second current source 144, a first resistor, a second resistor, a sense transistor MSN that supplies a sense current corresponding to a voltage between both ends of the sense element to the first resistor, a first offset current source 146 that supplies a first offset current to the first resistor so as to suppress a decrease in a first differential voltage between one end of the first transistor of the first current source and one end of the second transistor of the second current source, and a second offset current source 148 that supplies a second offset current to the second resistor so as to suppress a decrease in a second differential voltage between one end of the second resistor and one end of the second transistor of the second current source.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a current generating circuit and a DC / DC converter. [Background technology]

[0002] It has been known in the past that DC / DC converters perform output feedback control by detecting the coil current in the output stage. For example, Patent Document 1 describes a DC / DC converter that has a current detection unit that generates a current sense signal by sampling the coil current, and generates a desired output voltage from an input voltage by performing current-mode output feedback control using the current sense signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-174865

[0004] [overview] However, the inventors have come to recognize the following problem. One method for detecting coil current is to generate a sense current by converting the sense current based on the voltage across a sense element (such as a resistor or capacitor) connected in series or parallel to the coil. When a detection circuit for detecting coil current using this method is configured using circuit elements such as a transistor and a current source, it is conceivable to use the differential voltage between the input voltage of the DC / DC converter and the voltage at one end of the sense element to operate the circuit elements.

[0005] However, in this case, when the voltage at one end of the sense element is the output voltage of the DC / DC converter, if the output voltage approaches the input voltage and the differential voltage becomes small, the circuit elements of the detection circuit may not operate properly, and as a result, the detection circuit will not be able to generate a proper sense current using the voltage at one end of the sense element.

[0006] The present disclosure has been made in consideration of these circumstances, and one of its exemplary purposes is to provide a current generating circuit that can generate a sense current corresponding to the voltage across the sense element using a wider range of voltages at one end of the sense element.

[0007] a sense transistor configured to generate a sense current corresponding to a voltage across the sense element and supply the sense current to the first resistor; a first offset current source configured to supply a first offset current to the first resistor so as to prevent a first differential voltage between an end of the first current source opposite the first transistor and an end of the first transistor opposite the first current source; and a second offset current source configured to supply a second offset current to the second resistor so as to prevent a second differential voltage between an end of the second current source opposite the second transistor and an end of the second transistor opposite the second current source from decreasing. The gate of the first transistor is commonly connected to the source of the first transistor and the gate of the second transistor. The magnitude of the first current is equal to the magnitude of the second current. The resistance value of the first resistor is equal to the resistance value of the second resistor. The magnitude of the first offset current is equal to the magnitude of the second offset current.

[0008] Any combination of the above components and conversion of the expressions of the present disclosure into methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of a DC / DC converter according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a circuit diagram of a current sense amplifier according to the embodiment. [Figure 3] FIG. 3 is a diagram showing an example of a change in the source voltage of the first transistor according to the embodiment with respect to the output voltage. [Figure 4] FIG. 4 is a diagram showing an example of a change in the first offset current with respect to the output voltage according to the embodiment. [Figure 5] FIG. 5 is a circuit diagram of a current sense amplifier that can be substituted for the current sense amplifier according to the embodiment. [Figure 6] FIG. 6 is a block diagram of a current detection circuit according to a comparative technique. [Figure 7] FIG. 7 is a circuit diagram of a first current sense amplifier according to the comparative technique. [Figure 8] FIG. 8 is a circuit diagram of a second current sense amplifier according to the comparative technique. [Figure 9] FIG. 9 is a timing chart showing the results of simulating the operation of a DC / DC converter according to the comparative technique. [Figure 10] FIG. 10 is a timing chart showing an example of a result of simulating the operation of a DC / DC converter according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a circuit diagram for explaining a method of generating a sense current according to a first modification.

[0010] [Detailed explanation] (overview) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0011] a sense transistor configured to generate a sense current corresponding to a voltage across the sense element and supply the sense current to the first resistor; a first offset current source configured to supply a first offset current to the first resistor so as to prevent a first differential voltage between an end of the first current source opposite the first transistor and an end of the first transistor opposite the first current source; and a second offset current source configured to supply a second offset current to the second resistor so as to prevent a second differential voltage between an end of the second current source opposite the second transistor and an end of the second transistor opposite the second current source from decreasing. The gate of the first transistor is commonly connected to the source of the first transistor and the gate of the second transistor. The magnitude of the first current is equal to the magnitude of the second current. The resistance value of the first resistor is equal to the resistance value of the second resistor. The magnitude of the first offset current is equal to the magnitude of the second offset current.

[0012] This configuration prevents the first differential voltage and the second differential voltage from decreasing. This ensures that the first differential voltage and the second differential voltage are sufficient to properly operate the circuit elements of the current generating circuit, even if the voltage at one end of the sense element changes. As a result, a wider range of voltages at one end of the sense element can be used to generate a sense current that corresponds to the voltage across the sense element.

[0013] In one embodiment, the first offset current source and the second offset current source may provide a first offset current and a second offset current, respectively, to enable the first current source, the second current source, and the current mirror pair to operate.

[0014] In one embodiment, the first offset current source and the second offset current source may respectively supply the first offset current and the second offset current in response to the first differential voltage or the second differential voltage becoming equal to or less than a threshold voltage.

[0015] In one embodiment, the first offset current source and the second offset current source may increase the first offset current and the second offset current, respectively, in response to an increase in the voltage at one end of the sense element.

[0016] In one embodiment, the sense element may be a sense resistor, and the sense transistor may generate a sense current that is smaller than the current flowing through the sense resistor in response to a voltage across the sense resistor caused by the current flowing through the sense resistor.

[0017] In one embodiment, a DC / DC converter that generates an output voltage by stepping down an input voltage may include: an error amplifier that generates an error signal by amplifying an error between a feedback voltage of the output voltage and a reference voltage; the current generating circuit; a comparator that compares the error signal with a periodic ramp signal generated based on a sense current to generate a pulse modulated signal; an output stage including a high-side transistor and a low-side transistor that operates in response to the pulse modulated signal; and an inductor provided between the high-side transistor and the low-side transistor and an output terminal of the DC / DC converter. The sense transistor may generate a sense current based on a voltage generated across a sense element that corresponds to a current flowing through the inductor.

[0018] In one embodiment, the voltage at one end of the sense element may be the output voltage.

[0019] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0020] In this specification, "component A is connected to component B" includes not only a case where component A and component B are directly physically connected, but also a case where component A and component B are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0021] Similarly, "component C is connected (provided) between component A and component B" includes not only a case where component A and component C, or component B and component C, are directly connected, but also a case where they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0022] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0023] In this specification, "mono-integrated" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are mono-integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate to adjust the circuit constants.

[0024] 1 is a block diagram of a DC / DC converter 1 according to an embodiment of the present disclosure. The DC / DC converter 1 according to this embodiment receives an input voltage V IN The output voltage V OUT The DC / DC converter 1 according to this embodiment includes a semiconductor circuit 10 and a peripheral circuit 20.

[0025] The peripheral circuit 20 includes an output stage 22, an inductor L1, a capacitor C1, resistors R1 and R2, and a sense resistor R SNS The peripheral circuit 20 has an output voltage V OUT is output from the output terminal OUT, and the feedback voltage V FB is fed back to the semiconductor circuit 10.

[0026] The output stage 22 includes a high-side transistor MH and a low-side transistor ML. The high-side transistor MH and the low-side transistor ML according to this embodiment are each configured as an N-channel MOS (Metal Oxide Semiconductor) transistor. The drain of the high-side transistor MH is connected to an input voltage V IN is supplied, and the source of the low-side transistor ML is connected to ground.

[0027] One end of the inductor L1 is connected between the high-side transistor MH and the low-side transistor ML. The inductor L1 has an inductor current I L The inductor current I L is the sense resistor R connected in series with the inductor L1. SNS It also flows through the sense resistor R SNS One end (first node N1) of the SNS The other end (second node N2) of the inductor L1 is connected to the other end of the inductor L1. The capacitor C1 is provided between the ground and the output terminal OUT. The resistors R1 and R2 are connected in series and divide the output voltage VOUT to generate the feedback voltage V FB Generate.

[0028] The semiconductor circuit 10 controls the operation of the DC / DC converter 1. The semiconductor circuit 10 may be configured as an IC (Integrated Circuit) integrated on a single semiconductor substrate. The semiconductor circuit 10 according to this embodiment includes an analog block 100, a driver 120, a current sense amplifier 140 (current generating circuit), a current sense controller 180, a feedback terminal FB, a high-side terminal TH, and a low-side terminal TL. The feedback terminal FB receives a feedback voltage V FB is entered.

[0029] The analog block 100 outputs the feedback voltage V FB and the sense current I generated by the current sense amplifier 140. SNS1The pulse signal S that controls the duty ratio of the output stage 22 is P The analog block 100 according to this embodiment includes an error amplifier 102, a comparator 104, and a logic circuit 110.

[0030] The error amplifier 102 outputs a reference voltage V REF and the feedback voltage V FB The error signal S ERR The inverting input terminal of the error amplifier 102 receives the feedback voltage V FB is input, and the non-inverting input terminal of the error amplifier 102 receives the reference voltage V REF is input. Error signal S ERR is input to the non-inverting input terminal of the comparator 104.

[0031] The comparator 104 detects the sense current I SNS1 A periodic ramp signal S generated based on RMP2 and the error signal S ERR and the pulse modulated signal S PWM Generates a pulse modulated signal S PWM is input to the logic circuit 110. The ramp signal S RMP2 includes waveforms such as ramp, slope, triangle or sawtooth.

[0032] The logic circuit 110 generates a pulse modulated signal S PWM The pulse signal S that controls the duty ratio of the output stage 22 is P The logic circuit 110 according to this embodiment includes a flip-flop circuit 112 and an oscillator 114 that generates a clock signal CLK. The flip-flop circuit 112 is an RS type flip-flop circuit, and generates a pulse modulated signal S PWM and a pulse signal S based on the clock signal CLK. P The pulse signal S P is input to the driver 120.

[0033] The driver 120 generates a pulse signal S PThe high-side transistor MH and the low-side transistor ML are driven via the high-side terminal TH and the low-side terminal TL based on the input voltage V IN The output voltage V OUT is generated.

[0034] The current sense amplifier 140 is connected to a sense resistor R SNS The inductor current I L Sense current I according to SNS1 Specifically, the current sense amplifier 140 generates the inductor current I L The sense current I SNS1 In this embodiment, the inductor current I L A sense current I smaller than SNS1 The sense current I SNS1 is a periodic ramp signal S RMP1 is combined with the ramp signal S RMP2 is generated.

[0035] The current sense controller 180 controls the operation of the current sense amplifier 140. For example, the current sense controller 180 outputs a control signal S CON The current sense controller 180 also generates an output voltage V OUT Based on this, the control signal S CON You may do so.

[0036] 2 is a circuit diagram of a current sense amplifier 140 according to this embodiment. The current sense amplifier 140 according to this embodiment includes a first transistor MN1, a second transistor MN2, a sense transistor MNS, a first current source 142, a second current source 144, a first offset current source 146, a second offset current source 148, a first resistor R 11 and the second resistor R 12 It has.

[0037] The first transistor MN1 and the second transistor MN2 are each composed of the same type of N-channel MOS transistor. The first transistor MN1 and the second transistor MN2 form a current mirror pair 150. Specifically, the gate of the first transistor MN1 is connected to the drain of the first transistor MN1 in common with the gate of the second transistor MN2.

[0038] The first current source 142 is connected to the input voltage V IN In response to this, the first transistor MN1 receives the first current I 11 The second current source 144 supplies the input voltage V IN In response to this, the second transistor MN2 generates a second current I 12 In this embodiment, the first current I 11 The magnitude of the second current I 12 is the same as the magnitude of (I 11 =I 12 ).

[0039] 1st resistance R 11 is connected between one end of the first transistor MN1 opposite to the first current source 142 and the sense resistor R SNS Specifically, the first resistor R 11 One end of the resistor R 11 The other end is connected to a first node N1.

[0040] 2nd resistor R 12 is connected between one end of the second transistor MN2 opposite to the second current source 144 and the sense resistor R SNS Specifically, the second resistor R 12 One end of the first resistor R is connected to the source of the second transistor MN2, and the other end of the second transistor MN2 is connected to the second node N2. 11 The resistance of the second resistor R 12 The resistance value is the same as that of 11 =R 12 ).

[0041] The first offset current source 146 is connected between the source of the first transistor MN1 and the first resistor R 11 The first offset current source 146 is connected between the first end of the first current source 142 opposite to the first transistor MN1 and the first end of the first transistor MN1 opposite to the first current source 142. 11 (=V IN -V S11 ) to prevent the first resistor R 11 The first offset current I OFF11 supply.

[0042] In this embodiment, the first offset current source 146 is connected to a first resistor R 11 to the first offset current I OFF11 As a result, a first offset current I flows from the first node N1 toward the source of the transistor MN1. OFF11 is the first resistor R 11 The first offset current I OFF11 is the first resistor R 11 , which generates a first offset current I OFF11 Voltage according to (R 11 ×I OFF11 ) is the first resistor R 11 As a result, the source voltage V of the first transistor MN1 S11 is suppressed from increasing, and the first differential voltage ΔV 11 The first differential voltage ΔV 11 Suppressing the decrease of the first differential voltage ΔV 11 and maintaining the magnitude of the first differential voltage ΔV 11 This includes increasing the

[0043] The second offset current source 148 is connected between the source of the second transistor MN2 and the second resistor R 12 The second offset current source 148 is connected between the end of the second current source 144 opposite to the second transistor MN2 and the end of the second transistor MN2 opposite to the second current source 144. 12 (=VIN -V S12 ) to prevent the second resistor R 12 The second offset current I OFF12 supply.

[0044] In this embodiment, the second offset current source 148 is connected to a second resistor R 12 to the second offset current I OFF12 As a result, a second offset current I flows from the second node N2 toward the source of the second transistor MN2. OFF12 is the second resistor R 12 The second offset current I OFF12 is the second resistor R 12 is supplied to generate a second offset current I OFF12 Voltage according to (R 12 ×I OFF12 ) is the second resistor R 12 As a result, the source voltage V of the second transistor MN2 S12 is suppressed from increasing, and the second differential voltage ΔV 12 The second differential voltage ΔV 12 Suppressing the decrease of the second differential voltage ΔV 12 and maintaining the magnitude of the second differential voltage ΔV 12 This includes increasing the

[0045] In this embodiment, the first offset current I OFF11 The magnitude of the second offset current I OFF12 is the same as the magnitude of (I OFF11 =I OFF12 ) below, the first offset current I OFF11 and the second offset current I OFF12 When there is no particular distinction between these, they are simply referred to as the "offset current I OFF1 " is also called.

[0046] The first offset current source 146 generates a first offset current I OFF11The second offset current source 148 may be a variable current source configured to adjust the magnitude of the second offset current I OFF12 The first offset current I may be a variable current source configured to be able to adjust the magnitude of the first offset current I OFF11 and the magnitude of the second offset current I OFF12 are respectively controlled by a control signal S from, for example, the current sense controller 180. CON The signal S contained in 11 and signal S 12 may be adjusted based on

[0047] The sense transistor MNS is an N-channel MOS transistor. SNS The voltage V across R1 Sense current I according to SNS1 and generates a sense current I SNS1 the first resistor R 11 The sense transistor MNS according to this embodiment is provided to supply a voltage to the sense resistor R SNS The inductor current I L sense resistor R SNS The voltage V across R1 Depending on the SNS The inductor current I L A sense current I smaller than SNS1 Generate.

[0048] The first offset current source 146 and the second offset current source 148 generate a first offset current I so that the first current source 142, the second current source 144, and the current mirror pair 150 can operate, respectively. OFF11 and the second offset current I OFF12 Specifically, the first current source 142 and the second current source 144 provide a first current I 11 and the second current I 12 The first offset current I is set to a value that allows the current mirror pair 150 to operate (i.e., the first transistor MN1 and the second transistor MN2 are both in the saturation region) while ensuring the voltage required to supply the first and second transistors MN1 and MN2. OFF11and the second offset current I OFF12 is supplied.

[0049] In this embodiment, the first offset current source 146 and the second offset current source 148 each generate a first differential voltage ΔV 11 or the second differential voltage ΔV 12 is the threshold voltage ΔV th The first offset current I OFF11 and the second offset current I OFF12 supply.

[0050] First differential voltage ΔV 11 or the second differential voltage ΔV 12 is the threshold voltage ΔV th The first offset current I OFF11 and the second offset current I OFF12 When the first offset current I is not supplied, there may not be enough voltage supplied to the first current source 142, the second current source 144, or the current mirror pair 150. OFF11 and the second offset current I OFF12 and supplies the first differential voltage ΔV 11 or the second differential voltage ΔV 12 By preventing the voltage Vcc from becoming small, the first current source 142, the second current source 144, or the current mirror pair 150 can be operated reliably.

[0051] In this embodiment, the first offset current source 146 and the second offset current source 148 each generate a first differential voltage ΔV 11 is the threshold voltage ΔV th The first offset current I OFF11 and the second offset current I OFF12 In this embodiment, the first differential voltage ΔV 11 is ΔV min (<ΔV th ), the first current source 142, the second current source 144, or the current mirror pair 150 can operate.

[0052] The first offset current source 146 and the second offset current source 148 are connected to the sense resistor R SNS In response to the increase in the voltage at one end of OFF11 and the second offset current I OFF12 At this time, the current sense controller 180 can increase the output voltage V OUT The first offset current I OFF11 and the second offset current I OFF12 The control signal S CON may be generated.

[0053] In this embodiment, the first offset current source 146 and the second offset current source 148 generate a first differential voltage ΔV 11 is the threshold voltage ΔV th When the output voltage V OUT As the first offset current I OFF11 and the second offset current I OFF12 This linearly increases the first offset current I OFF11 and the second offset current I OFF12 This can suppress the sudden change of the first offset current I OFF11 and the second offset current I OFF12 The influence of the change in the voltage on the operation of the DC / DC converter 1 is suppressed.

[0054] Here, the current sense amplifier 140 detects the inductor current I L Sense current I according to SNS1 The source voltage V of the first transistor MN1 can be generated. S11 and the source voltage V of the second transistor MN2 S12 and are the same (i.e., V S11 =V S12 ), the inductor current I L sense resistor R SNS The voltage V generated at R1 (=R SNS ×I L ), the following equation holds: V R1 +R 12 ×I12 =R 11 ×(I 11 +I SNS1 )···(1)

[0055] In this embodiment, I OFF11 =I OFF12 , R 11 =R 12 Therefore, equation (1) gives the first offset current I OFF11 and the second offset current I OFF12 is supplied, where I 11 =I 12 Therefore, from equation (1), the following equation holds: V R1 =R 11 ×I 11 +R 11 ×I SNS1 -R 12 ×I 12 =R 11 ×I SNS1 Therefore, the sense current I SNS1 and the inductor current I L The relationship is expressed by the following equation (2): I SNS1 =V R1 / R 11 =(R SNS / R 11 )×I L ···(2)

[0056] From equation (2), (R SNS / R 11 ) to adjust the inductor current I L The converted sense current I SNS1 In this embodiment, (R SNS / R 11 )<1, the inductor current I L A sense current I smaller than SNS1 is generated.

[0057] FIG. 3 shows the source voltage V of the first transistor MN1 according to this embodiment. S11The output voltage V OUT 3, the horizontal axis represents the change in the output voltage V OUT The vertical axis represents the source voltage V S11 The solid line indicates the source voltage V S11 The change in V shown in Figure 3 th2 ≦V S11 ≦V IN The hatched area A is the first differential voltage ΔV 11 or the second differential voltage ΔV 12 becomes too small and the first current source 142, the second current source 144 or the current mirror pair 150 cannot operate properly.

[0058] As shown in Figure 3, the source voltage V S11 is the output voltage V OUT As the voltage rises from 0V (GND), the output voltage V OUT V OUT1 and the source voltage V S11 is the voltage V th1 At the same time as the first differential voltage ΔV 11 is ΔV th When this happens, the first offset current I OFF11 and the second offset current I OFF12 is supplied and the output voltage V OUT The source voltage V S11 The increase in is suppressed.

[0059] In the example shown in Figure 3, V OUT1 ≦V OUT ≦V IN In V S11 V th1 The first offset current I OFF11 and the second offset current I OFF12 The first offset current I OFF11 and the second offset current I OFF12 If V is not supplied, S11 V th2 Above this, ΔV 11 is ΔV min In this embodiment, the first offset current IOFF11 and the second offset current I OFF12 is supplied, the source voltage V S11 V th2 does not reach the first differential voltage ΔV 11 is ΔV min As a result, it is possible to reliably operate the first current source 142, the second current source 144, or the current mirror pair 150. Therefore, according to the current sense amplifier 140 of this embodiment, 0≦V OUT ≦V IN In the range of L The sense current I SNS1 can be converted to

[0060] FIG. 4 shows the first offset current I OFF11 The output voltage V OUT 4 is a graph showing an example of a change in the output voltage V OUT The vertical axis represents the first offset current I OFF11 The second offset current I OFF12 The first offset current I OFF11 As shown in Figure 4, V OUT <V OUT1 In this case, the first offset current I OFF11 is not supplied (first offset current I OFF11 =0).

[0061] V OUT1 ≦V OUT ≦V IN So, the first offset current I OFF11 is V OUT increases linearly with increasing V OUT =V IN When , the maximum value I MAX As a result, as shown in Figure 3, V OUT1 ≦V OUT ≦V IN At source voltage V S11 V th1 The first offset current I OFF11 is V OUTBy gradually increasing the offset current I OFF1 Therefore, the influence of the supply of the voltage on the operation of the DC / DC converter 1 is suppressed.

[0062] In this embodiment, V OUT1 ≦V OUT ≦V IN In V OUT As the source voltage V S11 Although an example in which the first offset current I increases linearly has been shown, the present invention is not limited to this. For example, OFF11 is V OUT1 ≦V OUT ≦V IN In this case, the maximum value I MAX may be fixed at the output voltage V OUT The increase may be gradual (step-like) or curved as the temperature rises.

[0063] The DC / DC converter 1 and its current sense amplifier 140 according to this embodiment have been described above. The current sense amplifier 140 (current generating circuit) according to this embodiment has a first offset current source 146 and a second offset current source 148. The first offset current source 146 detects a first differential voltage ΔV between one end of the first current source 142 opposite to the first transistor MN1 and one end of the first transistor MN1 opposite to the first current source 142. 11 The first resistor R 11 The first offset current I OFF11 The second offset current source 148 supplies a second differential voltage ΔV between the end of the second current source 144 opposite to the second transistor MN2 and the end of the second transistor MN2 opposite to the second current source 144. 12 The second resistor R 12 The second offset current I OFF12 supply.

[0064] According to this configuration, the first differential voltage ΔV 11 and the second differential voltage ΔV 12 This prevents the sense resistor RSNS The voltage at one end of the sense element (output voltage V OUT ) changes (becomes larger), the first differential voltage ΔV 11 and the second differential voltage ΔV 12 As a result, a wider range of sense resistors R SNS Using the voltage at one end of the sense resistor R SNS The voltage V across R1 Sense current I according to SNS1 As a result, the sense resistor R SNS The voltage at one end of the IN Even if the sense resistor R SNS The inductor current I L The converted sense current I SNS1 can be generated.

[0065] 5 is a circuit diagram of a current sense amplifier 160 that can replace the current sense amplifier 140 according to this embodiment. The current sense amplifier 160 can be incorporated into the DC / DC converter 1 in place of the current sense amplifier 140 described above. The current sense amplifier 160 includes a first transistor MP1, a second transistor MP2, a sense transistor MPS, a first current source 162, a second current source 164, a first offset current source 166, a second offset current source 168, a first resistor R 21 and the second resistor R 22 It has.

[0066] The first transistor MP1 and the second transistor MP2 are each composed of the same type of P-channel MOS transistor. The first transistor MP1 and the second transistor MP2 form a current mirror pair 170. Specifically, the gate of the first transistor MP1 is connected to the drain of the first transistor MP1 in common with the gate of the second transistor MP2.

[0067] The first current source 162 supplies a first current I to the first transistor MP1.21 The second current source 164 supplies the second transistor MP2 with a second current I 22 where the first current I 21 The magnitude of the second current I 22 is the same as the magnitude of (I 21 =I 22 ).

[0068] 1st resistance R 21 is connected between one end of the first transistor MP1 opposite to the first current source 162 and the sense resistor R SNS Specifically, the first resistor R 21 One end of the resistor R is connected to the source of the first transistor MP1. 21 The other end is connected to a first node N1.

[0069] 2nd resistor R 22 is connected between one end of the second transistor MP2 opposite to the second current source 164 and the sense resistor R SNS Specifically, the second resistor R 22 One end of the first resistor R is connected to the source of the second transistor MP2, and the other end of the second transistor MP2 is connected to the second node N2. 21 The resistance of the second resistor R 22 The resistance value is the same as that of 21 =R 22 ).

[0070] The first offset current source 166 is connected between the source of the first transistor MP1 and the first resistor R 21 The first offset current source 166 is connected between the end of the first current source 162 opposite to the first transistor MP1 and the end of the first transistor MP1 opposite to the first current source 162. 21 (=V S21 ) to prevent the first resistor R 21 The first offset current I OFF21 supply.

[0071] In this embodiment, the first offset current source 166 is connected to a first resistor R21 The first offset current I OFF21 As a result, a first offset current I flows from the source of the transistor MP1 toward the first node N1. OFF21 is the first resistor R 21 The first offset current I OFF21 is the first resistor R 21 , which generates a first offset current I OFF21 Voltage according to (R 21 ×I OFF21 ) is the first resistor R 11 As a result, the source voltage V of the first transistor MP1 S21 is suppressed from becoming low, and the first differential voltage ΔV 21 The first differential voltage ΔV 21 Suppressing the decrease of the first differential voltage ΔV 21 and maintaining the magnitude of the first differential voltage ΔV 21 This also includes increasing the

[0072] The second offset current source 168 is connected between the source of the second transistor MP2 and the second resistor R 22 The second offset current source 168 is connected between the end of the second current source 164 opposite to the second transistor MP2 and the end of the second transistor MP2 opposite to the second current source 164. 22 (=V S22 ) to prevent the second resistor R 22 The second offset current I OFF22 supply.

[0073] In this embodiment, the second offset current source 168 is connected to a second resistor R 22 The second offset current I OFF22 As a result, a second offset current I flows from the source of the transistor MP2 toward the second node N2. OFF22 is the second resistor R 22 The second offset current I OFF22 is the second resistor R 22is supplied to generate a second offset current I OFF22 Voltage according to (R 22 ×I OFF22 ) is the second resistor R 22 As a result, the source voltage V of the second transistor MP2 S22 is suppressed from becoming low, and the second differential voltage ΔV 22 The second differential voltage ΔV 22 Suppressing the decrease of the second differential voltage ΔV 22 and maintaining the magnitude of the second differential voltage ΔV 22 This includes increasing the

[0074] The first offset current I OFF21 The magnitude of the second offset current I OFF22 is the same as the magnitude of (I OFF11 =I OFF12 ) below, the first offset current I OFF21 and the second offset current I OFF22 When there is no particular distinction between these, they are simply referred to as the "offset current I OFF2 The first offset current source 166 generates a first offset current I OFF21 The second offset current source 168 may be a variable current source configured to adjust the magnitude of the second offset current I OFF22 may be a variable current source configured to adjust the magnitude of

[0075] The sense transistor MPS is a P-channel MOS transistor. SNS The voltage V across R2 Sense current I according to SNS2 and generates a sense current I SNS2 the first resistor R 21 The sense transistor MPS according to this embodiment is provided to supply a voltage to the sense resistor R SNS The inductor current I L sense resistor R SNS The voltage V across R2 Depending on theSNS The inductor current I L A sense current I smaller than SNS2 Generate.

[0076] Sense current I SNS2 The magnitude of the sense current I in the current sense amplifier 140 is SNS1 Similarly, it is expressed by the following equation: I SNS2 =(R SNS / R 21 )×I L ···(3) From equation (2), (R SNS / R 21 ) to adjust the inductor current I L The converted sense current I SNS2 can be generated.

[0077] When the current sense amplifier 160 is used, V IN ≧V OUT ≥ 0, the inductor current I L The sense current I SNS1 The first offset current source 166 and the second offset current source 168 are respectively configured to convert the first offset current I OFF11 and the second offset current I OFF12 may be supplied.

[0078] The first offset current source 166 and the second offset current source 168 generate a first offset current I so that the first current source 162, the second current source 164, and the current mirror pair 170 can operate, respectively. OFF21 and the second offset current I OFF22 Specifically, the first current source 162 and the second current source 164 provide a first current I 11 and the second current I 12The first offset current I is set to a value that allows the current mirror pair 170 to operate (i.e., the first transistor MP1 and the second transistor MP2 are both in the saturation region) while ensuring the voltage required to supply the first and second transistors MP1 and MP2. OFF21 and the second offset current I OFF22 is supplied.

[0079] The first offset current source 166 and the second offset current source 168 each generate a first differential voltage ΔV 21 or the second differential voltage ΔV 22 is the threshold voltage ΔV th The first offset current I OFF21 and the second offset current I OFF22 may be supplied.

[0080] The advantages of the current sense amplifiers 140 and 160 according to this embodiment become clearer when compared with comparative techniques.

[0081] 6 is a block diagram of a current detection circuit 900 according to a comparative technique. In the following, the current detection circuit 900 according to the comparative technique is provided in place of the current sense amplifier 140 of the DC / DC converter 1, and the sense resistor R SNS The inductor current I L Sense current I according to SNS9 The current detection circuit 900 according to the comparison technique includes a NOT circuit 920, a first current sense amplifier 940, and a second current sense amplifier 960.

[0082] The current detection circuit 900 is configured such that one of the first current sense amplifier 940 and the second current sense amplifier 960 is enabled and the other is disabled. The first current sense amplifier 940 is controlled by a NOT circuit 920 in response to a control signal S SW1 The control signal S generated by inverting SW2 The second current sense amplifier 960 is enabled by an externally input control signal S SW1 Enabled by

[0083] Specifically, the threshold voltage is V th9 As such, 0≦V OUT <V th9 The first current sense amplifier 940 is enabled at V th9 ≦V OUT ≦V IN The second current sense amplifier 960 is enabled at 0≦V. OUT <V th9 In this case, the inductor current I L Sense current I according to SNS91 The second current sense amplifier 960 generates V th9 ≦V OUT ≦V IN In this case, the inductor current I L Sense current I according to SNS92 Generates a sense current I SNS91 ,I SNS92 is the sense current I of the current detection circuit 900. SNS9 is output as

[0084] 7 is a circuit diagram of a first current sense amplifier 940 according to the comparative technique. The first current sense amplifier 940 according to the comparative technique has substantially the same configuration as the current sense amplifier 140 according to the present embodiment, excluding the first offset current source 146 and the second offset current source 148. Therefore, in the first current sense amplifier 940, the first resistor R 11 and the second resistor R 12 offset current I OFF1 cannot supply.

[0085] Output voltage V OUT As the first resistor R 11 The voltage V at one end of 91 When the input voltage V IN and voltage V 91 Difference voltage ΔV 91 This makes it impossible to operate the first current source 142, the second current source 144, and the current mirror pair 150, and the sense current I SNS91Therefore, in the comparison technique, the first current sense amplifier 940 alone cannot generate a voltage between 0 and V OUT ≦V IN The sense current I SNS91 cannot be generated properly, and the second current sense amplifier 960 is required.

[0086] 8 is a circuit diagram of a second current sense amplifier 960 according to the comparative technique. The second current sense amplifier 960 according to the comparative technique has substantially the same configuration as the alternative current sense amplifier 160 according to the present embodiment, except that the first offset current source 166 and the second offset current source 168 are removed.

[0087] The second current sense amplifier 960 according to the comparative technique is a current sense amplifier that senses the sense current I SNS91 The output voltage V cannot be generated properly. OUT For the range of inductor current I L Sense current I according to SNS92 Specifically, the second current sense amplifier 960 generates the sense current I SNS91 V includes a range where it cannot be generated. th9 ≦V OUT ≦V IN The sense current I SNS92 Generate.

[0088] In the current detection circuit 900 according to the comparative technique, the two current sense amplifiers, the first current sense amplifier 940 and the second current sense amplifier 960, are connected to each other via a resistor R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R59, R60, R61, R6 OUT The sense current I SNS9 is generated.

[0089] 9 is a timing chart showing the results of simulating the operation of the DC / DC converter according to the comparative technology. From the top, the output voltage V OUT9 , the control signal S of the current detection circuit 900 SW1 , sense voltage V SNS9 and a pulse signal S for driving the output stage 22. P9The sense voltage V SNS9 is the sense current I SNS9 This is the voltage generated across a resistor (not shown) used for current detection when a current flows through the resistor. The sense voltage V SNS1 The inductor current I L is assumed to be constant at all times.

[0090] As shown in FIG. 9, at timing t1, the control signal S SW1 switches from low to high, and the enabled current sense amplifier switches from the second current sense amplifier 960 to the first current sense amplifier 940. At the time of this switching, the sense voltage V SNS9 Noise NOISE1 occurs.

[0091] Before and after timing t1, the sense voltage V SNS9 The magnitude of the sense voltage V SNS9 is roughly the sense voltage V SNS9 After the timing t1, the sense voltage V SNS9 is roughly the sense voltage V SNS9 Therefore, in the comparison technique, the inductor current I L The sense current I SNS9 changes.

[0092] This is thought to be because the first current sense amplifier 940 uses N-channel MOS transistors (first transistor MN1 and second transistor MN2), while the second current sense amplifier 960 uses P-channel MOS transistors (first transistor MP1 and second transistor MP2), and there is variation in the characteristics of the MOS transistors used in the two current sense amplifiers. L flows, and the same voltage flows across the sense resistor R SNS Even if the sense current I SNS91 ,I SNS92 will be different.

[0093] The DC / DC converter senses the current I SNS91 ,I SNS92 Since it operates by receiving feedback of the pulse signal S P9 The duty ratio of the output voltage V OUT9 affects the output voltage V OUT9 is gradually declining.

[0094] 10 is a timing chart showing an example of the results of simulating the operation of the DC / DC converter 1 according to this embodiment. OUT , the control signal S of the current sense controller 180 CON , sense voltage V SNS1 and a pulse signal S for driving the output stage 22. P The inductor current I L is assumed to be constant at all times.

[0095] Before timing t2, the offset current I OFF1 is not provided (I OFF1 At timing t2, the control signal S CON switches from low to high, and the offset current I OFF1 At this time, the offset current I OFF1 The magnitude of is constant from timing t2 onwards.

[0096] At timing t2, the sense voltage V SNS1 Although noise NOISE2 occurs in the sense voltage V SNS1 There is no change in the magnitude of the pulse signal S P The duty ratio of the output voltage V is also stable at time t2. OUT is also stable.

[0097] According to the DC / DC converter 1 of this embodiment, the voltage V ≤ V is detected by a single current sense amplifier 140 without switching between two current sense amplifiers as in the comparative technology. OUT ≦V IN The sense current I SNS1 Therefore, unlike the comparison technology, there is no effect on the operation of the DC / DC converter due to switching between two current sense amplifiers. OFF1 The sense voltage V SNS1 It was also confirmed that the effect on the offset current I OFF1 If the magnitude of the offset current I is suddenly changed, NOISE2 may occur. However, as explained with reference to FIGS. OFF1 It is also possible to prevent NOISE2 from being generated by gradually changing the magnitude of

[0098] (First Modification) FIG. 11 shows the sense current I SNS3 In the first modification, the inductor current I is detected by a method called DCR (Direct Current Resistance) detection. L The converted sense current I SNS3 This section explains how to generate the

[0099] In the first modification, the sense resistor R connected in series to the inductor L1 in the above embodiment is SNS Instead, a resistor R 31 and the sense capacitor C SNS (sense element) is connected in parallel to the inductor L1. 31 The sense capacitor C SNS The other end of the sense capacitor C is connected to the other end of the inductor L1 on the output stage 22 side. SNS Resistance R 31 The other end of the sense capacitor C is connected to the other end of the inductor L1. SNS The inductor current I L1 Voltage V according to Coccurs.

[0100] The two input terminals of the current sense amplifier 140 are connected to the sense capacitor C SNS One end (node ​​N3) of the sense capacitor C SNS This allows the current sense amplifier 140 to detect the voltage V C Sense current I according to SNS3 Therefore, the current sense amplifier 140 can generate the inductor current I L The converted sense current I SNS3 Instead of the current sense amplifier 140, the ground and the output voltage V OUT A current sense amplifier 160 using the differential voltage between

[0101] (Second Modification) In the above embodiment, an example has been described in which the transistors (first transistors MN1, MP1, second transistors MN2, MP2, and sense transistors MNS, MPS) included in the current sense amplifiers 140, 160 are MOS transistors. However, the current sense amplifiers may include bipolar transistors instead of MOS transistors.

[0102] (supplement) Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. Furthermore, not only the embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention.

[0103] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0104] (Item 1) a first transistor; a second transistor of the same type as the first transistor and forming a current mirror pair with the first transistor; a first current source that supplies a first current to the first transistor; a second current source that supplies a second current to the second transistor; a first resistor provided between one end of the first transistor opposite to the first current source and one end of a sense element; a second resistor provided between one end of the second transistor opposite to the second current source and the other end of the sense element; a sense transistor configured to generate a sense current corresponding to a voltage across the sense element and to supply the sense current to the first resistor; a first offset current source that supplies a first offset current to the first resistor so as to suppress a first differential voltage between one end of the first current source opposite to the first transistor and one end of the first transistor opposite to the first current source from becoming small; a second offset current source that supplies a second offset current to the second resistor so as to suppress a second differential voltage between one end of the second current source opposite to the second transistor and one end of the second transistor opposite to the second current source from becoming small; a gate of the first transistor and a gate of the second transistor are connected in common to a source of the first transistor; the magnitude of the first current is the same as the magnitude of the second current; The resistance value of the first resistor is the same as the resistance value of the second resistor; The magnitude of the first offset current is the same as the magnitude of the second offset current. Current generation circuit.

[0105] (Item 2) the first offset current source and the second offset current source respectively supply the first offset current and the second offset current so that the first current source, the second current source, and the current mirror pair can operate; Item 1. The current generating circuit according to item 1.

[0106] (Item 3) the first offset current source and the second offset current source supply the first offset current and the second offset current, respectively, in response to the first differential voltage or the second differential voltage becoming equal to or lower than a threshold voltage. Item 3. The current generating circuit according to item 1 or 2.

[0107] (Item 4) the first offset current source and the second offset current source increase the first offset current and the second offset current, respectively, in response to an increase in voltage at one end of the sense element; Item 3. The current generating circuit according to item 3.

[0108] (Item 5) the sense element is a sense resistor; the sense transistor generates a sense current smaller than the current flowing through the sense resistor in response to a voltage across the sense resistor generated by the current flowing through the sense resistor; 5. A current generating circuit according to any one of items 1 to 4.

[0109] (Item 6) A DC / DC converter that generates an output voltage by stepping down an input voltage, an error amplifier that generates an error signal by amplifying an error between a feedback voltage of the output voltage and a reference voltage; A current generating circuit according to any one of items 1 to 5; a comparator that compares a periodic ramp signal generated based on the sense current with the error signal to generate a pulse modulated signal; an output stage including a high-side transistor and a low-side transistor that operates in response to the pulse-modulated signal; an inductor provided between the high-side transistor and the low-side transistor and an output terminal of the DC / DC converter; the sense transistor generates the sense current based on a voltage generated across the sense element in response to a current flowing through the inductor. DC / DC converter.

[0110] (Item 7) The voltage at one end of the sense element is the output voltage. Item 6. The DC / DC converter according to item 6. [Explanation of symbols]

[0111] 1 DC / DC converter, 10 semiconductor circuit, 20 peripheral circuit, 22 output stage, 100 analog block, 102 error amplifier, 104 comparator, 110 logic circuit, 112 flip-flop circuit, 114 oscillator, 120 driver, 140, 160 current sense amplifier, 142, 162 first current source, 144, 164 second current source, 146, 166 first offset current source, 148, 168 second offset current source, 180 current sense controller, MH high-side transistor, ML low-side transistor, MN1, MP1 first transistor, MN2, MP2 second transistor, MNS, MPS sense transistor, R1, R2 resistor, R 11 ,R 21 1st resistance, R 12 ,R 22 2nd resistance, R SNS Sense resistor, L1: inductor, C1 capacitor.

Claims

1. a first transistor; a second transistor of the same type as the first transistor and forming a current mirror pair with the first transistor; a first current source that supplies a first current to the first transistor; a second current source that supplies a second current to the second transistor; a first resistor provided between one end of the first transistor opposite to the first current source and one end of a sense element; a second resistor provided between one end of the second transistor opposite to the second current source and the other end of the sense element; a sense transistor configured to generate a sense current corresponding to a voltage across the sense element and to supply the sense current to the first resistor; a first offset current source that supplies a first offset current to the first resistor so as to suppress a first differential voltage between one end of the first current source opposite to the first transistor and one end of the first transistor opposite to the first current source from becoming small; a second offset current source that supplies a second offset current to the second resistor so as to suppress a second differential voltage between one end of the second current source opposite to the second transistor and one end of the second transistor opposite to the second current source from becoming small; a gate of the first transistor and a gate of the second transistor are connected in common to a source of the first transistor; the magnitude of the first current is the same as the magnitude of the second current; The resistance value of the first resistor is the same as the resistance value of the second resistor, The magnitude of the first offset current is the same as the magnitude of the second offset current. Current generation circuit.

2. the first offset current source and the second offset current source respectively supply the first offset current and the second offset current so that the first current source, the second current source, and the current mirror pair can operate; The current generating circuit according to claim 1 .

3. the first offset current source and the second offset current source supply the first offset current and the second offset current, respectively, in response to the first differential voltage or the second differential voltage becoming equal to or lower than a threshold voltage. The current generating circuit according to claim 1 .

4. the first offset current source and the second offset current source increase the first offset current and the second offset current, respectively, in response to an increase in voltage at one end of the sense element; The current generating circuit according to claim 3 .

5. the sense element is a sense resistor; the sense transistor generates a sense current smaller than the current flowing through the sense resistor in response to a voltage across the sense resistor generated by the current flowing through the sense resistor; The current generating circuit according to claim 1 .

6. A DC / DC converter that generates an output voltage by stepping down an input voltage, an error amplifier that generates an error signal by amplifying an error between a feedback voltage of the output voltage and a reference voltage; A current generating circuit according to any one of claims 1 to 5; a comparator that compares a periodic ramp signal generated based on the sense current with the error signal to generate a pulse modulated signal; an output stage including a high-side transistor and a low-side transistor that operates in response to the pulse-modulated signal; an inductor provided between the high-side transistor and the low-side transistor and an output terminal of the DC / DC converter; the sense transistor generates the sense current based on a voltage generated across the sense element in response to a current flowing through the inductor. DC / DC converter.

7. The voltage at one end of the sense element is the output voltage.

7. The DC / DC converter according to claim 6.

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