Semiconductor device

Abstract

To improve the electrical characteristics of a semiconductor device.SOLUTION: The semiconductor device 1 includes an RC-IGBT chip 10 including a gate electrode 10G, a collector electrode, and an emitter electrode 10E, and an SiC-SBD chip 8 including a cathode electrode electrically connected to the collector electrode and an anode electrode 8A electrically connected to the emitter electrode 10E.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a reverse conducting-insulating gate bipolar transistor (RC-IGBT). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-120990

[0004] [overview] There is a demand for improvements in the electrical characteristics of semiconductor devices.

[0005] A semiconductor device according to one embodiment of the present disclosure includes an RC-IGBT chip including a gate electrode, a collector electrode, and an emitter electrode, and an SiC-SBD chip including a cathode electrode electrically connected to the collector electrode and an anode electrode electrically connected to the emitter electrode. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic perspective view of an exemplary semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic perspective view of the semiconductor device of FIG. 1 as viewed from a different direction. [Figure 3] FIG. 3 is a schematic plan view showing the internal structure of the semiconductor device of FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a circuit diagram schematically showing the circuit configuration of the semiconductor device of FIG. [Figure 6] FIG. 6 is a schematic plan view showing the RC-IGBT chip of the first embodiment. [Figure 7] FIG. 7 is a schematic plan view showing an example of the layout of the RC-IGBT chip of FIG. [Figure 8] FIG. 8 is a schematic plan view showing an example of the layout of the RC-IGBT chip of FIG. [Figure 9] FIG. 9 is a schematic plan view showing an enlarged area A of FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view of the RC-IGBT chip taken along line F10-F10 in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view of the RC-IGBT chip taken along line F11-F11 in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of the RC-IGBT chip taken along line F12-F12 in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view of the RC-IGBT chip taken along line F13-F13 in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing an example of the configuration of the SiC-SBD chip of FIG. [Figure 15] FIG. 15 is a graph showing the electric field strength in the outer peripheral region when a predetermined collector-emitter voltage is applied. [Figure 16] FIG. 16 is a graph showing the current-voltage characteristics of the RC-IGBT chip and the SiC-SBD chip. [Figure 17] FIG. 17 is a graph showing the relationship between the forward voltage and the peak surge current. [Figure 18] FIG. 18 is a schematic cross-sectional view showing the structure of an RC-IGBT chip in a semiconductor device of the comparative example. [Figure 19] FIG. 19 is a graph showing the relationship between the forward voltage and the forward current in the semiconductor device of the comparative example and the semiconductor device of the first embodiment. [Figure 20]FIG. 20 is a schematic cross-sectional view showing a cross-sectional structure of a peripheral portion of an exemplary RC-IGBT chip according to the second embodiment. [Figure 21] FIG. 21 is a graph showing the current-voltage characteristics of the RC-IGBT chip and the SiC-SBD chip of the second embodiment. [Figure 22] FIG. 22 is a graph showing the relationship between the forward current and the forward voltage depending on the arrangement position of the cathode region in the semiconductor device of the third embodiment. [Figure 23] FIG. 23 is a graph showing the relationship between the position of the cathode region and the forward current of the diode. [Figure 24] FIG. 24 is a graph showing the relationship between the position of the cathode region and the forward current of the diode. [Figure 25] FIG. 25 is a graph showing the relationship between peak surge current and forward voltage when the position of the cathode region is adjusted. [Figure 26] FIG. 26 is a schematic cross-sectional view showing the structure of the peripheral portion of the RC-IGBT chip including the cathode region of the first layout example according to the third embodiment. [Figure 27] FIG. 27 is a schematic cross-sectional view showing the structure of the peripheral portion of the RC-IGBT chip including the cathode region in the second layout example according to the third embodiment. [Figure 28] FIG. 28 is a schematic cross-sectional view showing the structure of the peripheral portion of the RC-IGBT chip of the modified example. [Figure 29] FIG. 29 is a schematic cross-sectional view showing the structure of the peripheral portion of the RC-IGBT chip of the modified example. [Figure 30] FIG. 30 is a schematic cross-sectional view showing the structure of the peripheral portion of the RC-IGBT chip of the modified example. [Figure 31] FIG. 31 is a graph showing peak surge currents in Experimental Examples 1 to 4. As shown in FIG. [Figure 32] FIG. 32 is a schematic cross-sectional view showing the structure of a SiC-SBD chip. [Figure 33] FIG. 33 is a schematic perspective view showing a configuration of a semiconductor device according to a modified example. [Figure 34] FIG. 34 is a schematic plan view showing the internal structure of the first discrete semiconductor of FIG. [Figure 35] FIG. 35 is a schematic plan view showing the internal structure of the second discrete semiconductor of FIG.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] Terms such as "first," "second," and "third" are used in this disclosure merely to label and are not necessarily intended to dictate any ordering of their objects. The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0011] First Embodiment [Schematic configuration of semiconductor device] The configuration of a semiconductor device 1 including an RC-IGBT chip 10 and a SiC-SBD chip 8 according to a first embodiment will be described with reference to FIGS. 1 to 5. FIG. 1 schematically shows a perspective structure of the semiconductor device 1. FIG. 2 schematically shows a perspective structure of the semiconductor device 1 viewed from a different direction than that of FIG. 1. FIG. 3 schematically shows a planar structure of the interior of the semiconductor device 1. FIG. 4 schematically shows a cross-sectional structure of the semiconductor device 1 taken along line F4-F4 in FIG. 3. FIG. 5 schematically shows a circuit configuration of the semiconductor device 1. In FIG. 3, a sealing resin 2 (described later) is shown by a two-dot chain line to show the internal structure of the semiconductor device 1.

[0012] As shown in FIGS. 1 to 4, the semiconductor device 1 is a module in which an RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) and a freewheeling diode are housed in a single package. The freewheeling diode is also called a freewheeling diode. As shown in FIG. 5, the semiconductor device 1 includes a configuration in which a freewheeling diode 1B is connected in anti-parallel to an RC-IGBT 1A. More specifically, the RC-IGBT 1A includes an IGBT 1AA and a diode 1AB connected in anti-parallel to the IGBT 1AA. This diode 1AB is a freewheeling diode built into the RC-IGBT 1A. The freewheeling diode 1B connected in anti-parallel to the RC-IGBT 1A is a diode provided external to the RC-IGBT 1A.

[0013] As shown in FIGS. 1 and 2, the semiconductor device 1 of the first embodiment is a three-terminal TO (Transistor Outline) package, specifically a TO-247 package. The semiconductor device 1 includes a sealing resin 2. The sealing resin 2 is made of, for example, a molded resin. A material for the sealing resin 2, for example, a black epoxy resin, is used. In one example, the sealing resin 2 has a rectangular parallelepiped shape with the Z direction as its thickness direction. Here, two mutually orthogonal directions among directions orthogonal to the Z direction are referred to as the "X direction" and the "Y direction," respectively. In the following description, "plan view" means viewing the semiconductor device 1 or components of the semiconductor device 1 from the Z direction.

[0014] The package structure of the semiconductor device 1 is not limited to a TO-type package and can be changed as desired. The semiconductor device 1 may be configured as various packages such as an SOP (Small Outline Package), a QFN (Quad For Non-Lead Package), a DFP (Dual Flat Package), a DIP (Dual Inline Package), a QFP (Quad Flat Package), a SIP (Single Inline Package), or an SOJ (Small Outline J-leaded Package), or similar. These packages differ from the TO-type package in the shape of the sealing resin 2 and the structure of the lead terminals, but their basic structure (including the electrical structure) is the same as that of the TO-type package.

[0015] The sealing resin 2 includes an upper sealing surface 2S, a lower sealing surface 2R opposite to the upper sealing surface 2S, and first to fourth sealing side surfaces 2A to 2D connecting the upper sealing surface 2S and the lower sealing surface 2R. The upper sealing surface 2S has a quadrangular shape in a plan view. In one example, the upper sealing surface 2S has a rectangular shape with its longer sides in the Y direction and its shorter sides in the X direction. The first sealing side surface 2A and the second sealing side surface 2B constitute both end surfaces of the sealing resin 2 in the Y direction, and the third sealing side surface 2C and the fourth sealing side surface 2D constitute both end surfaces of the sealing resin 2 in the X direction.

[0016] The sealing resin 2 includes a through hole 2E and openings 2F and 2G that expose a metal plate 4 (described later) when viewed from the sealing top surface 2S. The through hole 2E penetrates the sealing resin 2 in the Z direction. The through hole 2E is provided in the sealing resin 2 closer to the second sealing side surface 2B in the Y direction. The openings 2F and 2G are provided at the same position as the through hole 2E in the Y direction. The opening 2F is provided closer to the third sealing side surface 2C than the through hole 2E in the X direction, and the opening 2G is provided closer to the fourth sealing side surface 2D than the through hole 2E in the X direction. The opening 2F is provided from the sealing top surface 2S to the third sealing side surface 2C. The opening 2F has a curved concave shape that opens toward the third sealing side surface 2C in a plan view. The opening 2G is provided from the sealing top surface 2S to the fourth sealing side surface 2D. The opening 2G has a curved concave shape that opens toward the fourth sealing side surface 2D in a plan view.

[0017] 3, the semiconductor device 1 includes a metal plate 4, a first lead 6A, and a second lead 6B that are partially sealed in sealing resin 2, and an RC-IGBT chip 10 and a SiC-SBD chip 8 that are also sealed in sealing resin 2. The RC-IGBT chip 10 includes an RC-IGBT 1A shown in FIG. 5. The SiC-SBD chip 8 includes a free wheel diode 1B shown in FIG. 5.

[0018] The metal plate 4 is flat and has a thickness in the Z direction. The metal plate 4 is made of a material containing at least one of copper (Cu), iron (Fe), and aluminum (Al). The metal plate 4 includes a die pad 4A and leads 4B. The die pad 4A and leads 4B are, for example, integrated. The die pad 4A is provided so as to overlap the sealing upper surface 2S in plan view. The leads 4B include a portion that protrudes in the Y direction from the first sealing side surface 2A in plan view.

[0019] The die pad 4A has a quadrangular shape in plan view. In the first embodiment, the die pad 4A has a rectangular shape with its long sides in the Y direction and its short sides in the X direction in plan view. A part of the end of the die pad 4A closer to the third sealing side surface 2C in the X direction is exposed through the opening 2F of the sealing resin 2. A part of the end of the die pad 4A closer to the fourth sealing side surface 2D in the X direction is exposed through the opening 2G of the sealing resin 2. As shown in FIG. 2, the die pad 4A is exposed from the sealing lower surface 2R.

[0020] The die pad 4A includes a through hole 4C that penetrates the die pad 4A in the Z direction. The through hole 4C is in communication with the through hole 2E of the sealing resin 2. The diameter of the through hole 2E of the sealing resin 2 is smaller than the diameter of the through hole 4C of the die pad 4A. In other words, the sealing resin 2 is provided on the inner surface that defines the through hole 4C of the die pad 4A.

[0021] The lead 4B is connected to the center of the die pad 4A in the X direction and to an end portion closer to the first sealing side surface 2A in the Y direction. The lead 4B protrudes from the center of the first sealing side surface 2A in the X direction in a plan view. The lead 4B constitutes an external terminal of the semiconductor device 1.

[0022] The first lead 6A and the second lead 6B are disposed on both sides of the lead 4B in the X direction in a plan view. The first lead 6A is disposed closer to the third sealing side surface 2C than the lead 4B, and the second lead 6B is disposed closer to the fourth sealing side surface 2D than the lead 4B. Both the first lead 6A and the second lead 6B are made of a material containing at least one of Cu, Fe, and Al. In one example, both the first lead 6A and the second lead 6B may be made of the same material as the metal plate 4. Both the first lead 6A and the second lead 6B protrude in the Y direction from the first sealing side surface 2A in a plan view. Both the first lead 6A and the second lead 6B constitute external terminals of the semiconductor device 1. A plating film made of a metal having high affinity (bonding strength) for solder may be provided on the outer surfaces of the lead 4B, the first lead 6A, and the second lead 6B. The plating film may include at least one of a nickel (Ni) plating film, a palladium (Pd) plating film, and a gold (Au) plating film.

[0023] The RC-IGBT chip 10 and the SiC-SBD chip 8 are individually provided semiconductor chips. Both the RC-IGBT chip 10 and the SiC-SBD chip 8 are mounted on a die pad 4A of a metal plate 4. More specifically, as shown in FIG. 4 , both the RC-IGBT chip 10 and the SiC-SBD chip 8 are bonded to the die pad 4A by a conductive bonding material SD.

[0024] As shown in FIG. 3 , both the RC-IGBT chip 10 and the SiC-SBD chip 8 are arranged in the die pad 4A closer to the first sealing side surface 2A than the through hole 4C in the Y direction. In other words, both the RC-IGBT chip 10 and the SiC-SBD chip 8 are arranged in the die pad 4A closer to the first lead 6A and the second lead 6B than the through hole 4C in the Y direction. The RC-IGBT chip 10 and the SiC-SBD chip 8 are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The RC-IGBT chip 10 is arranged in the die pad 4A closer to the third sealing side surface 2C in the X direction. In other words, the RC-IGBT chip 10 is arranged in the die pad 4A closer to the first lead 6A in the X direction. The SiC-SBD chip 8 is arranged in the die pad 4A closer to the fourth sealing side surface 2D in the X direction. In other words, the SiC-SBD chip 8 is disposed on the die pad 4A closer to the second lead 6B in the X direction.

[0025] The RC-IGBT chip 10 includes a gate electrode 10G, an emitter electrode 10E, and a collector electrode 10C (see FIG. 4). The gate electrode 10G and the emitter electrode 10E are exposed from a first surface of the RC-IGBT chip 10. The collector electrode 10C is provided on a second surface of the RC-IGBT chip 10 opposite the first surface. The second surface is the surface of the RC-IGBT chip 10 facing the die pad 4A. The collector electrode 10C is electrically connected to the die pad 4A by a conductive bonding material SD. The gate electrode 10G is electrically connected to the first lead 6A by a wire WA. The emitter electrode 10E is electrically connected to the second lead 6B by a wire WB. For example, a plurality of wires WB may be provided. In the example shown in FIG. 3, the emitter electrode 10E is electrically connected to the second lead 6B by two wires WB.

[0026] The gate connection member connecting the gate electrode 10G and the first lead 6A is not limited to the wire WA, but may be a ribbon, a clip, etc. The emitter connection member connecting the emitter electrode 10E and the second lead 6B is not limited to the wire WB, but may be a ribbon, a clip, etc.

[0027] The SiC-SBD chip 8 includes an anode electrode 8A and a cathode electrode 8K (see FIG. 4). The anode electrode 8A is exposed from a first surface of the SiC-SBD chip 8. The cathode electrode 8K is provided on a second surface of the SiC-SBD chip 8, which is opposite to the first surface. The second surface is the surface of the SiC-SBD chip 8 that faces the die pad 4A. The cathode electrode 8K is electrically connected to the die pad 4A by a conductive bonding material SD (see FIG. 4). The cathode electrode 8K is electrically connected to the second lead 6B by a wire WC. Note that the cathode connecting member that connects the cathode electrode 8K and the second lead 6B is not limited to the wire WC and may be a ribbon, a clip, or the like.

[0028] In this way, since the collector electrode 10C and the anode electrode 8A are electrically connected to the die pad 4A, the lead 4B connected to the die pad 4A also serves as the collector terminal and the anode terminal of the semiconductor device 1. Since the gate electrode 10G is electrically connected to the first lead 6A, the first lead 6A constitutes the gate terminal of the semiconductor device 1. Since the emitter electrode 10E and the cathode electrode 8K are electrically connected to the second lead 6B, the second lead 6B also serves as the emitter terminal and the cathode terminal of the semiconductor device 1. The detailed configuration of the SiC-SBD chip 8 will be described later.

[0029] [Configuration of semiconductor device] The overall configuration of the RC-IGBT chip 10 of the first embodiment will be described with reference to FIGS. 6 to 13. FIG. 6 schematically shows the planar structure of the RC-IGBT chip 10 of the first embodiment. FIG. 7 schematically shows an example of the layout of various wirings of the RC-IGBT chip 10 of FIG. 6. FIG. 8 schematically shows an example of the layout of a well region 54, a plurality of field regions 56, and gate line wiring 70, which will be described later. Note that FIG. 7 omits a cathode region 110, a field electrode 102, and a channel stop electrode 106, which will be described later. Also, for convenience, FIG. 8 collectively shows a plurality of field regions 56 as a single region.

[0030] FIG. 9 shows an enlarged view of region A in FIG. 8. FIG. 10 schematically shows a cross-sectional structure of the RC-IGBT chip 10 taken along line F10-F10 in FIG. 9. FIG. 11 schematically shows a cross-sectional structure of the RC-IGBT chip 10 taken along line F11-F11 in FIG. 9. FIG. 12 schematically shows a cross-sectional structure of the RC-IGBT chip 10 taken along line F12-F12 in FIG. 9. FIG. 13 schematically shows a cross-sectional structure of the peripheral portion of the RC-IGBT chip 10.

[0031] 6 to 9, the RC-IGBT chip 10 is an RC-IGBT semiconductor device having an RC-IGBT that integrally includes an IGBT and a diode, as described above. The diode is a freewheeling diode for the IGBT. Such an RC-IGBT semiconductor device may also be called a semiconductor switching device.

[0032] As shown in FIG. 6, the RC-IGBT chip 10 includes a hexahedral chip 12. The chip 12 can also be said to be formed in a flat plate shape with the Z direction as its thickness direction. The chip 12 may also be referred to as a "semiconductor chip." In the first embodiment, the chip 12 has a single-layer structure made of a silicon single crystal substrate (semiconductor substrate). The chip 12 has a first main surface 12A, a second main surface 12B (see FIG. 10) opposite the first main surface 12A, and first to fourth side surfaces 12C to 12F connecting the first main surface 12A and the second main surface 12B. Both the first main surface 12A and the second main surface 12B are formed in a quadrangular shape in a plan view. The first side surface 12C and the second side surface 12D constitute both end surfaces of the chip 12 in the Y direction. Both the first side surface 12C and the second side surface 12D extend in the X direction in a plan view. The third side surface 12E and the fourth side surface 12F constitute both end surfaces in the X direction of the chip 12. Both the third side surface 12E and the fourth side surface 12F extend in the Y direction in a plan view.

[0033] As shown in FIG. 7, the RC-IGBT chip 10 includes an IGBT region 14 provided in an inner portion of the first main surface 12A. The IGBT region 14 is a region having an IGBT structure and may be referred to as an "active region." In one example, the IGBT region 14 is formed in a polygonal shape having four sides parallel to the first to fourth side surfaces 12C to 12F in a plan view. In the example shown in FIG. 7, the IGBT region 14 includes a recess that is recessed from the center in the Y direction of the side along the third side surface 12E toward the fourth side surface 12F in a plan view. The recess is recessed in a polygonal shape in a plan view. In the example shown in FIG. 7, the recess is recessed in a quadrangular shape in a plan view.

[0034] The RC-IGBT chip 10 includes a pad region 16 provided in a region defined by recesses in the IGBT region 14 on the first main surface 12A, and an outer periphery region 18 provided on the periphery of the chip 12. The pad region 16 is formed in a polygonal shape in a plan view. In the example shown in FIG. 7, the pad region 16 is formed in a quadrangular shape in a plan view. The outer periphery region 18 is provided in an annular shape extending along the first to fourth side surfaces 12C to 12F so as to surround the IGBT region 14 in a plan view. In the example shown in FIG. 7, the outer periphery region 18 is formed in a quadrangular annular shape in a plan view. A portion of the outer periphery region 18 extending along the third side surface 12E is connected to the pad region 16. It can be said that the IGBT region 14 is provided inside the outer periphery region 18 on the first main surface 12A.

[0035] As shown in Fig. 10, the RC-IGBT chip 10 includes an n-type (second conductivity type) drift region 20 formed inside the chip 12. The drift region 20 is formed throughout the entire interior of the chip 12. In the first embodiment, the chip 12 is made of an n-type semiconductor substrate (an n-type semiconductor chip). The drift region 20 is formed by utilizing the chip 12.

[0036] The RC-IGBT chip 10 includes an n-type buffer region 22 formed in a surface layer portion of the second main surface 12B. In the first embodiment, the buffer region 22 is formed in a layer shape extending along the entire area of ​​the second main surface 12B. The buffer region 22 is exposed from the first to fourth side surfaces 12C to 12F (see FIG. 7). The buffer region 22 has a higher n-type impurity concentration than the drift region 20. The presence or absence of the buffer region 22 is optional, and a configuration without the buffer region 22 may also be employed.

[0037] The RC-IGBT chip 10 includes a p-type (first conductivity type) collector region 24 formed in a surface layer portion of the second main surface 12B. The collector region 24 is formed in a surface layer portion on the second main surface 12B side of the buffer region 22. In the first embodiment, the collector region 24 is formed in a layer shape extending along the second main surface 12B over substantially the entire area of ​​the second main surface 12B.

[0038] The RC-IGBT chip 10 includes a trench isolation structure 26 formed in the first main surface 12A so as to partition the IGBT region 14. A gate potential is applied to the trench isolation structure 26. The trench isolation structure 26 surrounds the IGBT region 14 and separates the IGBT region 14 from the peripheral region 18 and the pad region 16 (see FIG. 2). In the first embodiment, the trench isolation structure 26 is formed in a polygonal ring shape having four sides parallel to the first to fourth side surfaces 12C to 12F in a plan view.

[0039] The trench isolation structure 26 may have a width of 0.5 μm or more and 5 μm or less. Here, the width of the trench isolation structure 26 can be defined by the dimension in a direction perpendicular to the direction in which the trench isolation structure 26 extends in a plan view. The width of the trench isolation structure 26 is preferably 1 μm or more and 2.5 μm or less. The trench isolation structure 26 may have a depth of 1 μm or more and 20 μm or less. Here, the depth of the trench isolation structure 26 can be defined by the dimension in the Z direction of the trench isolation structure 26, in other words, the distance in the Z direction between the first main surface 12A and the bottom wall of an isolation trench 28 described below. The depth of the trench isolation structure 26 is preferably 4 μm or more and 10 μm or less.

[0040] The trench isolation structure 26 includes an isolation trench 28, an isolation insulating film 30, and an isolation buried electrode 32. The isolation trench 28 is dug downward from the first main surface 12A toward the second main surface 12B, and defines the wall surface of the trench isolation structure 26. The isolation insulating film 30 is formed in the shape of a film along the wall surface of the isolation trench 28. The isolation insulating film 30 defines a recess space within the isolation trench 28.

[0041] The isolation insulating film 30 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The isolation insulating film 30 preferably has a single-layer structure made of a single insulating film. It is particularly preferable that the isolation insulating film 30 includes a silicon oxide film made of an oxide of the chip 12.

[0042] The isolated buried electrode 32 is buried in the isolation trench 28 with the isolation insulating film 30 sandwiched therebetween. In the first embodiment, the isolated buried electrode 32 is made of conductive polysilicon. A gate potential is applied to the isolated buried electrode 32.

[0043] The RC-IGBT chip 10 includes an IGBT structure 34 formed in the IGBT region 14. The IGBT structure 34 may also be referred to as a "FET (Field Effect Transistor) structure." The IGBT structure 34 includes a p-type base region 36 formed in a surface layer portion of the first main surface 12A in the IGBT region 14. The base region 36 may also be referred to as a "body region" or a "channel region." The base region 36 is formed shallower than the trench isolation structure 26. That is, the base region 36 has a bottom located closer to the first main surface 12A than the bottom wall of the trench isolation structure 26. The base region 36 extends in a layered manner along the first main surface 12A. The base region 36 is in contact with the inner circumferential wall of the trench isolation structure 26.

[0044] The IGBT structure 34 includes a plurality of trench gate structures 38 formed on the first main surface 12A in the IGBT region 14. A gate potential is applied to the plurality of trench gate structures 38. The plurality of trench gate structures 38 penetrate the base region 36 to reach the drift region 20. As shown in FIG. 7 , the plurality of trench gate structures 38 are arranged at intervals in the X direction in a plan view. Each trench gate structure 38 is formed in a band shape extending in the Y direction in a plan view. In other words, the plurality of trench gate structures 38 are arranged in stripes extending in the Y direction.

[0045] Each trench gate structure 38 includes a first end 38A on one side (the first side surface 12C side) and a second end 38B on the other side (the second side surface 12D side) in its longitudinal direction (Y direction). The first end 38A and the second end 38B are mechanically and electrically connected to the trench isolation structure 26.

[0046] That is, the multiple trench gate structures 38, together with the trench isolation structure 26, form one ladder-shaped trench gate structure 38. The connection portion connecting the trench isolation structure 26 and the trench gate structure 38 may be considered as part of the trench isolation structure 26 or may be considered as part of the trench gate structure 38.

[0047] The multiple trench gate structures 38 may be arranged at intervals of 0.5 μm to 5 μm in the X direction. The intervals between the multiple trench gate structures 38 are preferably 1 μm to 3 μm. Each trench gate structure 38 may have a width of 0.5 μm to 5 μm. Here, the width of the trench gate structure 38 can be defined by the dimension in a direction perpendicular to the direction in which each trench gate structure 38 extends in a plan view.

[0048] The width of each trench gate structure 38 is preferably 1 μm or more and 2.5 μm or less. The width of each trench gate structure 38 is preferably equal to the width of the trench isolation structure 26. Each trench gate structure 38 may have a depth of 1 μm or more and 20 μm or less. Here, the depth of each trench gate structure 38 can be defined by the dimension of the trench gate structure 38 in the Z direction. The depth of each trench gate structure 38 is preferably 4 μm or more and 10 μm or less. The depth of each trench gate structure 38 is preferably equal to the depth of the trench isolation structure 26. Here, the depth of the trench gate structure 38 can be defined by the dimension of the trench gate structure 38 in the Z direction, in other words, the distance in the Z direction between the first main surface 12A and the bottom wall of a gate trench 40 described below.

[0049] One trench gate structure 38 will be described below. 10 , the trench gate structure 38 includes a gate trench 40, a gate insulating film 42, and a buried gate electrode 44. The gate trench 40 is dug downward from the first main surface 12A toward the second main surface 12B to define the wall surface of the trench gate structure 38. In the first embodiment, the gate trench 40 communicates with the isolation trench 28 at both longitudinal ends thereof, that is, a first end 38A and a second end 38B (both see FIG. 7 ). Specifically, as shown in FIG. 9 , the sidewall of the gate trench 40 communicates with the sidewall of the isolation trench 28, and the bottom wall of the gate trench 40 communicates with the bottom wall of the isolation trench 28.

[0050] As shown in FIGS. 9 and 10 , the gate insulating film 42 is formed in the form of a film along the wall surface of the gate trench 40. The gate insulating film 42 defines a recess space within the gate trench 40. The gate insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The gate insulating film 42 preferably has a single-layer structure formed of a single insulating film. It is particularly preferable that the gate insulating film 42 includes a silicon oxide film formed of an oxide of the chip 12. In the first embodiment, the gate insulating film 42 is formed of the same insulating film as the isolation insulating film 30. The gate insulating film 42 is connected to the isolation insulating film 30 at the communicating portion between the isolation trench 28 and the gate trench 40.

[0051] The buried gate electrode 44 is buried in the gate trench 40 with the gate insulating film 42 sandwiched therebetween. In the first embodiment, the buried gate electrode 44 is made of conductive polysilicon. A gate potential is applied to the buried gate electrode 44. The buried gate electrode 44 is connected to the isolation buried electrode 32 at the communicating portion between the isolation trench 28 and the gate trench 40.

[0052] 10 , the IGBT structure 34 includes a plurality of n-type emitter regions 46 formed in a surface layer portion of the base region 36 in a region along the plurality of trench gate structures 38. The plurality of emitter regions 46 are arranged on both sides of the plurality of trench gate structures 38. Each emitter region 46 is formed in a strip shape extending along the plurality of trench gate structures 38 in a plan view. Each emitter region 46 has a higher n-type impurity concentration than the drift region 20. It is preferable that the emitter regions 46 are not formed in a region sandwiched between the trench isolation structure 26 and the trench gate structure 38 in the surface layer portion of the base region 36.

[0053] The IGBT structure 34 includes a plurality of contact holes 48 formed in the first main surface 12A to expose the emitter regions 46. The plurality of contact holes 48 are respectively formed in regions between pairs of adjacent trench gate structures 38 that are spaced apart from one another among the plurality of trench gate structures 38. In the first embodiment, each contact hole 48 is formed in a shape in which the opening width is constant from the opening toward the bottom wall. Note that each contact hole 48 may also be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall.

[0054] In the first embodiment, the multiple contact holes 48 penetrate the emitter region 46 to reach the base region 36. Note that the multiple contact holes 48 may be spaced from the bottom of the emitter region 46 toward the first main surface 12A so as not to reach the base region 36. Each contact hole 48 is formed in a strip shape extending along the multiple trench gate structures 38 in a plan view. As shown in FIG. 12 , the multiple contact holes 48 are arranged spaced apart in the longitudinal direction (Y direction) from the trench isolation structure 26. Therefore, the multiple contact holes 48 are shorter in the longitudinal direction (Y direction) than the multiple trench gate structures 38 (see FIG. 11 ).

[0055] 10, the IGBT structure 34 includes a plurality of p-type contact regions 50 formed in regions different from the plurality of emitter regions 46 in the surface layer portion of the base region 36. The plurality of contact regions 50 are each formed in a strip shape extending along the corresponding contact hole 48 in a plan view. The bottom of each of the plurality of contact regions 50 is formed in a region between the bottom wall of the corresponding contact hole 48 and the bottom of the base region 36. Each contact region 50 has a higher p-type impurity concentration than the base region 36.

[0056] As shown in FIG. 8, the RC-IGBT chip 10 includes a p-type pad well region 52 formed in the surface layer portion of the first main surface 12A in the pad region 16. The pad well region 52 is formed so as to partition the IGBT region 14. The pad well region 52 may also be referred to as a "pad anode region." In the first embodiment, the pad well region 52 has a higher p-type impurity concentration than the base region 36 (see FIG. 5). Note that the pad well region 52 may have a lower p-type impurity concentration than the base region 36.

[0057] The pad well region 52 is formed in the pad region 16 at a distance from the periphery of the chip 12 toward the IGBT region 14. The pad well region 52 is formed in a polygonal shape (a square shape in the first embodiment) that matches the pad region 16 in a plan view. The pad well region 52 is in contact with the trench isolation structure 26 (see FIG. 7). The pad well region 52 is formed deeper than the base region 36. Specifically, the pad well region 52 is formed deeper than the trench isolation structure 26 (the plurality of trench gate structures 38). The pad well region 52 has a portion that covers the bottom wall of the trench isolation structure 26.

[0058] The pad well region 52 has a peripheral portion that extends from the pad region 16 into the IGBT region 14. The peripheral portion of the pad well region 52 has a portion that crosses the trench isolation structure 26 and covers the bottom walls of the plurality of trench gate structures 38. The peripheral portion of the pad well region 52 covers the sidewalls of the trench isolation structure 26 and the sidewalls of the plurality of trench gate structures 38 in the IGBT region 14, and is connected to the base region 36 in the surface layer portion of the first main surface 12A. In other words, the pad well region 52 is electrically connected to the base region 36 and the plurality of emitter regions 46 in the IGBT region 14.

[0059] As shown in FIGS. 10 to 13, the RC-IGBT chip 10 includes a p-type well region 54 formed in a surface layer portion of the first main surface 12A in the peripheral region 18. The well region 54 is formed so as to separate the IGBT region 14 from the peripheral region 18. The well region 54 may also be referred to as an "anode region." In the first embodiment, the well region 54 has a higher p-type impurity concentration than the base region 36. Note that the well region 54 may also have a lower p-type impurity concentration than the base region 36. It is preferable that the well region 54 has the same p-type impurity concentration as the pad well region 52.

[0060] The well region 54 is formed at an interval from the periphery of the chip 12 toward the IGBT region 14. The well region 54 is formed in a layer shape extending along the first main surface 12A. The well region 54 is exposed from the first main surface 12A. The well region 54 is formed in a band shape extending along the IGBT region 14 in a plan view. Specifically, as shown in FIG. 8 , the well region 54 is formed in a ring shape surrounding the IGBT region 14 in a plan view. The well region 54 has four sides parallel to the periphery of the chip 12. The well region 54 has an inner edge 54A on the IGBT region 14 side and an outer edge 54B on the periphery of the chip 12.

[0061] The well region 54 is formed integrally with the pad well region 52 in a portion extending along the third side surface 12E. In other words, the well region 54 integrally includes the pad well region 52 extending from the outer periphery region 18 side to the pad region 16. The width of the well region 54 may be 10 μm or more and 100 μm or less. The width of the well region 54 is preferably 40 μm or more and 80 μm or less. Here, the width of the well region 54 can be defined by the dimension in a direction perpendicular to the direction in which the well region 54 extends in a plan view.

[0062] 10 , the well region 54 is formed deeper than the base region 36. Specifically, the well region 54 is formed deeper than the trench isolation structure 26 (the plurality of trench gate structures 38). The well region 54 is in contact with the trench isolation structure 26. The well region 54 has a portion that covers the bottom wall of the trench isolation structure 26. The well region 54 is drawn from the outer periphery region 18 into the IGBT region 14. Therefore, an inner edge 54A of the well region 54 is located within the IGBT region 14.

[0063] 11 and 12 , the well region 54 has a portion that crosses the trench isolation structure 26 and covers the bottom walls of the plurality of trench gate structures 38. The well region 54 covers the side walls of the trench isolation structure 26 and the side walls of the plurality of trench gate structures 38 in the IGBT region 14, and is connected to the base region 36 in a surface layer portion of the first main surface 12A. In other words, as shown in FIGS. 10 and 12 , an inner edge 54A of the well region 54 is electrically connected to the base region 36 and the emitter region 46 in the IGBT region 14.

[0064] As shown in FIG. 13, the RC-IGBT chip 10 includes at least one p-type field region 56 formed in the surface layer portion of the first main surface 12A in the peripheral region 18. In one example, a plurality of field regions 56 (four in the first embodiment) are provided. The number of field regions 56 is arbitrary and may be 1 to 20 (typically 3 to 10). Each field region 56 may have a higher p-type impurity concentration than the base region 36. Each field region 56 may have the same p-type impurity concentration as the well region 54. Each field region 56 is formed in an electrically floating state.

[0065] A plurality of field regions 56 are formed between the periphery of chip 12 and well region 54, with a gap between them. Each field region 56 is formed in a strip shape extending along well region 54 in plan view. In one example, as shown in FIG. 8, each field region 56 is formed in a ring shape (a square ring shape in the first embodiment) surrounding well region 54 in plan view.

[0066] 13, the multiple field regions 56 include an inner end field region 56A closest to the well region 54, an outer end field region 56D closest to the periphery of the chip 12, and intermediate field regions 56B and 56C located between the inner end field region 56A and the outer end field region 56D. Note that hereinafter, when the inner end field region 56A, the intermediate field regions 56B and 56C, and the outer end field region 56D are not to be distinguished from one another, they may be referred to simply as field regions 56.

[0067] Each field region 56 is preferably formed deeper than the base region 36. Each field region 56 is preferably formed shallower than the well region 54. Each field region 56 is preferably formed shallower than the well region 54 by a depth of 0.1 μm to 1 μm (preferably 0.5 μm or less) relative to the depth position of the bottom of the well region 54, for example.

[0068] Each field region 56 is preferably formed to a constant depth. In the width direction of the field regions 56, the distance between adjacent field regions 56 (hereinafter referred to as "the spacing between field regions 56") is preferably arranged so that it gradually increases toward the periphery of the chip 12. Note that the spacing between the multiple field regions 56 may be equal to one another.

[0069] Each field region 56 preferably has a width smaller than that of the well region 54. The widths of the innermost field region 56A and the middle field regions 56B and 56C are equal to each other. The width of the outermost field region 56D is equal to that of the innermost field region 56A and the middle field regions 56B and 56C. Hereinafter, when there is no need to distinguish between the widths of the innermost field region 56A, the middle field regions 56B and 56C, and the outermost field region 56D, they will simply be referred to as the "width WF of the field region 56." Furthermore, the width WF of the field region 56 (the width of the innermost field region 56A, the width of the middle field regions 56B and 56C, and the width of the outermost field region 56D) can be defined by the dimension in a direction perpendicular to the extension direction of the field region 56 in a plan view.

[0070] The width WF of each field region 56 may be 1 μm or more and 50 μm or less. The width WF of each field region 56 may be set to a value within any of the following ranges: 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, and 40 μm or more and 50 μm or less. The width WF of each field region 56 is preferably 10 μm or more and 30 μm or less.

[0071] The spacing between the field regions 56 may be 10 μm or more and 30 μm or less. The spacing between the field regions 56 may be 10 μm or more and 20 μm or less. The spacing between the field regions 56 may be 10 μm or more and 15 μm or less.

[0072] The RC-IGBT chip 10 includes an n-type channel stop region 58 formed in a surface layer portion of the first main surface 12A at intervals from the multiple field regions 56 toward the periphery of the chip 12 in the peripheral region 18. The channel stop region 58 has a higher n-type impurity concentration than the drift region 20. The channel stop region 58 may be exposed from the first to fourth side surfaces 12C to 12F (see FIG. 8).

[0073] 8, the channel stop region 58 is formed in a band shape extending along the periphery of the chip 12 in a plan view. In one example, the channel stop region 58 is formed in a ring shape (the square ring shape in the first embodiment) surrounding the plurality of field regions 56 in a plan view. The channel stop region 58 is formed in an electrically floating state.

[0074] As shown in FIGS. 10 to 13, the RC-IGBT chip 10 includes an insulating film 60 that selectively covers the first main surface 12A. In the first embodiment, the insulating film 60 has a layered structure including a main surface insulating film 62 and an interlayer insulating film 64. The main surface insulating film 62 selectively covers the first main surface 12A in the IGBT region 14, the peripheral region 18, and the pad region 16 (see FIG. 8). The main surface insulating film 62 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The main surface insulating film 62 preferably has a single-layer structure composed of a single insulating film.

[0075] It is particularly preferable that the main surface insulating film 62 includes a silicon oxide film made of an oxide of the chip 12. In one example, as shown in Figures 10 and 11, the main surface insulating film 62 is made of the same insulating film as the gate insulating film 42. The main surface insulating film 62 covers the first main surface 12A so as to expose the trench isolation structure 26 and the plurality of trench gate structures 38.

[0076] Specifically, the main surface insulating film 62 is connected to the isolation insulating film 30 and the gate insulating film 42. On the other hand, the main surface insulating film 62 exposes the isolation buried electrode 32 and the gate buried electrode 44. The main surface insulating film 62 covers the pad well region 52 (see FIG. 8 ), the well region 54, the plurality of field regions 56, and the channel stop region 58 in the pad region 16 and the peripheral region 18.

[0077] The interlayer insulating film 64 covers the main surface insulating film 62. The interlayer insulating film 64 is thicker than the main surface insulating film 62. The interlayer insulating film 64 may have a single-layer structure composed of a single insulating film, or a stacked structure including multiple insulating films. The interlayer insulating film 64 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The interlayer insulating film 64 may include at least one of an NSG (Non-doped Silicate Glass) film, a PSG (Phosphor Silicate Glass) film, and a BPSG (Boron Phosphor Silicate Glass) film, which are examples of silicon oxide films.

[0078] The interlayer insulating film 64 covers the main surface insulating film 62 in the IGBT region 14, the peripheral region 18, and the pad region 16. The interlayer insulating film 64 covers the main surface insulating film 62, the trench isolation structure 26, and the plurality of trench gate structures 38 in the IGBT region 14. As shown in FIG. 13 , the interlayer insulating film 64 covers the pad well region 52, the well region 54, the plurality of field regions 56, and the channel stop region 58 with the main surface insulating film 62 sandwiched between them in the pad region 16 (see FIG. 8 ) and the peripheral region 18.

[0079] As shown in FIG. 8, the RC-IGBT chip 10 includes a gate wiring 66 arranged in the form of a film inside the insulating film 60. In the first embodiment, the gate wiring 66 is made of a conductive polysilicon film. In one example, as shown in FIGS. 8 and 11, the gate wiring 66 includes a gate pad wiring 68, a gate line wiring 70, and a plurality of gate connection wirings 72. The gate line wiring 70 may also be referred to as a "gate finger wiring."

[0080] As shown in FIG. 8, the gate pad wiring 68 is disposed inside a portion of the insulating film 60 that covers the pad region 16. The gate pad wiring 68 faces the pad well region 52 in the thickness direction (Z direction) of the chip 12. Specifically, the gate pad wiring 68 is disposed in the form of a film on the main surface insulating film 62 and is covered by an interlayer insulating film 64 (see FIG. 11). The gate pad wiring 68 is formed in a polygonal shape (a quadrangular shape in the first embodiment) that matches the pad region 16 in a plan view. The peripheral portion of the gate pad wiring 68 may be located within the pad region 16.

[0081] The peripheral portion of the gate pad wiring 68 may be drawn from the pad region 16 toward the IGBT region 14. In this case, the peripheral portion of the gate pad wiring 68 may be drawn from above the main surface insulating film 62 onto a portion of the trench isolation structure 26 (see FIG. 11) that defines the pad region 16, and may be connected to the isolated buried electrode 32 (see FIG. 11). The peripheral portion of the gate pad wiring 68 may also cover a portion (first end 38A and second end 38B (see FIG. 7)) of the plurality of trench gate structures 38, and may be connected to the plurality of buried gate electrodes 44 (see FIG. 11).

[0082] The gate line wiring 70 is disposed inside a portion of the insulating film 60 that covers the outer periphery region 18. As shown in FIGS. 10 to 12, the gate line wiring 70 faces the well region 54 in the thickness direction (Z direction) of the chip 12. Specifically, the gate line wiring 70 is disposed in the form of a film on the main surface insulating film 62 and is covered by the interlayer insulating film 64. In the first embodiment, the gate line wiring 70 is disposed only in the portion that covers the well region 54. That is, the gate line wiring 70 faces the inner part of the well region 54 at intervals from the outer edge 54B and the inner edge 54A of the well region 54 in a plan view. Moreover, the entire area of ​​the gate line wiring 70 faces the well region 54 with the main surface insulating film 62 sandwiched therebetween.

[0083] As shown in FIG. 8, the gate line wiring 70 extends in a strip shape along the well region 54 in a plan view. The gate line wiring 70 preferably defines the IGBT region 14 in multiple directions in a plan view. In the first embodiment, the gate line wiring 70 is formed in a strip shape extending along the first to fourth side faces 12C to 12F in a plan view. The gate line wiring 70 defines the IGBT region 14 in four directions. The gate line wiring 70 may be formed in an endless strip shape or a strip shape with ends so as to surround the IGBT region 14. In one example, the gate line wiring 70 is formed in a ring shape (a quadrangular ring shape in the first embodiment) surrounding the IGBT region 14.

[0084] The gate line wiring 70 is formed integrally with the gate pad wiring 68 in a portion extending along the third side surface 12E. In other words, the gate line wiring 70 integrally includes the gate pad wiring 68 drawn from the peripheral region 18 to the pad region 16. The gate line wiring 70 has a width less than the width of the well region 54. The width of the gate line wiring 70 may be 10 μm or more and 100 μm or less. The width of the gate line wiring 70 is preferably 15 μm or more and 60 μm or less. Here, the width of the gate line wiring 70 can be defined by the dimension in a direction perpendicular to the direction in which the gate line wiring 70 extends in a plan view.

[0085] 9 and 11, the plurality of gate connection wirings 72 are disposed inside the insulating film 60 so as to electrically connect the gate line wirings 70 to the plurality of trench gate structures 38. The plurality of gate connection wirings 72 are drawn from a portion of the gate line wirings 70 extending along the first side surface 12C (see FIG. 8) toward the first ends 38A (see FIG. 7) of the plurality of trench gate structures 38. The plurality of gate connection wirings 72 are drawn from a portion of the gate line wirings 70 extending along the second side surface 12D (see FIG. 8) toward the second ends 38B (see FIG. 7) of the plurality of trench gate structures 38.

[0086] The multiple gate connection wirings 72 are arranged at intervals along the gate line wiring 70 on the first side surface 12C side. Each gate connection wiring 72 on the first side surface 12C side is drawn out toward the trench isolation structure 26. The multiple gate connection wirings 72 are preferably arranged at equal intervals in the X direction. The multiple gate connection wirings 72 are drawn out from above the main surface insulating film 62 to above the trench isolation structure 26 on the first side surface 12C side and connected to the isolated buried electrode 32. In the first embodiment, the multiple gate connection wirings 72 respectively cover the first ends 38A of the multiple trench gate structures 38 and are connected to the multiple gate buried electrodes 44.

[0087] The plurality of gate connection wirings 72 are arranged at intervals along the gate line wiring 70 on the second side surface 12D side. Each gate connection wiring 72 on the second side surface 12D side is drawn out toward the trench isolation structure 26. The plurality of gate connection wirings 72 are preferably arranged at equal intervals in the X direction. The plurality of gate connection wirings 72 are drawn out from above the main surface insulating film 62 onto the trench isolation structure 26 on the second side surface 12D side and connected to the isolated buried electrode 32.

[0088] In the first embodiment, the multiple gate connection wirings 72 cover the second ends 38B of the multiple trench gate structures 38, respectively, and are connected to the multiple gate buried electrodes 44. In the first embodiment, the gate wiring 66 is made of the same conductive material as the isolated buried electrode 32 and the multiple gate buried electrodes 44. The gate wiring 66 includes lead-out portions that are led out from the isolated buried electrode 32 and the multiple gate buried electrodes 44 onto the main surface insulating film 62 (see FIG. 11 ).

[0089] 10, the RC-IGBT chip 10 has a plurality of emitter openings 74 that expose a plurality of emitter regions 46 in a portion of the insulating film 60 that covers the IGBT region 14. The plurality of emitter openings 74 are formed in a one-to-one correspondence with the plurality of contact holes 48. The plurality of emitter openings 74 are each connected to a corresponding contact hole 48. The plurality of emitter openings 74 are each formed in a strip shape that extends along the corresponding contact hole 48 in a plan view.

[0090] The RC-IGBT chip 10 includes a plurality of emitter connection electrodes 76 embedded in the insulating film 60 so as to be electrically connected to the plurality of emitter regions 46. The plurality of emitter connection electrodes 76 are embedded in a plurality of emitter openings 74. The plurality of emitter connection electrodes 76 extend from the plurality of emitter openings 74 into the plurality of contact holes 48, thereby being electrically connected to the emitter regions 46 and the contact region 50.

[0091] Each emitter-connecting electrode 76 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each emitter-connecting electrode 76 has a layered structure including a Ti-based metal film and a W-based metal film. The Ti-based metal may include at least one of a pure Ti film (a Ti film with a purity of 99% or more) and a Ti alloy film. The Ti alloy film may be a TiN film. The W-based metal may include at least one of a pure W film (a W film with a purity of 99% or more) and a W alloy film.

[0092] The Al-based metal film may include at least one of a pure Al film (an Al film with a purity of 99% or more) and an Al alloy film. The Al alloy film may include at least one of an AlCu alloy, an AlSi alloy, and an AlSiCu alloy. The Cu-based metal may include at least one of a pure Cu film (a Cu film with a purity of 99% or more) and a Cu alloy film. In the following description, the Ti-based metal film, the W-based metal film, the Al-based metal film, and the Cu-based metal film include the above.

[0093] The RC-IGBT chip 10 includes at least one gate opening 78 (multiple in the first embodiment) that selectively exposes the gate line wiring 70 in a portion of the insulating film 60 that covers the gate line wiring 70. The number of gate openings 78 can be changed as desired. In one example, a single gate opening 78 may be formed in the insulating film 60.

[0094] 9 and 10 , the multiple gate openings 78 expose the inner portions of the gate line wiring 70 at intervals from the inner and outer edges of the gate line wiring 70. The multiple gate openings 78 are formed at intervals from one another from the IGBT region 14 side toward the peripheral edge of the chip 12. Each gate opening 78 extends in a strip shape along the gate line wiring 70. Each gate opening 78 may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 14. In one example, each gate opening 78 is formed in a ring shape (a square ring shape in the first embodiment) surrounding the IGBT region 14.

[0095] Although specific illustrations are omitted, the RC-IGBT chip 10 may include at least one (multiple in the first embodiment) gate opening 78 that selectively exposes the gate pad wiring 68 in the portion of the insulating film 60 that covers the gate pad wiring 68.

[0096] The RC-IGBT chip 10 includes at least one gate connection electrode 80 (multiple in the first embodiment) embedded in the insulating film 60 so as to be electrically connected to the gate line wiring 70. Each gate connection electrode 80 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each gate connection electrode 80 has a stacked structure including a Ti-based metal film and a W-based metal film.

[0097] The plurality of gate connection electrodes 80 are embedded in the plurality of gate openings 78 in a one-to-one correspondence, respectively. The plurality of gate connection electrodes 80 are electrically connected to the gate line wiring 70 in the corresponding gate openings 78. When a gate opening 78 that exposes the gate pad wiring 68 is formed in the insulating film 60, a gate connection electrode 80 that is electrically connected to the gate pad wiring 68 may be formed in the gate opening 78.

[0098] The RC-IGBT chip 10 includes a plurality of well openings 82 that selectively expose the well region 54 in a portion of the insulating film 60 that covers the peripheral region 18. The plurality of well openings 82 include at least one (a plurality in the first embodiment) first well opening 82A that exposes the well region 54 on the IGBT region 14 side, and at least one (a plurality in the first embodiment) second well opening 82B that exposes the well region 54 on the peripheral edge side of the chip 12. The number of first well openings 82A and the number of second well openings 82B can be changed as desired. In one example, a single first well opening 82A may be formed in the insulating film 60. In another example, a single second well opening 82B may be formed in the insulating film 60.

[0099] The multiple first well openings 82A are formed at intervals from the middle of the well region 54 in the width direction toward the inner edge 54A of the well region 54. The multiple first well openings 82A selectively expose the region of the well region 54 on the inner edge 54A side. Specifically, the multiple first well openings 82A are formed at intervals from the gate line wiring 70 toward the inner edge 54A of the well region 54, thereby selectively exposing the inner edge portion of the well region 54.

[0100] 9 and 10 , the multiple first well openings 82A are formed at intervals from one another from the IGBT region 14 side toward the peripheral edge of the chip 12. Each first well opening 82A extends in a strip shape along the well region 54. Each first well opening 82A has a portion extending in the X direction along the well region 54 and a portion extending in the Y direction along the well region 54.

[0101] 9, each first well opening 82A includes a plurality of segment openings 82AA formed at intervals so as to expose regions between the plurality of gate connection wirings 72 in a portion extending in the X direction. In other words, the plurality of segment openings 82AA are formed at intervals from the plurality of gate connection wirings 72 so as not to expose the plurality of gate connection wirings 72. The plurality of segment openings 82AA are arranged in a region surrounded by the trench isolation structure 26 (the plurality of trench gate structures 38), the gate line wirings 70, and the plurality of gate connection wirings 72. The plurality of segment openings 82AA are each formed in a strip shape extending in the X direction.

[0102] 10, the multiple second well openings 82B are formed at intervals from the middle of the well region 54 in the width direction toward the outer edge 54B of the well region 54. The multiple second well openings 82B selectively expose the region of the well region 54 on the outer edge 54B side. Specifically, the multiple second well openings 82B are formed at intervals from the gate line wiring 70 toward the outer edge 54B of the well region 54, thereby selectively exposing the outer edge portion of the well region 54.

[0103] 9 and 10, the multiple second well openings 82B are formed at intervals from one another from the IGBT region 14 side toward the peripheral edge of the chip 12. Each second well opening 82B extends in a strip shape along the well region 54. Each second well opening 82B may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 14. In one example, each second well opening 82B is formed in a ring shape (a square ring shape in the first embodiment) surrounding the IGBT region 14.

[0104] 10 , the RC-IGBT chip 10 includes a plurality of well connection electrodes 84 embedded in the insulating film 60 so as to be electrically connected to the well regions 54. Each well connection electrode 84 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each well connection electrode 84 has a stacked structure including a Ti-based metal film and a W-based metal film.

[0105] The multiple well-connecting electrodes 84 include at least one (multiple in the first embodiment) first well-connecting electrode 84A and at least one (multiple in the first embodiment) second well-connecting electrode 84B. Each first well-connecting electrode 84A is connected to the well region 54 on the inner edge 54A side of the well region 54 (toward the IGBT region 14). Each second well-connecting electrode 84B is connected to the well region 54 on the outer edge 54B side of the well region 54 (toward the peripheral edge of the chip 12). The numbers of the first well-connecting electrodes 84A and the second well-connecting electrodes 84B can be changed as desired. For example, there may be a single first well-connecting electrode 84A. For example, there may be a single second well-connecting electrode 84B.

[0106] The multiple first well connection electrodes 84A are embedded in the multiple first well openings 82A in a one-to-one correspondence. That is, the multiple first well connection electrodes 84A are formed at intervals from the middle of the well region 54 in the width direction toward the inner edge 54A of the well region 54. The multiple first well connection electrodes 84A are electrically connected to a region of the well region 54 on the inner edge 54A side. Specifically, the multiple first well connection electrodes 84A are formed at intervals from the gate line wiring 70 in a region on the inner edge 54A side of the well region 54, and are thereby electrically connected to the inner edge of the well region 54.

[0107] The second well connection electrodes 84B are embedded in the second well openings 82B in a one-to-one correspondence. That is, the second well connection electrodes 84B are formed at intervals from the middle of the well region 54 in the width direction toward the outer edge 54B of the well region 54. Here, the width direction of the well region 54 can be defined as a direction perpendicular to the direction in which the well region 54 extends in a plan view. The second well connection electrodes 84B are electrically connected to a region of the well region 54 on the outer edge 54B side. Specifically, the second well connection electrodes 84B are formed at intervals in a region on the outer edge 54B side of the well region 54 from the gate line wiring 70, thereby electrically connecting to the outer edge of the well region 54.

[0108] As shown in FIG. 6, the RC-IGBT chip 10 includes a gate electrode 86 disposed on the insulating film 60. The gate electrode 86 corresponds to the gate electrode 10G of the RC-IGBT chip 10 shown in FIG. 5. The gate electrode 86 is made of a conductive material different from that of the gate wiring 66 (see FIG. 8). In the first embodiment, the gate electrode 86 is made of a metal film. The gate electrode 86 has a lower resistance value than the gate wiring 66. The gate electrode 86 may be referred to as a "gate metal." The gate electrode 86 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, the gate electrode 86 has a stacked structure including a Ti-based metal film and an Al-based metal film.

[0109] 6 and 7, the gate electrode 86 includes a gate pad electrode 88 and a gate line electrode 90. The gate line electrode 90 may also be referred to as a "gate finger electrode." The gate pad electrode 88 is disposed on a portion of the insulating film 60 that covers the gate pad wiring 68. In one example, the gate pad electrode 88 is formed in a polygonal shape (a quadrangular shape in the first embodiment) that matches the pad region 16 in a plan view.

[0110] The gate pad electrode 88 faces the gate pad wiring 68 (see FIG. 8) across a part of the insulating film 60 (interlayer insulating film 64) in the thickness direction of the chip 12. The gate pad electrode 88 faces the pad well region 52 (see FIG. 8) across the insulating film 60 and the gate pad wiring 68 in the thickness direction of the chip 12. When the gate connection electrode 80 is connected to the gate pad wiring 68, the gate pad electrode 88 is electrically connected to the gate pad wiring 68 via the gate connection electrode 80 (see FIG. 10).

[0111] The gate pad electrode 88 may have a planar area equal to or larger than the planar area of ​​the pad region 16, or may have a planar area smaller than the planar area of ​​the pad region 16. The gate pad electrode 88 may have a planar area equal to or larger than the planar area of ​​the gate pad wiring 68, or may have a planar area smaller than the planar area of ​​the gate pad wiring 68.

[0112] As shown in FIGS. 10 to 12, the gate line electrode 90 is disposed on the insulating film 60 on a portion covering the gate line wiring 70. The gate line electrode 90 is formed integrally with the gate pad electrode 88 (see FIG. 7). The gate line electrode 90 is drawn out in a strip shape from the gate pad electrode 88 onto the insulating film 60. In the first embodiment, the gate line electrode 90 is drawn out from the gate pad electrode 88 onto the insulating film 60 to a region between the first well connecting electrode 84A and the second well connecting electrode 84B.

[0113] The gate line electrode 90 is arranged at a distance from the first well connection electrode 84A and the second well connection electrode 84B. The gate line electrode 90 covers the multiple gate connection electrodes 80. In other words, the gate line electrode 90 is arranged at a distance from the first well connection electrode 84A toward the outer edge 54B of the well region 54 (toward the periphery of the chip 12). The gate line electrode 90 is arranged at a distance from the second well connection electrode 84B toward the inner edge 54A of the well region 54 (toward the IGBT region 14). The gate line electrode 90 is electrically connected to the gate line wiring 70 via the multiple gate connection electrodes 80.

[0114] The gate line electrode 90 faces the gate line electrode 90 in the thickness direction of the chip 12, with a part of the insulating film 60 sandwiched therebetween. The gate line electrode 90 faces the well region 54 in the thickness direction of the chip 12, with the insulating film 60 and the gate line wiring 70 sandwiched therebetween. The gate line electrode 90 has a width smaller than the width of the well region 54. It is preferable that the gate line electrode 90 has a width smaller than the width of the gate line wiring 70. The width of the gate line electrode 90 can be changed arbitrarily, and may be, for example, equal to or greater than the width of the gate line wiring 70.

[0115] As shown in FIGS. 6 and 7, the gate line electrode 90 extends in a strip shape along the gate line wiring 70 in a plan view. The gate line electrode 90 preferably defines the IGBT region 14 from multiple directions in a plan view. In the first embodiment, the gate line electrode 90 is formed in a strip shape extending along the first to fourth side faces 12C to 12F in a plan view. The gate line electrode 90 defines the IGBT region 14 from four directions. The gate line electrode 90 may be formed in an endless strip shape or a strip shape with ends so as to surround the IGBT region 14. In one example, the gate line electrode 90 is formed in a ring shape (a quadrangular ring shape in the first embodiment) surrounding the IGBT region 14, and has a pair of open ends 90A in a portion extending along the fourth side face 12F.

[0116] The RC-IGBT chip 10 includes an emitter electrode 92 disposed on the insulating film 60 and spaced apart from the gate electrode 86. The emitter electrode 92 corresponds to the emitter electrode 10E of the RC-IGBT chip 10 shown in FIG. 5. The emitter electrode 92 is made of a conductive material different from that of the gate wiring 66. In the first embodiment, the emitter electrode 92 is made of a metal film. The emitter electrode 92 has a lower resistance than the gate wiring 66 (see FIG. 8). The emitter electrode 92 may also be referred to as an "emitter metal." The emitter electrode 92 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, the emitter electrode 92 has a layered structure including a Ti-based metal film and an Al-based metal film. In other words, the emitter electrode 92 is made of the same material as the gate electrode 86.

[0117] The emitter electrode 92 includes an emitter pad electrode 94 and an emitter line electrode 96. The emitter line electrode 96 may also be referred to as an "emitter finger electrode." The emitter pad electrode 94 is disposed on a portion of the insulating film 60 that covers the IGBT region 14. In one example, the emitter pad electrode 94 is disposed at a distance from the gate pad electrode 88 and the gate line electrode 90. The emitter pad electrode 94 is formed in a polygonal shape having a recess that is recessed along the gate pad electrode 88 in a plan view.

[0118] 10 , the emitter pad electrode 94 collectively covers the trench gate structures 38 and the emitter connecting electrodes 76. The emitter pad electrode 94 faces the trench gate structures 38 with the insulating film 60 sandwiched therebetween. The emitter pad electrode 94 is electrically connected to the emitter regions 46 via the emitter connecting electrodes 76. The emitter pad electrode 94 includes an emitter lead-out portion 94A that is led out from the IGBT region 14 to the peripheral region 18, across the region immediately above the trench isolation structure 26, so as to face the well region 54 in the thickness direction of the chip 12.

[0119] The emitter lead-out portion 94A covers the region on the inner edge 54A side of the well region 54 relative to the middle portion in the width direction of the well region 54. Specifically, the emitter lead-out portion 94A covers the inner edge portion of the well region 54 at a distance from the gate line electrode 90 toward the IGBT region 14, and also collectively covers the multiple first well connection electrodes 84A. As a result, the emitter pad electrode 94 is electrically connected to the inner edge portion of the well region 54 via the multiple first well connection electrodes 84A.

[0120] 6 and 10, the emitter line electrode 96 is formed integrally with the emitter pad electrode 94. The emitter line electrode 96 is drawn out from the emitter pad electrode 94 onto the insulating film 60. Specifically, the emitter line electrode 96 passes through the region between the pair of open ends 90A of the gate line electrode 90 on the insulating film 60 and is drawn out in a strip shape from the emitter pad electrode 94 to the outer circumferential region 18.

[0121] 10 to 12, the emitter line electrode 96 is routed over a portion of the insulating film 60 that covers the well region 54. In other words, the emitter line electrode 96 faces the well region 54 in the thickness direction of the chip 12, with the insulating film 60 sandwiched between them. The emitter line electrode 96 is arranged at a distance from the gate line electrode 90 on the outer edge 54B side of the well region 54 (the peripheral edge side of the chip 12) so as to cover the multiple second well connection electrodes 84B. As a result, the emitter line electrode 96 is electrically connected to the outer edge of the well region 54 via the multiple second well connection electrodes 84B.

[0122] As shown in FIGS. 6 and 7, the emitter line electrode 96 extends in a strip shape along the outer edge 54B of the well region 54 in a plan view. The emitter line electrode 96 preferably defines the IGBT region 14 from multiple directions in a plan view. In the first embodiment, the emitter line electrode 96 is formed in a strip shape extending along the first to fourth side faces 12C to 12F in a plan view. The emitter line electrode 96 defines the IGBT region 14 from four directions. The emitter line electrode 96 may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 14. In one example, the emitter line electrode 96 is formed in a ring shape (a quadrangular ring shape in the first embodiment) surrounding the IGBT region 14.

[0123] 13, the insulating film 60 includes at least one field opening 98 (multiple in the first embodiment) that selectively exposes each field region 56 in the peripheral region 18. The multiple field openings 98 expose the corresponding field regions 56 in a one-to-many correspondence. Note that a single field opening 98 may also expose the corresponding field regions 56 in a one-to-one correspondence. The multiple field openings 98 are formed in a strip shape extending along the corresponding field regions 56. In one example, the multiple field openings 98 are formed in a ring shape (a square ring shape in the first embodiment) extending along the corresponding field regions 56.

[0124] The RC-IGBT chip 10 includes at least one field connection electrode 100 (multiple in the first embodiment) embedded in an insulating film 60 so as to be electrically connected to a corresponding field region 56. Each field connection electrode 100 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, each field connection electrode 100 has a stacked structure including a Ti-based metal film and a W-based metal film.

[0125] The plurality of field connection electrodes 100 are embedded in the plurality of field openings 98 in a one-to-one correspondence. The plurality of field connection electrodes 100 are electrically connected to the corresponding field regions 56 in the corresponding field openings 98. In the first embodiment, the plurality of field connection electrodes 100 are formed in an electrically floating state.

[0126] The RC-IGBT chip 10 includes a plurality of field electrodes 102 formed on the insulating film 60 in the peripheral region 18. The plurality of field electrodes 102 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In one example, each field electrode 102 may have a stacked structure including a Ti-based metal film and a W-based metal film. The plurality of field electrodes 102 are formed in an electrically floating state.

[0127] The plurality of field electrodes 102 are formed in one-to-one correspondence with the corresponding field regions 56. Each field electrode 102 collectively covers the corresponding plurality of field-connecting electrodes 100. Each field electrode 102 is electrically connected to the corresponding field region 56 via the corresponding plurality of field-connecting electrodes 100.

[0128] The plurality of field electrodes 102 are formed in strip shapes extending along the corresponding field regions 56. In one example, the plurality of field electrodes 102 are formed in ring shapes (square ring shapes in the first embodiment) extending along the corresponding field regions 56.

[0129] The multiple field electrodes 102 include an inner edge field electrode 102A corresponding to the inner edge field region 56A, middle field electrodes 102B and 102C corresponding to the middle field regions 56B and 56C, and an outer edge field electrode 102D corresponding to the outer edge field region 56D. The outer edge field electrode 102D includes a field lead portion 102E extending toward the periphery of the chip 12. Therefore, the width of the outer edge field electrode 102D is greater than the widths of the inner edge field electrode 102A and the middle field electrodes 102B and 102C. In one example, the width of the inner edge field electrode 102A and the widths of the middle field electrodes 102B and 102C are equal to each other.

[0130] The insulating film 60 includes a channel stop opening 104 that exposes the channel stop region 58 in the peripheral region 18. The channel stop opening 104 is formed in a strip shape extending along the channel stop region 58. In one example, the channel stop opening 104 is formed in a ring shape (a square ring shape in the first embodiment) extending along the channel stop region 58. The channel stop opening 104 communicates with the peripheral edge of the chip 12.

[0131] The RC-IGBT chip 10 includes a channel stop electrode 106 formed on the insulating film 60 in the peripheral region 18. The channel stop electrode 106 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In the first embodiment, the channel stop electrode 106 may have a stacked structure including a Ti-based metal film and a W-based metal film. The channel stop electrode 106 is formed in an electrically floating state.

[0132] The channel stop electrode 106 is formed in a strip shape extending along the channel stop region 58. In one example, the channel stop electrode 106 is formed in a strip shape (a square ring shape in the first embodiment) extending along the channel stop region 58. The channel stop electrode 106 is electrically connected to the channel stop region 58 by extending from above the insulating film 60 into the channel stop opening 104. The channel stop electrode 106 may be formed at an interval from the periphery of the chip 12 toward the IGBT region 14 so as to expose the peripheral portion (channel stop region 58) of the first main surface 12A.

[0133] The RC-IGBT chip 10 includes a collector electrode 108 provided on the second main surface 12B. The collector electrode 108 corresponds to the collector electrode 10C of the RC-IGBT chip 10 shown in FIG. 4. In one example, the collector electrode 108 covers the second main surface 12B. The collector electrode 108 is electrically connected to the collector region 24 exposed from the second main surface 12B. The collector electrode 108 forms ohmic contact with the collector region 24. The collector electrode 108 may cover the entire second main surface 12B so as to be continuous with the periphery of the chip 12 (first to fourth side surfaces 12C to 12F).

[0134] Collector electrode 108 may have a single-film structure or a multilayer structure including at least one of a Ti film, a Ni film, a Pd film, an Au film, an Ag film, and an Al film. Collector electrode 108 preferably includes at least a Ti film that directly covers second main surface 12B. Collector electrode 108 may have a multilayer structure including, for example, a Ti film, a Ni film, a Pd film, and an Au film stacked in this order from the second main surface 12B side.

[0135] (cathode region) 13, the RC-IGBT chip 10 includes an n-type cathode region 110 formed in the surface layer portion of the second main surface 12B in the peripheral region 18. The cathode region 110 has a higher n-type impurity concentration than the p-type impurity concentration of the collector region 24. The cathode region 110 is a region in which the conductivity type of a portion of the collector region 24 is replaced from p-type to n-type. The cathode region 110 preferably has a higher n-type impurity concentration than the drift region 20 (buffer region 22).

[0136] The cathode region 110 extends in a layered form along the second major surface 12B. The cathode region 110 is exposed from the second major surface 12B. The cathode region 110 penetrates the collector region 24 to be connected to the buffer region 22. The cathode region 110 is electrically connected to the collector electrode 108. The cathode region 110 forms an ohmic contact with the collector electrode 108. The cathode region 110 and the well region 54 form a diode 112. The diode 112 is configured as a freewheeling diode for the IGBT structure 34.

[0137] When a forward voltage VF of the diode 112 is applied between the emitter electrode 92 and the collector electrode 108, a forward current IF flows through the diode 112. The forward current IF flows from the second well-connecting electrode 84B to the cathode region 110, for example.

[0138] The cathode region 110 is disposed at a position facing the well region 54 in the thickness direction of the chip 12. The cathode region 110 may be formed in an endless or ended strip shape so as to surround the IGBT region 14 in a plan view. In one example, the cathode region 110 is formed in a ring shape (a square ring shape in the first embodiment) surrounding the well region 54. The cathode region 110 in the first embodiment is formed in a square ring shape with rounded corners in a plan view. Therefore, the cathode region 110 has a predetermined width W1 in a plan view. Here, the width W1 of the cathode region 110 can be defined by the dimension in a direction perpendicular to the extension direction of the cathode region 110 in a plan view.

[0139] An inner edge 111A of the cathode region 110 is located opposite an inner edge 54A of the well region 54 in a plan view. Therefore, the inner edge 111A of the cathode region 110 is located closer to the IGBT region 14 than the trench isolation structure 26. The inner edge 111A of the cathode region 110 is located on the outer edge of the IGBT region 14.

[0140] The width W1 of the cathode region 110 is larger than the width WP of the well region 54. Therefore, the cathode region 110 extends closer to the periphery of the chip 12 than the well region 54 in a plan view. In other words, the outer edge 111B of the cathode region 110 is located closer to the periphery of the chip 12 than the outer edge 54B of the well region 54 in a plan view. As a result, the cathode region 110 is provided to face the outer edge 54B of the well region 54 in the thickness direction of the chip 12. Furthermore, the cathode region 110 is provided to face the multiple field regions 56 in the thickness direction of the chip 12. More specifically, the cathode region 110 is provided to face the inner end field region 56A of the multiple field regions 56 in the thickness direction of the chip 12. On the other hand, the cathode region 110 is provided at a distance from the field region 56 toward the well region 54 so as not to face the middle field regions 56B and 56C and the outer end field region 56D among the multiple field regions 56. Therefore, the outer edge 111B of the cathode region 110 is located between the inner end field region 56A and the middle field region 56B in a plan view. In one example, the outer edge 111B of the cathode region 110 is provided at a position facing the outer edge of the inner end field region 56A in the thickness direction of the chip 12.

[0141] Also, in one example, the width W1 of the cathode region 110 may be greater than the total width WT of the multiple field regions 56. In one example, the width W1 of the cathode region 110 may be less than the distance Dwc between the well region 54 and the channel stop region 58.

[0142] [Diode configuration] The detailed configuration of the SiC-SBD chip 8 will be described with reference to Fig. 14. Fig. 14 shows a schematic cross-sectional structure of the SiC-SBD chip 8 cut along the XZ plane.

[0143] 14, the SiC-SBD chip 8 includes a diode chip 130. The diode chip 130 may be made of a wide bandgap semiconductor having a bandgap exceeding the bandgap of Si. In other words, the diode chip 130 may be made of a semiconductor different from that of the RC-IGBT chip 10.

[0144] The diode chip 130 is preferably made of a wide bandgap semiconductor. The diode chip 130 is made of SiC, an example of a wide bandgap semiconductor. That is, the SiC-SBD chip 8 is made of a SiC-SBD (Schottky Barrier Diode). The diode chip 130 includes a first diode surface 132 and a second diode surface 134 opposite to the first diode surface 132. The first diode surface 132 is a surface on which the main portion of the SBD is fabricated.

[0145] The SiC-SBD chip 8 includes an interlayer insulating film 136, an anode electrode 138, and a cathode electrode 140 provided on the diode chip . An interlayer insulating film 136 covers the first diode surface 132. The interlayer insulating film 136 may contain at least one of silicon oxide and silicon nitride. An anode electrode 138 is provided on the interlayer insulating film 136. The anode electrode 138 penetrates the interlayer insulating film 136 and is electrically connected to the anode of the SiC-SBD chip 8. A cathode electrode 140 covers the second diode surface 134. The cathode electrode 140 is electrically connected to the cathode of the SiC-SBD chip 8. Thus, the diode chip 130 has a vertically structured SiC-SBD chip 8. Here, the anode electrode 138 corresponds to the anode electrode 8A (see FIG. 4) of the SiC-SBD chip 8, and the cathode electrode 140 corresponds to the cathode electrode 8K (see FIG. 4) of the SiC-SBD chip 8.

[0146] [Electrical characteristics of semiconductor devices] The electrical characteristics of the semiconductor device 1 will be described with reference to FIGS. 15 is a graph showing the electric field strength in the peripheral region 18 when a predetermined collector-emitter voltage Vce is applied. The predetermined collector-emitter voltage Vce is, for example, 650 V. The horizontal axis of FIG. 15 represents the position of the peripheral portion (peripheral region 18) of the chip 12. The vertical axis of FIG. 15 represents the electric field strength.

[0147] In Figure 15, the range RW on the horizontal axis indicates the arrangement area of ​​the outer edge of the well region 54 in the outer periphery region 18. The range RA on the horizontal axis indicates the arrangement area of ​​the inner end field region 56A in the outer periphery region 18. The range RB on the horizontal axis indicates the arrangement area of ​​the intermediate field region 56B in the outer periphery region 18. The range RC on the horizontal axis indicates the arrangement area of ​​the intermediate field region 56C in the outer periphery region 18. The range RD on the horizontal axis indicates the arrangement area of ​​the outer end field region 56D in the outer periphery region 18.

[0148] 15, peaks of electric field intensity occur at the outer edge of well region 54, inner field region 56A, intermediate field regions 56B and 56C, and outer field region 56D. In other words, when cathode region 110 is positioned opposite the outer edge of well region 54, inner field region 56A, intermediate field regions 56B and 56C, and outer field region 56D in the thickness direction, electric field concentration at the outer edge of well region 54, inner field region 56A, intermediate field regions 56B and 56C, and outer field region 56D can be alleviated.

[0149] 15, the position PK corresponding to the maximum electric field strength is located within the range RA corresponding to the inner field region 56A. The outer edge of the well region 54 has the next highest electric field strength after the position PK. As shown in FIG. 13, the cathode region 110 is provided to face the outer edge of the well region 54 and the inner field region 56A of the multiple field regions 56 in the thickness direction of the chip 12. This alleviates electric field concentration in the outer edge of the well region 54 and the inner field region 56A, where the electric field strength tends to be high in the peripheral region 18.

[0150] 16 is a graph showing the current-voltage characteristics of the RC-IGBT chip 10 and the SiC-SBD chip 8. In FIG. 16, the rated current IFA of the SiC-SBD chip 8 is indicated by a dashed line. The vertical axis of the graph in FIG. 16 represents the forward current IF (A) of the diode 112 of the RC-IGBT chip 10 and the forward current IF (A) of the SiC-SBD chip 8. The horizontal axis of the graph in FIG. 16 represents the forward voltage VF (V) of the diode 112 of the RC-IGBT chip 10 and the forward voltage VF (V) of the SiC-SBD chip 8.

[0151] 16 shows a first characteristic G1 and a second characteristic G2 as graphs. The first characteristic G1 shows the forward current-voltage characteristics of the diode 112 of the RC-IGBT chip 10 when it is electrically isolated from the SiC-SBD chip 8. The first characteristic G1 is the characteristic when a forward voltage VF is applied between the anode and cathode of the diode 112 when the gate voltage of the RC-IGBT chip 10 is 0 V (the RC-IGBT chip 10 is in an off state). The second characteristic G2 shows the forward current-voltage characteristics of the SiC-SBD chip 8 when it is electrically isolated from the RC-IGBT chip 10. The second characteristic G2 is the characteristic when a forward voltage VF is applied between the anode and cathode of the SiC-SBD chip 8. The direction in which the forward voltage VF of the SiC-SBD chip 8 is applied coincides with the direction in which the forward voltage VF of the diode 112 is applied. The direction in which the forward current IF flows through the SiC-SBD chip 8 coincides with the direction in which the forward current IF flows through the diode 112 .

[0152] In the first characteristic G1, the RC-IGBT chip 10 does not operate when the forward threshold voltage VF1 is less than that. On the other hand, when the forward threshold voltage VF1 or greater is reached, the RC-IGBT chip 10 becomes conductive between the emitter and collector, and a forward current IF begins to flow. The forward threshold voltage VF1 can be defined as the forward voltage VF at which the forward current IF begins to flow through the diode 112.

[0153] In the second characteristic G2, the SiC-SBD chip 8 does not operate when the forward threshold voltage is less than VF2. On the other hand, when the forward threshold voltage is equal to or greater than VF2, a forward current IF begins to flow through the SiC-SBD chip 8. In the first embodiment, the forward threshold voltage VF2 of the SiC-SBD chip 8 and the forward threshold voltage VF1 of the diode 112 of the RC-IGBT chip 10 are approximately the same forward voltage.

[0154] In the second characteristic G2, the forward current I increases as the forward voltage VF increases after the forward voltage VF reaches the forward threshold voltage VF2. Here, in the second characteristic G2, the increase in the forward current I with respect to the increase in the forward voltage VF is nearly linear.

[0155] In the first characteristic G1, the forward current I increases with increasing forward voltage VF in a curved manner similar to the graph of a quadratic function. Therefore, compared to the second characteristic G2, the first characteristic G1 exhibits a more gradual increase in forward current I as the forward voltage VF increases after the forward voltage VF reaches the forward threshold voltage VF1. That is, in the first characteristic G1, the forward voltage VF at the same current is lower than the forward voltage VF of the SiC-SBD chip 8 within a predetermined range from the forward threshold voltage VF1. On the other hand, in the first characteristic G1, once the forward voltage VF exceeds the predetermined range, the forward voltage VF at the same current becomes higher than the forward voltage VF of the SiC-SBD chip 8. Furthermore, in the first characteristic G1, the forward current I of the RC-IGBT chip 10 becomes lower than the forward current I of the SiC-SBD chip 8 within a range lower than the rated current IFA of the SiC-SBD chip 8.

[0156] As described above, the first characteristic G1 and the second characteristic G2 are divided into a first region R1 where the forward current I of the RC-IGBT chip 10 is smaller than the forward current I of the SiC-SBD chip 8, and a second region R2 where the forward current I of the RC-IGBT chip 10 is larger than the forward current I of the SiC-SBD chip 8. The second region R2 is a region where the forward current I is higher than that of the first region R1. In the first region R1, the forward current I of the diode 112 of the RC-IGBT chip 10 is smaller than the forward current I of the SiC-SBD chip 8 at the same forward voltage VF. That is, in the first region R1, current flows preferentially through the SiC-SBD chip 8 over the diode 112 of the RC-IGBT chip 10. On the other hand, in the second region R2, the forward current I of the diode 112 of the RC-IGBT chip 10 is larger than the forward current I of the SiC-SBD chip 8 at the same forward voltage VF. That is, in the second region R2, the current flows preferentially through the diode 112 of the RC-IGBT chip 10 rather than through the SiC-SBD chip 8.

[0157] In the first embodiment, the boundary RBD between the first region R1 and the second region R2 is larger than the rated current IFA of the SiC-SBD chip 8. Therefore, in the range equal to or less than the rated current of the SiC-SBD chip 8, current flows preferentially through the SiC-SBD chip 8 rather than through the diode 112 of the RC-IGBT chip 10.

[0158] Here, the first characteristic G1 is determined based on the position and area of ​​the cathode region 110. That is, at least one of the position and area of ​​the cathode region 110 is set so that the boundary RBD between the first region R1 and the second region R2 shown in FIG. 16 is larger than the rated current IFA of the SiC-SBD chip 8. It can also be said that the first characteristic G1 is set so that the forward current I of the RC-IGBT chip 10 is smaller than the forward current I of the SiC-SBD chip 8 within a range smaller than the rated current IFA of the SiC-SBD chip 8. Specifically, as shown in FIG. 13 , the cathode region 110 is provided so as to face the entire well region 54 and the inner end field region 56A of the multiple field regions 56 in the thickness direction of the chip 12. In this way, the area of ​​the cathode region 110 can be adjusted by changing the width W1 of the cathode region 110. On the other hand, the cathode region 110 is provided so as not to face the IGBT region 14, nor the intermediate field regions 56B, 56C and the outer end field region 56D of the multiple field regions 56, in the thickness direction of the chip 12. In this way, by providing the cathode region 110, the RC-IGBT chip 10 allows current to be returned preferentially to the SiC-SBD chip 8 over the diode 112 of the RC-IGBT chip 10 in a range equal to or less than the rated current IFA of the SiC-SBD chip 8.

[0159] [Operation of the first embodiment] The operation of the semiconductor device 1 of the first embodiment will be described with reference to FIGS. Fig. 17 is a graph showing the relationship between forward voltage VF and peak surge current IFSM. In Fig. 17, circles indicate plots showing the relationship between forward voltage VF and peak surge current IFSM for a configuration including only the RC-IGBT chip 10. Squares indicate plots showing the relationship between forward voltage VF and peak surge current IFSM for a configuration including only the SiC-SBD chip 8. Triangles indicate plots showing the relationship between forward voltage VF and peak surge current IFSM for the semiconductor device 1 (a combination of the RC-IGBT chip 10 and the SiC-SBD chip 8).

[0160] The semiconductor device 1 includes the RC-IGBT chip 10 and the SiC-SBD chip 8, and thus allows current to flow through both the diode 112 of the RC-IGBT chip 10 and the SiC-SBD chip 8. Therefore, as shown in Fig. 17, the semiconductor device 1 can increase the peak surge current IFSM compared to a configuration including only the RC-IGBT chip 10 and a configuration including only the SiC-SBD chip 8.

[0161] 18 schematically shows the cross-sectional structure of an RC-IGBT chip 10X in a semiconductor device of the comparative example. The RC-IGBT chip 10X of the comparative example differs from the RC-IGBT chip 10 of the first embodiment in the arrangement position and area of ​​the cathode region 110X. More specifically, the cathode region 110X is provided over the entire well region 54, the inner end field region 56A, and a part of the IGBT region 14.

[0162] Fig. 19 is a graph showing the relationship between current-voltage characteristics in a semiconductor device of a comparative example and the semiconductor device 1 of the first embodiment. The vertical axis of the graph in Fig. 19 represents the forward current I F (A) of the diode 112X of the RC-IGBT chip 10X and the forward current I F (A) of the SiC-SBD chip 8. The horizontal axis of the graph in Fig. 19 represents the forward voltage V F (V) of the diode 112X of the RC-IGBT chip 10X and the forward voltage V F (V) of the SiC-SBD chip 8.

[0163] 19 shows a comparative characteristic GX and a second characteristic G2 as graphs. The comparative characteristic GX shows the forward current-voltage characteristics of the diode 112X of the RC-IGBT chip 10X in a state where it is electrically isolated from the SiC-SBD chip 8. The comparative characteristic GX is the characteristic when a forward voltage VF is applied between the anode and cathode of the diode 112X when the gate voltage of the RC-IGBT chip 10X is 0 V (the RC-IGBT chip 10X is in an off state).

[0164] As shown in FIG. 19, in the comparative characteristic GX, the RC-IGBT chip 10 does not operate when the forward threshold voltage VFX is less than the forward threshold voltage VFX. On the other hand, when the forward threshold voltage VFX is equal to or greater than the RC-IGBT chip 10, conduction occurs between the emitter and collector, and a forward current IF begins to flow. The forward threshold voltage VFX can be defined as the forward voltage VF at which the forward current IF begins to flow through the diode 112X. In one example, the forward threshold voltage VFX is approximately equal to the forward threshold voltage VF1 (see FIG. 16) of the semiconductor device 1 of the first embodiment.

[0165] In comparison with the second characteristic G2, the comparative characteristic GX shows that the forward current I increases more gradually as the forward voltage VF increases after the forward voltage VF reaches the forward threshold voltage VFX. That is, in the comparative characteristic GX, the forward voltage VF at the same current is lower than the forward voltage VF of the SiC-SBD chip 8 within a predetermined range from the forward threshold voltage VFX. On the other hand, in the comparative characteristic GX, once the forward voltage VF exceeds the predetermined range, the forward voltage VF at the same current becomes higher than the forward voltage VF of the SiC-SBD chip 8.

[0166] As described above, the comparison characteristic GX and the second characteristic G2 are divided into a first comparison region RX1 where the forward current I of the RC-IGBT chip 10 is smaller than the forward current I of the SiC-SBD chip 8, and a second comparison region RX2 where the forward current I of the RC-IGBT chip 10 is larger than the forward current I of the SiC-SBD chip 8. The second comparison region RX2 is a region where the forward current I is higher than that of the first comparison region RX1. In the first comparison region RX1, the forward current I of the diode 112X of the RC-IGBT chip 10X is smaller than the forward current I of the SiC-SBD chip 8 at the same forward voltage VF. In other words, in the first comparison region RX1, current flows preferentially through the SiC-SBD chip 8 rather than through the diode 112X of the RC-IGBT chip 10X. On the other hand, in the second comparison region RX2, at the same forward voltage VF, the forward current I of the diode 112X of the RC-IGBT chip 10X is larger than the forward current I of the SiC-SBD chip 8. In other words, in the second comparison region RX2, current flows preferentially through the diode 112X of the RC-IGBT chip 10X rather than through the SiC-SBD chip 8.

[0167] In the semiconductor device of the comparative example, the boundary RXA between the first comparison region RX1 and the second comparison region RX2 is smaller than the rated current IFA of the SiC-SBD chip 8. Therefore, in a range equal to or less than the rated current of the SiC-SBD chip 8, current may flow preferentially through the diode 112X of the RC-IGBT chip 10X rather than through the SiC-SBD chip 8.

[0168] On the other hand, as shown in FIG. 16, in the semiconductor device 1 of the first embodiment, current flows preferentially through the SiC-SBD chip 8 rather than through the diode 112 of the RC-IGBT chip 10 in a range equal to or less than the rated current IFA of the SiC-SBD chip 8.

[0169] [Effects of the first embodiment] According to the semiconductor device 1 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 1 includes an RC-IGBT chip 10 including a gate electrode 10G, a collector electrode 10C, and an emitter electrode 10E, and an SiC-SBD chip 8 including a cathode electrode 8K electrically connected to the collector electrode 10C and an anode electrode 8A electrically connected to the emitter electrode 10E.

[0170] According to this configuration, the diode 1AB (112) of the RC-IGBT chip 10 and the freewheeling diode 1B of the SiC-SBD chip 8 are connected in parallel, so that the peak surge current IFSM can be increased. In other words, the IFSM tolerance can be improved.

[0171] (1-2) The characteristics of the forward voltage VF and forward current IF of the RC-IGBT chip 10 and the SiC-SBD chip 8 are divided into a first region R1 where the forward current IF of the RC-IGBT chip 10 is smaller than the forward current IF of the SiC-SBD chip 8, and a second region R2 where the forward current IF is higher than that of the first region R1 and where the forward current IF of the RC-IGBT chip 10 is larger than the forward current IF of the SiC-SBD chip 8. The boundary RBD between the first region R1 and the second region R2 is larger than the rated current IFA of the SiC-SBD chip 8.

[0172] According to this configuration, in a region of forward current I F equal to or less than the rated current I F of the SiC-SBD chip 8, current flows preferentially through the SiC-SBD chip 8 over the RC-IGBT chip 10. Here, since SiC-SBDs have better recovery characteristics than the diodes of RC-IGBTs, current flows preferentially through the SiC-SBD chip 8 over the diode 112 of the RC-IGBT chip 10, thereby reducing loss in the forward current I F. On the other hand, when a forward current I F greater than the rated current I F of the SiC-SBD chip flows through the semiconductor device 1, the forward current I F flows through both the diode 112 of the RC-IGBT chip 10 and the SiC-SBD chip 8, thereby improving the peak surge current I F S.

[0173] (1-3) The RC-IGBT chip 10 includes a chip 12 including a first main surface 12A and a second main surface 12B opposite to the first main surface 12A, an outer periphery region 18 provided on the periphery of the first main surface 12A, an IGBT region 14 provided on the first main surface 12A inside the outer periphery region 18, a p-type well region 54 provided in a surface layer of the first main surface 12A in the outer periphery region 18 so as to define the IGBT region 14, and an n-type cathode region 110 provided in a surface layer of the second main surface 12B of the outer periphery region 18 and constituting a diode 112 together with the well region 54. At least one of the position and area of ​​the cathode region 110 is set so that the forward current I of the RC-IGBT chip 10 is smaller than the forward current I of the SiC-SBD chip 8 within a range smaller than the rated current I of the SiC-SBD chip 8. According to this configuration, by adjusting at least one of the arrangement position and area of ​​the cathode region 110, the effect of (1-2) above can be easily obtained.

[0174] (1-4) At least one of the position and area of ​​the cathode region 110 is set so that the boundary RBD between the first region R1 and the second region R2 is larger than the rated current IFA of the SiC-SBD chip 8. According to this configuration, by adjusting at least one of the position and area of ​​the cathode region 110, the effect of (1-2) above can be easily obtained.

[0175] (1-5) The RC-IGBT chip 10 includes a plurality of p-type field regions 56 arranged at a distance from one another. The plurality of field regions 56 are provided at intervals from the well region 54 toward the periphery of the chip 12 in the surface layer portion of the first main surface 12A of the peripheral region 18. The cathode region 110 includes a portion arranged in a position facing at least one of the plurality of field regions 56 in the thickness direction of the chip 12.

[0176] With this configuration, the cathode region 110 faces at least one of the field regions 56 in the thickness direction of the chip 12, thereby mitigating electric field concentration in the field regions 56. As a result, when a collector-emitter voltage Vce is applied, the voltage in the field regions 56 is less likely to reach a breakdown voltage (BV). This improves resistance to the breakdown voltage. In other words, the electrical characteristics of the semiconductor device 1 can be improved.

[0177] (1-6) The cathode region 110 includes a portion that is disposed in a position facing the inner end field region 56A, which is the closest to the well region 54 among the multiple field regions 56, in the thickness direction of the chip 12.

[0178] With this configuration, the cathode region 110 faces the inner end field region 56A in the thickness direction of the chip 12, thereby mitigating electric field concentration in the inner end field region 56A, which has the highest electric field strength among the multiple field regions 56. As a result, when the collector-emitter voltage Vce is applied, the voltage in the inner end field region 56A is less likely to reach the breakdown voltage. This improves resistance to the breakdown voltage. In other words, the electrical characteristics of the semiconductor device 1 can be improved.

[0179] (1-7) Each of the plurality of field regions 56 has a predetermined width WF. The width W1 of the cathode region 110 is larger than the width WF of one of the plurality of field regions 56.

[0180] According to this configuration, the area of ​​the cathode region 110 can be increased, and therefore the forward current IF in the second region R2 can be increased, thereby improving the peak surge current IFSM.

[0181] (1-8) The cathode regions 110 are provided so as to face the entire periphery of the inner end field regions 56A that face each other in the thickness direction of the chip 12. This configuration can alleviate electric field concentration over the entire periphery of the inner end field regions 56A.

[0182] (1-9) The cathode regions 110 are arranged to face each other in the thickness direction of the chip 12 across the entire well region 54 and the inner end field region 56A of the plurality of field regions 56.

[0183] This configuration can mitigate electric field concentration in the outer edge portion of the well region 54, where the electric field intensity is high, and in the inner end field region 56A, where the electric field intensity is high, among the multiple field regions 56. In addition, by increasing the area of ​​the cathode region 110, the boundary RBD between the first region R1 and the second region R2 becomes larger than the rated current IFA of the SiC-SBD chip 8, and the forward current IF in the second region R2 can be increased. Therefore, the peak surge current IFSM can be improved.

[0184] Second Embodiment 20 and 21, the semiconductor device 1 of the second embodiment will be described. The semiconductor device 1 of the second embodiment differs from the semiconductor device 1 of the first embodiment mainly in the arrangement position of the cathode region 110 and the width W1 in a plan view. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0185] FIG. 20 shows a schematic cross-sectional structure of the peripheral portion of the chip 12. As shown in FIG. As shown in FIG. 20, the cathode region 110 is provided so as to face the outer edge of the well region 54 and an inner end field region 56A of the plurality of field regions 56 in the thickness direction of the chip 12.

[0186] The width W1 of the cathode region 110 is smaller than the width W1 of the cathode region 110 in the first embodiment (see FIG. 13). The width W1 of the cathode region 110 is smaller than the width WP of the well region 54. The width W1 of the cathode region 110 is smaller than the distance Dwc between the well region 54 and the channel stop region 58. The width W1 of the cathode region 110 is smaller than the total width WT of the multiple field regions 56. The width W1 of the cathode region 110 is larger than the width of the inner end field region 56A.

[0187] As in the first embodiment, the outer edge 111B of the cathode region 110 is located opposite the outer edge of the inner end field region 56A in the thickness direction of the chip 12. The inner edge 111A of the cathode region 110 is located closer to the IGBT region 14 than the outer edge 54B of the well region 54. In other words, the cathode region 110 includes a portion that faces the well region 54 in the thickness direction of the chip 12. The inner edge 111A of the cathode region 110 is located closer to the periphery of the chip 12 than the second well connection electrode 84B.

[0188] [Electrical characteristics of semiconductor devices] The electrical characteristics of the semiconductor device 1 of the second embodiment will be described with reference to Fig. 21. Fig. 21 is a graph showing the current-voltage characteristics of the RC-IGBT chip 10 and the SiC-SBD chip 8. In Fig. 21, the rated current IFA of the SiC-SBD chip 8 is indicated by a dashed line. The vertical axis of the graph in Fig. 21 represents the forward current IF (A) of the diode 112 of the RC-IGBT chip 10 and the forward current IF (A) of the SiC-SBD chip 8. The horizontal axis of the graph in Fig. 21 represents the forward voltage VF (V) of the diode 112 of the RC-IGBT chip 10 and the forward voltage VF (V) of the SiC-SBD chip 8.

[0189] 21 shows a first characteristic T1 and a second characteristic T2 as graphs. The first characteristic T1 represents the forward current-voltage characteristic of the diode 112 of the RC-IGBT chip 10 when the RC-IGBT chip 10 is electrically isolated from the SiC-SBD chip 8. The first characteristic T1 represents the characteristic when a forward voltage VF is applied between the anode and cathode of the diode 112 when the gate voltage of the RC-IGBT chip 10 is 0 V (the RC-IGBT chip 10 is in an off state). The second characteristic T2 represents the forward current-voltage characteristic of the SiC-SBD chip 8 when the RC-IGBT chip 10 is electrically isolated from the RC-IGBT chip 10. The second characteristic T2 represents the characteristic when a forward voltage VF is applied between the anode and cathode of the SiC-SBD chip 8. The second characteristic T2 is the same as the second characteristic G2 (see FIG. 16) of the first embodiment.

[0190] In the first characteristic T1, the diode 112 of the RC-IGBT chip 10 does not operate when the forward threshold voltage VF1 is less than the forward threshold voltage VF1. On the other hand, when the forward threshold voltage VF1 or more is reached, the diode 112 becomes conductive between the emitter and collector, and a forward current IF begins to flow. The forward threshold voltage VF1 is the same value as the forward threshold voltage VF1 in the first embodiment.

[0191] Compared to the second characteristic T2, the first characteristic T1 shows that the forward current I increases more gradually with an increase in the forward voltage VF after the forward voltage VF reaches the forward threshold voltage VF1 than the first characteristic G1 of the first embodiment (see FIG. 16 ). As a result, the forward current I at the same forward voltage VF in the first characteristic T1 is smaller than the forward current I of the SiC-SBD chip 8. That is, in the first characteristic T1 and the second characteristic T2, the forward current I of the RC-IGBT chip 10 is smaller than the forward current I of the SiC-SBD chip 8 over the entire range of the forward voltage VF. As a result, in the RC-IGBT chip 10, current is circulated preferentially through the SiC-SBD chip 8 over the diode 112 of the RC-IGBT chip 10 within a range equal to or less than the rated current of the SiC-SBD chip 8.

[0192] Here, the first characteristic T1 is determined based on the arrangement position and area of ​​the cathode region 110. That is, as shown in FIG. 19 , the cathode region 110 is provided so as to face the outer edge of the well region 54 and the innermost field region 56A of the multiple field regions 56 in the thickness direction of the chip 12. On the other hand, the cathode region 110 is provided so as not to face the IGBT region 14, or the intermediate field regions 56B and 56C and the outermost field region 56D of the multiple field regions 56 in the thickness direction of the chip 12. By providing the cathode region 110 in this manner, the RC-IGBT chip 10 allows current to flow preferentially through the SiC-SBD chip 8 over the diode 112 of the RC-IGBT chip 10 within a range equal to or less than the rated current of the SiC-SBD chip 8.

[0193] [Effects of the second embodiment] According to the semiconductor device 1 of the second embodiment, in addition to the effects (1-1) and (1-5) to (1-8) of the first embodiment, the following effects can be obtained.

[0194] (2-1) In the characteristics of the forward voltage VF and forward current IF of the RC-IGBT chip 10 and the SiC-SBD chip 8, the forward current IF of the RC-IGBT chip 10 is smaller than the forward current IF of the SiC-SBD chip 8 over the entire range of the forward voltage VF.

[0195] With this configuration, current flows preferentially through the SiC-SBD chip 8 over the RC-IGBT chip 10. Here, since SiC-SBDs have better recovery characteristics than the diodes of RC-IGBTs, current flows preferentially through the SiC-SBD chip 8 over the diode 112 of the RC-IGBT chip 10, thereby reducing the loss of the forward current I. On the other hand, when a forward current I.F. larger than the rated current I.F.A. of the SiC-SBD chip flows through the semiconductor device 1, the forward current I.F. flows through both the diode 112 of the RC-IGBT chip 10 and the SiC-SBD chip 8, thereby increasing the peak surge current I.F.S.M.

[0196] (2-2) Over the entire range of the forward voltage VF, at least one of the layout position and area of ​​the cathode region 110 is set so that the forward current I of the RC-IGBT chip 10 is smaller than the forward current I of the SiC-SBD chip 8. According to this configuration, by adjusting at least one of the layout position and area of ​​the cathode region 110, the effect of (2-1) above can be easily obtained.

[0197] (2-3) The cathode region 110 is located closer to the periphery of the chip 12 than the IGBT region 14 and is disposed so as to face at least the well region 54 . According to this configuration, the cathode region 110 is not provided in the IGBT region 14, so that it is possible to prevent the region where the IGBT is formed from becoming smaller in the IGBT region 14. Therefore, it is possible to prevent a deterioration in the electrical characteristics of the RC-IGBT chip 10 (for example, an increase in on-resistance).

[0198] <Third embodiment> 22 to 27, the semiconductor device 1 of the third embodiment will be described. The semiconductor device 1 of the third embodiment differs from the semiconductor device 1 of the first embodiment mainly in the position and area of ​​the cathode region 110. In the following, components common to the first embodiment will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0199] (How to set the cathode area position) 22 to 24, a method for setting the position of the cathode region 110 will be described. In the following description, for the components in the RC-IGBT chip 10 denoted by reference numerals, please refer to the reference numerals of the components of the RC-IGBT chip 10 shown in FIGS. 6 to 13.

[0200] As a method for setting the position of the cathode region 110, for example, the position of the cathode region 110 is set in consideration of the diode characteristics. Although not shown, similarly to the first and second embodiments, the arrangement position and area of ​​the cathode region 110 of the RC-IGBT chip 10 are set so that current returns preferentially to the SiC-SBD chip 8 over the diode 112 of the RC-IGBT chip 10 within a range equal to or less than the rated current of the SiC-SBD chip 8.

[0201] In addition, when a forward voltage VF of the diode 112 is applied between the emitter electrode 92 and the collector electrode 108, a forward current IF flows through the diode 112. The forward current IF flows, for example, from the first well-connecting electrode 84A and the second well-connecting electrode 84B to the cathode region 110. The electrical characteristics of the diode 112 during forward operation vary depending on the position of the cathode region 110. In the third embodiment, the position and area of ​​the cathode region 110 are set with further consideration given to the electrical characteristics of the diode 112 during forward operation.

[0202] FIG. 22 shows the relationship between the forward current IF and the forward voltage VF depending on the position of the cathode region 110. The vertical axis of the graph in FIG. 22 represents the forward current IF (A). The horizontal axis of the graph in FIG. 22 represents the forward voltage VF (V). FIG. 22 shows a first characteristic S1, a second characteristic S2, and a third characteristic S3. The first characteristic S1 represents the characteristic when the cathode region 110 is located at the gate reference position PG. The second characteristic S2 represents the characteristic when the cathode region 110 is located at the first well reference position PW1. The third characteristic S3 represents the characteristic when the cathode region 110 is located at the second well reference position PW2.

[0203] The gate reference position PG is a position directly below the center of the gate line electrode 90. In one example, the gate reference position PG is a position directly below the center of the gate line wiring 70. The gate reference position PG can also be said to be a position facing the gate line electrode 90 in the thickness direction of the chip 12. The gate reference position PG can also be said to be a position facing the gate line wiring 70 in the thickness direction of the chip 12.

[0204] The first well reference position PW1 is a position directly below the first well connecting electrode 84A. In the case of a single first well connecting electrode 84A, the first well reference position PW1 is a position directly below the single first well connecting electrode 84A. In the case of multiple first well connecting electrodes 84A, the first well reference position PW1 is a position directly below the midpoint between the innermost first well connecting electrode 84A arranged on the IGBT region 14 side and the outermost first well connecting electrode 84A arranged on the peripheral edge side of the chip 12.

[0205] The second well reference position PW2 is a position directly below the second well connecting electrode 84B. In the case of a single second well connecting electrode 84B, the second well reference position PW2 is a position directly below the single second well connecting electrode 84B. In the case of multiple second well connecting electrodes 84B, the second well reference position PW2 is a position directly below the midpoint between the innermost second well connecting electrode 84B arranged on the IGBT region 14 side and the outermost second well connecting electrode 84B arranged on the peripheral edge side of the chip 12.

[0206] 22, the forward current IF according to the second characteristic S2 is larger than the forward current IF according to the first characteristic S1. Moreover, the forward current IF according to the third characteristic S3 is larger than the forward current IF according to the first characteristic S1. As described above, the cathode region 110 is preferably disposed so as to avoid the gate reference position PG in order to suppress a detour current path. Furthermore, in consideration of the first to third characteristics S1 to S3 shown in FIG. 22, the cathode region 110 is preferably disposed at either or both of the first well reference position PW1 and the second well reference position PW2.

[0207] 23 and 24 are graphs showing the relationship between the position of the cathode region 110 and the forward current I of the diode 112. The vertical axis in FIGS. 23 and 24 represents the forward current I (A). The horizontal axis in FIGS. 23 and 24 represents the position of the cathode region 110. The graphs in FIGS. 23 and 24 show the change in forward current I when the position of the cathode region 110 is changed from directly below the well region 54 to directly below the intermediate field region 56C, which is located closer to the periphery of the chip 12 than the inner end field region 56A, among the multiple field regions 56. The width W1 of the cathode region 110 is fixed to a constant value (10 μm in FIGS. 23 and 24).

[0208] On the horizontal axis of FIGS. 23 and 24, the first well reference position PW1 is a position directly below the first well connecting electrode 84A. When a single first well connecting electrode 84A is formed, the first well reference position PW1 is a position directly below the center of the single first well connecting electrode 84A. When multiple first well connecting electrodes 84A are formed, the first well reference position PW1 is a position directly below the midpoint between the innermost first well connecting electrode 84A arranged on the IGBT region 14 side and the outermost first well connecting electrode 84A arranged on the peripheral edge side of the chip 12. The first well reference position PW1 can also be said to be a position facing the first well connecting electrode 84A in the thickness direction of the chip 12.

[0209] The second well reference position PW2 is a position directly below the second well connection electrode 84B. When a single second well connection electrode 84B is formed, the second well reference position PW2 is a position directly below the center of the single second well connection electrode 84B. When multiple second well connection electrodes 84B are formed, the second well reference position PW2 is a position directly below the midpoint between the innermost second well connection electrode 84B arranged on the IGBT region 14 side and the outermost second well connection electrode 84B arranged on the peripheral edge side of the chip 12. The second well reference position PW2 can also be said to be a position facing the second well connection electrode 84B in the thickness direction of the chip 12. Here, both the first well reference position PW1 and the second well reference position PW2 are examples of "well reference positions."

[0210] 23 and 24, the forward current I gradually decreases as the position of the cathode region 110 approaches from the first well reference position PW1 to the gate reference position PG. The forward current I gradually increases as the position of the cathode region 110 approaches from the gate reference position PG to the second well reference position PW2. The forward current I gradually decreases as the position of the cathode region 110 moves from the second well reference position PW2 toward the periphery of the chip 12. In other words, the forward current I gradually decreases as the position of the cathode region 110 moves from the outer edge 54B of the well region 54 toward the channel stop region 58. In other words, the forward current I gradually increases as the position of the cathode region 110 moves from the channel stop region 58 toward the outer edge 54B of the well region 54. Therefore, the forward current I increases as the cathode region 110 is positioned from the outermost field region 56D toward the well region 54 among the multiple field regions 56. That is, the forward current I when the cathode region 110 is positioned directly below the innermost field region 56A and the intermediate field regions 56B and 56C is larger than the forward current I when the cathode region 110 is positioned directly below the outermost field region 56D. In addition, the forward current I when the cathode region 110 is positioned directly below the intermediate field region 56B is larger than the forward current I when the cathode region 110 is positioned directly below the intermediate field region 56C of the cathode region 110. The forward current I when the cathode region 110 is positioned directly below the innermost field region 56A is larger than the forward current I when the cathode region 110 is positioned directly below the intermediate field region 56B of the cathode region 110.

[0211] Furthermore, the forward current IF has a first maximum value v1 when the cathode region 110 is located at the first well reference position PW1. The forward current IF has a minimum value v2 when the cathode region 110 is located at the gate reference position PG. The forward current IF has a second maximum value v3 when the cathode region 110 is located at the second well reference position PW2.

[0212] When the cathode region 110 is located near the center between the first well reference position PW1 and the gate reference position PG, the forward current I is near the intermediate value between the first maximum value v1 and the minimum value v2. The value near the intermediate value between the first maximum value v1 and the minimum value v2 is also near the first inflection point v4 between the first maximum value v1 and the minimum value v2.

[0213] When the cathode region 110 is located near the position immediately below the midpoint between the gate reference position PG and the second well reference position PW2, the forward current I is near the intermediate value between the minimum value v2 and the second maximum value v3. The value near the intermediate value between the minimum value v2 and the second maximum value v3 is also near the second inflection point v5 between the minimum value v2 and the second maximum value v3.

[0214] For the above reasons, it is preferable that a prohibited range 122 that prohibits placement of the cathode region 110 near the gate reference position PG is set on the second main surface 12B. It is also preferable that a first allowed range 124 that permits placement of a part or the whole of the cathode region 110 near the first well reference position PW1 is set on the second main surface 12B. It is also preferable that a second allowed range 126 that permits placement of a part or the whole of the cathode region 110 is set near the second well reference position PW2.

[0215] Next, a description will be given of setting examples of the prohibited range 122, the first allowed range 124, and the second allowed range 126. Fig. 23 shows the first setting example, and Fig. 24 shows the second setting example. (First setting example) In the first setting example, the prohibited range 122, the first allowed range 124, and the second allowed range 126 are set separately for the distance between the first well reference position PW1 and the gate reference position PG, and the distance between the second well reference position PW2 and the gate reference position PG.

[0216] 23, when the cathode region 110 is located in a region on the first well reference position PW1 side, the prohibited range 122 and the first allowed range 124 may be set based on a first reference distance Da between the first well reference position PW1 and the gate reference position PG. Here, the first reference distance Da is an example of a "reference distance as the distance between the center of the gate line electrode and the well connecting electrode."

[0217] In this case, the prohibited range 122 is set within a range not exceeding half the first reference distance Da from the gate reference position PG. The prohibited range 122 is set on the IGBT region 14 side from the first well reference position PW1. In this case, the cathode region 110 is disposed at least half the first reference distance Da away from the gate reference position PG toward the first well reference position PW1. In other words, the cathode region 110 is not disposed within a range not exceeding half the first reference distance Da from the gate reference position PG toward the first well reference position PW1.

[0218] On the other hand, the first allowable range 124 is set within a range not exceeding half the first reference distance Da from the first well reference position PW1. The first allowable range 124 is set on the IGBT region 14 side and the gate reference position PG side from the first well reference position PW1. In this case, at least a portion of the cathode region 110 is disposed within a range not exceeding half the first reference distance Da from the first well reference position PW1. In other words, the cathode region 110 has a portion disposed within a range not exceeding half the first reference distance Da from the first well reference position PW1 directly below the first well connecting electrode 84A.

[0219] Furthermore, when the cathode region 110 is disposed in a region on the side of the second well reference position PW2, the forbidden range 122 and the second allowed range 126 are set based on a second reference distance Db between the second well reference position PW2 and the gate reference position PG. Here, the second reference distance Db is an example of a "reference distance as the distance between the center of the gate line electrode and the well connecting electrode."

[0220] In this case, the prohibited area 122 is set within a range not exceeding half the second reference distance Db from the gate reference position PG. The prohibited area 122 is set on the second well reference position PW2 side from the gate reference position PG. In this case, the cathode region 110 is positioned at least half the second reference distance Db from the gate reference position PG toward the second well reference position PW2. In other words, the cathode region 110 is not positioned within a range not exceeding half the first reference distance Da from the gate reference position PG toward the second well reference position PW2.

[0221] On the other hand, the second allowable range 126 is set within a range not exceeding half the second reference distance Db from the second well reference position PW2. The second allowable range 126 is set on the periphery of the chip 12 and on the gate reference position PG side from the second well reference position PW2. In this case, at least a portion of the cathode region 110 is positioned within a range not exceeding half the second reference distance Db from the second well reference position PW2. In other words, the cathode region 110 has a portion positioned within a range not exceeding half the first reference distance Da from the second well reference position PW2 directly below the second well connection electrode 84B.

[0222] When the cathode region 110 is positioned in both the region on the first well reference position PW1 side and the region on the second well reference position PW2 side, the prohibited range 122 is set to a range not exceeding 1 / 2 the first reference distance Da from the gate reference position PG toward the first well reference position PW1 side, and a range not exceeding 1 / 2 the second reference distance Db from the gate reference position PG toward the second well connection electrode 84B side.

[0223] On the other hand, the first allowable range 124 is set within a range not exceeding half the distance of the first reference distance Da with respect to the first well reference position PW1. The first allowable range 124 is set on the IGBT region 14 side and the gate reference position PG side with respect to the first well reference position PW1. On the other hand, the second allowable range 126 is set within a range not exceeding half the distance of the second reference distance Db with respect to the second well reference position PW2. The second allowable range 126 is set on the peripheral edge side of the chip 12 and the gate reference position PG side with respect to the second well reference position PW2.

[0224] The first reference distance Da may be 1 μm or more and 50 μm or less. The first reference distance Da may be set to a value within any of the following ranges: 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, and 45 μm or more and 50 μm or less. The first reference distance Da is preferably 10 μm or more and 30 μm or less. Furthermore, the first reference distance Da is preferably 10 μm or more and 20 μm or less.

[0225] The second reference distance Db may be less than the first reference distance Da or may be greater than or equal to the first reference distance Da. In one example, the second reference distance Db is greater than the first reference distance Da. The second reference distance Db may be 1 μm or greater and 100 μm or less. The second reference distance Db may be set to a value within any of the following ranges: 1 μm or greater and 5 μm or less, 5 μm or greater and 10 μm or less, 10 μm or greater and 20 μm or less, 20 μm or greater and 30 μm or less, 30 μm or greater and 40 μm or less, 40 μm or greater and 50 μm or less, 50 μm or greater and 60 μm or less, 60 μm or greater and 70 μm or less, 70 μm or greater and 80 μm or less, 80 μm or greater and 90 μm or less, and 90 μm or greater and 100 μm or less. The second reference distance Db is preferably 10 μm or greater and 60 μm or less. Moreover, the second reference distance Db is preferably not less than 20 μm and not more than 40 μm.

[0226] (Second setting example) In the second setting example, the prohibited range 122, the first allowed range 124, and the second allowed range 126 are set based on the distance between the first well reference position PW1 and the second well reference position PW2. As shown in Fig. 24, when the cathode region 110 is placed at an intermediate reference position PW3 immediately below the midpoint between the first well reference position PW1 and the second well reference position PW2, the forward current I F becomes a value close to the minimum value v2.

[0227] The forward current I F becomes a value near the intermediate value between the first maximum value v1 and the minimum value v2 (a value near the first inflection point v4) when the cathode region 110 is positioned near the point immediately below the midpoint between the first well reference position PW1 and the intermediate reference position PW3. The forward current I F becomes a value near the intermediate value between the second maximum value v3 and the minimum value v2 (a value near the second inflection point v5) when the cathode region 110 is positioned near the point immediately below the midpoint between the second well reference position PW2 and the intermediate reference position PW3.

[0228] For the above reasons, the prohibited range 122, the first allowed range 124, and the second allowed range 126 may be set based on the third reference distance Dc between the first well reference position PW1 and the second well reference position PW2. The third reference distance Dc is also the sum of the first reference distance Da and the second reference distance Db (Dc = Da + Db) shown in FIG. 23. That is, in the second setting example, the prohibited range 122, the first allowed range 124, and the second allowed range 126 are set based on the third reference distance Dc without using the first reference distance Da and the second reference distance Db. Here, the third reference distance Dc is an example of a "reference distance as the distance between the first well connecting electrode and the second well connecting electrode."

[0229] In this case, the prohibited range 122 may be set to a range not exceeding ¼ of the third reference distance Dc from an intermediate reference position PW3 immediately below the midpoint between the first well reference position PW1 and the second well reference position PW2. When the cathode region 110 is positioned in a region on the first well reference position PW1 side, the prohibited range 122 is set on the first well reference position PW1 side using the intermediate reference position PW3 as a reference. When the cathode region 110 is positioned in a region on the second well reference position PW2 side, the prohibited range 122 is set on the second well reference position PW2 side using the intermediate reference position PW3 as a reference.

[0230] On the other hand, the first allowable range 124 is set within a range not exceeding ¼ of the third reference distance Dc with respect to the first well reference position PW1. The first allowable range 124 is set on the IGBT region 14 side and the gate reference position PG side with respect to the first well reference position PW1. On the other hand, the second allowable range 126 is set within a range not exceeding ¼ of the third reference distance Dc with respect to the second well reference position PW2. The second allowable range 126 is set on the IGBT region 14 side and the gate reference position PG side with respect to the second well reference position PW2.

[0231] 24, the cathode region 110 is disposed at a distance from the intermediate reference position PW3. The cathode region 110 is preferably disposed in an area outside the prohibited range 122. In other words, the cathode region 110 is preferably not disposed within a range that does not exceed ¼ of the third reference distance Dc from the intermediate reference position PW3.

[0232] The cathode region 110 may be located in a region closer to the first well reference position PW1 than the intermediate reference position PW3. In this case, it is preferable that a portion or the entire cathode region 110 be located within the first allowable range 124. That is, it is preferable that the cathode region 110 is not located within a range from the intermediate reference position PW3 toward the first well connection electrode 84A that does not exceed ¼ of the third reference distance Dc. It is also preferable that the cathode region 110 has a portion located within a range from the first well reference position PW1 toward the intermediate reference position PW3 that does not exceed ¼ of the third reference distance Dc. In this case, it is preferable that the cathode region 110 be located at the first well reference position PW1. That is, it is preferable that the cathode region 110 faces the first well connection electrode 84A in the thickness direction of the chip 12.

[0233] The cathode region 110 may also be located in a region closer to the second well reference position PW2 than the intermediate reference position PW3. In this case, it is preferable that a portion or the entire cathode region 110 be located within the second allowable range 126. That is, it is preferable that the cathode region 110 is not located within a distance not exceeding 1 / 4 of the third reference distance Dc from the intermediate reference position PW3 toward the second well connection electrode 84B. It is also preferable that the cathode region 110 has a portion located within a distance not exceeding 1 / 4 of the third reference distance Dc from the second well reference position PW2 toward the intermediate reference position PW3. In this case, it is preferable that the cathode region 110 be located at the second well reference position PW2. That is, it is preferable that the cathode region 110 faces the second well connection electrode 84B in the thickness direction of the chip 12.

[0234] (Peak surge current IFSM) The relationship between the position of the cathode region 110 and the peak surge current IFSM will be described with reference to Fig. 25. Fig. 25 is a graph showing the relationship between the peak surge current IFSM and the forward voltage VF when the position of the cathode region 110 is adjusted. The vertical axis of Fig. 25 represents the peak surge current IFSM (A), and the horizontal axis of Fig. 25 represents the forward voltage VF (V). The peak surge current IFSM is the peak value of a commercial sinusoidal half-wave current (50 Hz or 60 Hz) of one cycle or more that is permissible without causing breakdown.

[0235] 25 shows first to sixth plot points P1 to P6. The first to third plot points P1 to P3 show the characteristics when the cathode region 110 is arranged at a distance from the well region 54 towards the periphery of the chip 12. The positions of the cathode regions 110 approach the well region 54 in the order of the first plot point P1, the second plot point P2, and the third plot point P3.

[0236] The fourth to sixth plot points P4 to P6 show the characteristics when the cathode region 110 is placed in a position facing the well region 54. The positions of the cathode region 110 approach the second well reference position PW2 from the outer edge 54B side of the well region 54 in the order of the fourth plot point P4, the fifth plot point P5, and the sixth plot point P6. The sixth plot point P6 shows the characteristics when the cathode region 110 is placed at the second well reference position PW2. At the first to sixth plot points P1 to P6, the width W1 of the cathode region 110 is fixed to a constant value (here, 10 μm).

[0237] With reference to the first to sixth plot points P1 to P6, the peak surge current IFSM associated with the fourth to sixth plot points P4 to P6 is greater than the peak surge current IFSM associated with the first to third plot points P1 to P3. The peak surge current IFSM associated with the sixth plot point P6 is greater than the peak surge current IFSM associated with the first to fifth plot points P1 to P5. Therefore, from the viewpoint of the peak surge current IFSM, it is preferable that the cathode region 110 be disposed in a region immediately below the well region 54. In particular, it is preferable that the cathode region 110 be disposed at the second well reference position PW2.

[0238] (Cathode area layout) Next, layout examples of the cathode region 110 will be described with reference to Fig. 26. Fig. 26 shows the cross-sectional structure of the peripheral portion of the chip 12 including the cathode region 110 of a first layout example. Fig. 27 shows the cross-sectional structure of the peripheral portion of the chip 12 including the cathode region 110 of a second layout example.

[0239] 26, the RC-IGBT chip 10 may include, as the cathode region 110, a cathode region 110 according to a layout example that is provided in consideration of the results of FIGS. 22 to 25 described above. The cathode region 110 is arranged at a distance from the gate reference position PG along the second main surface 12B. Specifically, the cathode region 110 is arranged at a distance from the gate reference position PG toward the second well reference position PW2 along the second main surface 12B. In other words, the cathode region 110 is arranged to face, in the thickness direction of the chip 12, a region that is spaced apart from the gate line electrode 90 toward the second well connection electrode 84B.

[0240] In the third embodiment, the cathode region 110 is disposed so as to face, in the thickness direction of the chip 12, a region spaced closer to the second well connecting electrode 84B than the gate line electrode 90. For this reason, it can be said that the cathode region 110 is disposed so as to face, in the thickness direction of the chip 12, a region spaced closer to the second well connecting electrode 84B than the gate line electrode 90.

[0241] The cathode region 110 is located in the second allowed range 126 but is not located in the prohibited range 122. Here, the prohibited range 122 and the second allowed range 126 according to the first or second setting example may be applied. The cathode region 110 is located at the second well reference position PW2. The cathode region 110 includes a portion facing the plurality of second well connection electrodes 84B in the thickness direction of the chip 12. The cathode region 110 is located at a distance from the gate line electrode 90 toward the second well reference position PW2 so as not to face the gate line electrode 90 in the thickness direction of the chip 12.

[0242] The cathode region 110 is arranged at a distance from a position directly below the center of the gate line wiring 70 toward the second well reference position PW2. The cathode region 110 is arranged at a distance from a position directly below the plurality of gate connection electrodes 80 toward the second well reference position PW2 so as not to face the plurality of gate connection electrodes 80 in the thickness direction of the chip 12. The cathode region 110 is arranged at a distance from the gate line wiring 70 toward the second well reference position PW2 so as not to face the gate line wiring 70 in the thickness direction of the chip 12.

[0243] The cathode region 110 is disposed at a distance from a position directly below the outer edge 54B of the well region 54 toward the second well reference position PW2. The cathode region 110 is disposed only in a region facing the well region 54 in the thickness direction of the chip 12 in the surface layer portion of the second main surface 12B.

[0244] 27, the RC-IGBT chip 10 may include a cathode region 110 according to the second layout example as the cathode region 110. The cathode region 110 includes a first cathode region 110A arranged on the first well reference position PW1 side and a second cathode region 110B arranged on the second well reference position PW2 side.

[0245] The first cathode region 110A is disposed at a distance from the gate reference position PG along the second main surface 12B. Specifically, the first cathode region 110A is disposed at a distance from the gate reference position PG to the first well reference position PW1 side (the IGBT region 14 side) along the second main surface 12B.

[0246] The first cathode region 110A is located in the first allowed range 124, but is not located in the prohibited range 122. Here, the prohibited range 122 and the first allowed range 124 according to the first setting example or the second setting example may be applied. The first cathode region 110A is located at the first well reference position PW1. The first cathode region 110A faces a plurality of first well connection electrodes 84A in the thickness direction of the chip 12. The first cathode region 110A is located at a distance from the gate line electrode 90 toward the first well reference position PW1 so as not to face the gate line electrode 90 in the thickness direction of the chip 12.

[0247] The first cathode region 110A is disposed at a distance from a position directly below the center of the gate line wiring 70 toward the first well reference position PW1. The first cathode region 110A is disposed at a distance from a position directly below the plurality of gate connection electrodes 80 toward the first well reference position PW1 so as not to face the plurality of gate connection electrodes 80 in the thickness direction of the chip 12. The first cathode region 110A is disposed at a distance from the gate line wiring 70 toward the first well reference position PW1 so as not to face the gate line wiring 70 in the thickness direction of the chip 12.

[0248] The first cathode region 110A is preferably disposed at a distance from a position directly below the inner edge 54A of the well region 54 toward the first well reference position PW1, regardless of the first allowable range 124. In other words, the first cathode region 110A is disposed only in a region of the surface layer portion of the second main surface 12B that faces the well region 54 in the thickness direction of the chip 12.

[0249] Furthermore, the first cathode region 110A is preferably arranged at a distance from the plurality of trench gate structures 38 on the peripheral edge side of the chip 12 so as not to face the plurality of trench gate structures 38 in the thickness direction of the chip 12. The first cathode region 110A is preferably arranged at a distance from the trench isolation structure 26 on the peripheral edge side of the chip 12 so as not to face the trench isolation structure 26 in the thickness direction of the chip 12.

[0250] In other words, the first cathode region 110A is preferably disposed at a distance from the IGBT region 14 toward the periphery of the chip 12 so as not to face the IGBT region 14 in the thickness direction of the chip 12. In other words, the first cathode region 110A is preferably disposed only in the outer periphery region 18, and not in the IGBT region 14. For this reason, the first cathode region 110A does not face the base region 36 in the thickness direction of the chip 12. In this case, it is possible to suppress the electrical influence from the IGBT region 14 to the diode 112, and also to suppress the electrical influence from the diode 112 to the IGBT region 14. In this way, it can be said that the first cathode region 110A is provided in a ring shape (a quadrangular ring shape in the first embodiment) surrounding the IGBT region 14 in a plan view.

[0251] The second cathode region 110B is provided in a layout similar to that of the cathode region 110 according to the first layout example shown in Fig. 26. In one example, the second cathode region 110B is arranged at a distance from the intermediate reference position PW3 toward the second well connection electrode 84B. The second cathode region 110B faces the first cathode region 110A in the surface layer portion of the second main surface 12B, with part of the collector region 24 sandwiched therebetween.

[0252] In the first and second layout examples, a portion of the collector region 24 faces the gate line wiring 70, the gate connection electrode 80, and the gate line electrode 90 in the thickness direction of the chip 12. It is preferable that a portion of the collector region 24 faces the entire gate line electrode 90 in the thickness direction of the chip 12. It is preferable that a portion of the collector region 24 faces the entire gate line wiring 70 in the thickness direction of the chip 12.

[0253] [Effects of the third embodiment] According to the semiconductor device 1 of the third embodiment, in addition to the effects (1-1) to (1-4) of the first embodiment, the following effects can be obtained.

[0254] (3-1) The cathode region 110 is provided on the surface layer of the second main surface 12B of the chip 12 so as to face the well region 54 and spaced from the gate reference position PG directly below the center of the gate line electrode 90 toward the well connection electrode 84.

[0255] This configuration can prevent the formation of a current detour path that goes around to the region immediately below the gate line electrode 90 in the region between the well-connecting electrode 84 and the cathode region 110. This allows the cathode region 110 to increase the forward current I of the diode 112.

[0256] (3-2) The cathode region 110 is disposed so as to face the well-connecting electrode 84 in the thickness direction of the chip 12. This configuration allows the formation of a current path that linearly connects the well-connecting electrode 84 and the cathode region 110. This increases the forward current I of the diode 112 during forward operation, thereby improving the electrical characteristics of the semiconductor device 1.

[0257] (3-3) The cathode region 110 does not face the gate line electrode 90 in the thickness direction of the chip 12. According to this configuration, the formation of a current detouring path that goes around to the region directly below the gate line electrode 90 can be appropriately suppressed.

[0258] (3-4) The well-connecting electrode 84 includes at least one of a first well-connecting electrode 84A arranged on the inner edge 54A side of the well region 54 and a second well-connecting electrode 84B arranged on the outer edge 54B side of the well region 54.

[0259] According to this configuration, when the well-connecting electrode 84 includes the first well-connecting electrode 84A, the gate line electrode 90 is disposed at a distance from the first well-connecting electrode 84A toward the outer edge 54B of the well region 54 (toward the periphery of the chip 12). In this case, the cathode region 110 is disposed at a distance from a position directly below the center of the gate line electrode 90 along the second main surface 12B toward the inner edge 54A of the well region 54 (toward the IGBT region 14). This allows the formation of a current path that linearly connects the first well-connecting electrode 84A and the cathode region 110.

[0260] In this case, the RC-IGBT chip 10 preferably includes an emitter pad electrode 94. The emitter pad electrode 94 is disposed on the insulating film 60 at a distance from the gate line electrode 90 toward the IGBT region 14 so as to be electrically connected to the well region 54 via the first well-connecting electrode 84A. The cathode region 110 faces the emitter pad electrode 94 in the thickness direction of the chip 12. This allows the formation of a current path that linearly connects the emitter pad electrode 94 and the cathode region 110.

[0261] Furthermore, when the well-connecting electrode 84 includes the second well-connecting electrode 84B, the gate line electrode 90 may be disposed at a distance from the second well-connecting electrode 84B to the inner edge 54A (toward the IGBT region 14) of the well region 54. In this case, the cathode region 110 is disposed at a distance from a position directly below the center of the gate line electrode 90 along the second main surface 12B to the outer edge 54B side of the well region 54 (toward the peripheral edge of the chip 12). This allows the formation of a current path that linearly connects the second well-connecting electrode 84B and the cathode region 110.

[0262] In this case, the RC-IGBT chip 10 preferably includes an emitter line electrode 96. The emitter line electrode 96 is arranged on the insulating film 60 at a distance from the gate line electrode 90 toward the periphery of the chip 12 so as to be electrically connected to the well region 54 via the second well-connecting electrode 84B. The cathode region 110 faces the emitter line electrode 96 in the thickness direction of the chip 12. This allows the formation of a current path that linearly connects the emitter line electrode 96 and the cathode region 110.

[0263] (3-5) The RC-IGBT chip 10 includes a gate line wiring 70 and a gate connection electrode 80. The gate line wiring 70 is disposed inside the insulating film 60 so as to face the well region 54 in the thickness direction of the chip 12. The gate connection electrode 80 is embedded in the insulating film 60 so as to be connected to the gate line wiring 70. In this case, the gate line electrode 90 is electrically connected to the gate line wiring 70 via the gate connection electrode 80. The cathode region 110 is disposed along the second main surface 12B at a distance from a position directly below the center of the gate line wiring 70. This configuration can prevent the formation of a detour current path that goes around to the region directly below the gate line wiring 70.

[0264] (3-6) The cathode region 110 does not face the gate connection electrode 80 in the thickness direction of the chip 12. The cathode region 110 does not face the gate line wiring 70 in the thickness direction of the chip 12. This configuration makes it possible to appropriately prevent the formation of a detour current path that goes around to the region directly below the gate line wiring 70.

[0265] (3-7) The cathode region 110 is disposed only in the region facing the well region 54 in the surface layer portion of the second main surface 12B. According to this configuration, the current path of the forward current IF of the diode 112 can be limited to the region between the well region 54 and the cathode region 110. Therefore, the decrease in the forward current IF can be appropriately suppressed.

[0266] (3-8) The cathode region 110 is disposed along the second main surface 12B at a distance from the gate reference position PG directly below the center of the gate line electrode 90 toward the well connecting electrode 84. This configuration can prevent the formation of a detour current path that goes around to the region immediately below the gate line electrode 90 in the region between the well connecting electrode 84 and the cathode region 110, and can shorten the current path between the well connecting electrode 84 and the cathode region 110. This can increase the forward current I F of the diode 112 during forward operation. This can improve the electrical characteristics of the semiconductor device 1.

[0267] (3-9) When the distance between the center of the gate line electrode 90 and the first well connection electrode 84A is defined as the first reference distance Da, the cathode region 110 is not disposed within a range that does not exceed half the distance from the gate reference position PG of the first reference distance Da. In other words, the cathode region 110 is disposed in a region outside the prohibited range 122. This structure can prevent the formation of a current detour path that goes around to the region directly below the gate line electrode 90. This can increase the forward current IF.

[0268] (3-10) When the distance between the center of the gate line electrode 90 and the well connecting electrode 84 is defined as a first reference distance Da, the cathode region 110 has a portion that is located within a range not exceeding half the distance of the first reference distance Da from the first well reference position PW1 directly below the first well connecting electrode 84A. In other words, when part or all of the cathode region 110 is located in a region on the first well reference position PW1 side, it is located within the first allowable range 124. With this configuration, the current path between the first well connecting electrode 84A and the cathode region 110 is shortened, thereby making it possible to appropriately increase the forward current IF.

[0269] (3-11) The cathode region 110 is disposed at the first well reference position PW1. According to this configuration, a current path is formed that linearly connects the first well-connecting electrode 84A and the cathode region 110, so that the forward current IF can be increased appropriately.

[0270] (3-12) When the distance between the center of the gate line electrode 90 and the second well connecting electrode 84B is defined as the second reference distance Db, the cathode region 110 is not disposed within a range that does not exceed half the distance from the gate reference position PG of the second reference distance Db. In other words, the cathode region 110 is disposed in an area outside the prohibited area 122. This configuration can prevent the formation of a current detour path that goes around to the area directly below the gate line electrode 90. This can increase the forward current IF.

[0271] (3-13) When the distance between the center of the gate line electrode 90 and the second well connecting electrode 84B is defined as a second reference distance Db, the cathode region 110 has a portion that is located within a range not exceeding half the range of the second reference distance Db from the second well reference position PW2 directly below the second well connecting electrode 84B. In other words, when part or all of the cathode region 110 is located in a region on the second well reference position PW2 side, it is located within the second allowable range 126. With this configuration, the current path between the second well connecting electrode 84B and the cathode region 110 is shortened, thereby making it possible to appropriately increase the forward current I.

[0272] (3-14) The cathode region 110 is disposed at the second well reference position PW2. According to this configuration, a current path is formed that linearly connects the second well-connecting electrode 84B and the cathode region 110, so that the forward current IF can be increased appropriately.

[0273] (3-15) The cathode region 110 is disposed along the second main surface 12B at a distance from an intermediate reference position PW3 immediately below the middle between the first well-connecting electrode 84A and the second well-connecting electrode 84B.

[0274] This configuration can prevent the formation of a detour current path that goes around to the region immediately below the middle between the first well connecting electrode 84A and the second well connecting electrode 84B. This can increase the forward current I of the diode 112 during forward operation. This can improve the electrical characteristics of the semiconductor device 1.

[0275] (3-16) When the distance between the first well-connecting electrode 84A and the second well-connecting electrode 84B is defined as the third reference distance Dc, the cathode region 110 is not disposed within a range that does not exceed ¼ of the distance from the intermediate reference position PW3. In other words, the cathode region 110 is disposed outside the prohibited range 122. This configuration makes it possible to appropriately prevent the formation of a detour current path that goes around to the region immediately below the intermediate position between the first well-connecting electrode 84A and the second well-connecting electrode 84B.

[0276] (3-17) The cathode region 110 is disposed at a distance from the intermediate reference position PW3 toward the first well-connecting electrode 84A. According to this configuration, the current path between the first well-connecting electrode 84A and the cathode region 110 can be shortened, and the forward current IF can be increased.

[0277] (3-18) When the distance between the first well connecting electrode 84A and the second well connecting electrode 84B is defined as a third reference distance Dc, the cathode region 110 has a portion that is located within a range not exceeding ¼ of the third reference distance Dc from the first well reference position PW1 directly below the first well connecting electrode 84A. In other words, when part or all of the cathode region 110 is located in a region on the first well reference position PW1 side, it is located within the first allowable range 124. With this configuration, the current path between the first well connecting electrode 84A and the cathode region 110 can be shortened, thereby appropriately increasing the forward current I.

[0278] (3-19) The cathode region 110 has a portion overlapping the first well reference position PW1. With this configuration, a current path that linearly connects the first well connecting electrode 84A and the cathode region 110 can be formed, thereby appropriately increasing the forward current I F.

[0279] (3-20) The cathode region 110 is disposed at a distance from the intermediate reference position PW3 toward the second well connecting electrode 84B. According to this configuration, the current path between the second well-connecting electrode 84B and the cathode region 110 can be shortened, and the forward current IF can be increased.

[0280] (3-21) When the distance between the first well connecting electrode 84A and the second well connecting electrode 84B is defined as a third reference distance Dc, the cathode region 110 has a portion that is located within a range not exceeding ¼ of the third reference distance Dc from the second well reference position PW2 directly below the second well connecting electrode 84B. In other words, when part or all of the cathode region 110 is located in a region on the second well reference position PW2 side, it is located within the second allowable range 126. With this configuration, the current path between the second well connecting electrode 84B and the cathode region 110 can be shortened, thereby appropriately increasing the forward current I.

[0281] (3-22) The cathode region 110 has a portion overlapping the second well reference position PW2. With this configuration, a current path that linearly connects the second well connecting electrode 84B and the cathode region 110 can be formed, thereby appropriately increasing the forward current I F.

[0282] <Example of change> The above-described embodiments can be modified as follows: The following modifications can be combined with each other to the extent that they are not technically inconsistent.

[0283] In each of the above embodiments, it is possible to arbitrarily change the position and area of ​​the cathode region 110. For example, the position and area of ​​the cathode region 110 may be determined as long as, in the characteristics of the forward voltage VF and forward current IF of the RC-IGBT chip 10 and the SiC-SBD chip 8, a boundary RBD between a first region R1 in which the forward current IF of the RC-IGBT chip 10 is smaller than the forward current IF of the SiC-SBD chip 8 and a second region R2 in which the forward current IF of the RC-IGBT chip 10 is higher than the forward current IF of the SiC-SBD chip 8 is larger than the rated current IFA of the SiC-SBD chip 8.

[0284] 28 to 30 show first to third examples of the arrangement position and area of ​​the cathode region 110 having such electrical characteristics of the semiconductor device 1. Figures 28 to 30 show schematic cross-sectional structures of the peripheral side of the chip 12.

[0285] As shown in FIG. 28, in a first example, the cathode region 110 may be arranged closer to the periphery of the chip 12 than the well region 54. The cathode region 110 may be arranged in a position facing the middle field region 56B of the multiple field regions 56 in the thickness direction of the chip 12. In the example shown in FIG. 28, the width W1 of the cathode region 110 may be equal to the width WF of the middle field region 56B. The cathode region 110 may be annular in plan view, surrounding the inner end field region 56A.

[0286] As shown in FIG. 29 , in the second example, similar to the first example, the cathode region 110 may be disposed closer to the periphery of the chip 12 than the well region 54. The cathode region 110 may be disposed across both the inner end field region 56A and the intermediate field region 56B of the multiple field regions 56 in the thickness direction of the chip 12. In the example shown in FIG. 29 , the width W1 of the cathode region 110 is greater than both the width of the inner end field region 56A and the width of the intermediate field region 56B. Furthermore, the width W1 of the cathode region 110 is greater than the sum of the widths of the inner end field region 56A and the intermediate field region 56B. The cathode region 110 may be annular in plan view.

[0287] As shown in FIG. 30, in the third example, the cathode region 110 includes a first cathode region 110P and a second cathode region 110Q that are spaced apart from each other in the X direction. The first cathode region 110P is disposed at a position facing the second well connecting electrode 84B in the thickness direction of the chip 12. The first cathode region 110P can also be said to be disposed at the second well reference position PW2. The first cathode region 110P may also be disposed at a position facing the first well connecting electrode 84A in the thickness direction of the chip 12. In other words, the first cathode region 110P may be disposed at the first well reference position PW1. The position of the first cathode region 110P may be the same as in the third embodiment.

[0288] The second cathode region 110Q may be disposed closer to the periphery of the chip 12 than the well region 54. In the example shown in Fig. 30, the second cathode region 110Q is the same as the cathode region 110 of the second example.

[0289] The cathode region 110 may be the cathode region 110X shown in FIG. 17. In the cathode region 110X, as shown in FIG. 18, the boundary RXA between the first comparison region RX1 and the second comparison region RX2 is smaller than the rated current IFA of the SiC-SBD chip 8. On the other hand, the cathode region 110X can improve the peak surge current IFSM. FIG. 31 shows the peak surge current IFSM in the first to fourth experimental examples. The first experimental example is configured with only the SiC-SBD chip 8. The second experimental example is configured with the cathode region 110X shown in FIG. 17. The third experimental example is configured with the first embodiment. The fourth experimental example is configured with the second embodiment. As shown in FIG. 31, the peak surge current IFSM in the second experimental example is larger than the peak surge currents IFSM in the first, third, and fourth experimental examples.

[0290] In the first embodiment, the cathode region 110 may be provided at a distance from the base region 36 toward the periphery of the chip 12 so as not to face the base region 36 at least in the thickness direction of the chip 12. The cathode region 110 may be disposed at a distance from the plurality of trench gate structures 38 toward the periphery of the chip 12 so as not to face the plurality of trench gate structures 38 in the thickness direction of the chip 12. The cathode region 110 may be disposed at a distance from the trench isolation structure 26 toward the periphery of the chip 12 so as not to face the trench isolation structure 26 in the thickness direction of the chip 12.

[0291] In this way, the cathode region 110 may be disposed at a distance from the IGBT region 14 on the peripheral edge side of the chip 12 so as not to face the IGBT region 14 in the thickness direction of the chip 12. In other words, the cathode region 110 may be provided only in the peripheral region 18, but not in the IGBT region 14. In this case, the electrical influence from the IGBT region 14 to the diode 112 can be suppressed, and the electrical influence from the diode 112 to the IGBT region 14 can also be suppressed.

[0292] The cathode region 110 may be disposed in a position facing at least one of the plurality of field regions 56 in the thickness direction of the chip 12. In one example, the cathode region 110 may be disposed in a position facing the middle field regions 56B and 56C in the thickness direction of the chip 12. In one example, the cathode region 110 may be disposed in a position facing the outer end field region 56D in the thickness direction of the chip 12. In one example, the cathode region 110 may be disposed in a position facing all of the plurality of field regions 56 in the thickness direction of the chip 12.

[0293] In each embodiment, the shape of the cathode region 110 in plan view is not limited to a ring shape surrounding the IGBT region 14, and can be changed as desired. In each embodiment, the configuration of the SiC-SBD chip 8 can be changed as desired. In one example, as shown in Fig. 32, the SiC-SBD chip 8 includes a diode chip 130, an n-type diode region 142, a p-type guard region 144, an interlayer insulating film 136, an anode electrode 138, and a cathode electrode 140.

[0294] The diode chip 130 is composed of a SiC chip 131 made of hexagonal SiC. The SiC chip 131 is made of 2H (Hexagonal)-SiC, 4H-SiC, or 6H-SiC. In one example, the SiC chip 131 is made of 4H-SiC. The first diode surface 132 may face the silicon surface ((0001) surface) of the SiC, and the second diode surface 134 may face the carbon surface ((000-1) surface) of the SiC.

[0295] Both the first diode surface 132 and the second diode surface 134 may have a predetermined off angle inclined in a predetermined off direction with respect to the c-plane of SiC. The off direction is preferably the a-axis direction ([11-20] direction). The off angle may be 0° or more and 10° or less. The off angle is preferably greater than 0° and 4.5° or less.

[0296] The SiC chip 131 is, for example, + The diode has a stacked structure including an n-type SiC substrate 131A and an n-type SiC epitaxial layer 131B. The first diode surface 132 is formed by the SiC epitaxial layer 131B. The second diode surface 134 is formed by the SiC substrate 131A. The n-type impurity concentration of the SiC epitaxial layer 131B is lower than the n-type impurity concentration of the SiC substrate 131A. The thickness of the SiC epitaxial layer 131B is lower than the thickness of the SiC substrate 131A. The thickness of the SiC substrate 131A can be 40 μm or more and 250 μm or less. The thickness of the SiC epitaxial layer 131B can be 1 μm or more and 50 μm or less.

[0297] The diode region 142 is provided in a surface layer portion of the first diode surface 132. The diode region 142 is provided in a central portion of the first diode surface 132. The diode region 142 may have any shape in a plan view. The diode region 142 may be provided by utilizing a part of the SiC epitaxial layer 131B.

[0298] The n-type impurity concentration of the diode region 142 is equal to the n-type impurity concentration of the SiC epitaxial layer 131B. The n-type impurity concentration of the diode region 142 may be higher than the n-type impurity concentration of the SiC epitaxial layer 131B. In this case, the diode region 142 is provided by introducing n-type impurities into a surface portion of the SiC epitaxial layer 131B.

[0299] The guard region 144 is provided on the surface layer portion of the first diode surface 132 so as to partition the diode region 142. The guard region 144 has a strip shape extending along the diode region 142 in a planar view. In one example, the guard region 144 has a ring shape surrounding the diode region 142 in a planar view. As a result, the guard region 144 is configured as a guard ring region. The shape of the diode region 142 in a planar view is adjusted by the shape of the guard region 144 in a planar view. The guard region 144 may have a polygonal ring shape or a circular ring shape in a planar view.

[0300] The interlayer insulating film 136 is provided on the first diode surface 132. The interlayer insulating film 136 includes an opening 136A that exposes the diode region 142. The opening 136A also exposes the inner periphery of the guard region 144. The shape of the opening 136A in plan view is arbitrary.

[0301] The anode electrode 138 extends into the opening 136A from above the interlayer insulating film 136. The anode electrode 138 is electrically connected to the diode region 142 and the guard region 144 within the opening 136A. The anode electrode 138 forms a Schottky junction with the diode region 142. This forms a SiC-SBD in which the anode electrode 138 serves as the anode and the SiC chip 131 serves as the cathode.

[0302] The anode electrode 138 has a layered structure including a barrier electrode 138A and a main electrode 138B, which are layered in this order from the first diode surface 132 side. The barrier electrode 138A forms a Schottky junction with the diode region 142. The barrier electrode 138A may include at least one of a Ti layer, a Pd layer, a chromium (Cr) layer, a vanadium (V) layer, a molybdenum (Mo) layer, a tungsten (W) layer, a platinum (Pt) layer, and a Ni layer. The main electrode 138B may include at least one of a pure Cu layer (a Cu layer with a purity of 99% or more), a pure Al layer (an Al layer with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0303] The cathode electrode 140 covers the second diode surface 134. The cathode electrode 140 is electrically connected to the SiC substrate 131A. The cathode electrode 140 forms ohmic contact with the SiC substrate 131A. The cathode electrode 140 may include at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer.

[0304] The position of the cathode region 110 can be changed arbitrarily. In one example, the cathode region 110 may be disposed in the IGBT region 14. In each embodiment, an n-type semiconductor region may be replaced with a p-type semiconductor region, and a p-type semiconductor region may be replaced with an n-type semiconductor region. A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0305] In each embodiment, it is possible to arbitrarily change the configuration of the semiconductor device 1. In one example, as shown in Figures 33 to 35, the semiconductor device 1 includes a first discrete semiconductor 1P and a second discrete semiconductor 1Q.

[0306] As shown in Fig. 34, the first discrete semiconductor 1P has a configuration in which an RC-IGBT chip 10 is accommodated in one package. As shown in Fig. 35, the second discrete semiconductor 1Q has a configuration in which an SiC-SBD chip 8 is accommodated in one package.

[0307] 33, the electrical connection between the first discrete semiconductor 1P and the second discrete semiconductor 1Q is indicated by a two-dot chain line. The semiconductor device 1 is actually composed of the first discrete semiconductor 1P and the second discrete semiconductor 1Q that are electrically connected to each other through wiring provided on a circuit board such as a PCB (Printed Circuit Board).

[0308] As shown in Fig. 34, the first discrete semiconductor 1P is configured in a three-terminal TO-type package (specifically, a TO-220 package). The first discrete semiconductor 1P includes a sealing resin 2P. The sealing resin 2P has a rectangular parallelepiped shape. The sealing resin 2P is configured from a mold resin (e.g., epoxy resin).

[0309] The first discrete semiconductor 1P includes a metal plate 4P disposed within the sealing resin 2P. The metal plate 4P is flat and has a thickness in the Z direction. The metal plate 4P is made of a material containing at least one of Cu, Fe, and Al. The metal plate 4P includes a die pad 4PA and a collector lead terminal 4PB. The die pad 4PA and the collector lead terminal 4PB are, for example, integrated. The die pad 4PA includes a first portion 4PC provided within the sealing resin 2P in a plan view and a second portion 4PD protruding in the Y direction from the sealing resin 2P in a plan view. The first portion 4PC and the second portion 4PD are integrated. The collector lead terminal 4PB includes a portion protruding in the Y direction from the sealing resin 2P in a plan view. The collector lead terminal 4PB is provided on the opposite side of the first portion 4PC from the second portion 4PD in the Y direction.

[0310] The first portion 4PC has a rectangular shape in a plan view. The RC-IGBT chip 10 is mounted on the first portion 4PC. More specifically, the RC-IGBT chip 10 is joined to the first portion 4PC by a conductive bonding material (not shown). It can also be said that the collector electrode 10C of the RC-IGBT chip 10 is electrically connected to the first portion 4PC by the conductive bonding material. As a result, the collector electrode 10C is electrically connected to the metal plate 4P.

[0311] The second portion 4PD includes a through-hole 4PE that penetrates the die pad 4PA in the Z direction. The through-hole 4PE has a circular shape in a plan view. The first discrete semiconductor 1P is screwed to an external heat sink or the like by passing a fixing member such as a screw through the through-hole 4PE. The shape of the through-hole 4PE in a plan view can be changed as desired.

[0312] The collector lead terminal 4PB is connected to the center of the die pad 4PA in the X direction and an end portion thereof closer to the first sealing side surface 2A in the Y direction. The collector lead terminal 4PB protrudes from the center of the sealing resin 2P in the X direction in a plan view. The collector lead terminal 4PB constitutes an external terminal of the semiconductor device 1.

[0313] The first discrete semiconductor 1P includes a gate lead terminal 6PA and an emitter lead terminal 6PB. The gate lead terminal 6PA and the emitter lead terminal 6PB are disposed on both sides of the collector lead terminal 4PB in the X direction in a plan view. Both the gate lead terminal 6PA and the emitter lead terminal 6PB are made of a material containing at least one of Cu, Fe, and Al. In one example, both the gate lead terminal 6PA and the emitter lead terminal 6PB may be made of the same material as the metal plate 4P. Both the gate lead terminal 6PA and the emitter lead terminal 6PB protrude in the Y direction from the sealing resin 2P in a plan view. Both the gate lead terminal 6PA and the emitter lead terminal 6PB constitute external terminals of the semiconductor device 1. A plating film made of a metal having high affinity (bonding strength) for solder may be provided on the outer surfaces of the collector lead terminal 4PB, the gate lead terminal 6PA, and the emitter lead terminal 6PB. The plating film may include at least one of a Ni plating film, a Pd plating film, and an Au plating film.

[0314] The gate electrode 10G is electrically connected to a gate lead terminal 6PA by a wire WPA, and the emitter electrode 10E is electrically connected to an emitter lead terminal 6PB by a wire WPB.

[0315] 35, the second discrete semiconductor 1Q is configured in a two-terminal TO-type package (specifically, a TO-220 package). The second discrete semiconductor 1Q includes a sealing resin 2Q. The sealing resin 2Q has a rectangular parallelepiped shape. The sealing resin 2Q is configured from a mold resin (e.g., epoxy resin).

[0316] The second discrete semiconductor 1Q includes a metal plate 4Q disposed in the sealing resin 2P. The metal plate 4Q has a configuration generally similar to that of the metal plate 4P shown in FIG. 34. The metal plate 4Q includes a die pad 4QA and a cathode lead terminal 4QB. The die pad 4QA and the cathode lead terminal 4QB are, for example, integrated. The die pad 4QA has the same configuration as the die pad 4PA. The die pad 4QA includes a first portion 4QC and a second portion 4QD, similar to the first portion 4PC and second portion 4PD of the die pad 4PA. The cathode lead terminal 4QB is connected to a position offset in the X direction from the center of the die pad 4QA. The cathode lead terminal 4QB constitutes an external terminal of the semiconductor device 1.

[0317] The SiC-SBD chip 8 is placed on the first portion 4QC. More specifically, the SiC-SBD chip 8 is bonded to the first portion 4QC by a conductive bonding material (not shown). It can be said that the cathode electrode 8K of the SiC-SBD chip 8 is electrically connected to the first portion 4QC by the conductive bonding material. As a result, the cathode electrode 8K is electrically connected to the metal plate 4Q.

[0318] The second portion 4QD includes a through-hole 4QE that penetrates the die pad 4QA in the Z direction. The through-hole 4QE has a circular shape in a plan view. The second discrete semiconductor 1Q is screwed to an external heat sink or the like by passing a fixing member such as a screw through the through-hole 4QE. The shape of the through-hole 4QE in a plan view can be changed as desired.

[0319] The second discrete semiconductor 1Q includes an anode lead terminal 6QA. The anode lead terminal 6QA is disposed spaced apart from the cathode lead terminal 4QB in the X direction in a plan view. The anode lead terminal 6QA is made of a material containing at least one of Cu, Fe, and Al. The anode lead terminal 6QA protrudes from the sealing resin 2Q in the Y direction in a plan view. The anode lead terminal 6QA constitutes an external terminal of the semiconductor device 1. A plating film made of a metal having high affinity (bonding strength) for solder may be provided on the outer surfaces of the cathode lead terminal 4QB and the anode lead terminal 6QA. The plating film may include at least one of a Ni plating film, a Pd plating film, and an Au plating film. The anode electrode 8A is electrically connected to the anode lead terminal 6QA by a wire WQ.

[0320] 33, the cathode lead terminal 4QB of the second discrete semiconductor 1Q is electrically connected to the collector lead terminal 4PB of the first discrete semiconductor 1P. Also, the anode lead terminal 6QA of the second discrete semiconductor 1Q is electrically connected to the emitter lead terminal 6PB of the first discrete semiconductor 1P. In this way, in the semiconductor device 1, the RC-IGBT and the SiC-SBD are connected in anti-parallel.

[0321] The package structure of the first discrete semiconductor 1P and the second discrete semiconductor 1Q is not limited to a TO-type package and can be changed as desired. Each of the first discrete semiconductor 1P and the second discrete semiconductor 1Q may be configured, for example, as an SOP, QFN, DFP, DIP, QFP, SIP, or SOJ package, or various similar packages. These packages differ from TO-type packages in the shape of the sealing resins 2P and 2Q and the structure of the lead terminals, but their basic structure (including the electrical structure) is the same as that of TO-type packages. Furthermore, the package structure of the second discrete semiconductor 1Q may differ from that of the first discrete semiconductor 1P.

[0322] In the characteristics of the forward voltage VF and the forward current IF in the RC-IGBT chip 10 and the SiC-SBD chip 8, the boundary RBD between the first region R1 and the second region R2 may be smaller than the rated current IFA of the SiC-SBD chip 8. In this case, in the RC-IGBT chip 10, at least one of the arrangement position and the area of ​​the cathode region 110 is set so that the boundary RBD between the first region R1 and the second region R2 is smaller than the rated current IFA of the SiC-SBD chip 8.

[0323] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0324] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this disclosure being "up" and "down" of the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0325] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0326] [Appendix 1] an RC-IGBT chip (10) including a gate electrode (10G), a collector electrode (10C), and an emitter electrode (10E); a SiC-SBD chip (8) including a cathode electrode (8K) electrically connected to the collector electrode (10C) and an anode electrode (8A) electrically connected to the emitter electrode (10E); A semiconductor device (1).

[0327] [Appendix 2] In the characteristics of forward voltage and forward current in the RC-IGBT chip (10) and the SiC-SBD chip (8), a first region (R1) in which the forward current of the RC-IGBT chip (10) is smaller than the forward current of the SiC-SBD chip (8); a second region (R2) in which the forward current is higher than that of the first region (R1), and in which the forward current of the RC-IGBT chip (10) is larger than the forward current of the SiC-SBD chip (8); It is divided into The boundary (RBD) between the first region (R1) and the second region (R2) has a current rating greater than the rated current of the SiC-SBD chip (8). 2. The semiconductor device according to claim 1.

[0328] [Appendix 3] In the forward voltage and forward current characteristics of the RC-IGBT chip (10) and the SiC-SBD chip (8), the forward current of the RC-IGBT chip (10) is smaller than the forward current of the SiC-SBD chip (8) over the entire range of forward voltage. 3. The semiconductor device according to claim 1 or 2.

[0329] [Appendix 4] The RC-IGBT chip (10) a chip (12) including a first main surface (12A) and a second main surface (12B) opposite to the first main surface (12A); an outer peripheral region (18) provided on the peripheral edge of the first main surface (12A); an IGBT region (14) provided inside the outer peripheral region (18) on the first main surface (12A); a well region (54) of a first conductivity type provided in a surface layer portion of the first main surface (12A) in the outer peripheral region (18) so as to define the IGBT region (14); a cathode region (110) of a second conductivity type provided in a surface layer portion of the second main surface (12B) of the outer peripheral region (18) and constituting a diode (112) together with the well region (54); Including, At least one of the arrangement position and area of ​​the cathode region (110) is set so that the forward current of the RC-IGBT chip (10) is smaller than the forward current of the SiC-SBD chip (8) within a range smaller than the rated current of the SiC-SBD chip (8). 3. The semiconductor device according to claim 2.

[0330] [Appendix 5] The RC-IGBT chip (10) a chip (12) including a first main surface (12A) and a second main surface (12B) opposite to the first main surface (12A); an outer peripheral region (18) provided on the peripheral edge of the first main surface (12A); an IGBT region (14) provided inside the outer peripheral region (18) on the first main surface (12A); a well region (54) of a first conductivity type provided in a surface layer portion of the first main surface (12A) in the outer peripheral region (18) so as to define the IGBT region (14); a cathode region (110) of a second conductivity type provided in a surface layer portion of the second main surface (12B) of the outer peripheral region (18) and constituting a diode (112) together with the well region (54); Including, At least one of the arrangement position and area of ​​the cathode region (110) is set so that the boundary (RBD) between the first region (R1) and the second region (R2) is larger than the rated current of the SiC-SBD chip (8). 3. The semiconductor device according to claim 2.

[0331] [Appendix 6] The RC-IGBT chip (10) a chip (12) including a first main surface (12A) and a second main surface (12B) opposite to the first main surface (12A); an outer peripheral region (18) provided on the peripheral edge of the first main surface (12A); an IGBT region (14) provided inside the outer peripheral region (18) on the first main surface (12A); a well region (54) of a first conductivity type provided in a surface layer portion of the first main surface (12A) in the outer peripheral region (18) so as to define the IGBT region (14); a cathode region (110) of a second conductivity type provided in a surface layer portion of the second main surface (12B) of the outer peripheral region (18) and constituting a diode (112) together with the well region (54); Including, At least one of the arrangement position and area of ​​the cathode region (110) is set so that the forward current of the RC-IGBT chip (10) is smaller than the forward current of the SiC-SBD chip (8) over the entire range of forward voltage. 4. The semiconductor device according to claim 3.

[0332] [Appendix 7] The cathode region (110) is disposed closer to the periphery of the chip (12) than the IGBT region (14) and faces at least the well region (54). 7. The semiconductor device according to any one of claims 4 to 6.

[0333] [Appendix 8] an insulating film (60) covering the well region (54); a well connection electrode (84 / 84A, 84B) embedded in the insulating film (60) so as to be connected to the well region (54); a gate line electrode (90) disposed on the insulating film (60) at a distance from the well-connecting electrode (84 / 84A, 84B) so as to face the well region (54); Including, The cathode region (110) includes a portion spaced apart from the gate reference position (PG) directly below the center of the gate line electrode (90) toward the well connection electrode (84 / 84A, 84B). 8. The semiconductor device according to claim 7.

[0334] [Appendix 9] The cathode region (110) includes a portion facing the well-connecting electrode (84 / 84A, 84B) in the thickness direction (Z) of the chip (12). 9. The semiconductor device according to claim 8.

[0335] [Appendix 10] The cathode region (110) is disposed closer to the well connection electrodes (84 / 84A, 84B) than the gate line electrode (90). 9. The semiconductor device according to claim 8.

[0336] [Appendix 11] the peripheral region (18) includes a plurality of field regions (56 / 56A-56D) of a first conductivity type that are spaced apart from one another and are provided at intervals from the well region (54) toward the periphery of the chip (12) in a surface layer portion of the first main surface (12A), The cathode region (110) includes a portion disposed in a position facing at least one of the plurality of field regions (56 / 56A to 56D) in the thickness direction (Z) of the chip (12). 11. The semiconductor device according to any one of claims 4 to 10.

[0337] [Appendix 12] The cathode region (110) includes a portion disposed at a position facing the field region (56A) closest to the well region (54) among the plurality of field regions (56 / 56A to 56D) in the thickness direction (Z) of the chip (12). 12. The semiconductor device according to claim 11.

[0338] [Appendix 13] Each of the plurality of field regions (56 / 56A to 56D) has a predetermined width (WF), The width (W1) of the cathode region (110) is larger than the width (WF) of one of the plurality of field regions (56 / 56A to 56D). 13. The semiconductor device according to claim 11 or 12.

[0339] [Appendix 14] The cathode region (110) is disposed closer to the periphery of the chip (12) than the well region (54). 7. The semiconductor device according to any one of claims 4 to 6.

[0340] [Appendix 15] Both the well region (54) and the cathode region (110) have predetermined widths (WP, W1); The width (W1) of the cathode region (110) is smaller than the width (WP) of the well region (54). 15. The semiconductor device according to any one of claims 4 to 14.

[0341] [Appendix 16] The cathode region (110) includes the entire well region (54) and a portion of the plurality of field regions (56 / 56A to 56D) that is disposed so as to face the field region (56A) that is closest to the well region (54). 12. The semiconductor device according to claim 11.

[0342] [Appendix 17] The cathode region (110) is provided in plurality. 17. The semiconductor device according to any one of claims 4 to 16.

[0343] [Appendix 18] The cathode region (110) is annular and surrounds the IGBT region (14) when viewed in the thickness direction (Z) of the chip (12). 18. The semiconductor device according to any one of claims 4 to 17.

[0344] [Appendix 19] The RC-IGBT chip (10) a chip (12) including a first main surface (12A) and a second main surface (12B) opposite to the first main surface (12A); an outer peripheral region (18) provided on the peripheral edge of the first main surface (12A); an IGBT region (14) provided inside the outer peripheral region (18) on the first main surface (12A); a well region (54) of a first conductivity type provided in a surface layer portion of the first main surface (12A) in the outer peripheral region (18) so as to define the IGBT region (14); a cathode region (110) of a second conductivity type provided in a surface layer portion of the second main surface (12B) and constituting a diode (112) together with the well region (54); Including, The cathode region (110) is disposed in the IGBT region (14). 2. The semiconductor device according to claim 1.

[0345] [Appendix 20] In the characteristics of forward voltage and forward current in the RC-IGBT chip (10) and the SiC-SBD chip (8), a first region (R1) in which the forward current of the RC-IGBT chip (10) is equal to or less than the forward current of the SiC-SBD chip (8); a second region (R2) in which the forward current is higher than that of the first region (R1), and in which the forward current of the RC-IGBT chip (10) is larger than the forward current of the SiC-SBD chip (8); Including, The boundary (RBD) between the first region (R1) and the second region (R2) has a current rating smaller than the rated current of the SiC-SBD chip (8). 2. The semiconductor device according to claim 1.

[0346] [Appendix 21] The RC-IGBT chip (10) a chip (12) including a first main surface (12A) and a second main surface (12B) opposite to the first main surface (12A); an outer peripheral region (18) provided on the peripheral edge of the first main surface (12A); an IGBT region (14) provided inside the outer peripheral region (18) on the first main surface (12A); a well region (54) of a first conductivity type provided in a surface layer portion of the first main surface (12A) in the outer peripheral region (18) so as to define the IGBT region (14); a cathode region (110) of a second conductivity type provided in a surface layer portion of the second main surface (12B) of the outer peripheral region (18) and constituting a diode (112) together with the well region (54); Including, At least one of the arrangement position and area of ​​the cathode region (110) is set so that the boundary (RBD) between the first region (R1) and the second region (R2) is smaller than the rated current of the SiC-SBD chip (8). 21. The semiconductor device according to claim 20.

[0347] [Appendix 22] an insulating film (60) covering the well region (54); a well connection electrode (84 / 84A, 84B) embedded in the insulating film (60) so as to be connected to the well region (54); a gate line electrode (90) disposed on the insulating film (60) at a distance from the well-connecting electrode (84 / 84A, 84B) so as to face the well region (54); Including, The cathode region is provided along the second main surface (12B) at a distance from a gate reference position (GP) directly below the center of the gate line electrode (90) toward the well connection electrode (84 / 84A, 84B) so as to face the well region (54) in a surface layer portion of the second main surface (12B). 7. The semiconductor device according to any one of claims 4 to 6.

[0348] [Appendix 23] When the distance between the center of the gate line electrode (90) and the well connection electrode (84 / 84A, 84B) is defined as a reference distance (Da / Db), the cathode region (110) is not disposed in a range (122) from the gate reference position (GP) toward the well connection electrode (84 / 84A, 84B) that does not exceed half the reference distance (Da / Db). 23. The semiconductor device according to claim 22.

[0349] [Appendix 24] When the distance between the center of the gate line electrode (90) and the well connecting electrode (84 / 84A, 84B) is defined as a reference distance (Da / Db), the cathode region (110) has a portion disposed within a range not exceeding half the reference distance (Da / Db) from a well reference position (PW1 / PW2) directly below the well connecting electrode (84 / 84A, 84B). 23. The semiconductor device according to claim 22.

[0350] [Appendix 25] The cathode region (110) is not disposed within a range not exceeding half the reference distance (Da / Db) from the gate reference position (PG) to the well connection electrode (84 / 84A, 84B). 25. The semiconductor device according to claim 24.

[0351] [Appendix 26] The cathode region (110) has a portion facing the well-connecting electrode (84 / 84A, 84B) in the thickness direction (Z) of the chip (12). 26. The semiconductor device according to any one of claims 22 to 25.

[0352] [Appendix 27] The cathode region (110) does not face the gate line electrode (90) in the thickness direction (Z) of the chip (12). 27. The semiconductor device according to any one of claims 22 to 26.

[0353] [Appendix 28] The gate line electrode (90) is disposed at a distance from the well connection electrode (84 / 84B) toward the IGBT region (14), The cathode region (110) is disposed along the second main surface (12B) at an interval from the gate reference position (GP) toward the well connection electrode (84 / 84B). 28. The semiconductor device according to any one of claims 22 to 27.

[0354] [Appendix 29] The cathode region (110) is disposed only in a region facing the well region (54) in the surface layer portion of the second main surface (12B). 29. The semiconductor device according to claim 28.

[0355] [Appendix 30] the gate line electrode (90) is disposed at a distance from the well connection electrode (84 / 84A) toward the periphery of the chip (12); The cathode region (110) is disposed along the second main surface (12B) at a distance from the gate reference position (PG) toward the IGBT region (14). 26. The semiconductor device according to any one of claims 22 to 25.

[0356] [Appendix 31] The cathode region (110) is disposed only in a region facing the well region (54) in the surface layer portion of the second main surface (12B). 31. The semiconductor device according to claim 30.

[0357] [Appendix 32] a gate line wiring (70) disposed inside the insulating film (60) so as to face the well region (54); a gate connection electrode (80) embedded in the insulating film (60) so as to be connected to the gate line wiring (70); further comprising The gate line electrode (90) is electrically connected to the gate line wiring (70) via the gate connection electrode (80). 32. The semiconductor device according to any one of claims 22 to 31.

[0358] [Appendix 33] The cathode region (110) does not face the gate connection electrode (80) in the thickness direction (Z) of the chip (12). 33. The semiconductor device according to claim 32.

[0359] [Appendix 34] The cathode region (110) does not face the gate line wiring (70) in the thickness direction (Z) of the chip (12). 34. The semiconductor device according to claim 32 or 33.

[0360] [Appendix 35] an insulating film (60) covering the well region (54); a first well connection electrode (84A) embedded in the insulating film (60) so as to be connected to the well region (54); a second well connection electrode (84B) embedded in the insulating film (60) at a distance from the first well connection electrode (84A) toward the periphery of the chip (12) so as to be connected to the well region (54); Including, The cathode region (110) is disposed along the second main surface (12B) at a distance from an intermediate reference position (PW3) immediately below the intermediate position between the first well-connecting electrode (84A) and the second well-connecting electrode (84B) so as to face the well region (54) in a surface layer portion of the second main surface (12B). 7. The semiconductor device according to any one of claims 4 to 6.

[0361] [Appendix 36] When the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the cathode region (110) is not disposed within a range not exceeding ¼ of the reference distance (Dc) from the intermediate reference position (PW3). 36. The semiconductor device according to claim 35.

[0362] [Appendix 37] The cathode region (110) is disposed at a distance from the intermediate reference position (PW3) toward the first well connecting electrode (84A). 36. The semiconductor device according to claim 35.

[0363] [Appendix 38] When the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the cathode region (110) is not disposed within a range from the intermediate reference position (PW3) toward the first well connecting electrode (84A) that does not exceed ¼ of the reference distance (Dc). 38. The semiconductor device according to claim 37.

[0364] [Appendix 39] When the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the cathode region (110) has a portion disposed within a range not exceeding ¼ of the reference distance (Dc) from a first well reference position (PW1) directly below the first well connecting electrode (84A) toward the intermediate reference position (PW3). 38. The semiconductor device according to claim 37.

[0365] [Appendix 40] The cathode region (110) is not disposed within a range not exceeding ¼ of the reference distance (Dc) from the intermediate reference position (PW3) to the first well connecting electrode (84A). 40. The semiconductor device according to claim 39.

[0366] [Appendix 41] The cathode region (110) faces the first well-connecting electrode (84A) in the thickness direction (Z) of the chip (12). 41. The semiconductor device according to any one of claims 37 to 40.

[0367] [Appendix 42] The cathode region (110) is disposed at a distance from the intermediate reference position (PW3) toward the second well connecting electrode (84B). 36. The semiconductor device according to claim 35.

[0368] [Appendix 43] When the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the cathode region (110) is not disposed within a range from the intermediate reference position (PW3) toward the second well connecting electrode (84B) that does not exceed ¼ of the reference distance (Dc). 43. The semiconductor device according to claim 42.

[0369] [Appendix 44] When the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the cathode region (110) has a portion disposed within a range not exceeding ¼ of the reference distance (Dc) from a second well reference position (PW2) directly below the second well connecting electrode (84B) toward the intermediate reference position (PW3). 43. The semiconductor device according to claim 42.

[0370] [Appendix 45] The cathode region (110) is not disposed within a range not exceeding ¼ of the reference distance (Dc) from the intermediate reference position (PW3) toward the second well connecting electrode (84B). 45. The semiconductor device according to claim 44.

[0371] [Appendix 46] The cathode region (110) faces the second well connection electrode (84B) in the thickness direction (Z) of the chip (12). 46. ​​The semiconductor device according to any one of appendices 42 to 45.

[0372] [Appendix 47] The cathode region (110) a first cathode region (110A) disposed at a distance from the intermediate reference position (PW3) toward the first well-connecting electrode (84A); a second cathode region (110B) disposed at a distance from the intermediate reference position (PW3) toward the second well connecting electrode (84B); Contains 36. The semiconductor device according to claim 35.

[0373] [Appendix 48] When the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the first cathode region (110A) is not disposed within a range from the intermediate reference position (PW3) toward the first well connecting electrode (84A) that does not exceed ¼ of the reference distance (Dc). 48. The semiconductor device according to claim 47.

[0374] [Appendix 49] When the distance between the first well connecting electrode (84A) and the second well connecting electrode (84B) is defined as a reference distance (Dc), the first cathode region (110A) has a portion disposed within a range not exceeding ¼ of the reference distance (Dc) from a first well reference position (PW1) directly below the first well connecting electrode (84A) toward the intermediate reference position (PW3). 48. The semiconductor device according to claim 47.

[0375] [Appendix 50] The first cathode region (110A) is not disposed within a range not exceeding a distance of ¼ of the reference distance (Dc) from the intermediate reference position (PW3) to the first well connecting electrode (84A). 49. The semiconductor device according to claim 49.

[0376] [Appendix 51] The second cathode region (110B) is not disposed within a range not exceeding ¼ of the reference distance (Dc) from the intermediate reference position (PW3) to the second well connecting electrode (84B). 51. The semiconductor device according to claim 50.

[0377] [Appendix 52] The second cathode region (110B) has a portion disposed within a distance not exceeding ¼ of the reference distance (Dc) from the second well reference position (PW2) directly below the second well connecting electrode (84B) toward the intermediate reference position (PW3). 51. The semiconductor device according to claim 50.

[0378] [Appendix 53] The second cathode region (120B) is not disposed within a range not exceeding ¼ of the reference distance (Dc) from the intermediate reference position (PW3) to the second well connecting electrode (84B). 53. The semiconductor device according to claim 52.

[0379] [Appendix 54] further including a collector region (24) of a first conductivity type (n) provided in a surface layer portion of the second main surface (12B), The cathode region (110) has a second conductivity type impurity concentration higher than the first conductivity type impurity concentration of the collector region (24). The semiconductor device according to any one of Supplementary Notes 22 to 53.

[0380] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0381] 1...Semiconductor device 1A...RC-IGBT 1AA...IGBT 1AB...Diode 1B...Freewheeling diode 1P...First discrete semiconductor 1Q: Second discrete semiconductor 2,2P,2Q…Sealing resin 2S…Sealing top surface 2R…Sealing bottom surface 2A~2D...1st~4th sealing side 2E…Through hole 2F,2G…Opening 4,4P,4Q…Metal plate 4A, 4PA, 4QA...Die pad 4B...Lead 4C,4PE,4QE…Through hole 4PB...Collector lead terminal 4PC,4QC…1st part 4PD,4QD…Second part 4QB...Cathode lead terminal 6A...1st lead 6B...2nd lead 6PA...Gate lead terminal 6PB...Emitter lead terminal 6QA...Anode lead terminal 8...SiC-SBD chip 8A...Anode electrode 8K...cathode electrode 10...RC-IGBT chip 10C...Collector electrode 10E...Emitter electrode 10G...gate electrode 12. Chip 12A...First principal surface 12B...Second principal surface 12C~12F…1st~4th side 14…IGBT area 16...Pad area 18...Outer area 20...Drift region 22...Buffer area 24...Collector region 26...Trench isolation structure 28...Isolation trench 30...Isolation insulating film 32…Separate buried electrode 34…IGBT structure 36...Base area 38...Trench gate structure 38A…First end 38B…Second end 40...Gate trench 42...Gate insulating film 44...Gate buried electrode 46...Emitter area 48...Contact hole 50...Contact area 52...Pad well area 54...Well area 54A...Common-law marriage 54B...Outer edge 56...Field area 56A...Inner field area 56B, 56C...Intermediate field area 56D...Outer field area 58...Channel stop region 60...Insulating film 62...Main surface insulating film 64...Interlayer insulating film 66...Gate wiring 68...Gate pad wiring 70...Gate line wiring 72...Gate connection wiring 74...Emitter opening 76...Emitter connection electrode 78...Gate opening 80...Gate connection electrode 82...Well opening 82A...First well opening 82AA...Segment opening 82B...Second well opening 84...Well connecting electrode 84A...First well connecting electrode 84B...Second well connecting electrode 86...Gate electrode 88...Gate pad electrode 90...Gate line electrode 90A…Open end 92...Emitter electrode 94...Emitter pad electrode 94A...Emitter lead-out section 96...Emitter line electrode 98...Field opening 100...Field connection electrode 102...Field electrode 102A...Inner end field electrode 102B, 102C...Intermediate field electrodes 102D...Outer field electrode 102E...Field drawer 104...Channel stop opening 106...Channel stop electrode 108...Collector electrode 110...cathode region 110A, 110P...first cathode region 110B, 110Q...Second cathode region 111A...Common-law marriage 111B...Outer edge 112...Diode 122...Prohibited area 124...First Permitted Range 126...Second Permitted Range 130...Diode chip 131...SiC chip 131A…SiC substrate 131B...SiC epitaxial layer 132...First diode surface 134...Second diode surface 136...Interlayer insulating film 136A…Opening 138...Anode electrode 138A...Barrier electrode 138B…Main electrode 140...Cathode electrode 142...Diode region 144...Guard area SD: Conductive adhesive WA, WB, WC, WPA, WPB, WQ...wire Dwc: distance in the X direction between the well region and the channel stop region W1: Width of the cathode region WP: Width of well area WF: Width of each of the multiple field regions WT: Total width of multiple field areas PW1: Reference position of first well PW2: Reference position of second well PW3…Intermediate reference position PG: Gate reference position v1...first maximum value v2…Minimum value v3: Second maximum v4…1st inflection point v5…Second inflection point Da...First reference distance Db: Second reference distance Dc: Third reference distance G1, S1, T1...First characteristic G2, S2, T2…Second characteristic S3...Third characteristic R1…first area R2…Second area RBD…boundary RA~RD...Field area range RW: The outer edge of the well area

Claims

1. an RC-IGBT chip including a gate electrode, a collector electrode, and an emitter electrode; a SiC-SBD chip including a cathode electrode electrically connected to the collector electrode and an anode electrode electrically connected to the emitter electrode; 10. A semiconductor device comprising:

2. In the characteristics of forward voltage and forward current in the RC-IGBT chip and the SiC-SBD chip, a first region in which a forward current of the RC-IGBT chip is smaller than a forward current of the SiC-SBD chip; a second region having a higher forward current than the first region, in which the forward current of the RC-IGBT chip is larger than the forward current of the SiC-SBD chip; It is divided into The boundary between the first region and the second region has a current greater than the rated current of the SiC-SBD chip. The semiconductor device according to claim 1 .

3. In the characteristics of forward voltage and forward current of the RC-IGBT chip and the SiC-SBD chip, the forward current of the RC-IGBT chip is smaller than the forward current of the SiC-SBD chip over the entire range of forward voltage. The semiconductor device according to claim 1 .

4. The RC-IGBT chip is a chip including a first major surface and a second major surface opposite the first major surface; an outer peripheral region provided on a peripheral edge portion of the first main surface; an IGBT region provided inside the outer circumferential region in the first main surface; a well region of a first conductivity type provided in a surface layer portion of the first main surface in the peripheral region so as to define the IGBT region; a cathode region of a second conductivity type provided in a surface layer portion of the second main surface of the peripheral region and constituting a diode together with the well region; Including, At least one of the arrangement position and area of ​​the cathode region is set so that the forward current of the RC-IGBT chip is smaller than the forward current of the SiC-SBD chip within a range smaller than the rated current of the SiC-SBD chip. The semiconductor device according to claim 2 .

5. The RC-IGBT chip is a chip including a first major surface and a second major surface opposite the first major surface; an outer peripheral region provided on a peripheral edge portion of the first main surface; an IGBT region provided inside the outer circumferential region in the first main surface; a well region of a first conductivity type provided in a surface layer portion of the first main surface in the peripheral region so as to define the IGBT region; a cathode region of a second conductivity type provided in a surface layer portion of the second main surface of the peripheral region and constituting a diode together with the well region; Including, At least one of the layout position and area of ​​the cathode region is set so that the boundary between the first region and the second region is larger than the rated current of the SiC-SBD chip. The semiconductor device according to claim 2 .

6. The RC-IGBT chip is a chip including a first major surface and a second major surface opposite the first major surface; an outer peripheral region provided on a peripheral edge portion of the first main surface; an IGBT region provided inside the outer circumferential region in the first main surface; a well region of a first conductivity type provided in a surface layer portion of the first main surface in the peripheral region so as to define the IGBT region; a cathode region of a second conductivity type provided in a surface layer portion of the second main surface of the peripheral region and constituting a diode together with the well region; Including, At least one of the arrangement position and area of ​​the cathode region is set so that the forward current of the RC-IGBT chip is smaller than the forward current of the SiC-SBD chip over the entire range of forward voltage. The semiconductor device according to claim 3 .

7. The cathode region is disposed closer to the periphery of the chip than the IGBT region and is opposed to at least the well region. The semiconductor device according to claim 4 .

8. an insulating film covering the well region; a well connection electrode embedded in the insulating film so as to be connected to the well region; a gate line electrode disposed on the insulating film at a distance from the well connecting electrode so as to face the well region; Including, The cathode region includes a portion disposed at a distance from a gate reference position directly under the center of the gate line electrode toward the well connecting electrode. The semiconductor device according to claim 7 .

9. The cathode region includes a portion facing the well-connecting electrode in the thickness direction of the chip. The semiconductor device according to claim 8 .

10. The cathode region is disposed closer to the well connecting electrode than the gate line electrode. The semiconductor device according to claim 8 .

11. a plurality of field regions of a first conductivity type provided at intervals from the well region toward the periphery of the chip in a surface layer portion of the first main surface of the peripheral region and arranged apart from each other; The cathode region includes a portion disposed at a position facing at least one of the plurality of field regions in a thickness direction of the chip. The semiconductor device according to claim 4 .

12. The cathode region includes a portion disposed at a position facing a field region of the plurality of field regions that is closest to the well region in a thickness direction of the chip. The semiconductor device according to claim 11.

13. each of the plurality of field regions has a predetermined width; The width of the cathode region is greater than the width of one of the plurality of field regions. The semiconductor device according to claim 11.

14. The cathode region is disposed closer to the periphery of the chip than the well region. The semiconductor device according to claim 4 .

15. both the well region and the cathode region have a predetermined width; The width of the cathode region is smaller than the width of the well region. The semiconductor device according to claim 4 .

16. The cathode region includes the entire well region and a portion of the plurality of field regions that is disposed so as to face the field region that is closest to the well region. The semiconductor device according to claim 11.

17. The cathode region is provided in plurality. The semiconductor device according to claim 4 .

18. The cathode region is annular and surrounds the IGBT region when viewed in the thickness direction of the chip. The semiconductor device according to any one of claims 4 to 17.

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