Processor, information processing apparatus, and processor control method

Abstract

To provide a processor, an information processor, and a control method of the processor for reducing an increase in circuit scale and circuit complexity.SOLUTION: The package-unit allowable power determination unit 102 determines the smaller one of the first required power required for the entire CPU core die and the first power limit for the entire CPU core die as the first allowable power allowed for the entire CPU core die. The per-die allowable power determination unit 106 determines the second allowable power of each CPU core die based on the first allowable power and the smaller one of the second required power and the second power limit of each CPU core die. The transmitter transmits the second allowable power to the CPU core die and causes the CPU core die to be supplied with the second allowable power.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a processor, an information processing device, and a method for controlling a processor. [Background technology]

[0002] A processor may contain multiple dies. For example, a chiplet configuration exists in which a single processor LSI (Large Scale Integration) package contains four CPU (Central Processing Unit) core dies and one control die. The CPU core die contains multiple CPU cores and a power control circuit. The control die contains a power adjustment circuit. For example, a pair of CPU core dies are connected to a single VRM (Voltage Regulator Module), and each receives voltage from the VRM.

[0003] In a processor with multiple CPU core dies, each CPU core die communicates its required power consumption to the power allowance adjustment circuit, which then controls power consumption based on the sequentially changing power requirements of each CPU core die.

[0004] More specifically, during operation, each CPU core mounted on the CPU core die sends a frequency change request to the power control circuit mounted on the CPU core die in response to the arithmetic instruction being executed. The power control circuit transmits the power required to operate all CPU cores on the CPU core die on which it is mounted at the requested frequency as the requested power to the allowable power adjustment circuit. The allowable power adjustment circuit determines the allowable power for each CPU core die based on the requested power and a power limit, which is a predetermined upper limit of the power supply, and transmits information about the determined allowable power to each CPU core die. The power control circuit calculates the CPU core frequency within a range that keeps the power of the CPU core die on which it is mounted below the allowable power, and issues a frequency change instruction to each CPU core and also changes the VRM voltage.

[0005] However, if all the dies require a large amount of power, the maximum power supply of the voltage regulator that supplies power to the CPU cores may be exceeded. Therefore, it is preferable for the allowable power adjustment circuit to perform power control that allocates power to each CPU core die so as not to exceed the maximum power supply and to meet the power requirements of each CPU core die as much as possible. When performing such power control, one possible method is to determine the allowable power by strictly allocating power evenly so as to meet the power requirements of each CPU core die as much as possible.

[0006] As a method of distributing power in a computer, a technique has been proposed in which tokens are associated with cores, tokens are moved from cores with excess tokens to cores that need additional tokens, and the operating frequency of the core is increased by an increment represented by the token. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Special Publication No. 2023-535564 Summary of the Invention [Problem to be solved by the invention]

[0008] However, determining the allowable power through strict equal allocation can result in an increase in circuit size. For example, doubling the number of CPU core dies doubles the amount of required power information, and additional circuits are required to determine the allowable power for each CPU core die. Furthermore, if a power-required sorting circuit is present, the number of sorting circuits may increase exponentially with the square of the number of CPU core dies. The number of fixed-value divisors used to generate parameters for determining the allowable power increases with the number of CPU core dies. Furthermore, when power is shared between different VRMs, the number of CPU core dies involved increases, increasing the circuit complexity. Furthermore, increased circuit complexity can lead to an increase in circuit size and the number of logic stages, potentially worsening latency.

[0009] Furthermore, the technology for distributing power using tokens does not take into consideration the increase in circuit size, and if the number of CPU core dies is increased, there is a risk that the circuit size will increase accordingly.

[0010] The disclosed technology has been made in view of the above, and aims to provide a processor, an information processing device, and a method for controlling a processor that reduce increases in circuit size and circuit complexity. [Means for solving the problem]

[0011] In one aspect of the processor, information processing device, and processor control method disclosed herein, the processor includes a plurality of arithmetic units and the following units: a first allowable power determination unit determines the smaller of a first required power required by the plurality of arithmetic units as a first allowable power to be allowed for the plurality of arithmetic units as a whole or a first power limit for the plurality of arithmetic units as a whole; a second allowable power determination unit determines the smaller of a second required power or a second power limit for each arithmetic unit as well as the first allowable power; and a transmission unit transmits the second allowable power to the arithmetic units to receive the second allowable power. [Effects of the Invention]

[0012] In one aspect, the present invention can reduce an increase in circuit size and circuit complexity. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a hardware configuration diagram of a server according to the first embodiment. [Figure 2] FIG. 2 is a block diagram of the allowable power control circuit. [Figure 3] FIG. 3 is a diagram illustrating an example of a hardware configuration of the allowable power adjustment circuit. [Figure 4] FIG. 4 is a diagram showing a VRM-based allowable power determination table. [Figure 5] FIG. 5 is a diagram showing a die-by-die allowable power determination table. [Figure 6] FIG. 6 is a flowchart of an allowable power adjustment process performed by the allowable power adjustment circuit according to the first embodiment. [Figure 7] FIG. 7 is a flowchart of a process for determining the package-unit allowable power. [Figure 8] FIG. 8 is a flowchart of the process for determining the corrected VRM unit required power. [Figure 9] FIG. 9 is a flowchart of the process for determining the modified required power per die. [Figure 10] FIG. 10 is a flowchart of a process for determining the VRM permissible power. [Figure 11] FIG. 11 is a flowchart of a process for determining the die-based allowable power. [Figure 12] FIG. 12 is a diagram showing an example of a circuit for performing strict equal allocation. [Figure 13] FIG. 13 is a flowchart of a process for determining the die-based allowable power when performing strict uniform allocation. [Figure 14] FIG. 14 is a hardware configuration diagram according to the second embodiment. [Figure 15] FIG. 15 is a flowchart of an allowable power adjustment process performed by the allowable power adjustment circuit according to the second embodiment. [Figure 16] FIG. 16 is a flowchart of the process for determining the modified Ln tier required power. [Figure 17] FIG. 17 is a flowchart of the process for determining the modified Li tier required power. [Figure 18] FIG. 18 is a flowchart of the process for determining the Li tier allowable power. [Figure 19] FIG. 19 is a flowchart of the process for determining the modified L0 tier required power. [Figure 20] FIG. 20 is a flowchart of the process of determining the L0 tier allowable power. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of a processor, an information processing device, and a method for controlling a processor disclosed in the present application will be described in detail with reference to the accompanying drawings. Note that the processor, the information processing device, and the method for controlling a processor disclosed in the present application are not limited to the following embodiments. [Example]

[0015] 1 is a hardware configuration diagram of a server according to Example 1. The server 1, which is an information processing device, includes an LSI package 10, voltage regulators (VRM) V0 and V1, and a power supply device 20, as shown in FIG.

[0016] The LSI package 10 is a processor and may be called a chiplet. The LSI package 10 according to this embodiment includes a power control die 11, a voltage regulator 12, and CPU core dies D00, D01, D10, and D11. However, the four CPU core dies D00, D01, D10, and D11 are merely an example, and there is no particular limit to the number. The CPU core dies D00, D01, D10, and D11 are examples of "multiple computing mechanisms."

[0017] Voltage regulators V0 and V1 receive power from a power supply device 20. Voltage regulator V0 supplies power to CPU core dies D00 and D01 at a constant voltage. Voltage regulator V1 supplies power to CPU core dies D10 and D11 at a constant voltage. In this embodiment, CPU core dies D00 and D01 are connected to voltage regulator V0, and two CPU core dies D10 and D11 are connected to voltage regulator V1, but there is no particular limit to the number of these. In addition, the LSI package 10 will be described as having two voltage regulators V0 and V1 mounted thereon, but there is no particular limit to the number of these.

[0018] The CPU core die D00 has a power control circuit 300 and multiple CPU cores 400. The CPU core die D01 has a power control circuit 301 and multiple CPU cores 401. The CPU core die D10 has a power control circuit 310 and multiple CPU cores 410. The CPU core die D11 has a power control circuit 311 and multiple CPU cores 411.

[0019] CPU core dies D00 and D01 are included in a die group that receives power from the same voltage regulator V0. CPU core dies D10 and D11 are included in a die group that receives power from the same voltage regulator V1. Here, because the CPU core dies D00, D01, D10, and D11 each have similar functions, the CPU core die D00 will be used as an example for explanation.

[0020] Each CPU core 400 notifies the power required per die for operation to the power control circuit 300. Thereafter, the CPU core 400 receives power supply from the voltage regulator V0 and is driven by the supplied power to execute calculations.

[0021] The power control circuit 300 receives notification of the die-by-die required power from each CPU core 400. The power control circuit 300 then sums the die-by-die required powers to calculate the die-by-die required power of the CPU core die D00. Hereinafter, the die-by-die required power of the CPU core die D00 will be referred to as the D00 required power. The power control circuit 300 notifies the allowable power adjustment circuit 100 of the D00 required power.

[0022] The power control circuit 300 then receives the per-die allowable power of the CPU core die D00 from the allowable power adjustment circuit 100. Hereinafter, the per-die allowable power of the CPU core die D00 will be referred to as the D00 allowable power. The power control circuit 300 then instructs the voltage regulator V0 to change the voltage so that the power consumption of the CPU core die D00 is equal to or less than the power indicated by the D00 allowable power, and instructs each CPU core 400 to change the frequency.

[0023] The voltage regulator 12 receives power from the power supply device 20. The voltage regulator 12 then supplies power to the power control die 11 at a constant voltage.

[0024] The power control die 11 has an allowable power adjustment circuit 100 and a power control CPU 200. The power control CPU 200 runs an OS (Operating System) and firmware. The OS and firmware run by the power control CPU 200 transmit predetermined package-based power limits, VRM-based power limits, and die-based power limits to the allowable power adjustment circuit 100.

[0025] The package-based power limit is a power limit that corresponds to the upper limit of power that can be provided to the entire LSI package 10. The VRM-based power limit is a power limit for the two CPU core dies D00 and D01 that share the voltage regulator V0, and a power limit for the two CPU core dies D10 and D11 that share the voltage regulator V1. The die-based power limit is a power limit for each of the CPU core dies D00, D01, D10, and D11.

[0026] Here, the magnitude relationship between the package-based power limit, VRM-based power limit, and die-based power limit per die is package-based power limit / 4≦VRM-based power limit / 2≦die-based power limit. For example, if VRM-based power limit / 2 > die-based power limit, even if the power supplied to CPU core die D00 is set to the die-based power limit, the power supplied to the two CPU core dies D00 and D01 with the VRM-based power limit will be less than the die-based power limit. Therefore, if the magnitude relationship is reversed, the operation of the allowable power adjustment circuit 100 will be the same as when VRM-based power limit / 2 = die-based power limit. In other words, the allowable power allocation can be determined based on the magnitude relationship described above.

[0027] The allowable power adjustment circuit 100 receives a package-based power limit, a VRM-based power limit, and a die-based power limit from the power control CPU 200. The allowable power adjustment circuit 100 also receives die-based required power from each of the power control circuits 300, 301, 310, and 311. The allowable power adjustment circuit 100 then determines die-based supply power for each of the CPU core dies D00, D01, D10, and D11 using the package-based power limit, VRM-based power limit, die-based power limit, and die-based required power. The allowable power adjustment circuit 100 then transmits the determined die-based supply power to each of the power control circuits 300, 301, 310, and 311.

[0028] Fig. 2 is a block diagram of an allowable power control circuit. Next, the determination of the per-die supply power by the allowable power adjustment circuit 100 will be described in detail with reference to Fig. 2. As shown in Fig. 2, the allowable power adjustment circuit 100 has an information receiving unit 101, a per-package allowable power determining unit 102, a modified per-VRM required power determining unit 103, and a modified per-die required power determining unit 104. Furthermore, the allowable power adjustment circuit 100 has a per-VRM allowable power determining unit 105, a per-die allowable power determining unit 106, and a transmitting unit 107.

[0029] The information receiving unit 101 is an interface for receiving information. The information receiving unit 101 receives the package-based power limit, the VRM-based power limit, and the die-based power limit transmitted from the power control CPU 200. The information receiving unit 101 also receives the die-based power requirements of the CPU core dies D00, D01, D10, and D11 from the power control circuits 300, 301, 310, and 311, respectively.

[0030] Then, the information receiving unit 101 outputs the package-based power limit and the die-based required power of the CPU core dies D00, D01, D10, and D11 to the package-based allowable power determining unit 102. The information receiving unit 101 also outputs the VRM-based power limit and the die-based required power of the CPU core dies D00, D01, D10, and D11 to the modified VRM-based required power determining unit 103. The information receiving unit 101 also outputs the die-based power limit and the die-based required power of the CPU core dies D00, D01, D10, and D11 to the modified die-based required power determining unit 104.

[0031] The package-unit allowable power determination unit 102 receives input of the package-unit power limit and the die-unit required power of the CPU core dies D00, D01, D10, and D11 from the information receiving unit 101. Then, the package-unit allowable power determination unit 102 adds up the die-unit required power of the CPU core dies D00, D01, D10, and D11 to calculate the package-unit required power, which is the required power for the entire LSI package 10.

[0032] Next, the package-unit allowable power determination unit 102 determines whether the package-unit required power is greater than the package-unit power limit. If the package-unit required power is greater than the package-unit power limit, the package-unit allowable power determination unit 102 sets the package-unit power limit as the modified package-unit required power. If the package-unit required power is equal to or less than the package-unit power limit, the package-unit allowable power determination unit 102 sets the package-unit required power as the modified package-unit required power. Then, the package-unit allowable power determination unit 102 sets the modified package-unit required power as the package-unit allowable power, which corresponds to the allowable power of the entire LSI package 10. Thereafter, the package-unit allowable power determination unit 102 outputs the package-unit allowable power to the VRM-unit allowable power determination unit 105.

[0033] The package-unit allowable power determination unit 102 is an example of a "first allowable power determination unit." The package-unit required power is an example of a "first required power required by the plurality of arithmetic units as a whole." The package-unit power limit is an example of a "first power limit for the plurality of arithmetic units as a whole." The package allowable power is an example of a "first allowable power allowed by the plurality of arithmetic units as a whole." That is, the package-unit allowable power determination unit 102 determines the smaller of the first required power or the first power limit as the first allowable power. The die-unit required power of the CPU core dies D00, D01, D10, and D11 is an example of a "second required power." The package-unit allowable power determination unit 102 then calculates the package required power, which is the first required power, by summing the die-unit required power of the CPU core dies D00, D01, D10, and D11, which is the second required power.

[0034] FIG. 3 is a diagram illustrating an example of the hardware configuration of an allowable power adjustment circuit. The power listed near each element in FIG. 3 is an example of the power value output from each element under the following conditions: This is an example of the power value when the package power limit is 650 W, the VLM unit power limit is 350 W, and the die unit power limit is 200 W. This is also an example of the power value when the D00 required power is 130 W, the D01 required power is 150 W, the D10 required power is 180 W, and the D11 required power is 200 W. Hereinafter, these conditions will be referred to as explanatory conditions.

[0035] The allowable power adjustment circuit 100 can be realized by the hardware configuration shown in Fig. 3. Here, the circuit 201 and the circuit 202 have the same circuit configuration. The circuit 210 and the circuit 220 have the same circuit configuration. The circuits 211, 212, 221, and 222 have the same circuit configuration.

[0036] The function of the package-unit allowable power determination unit 102 is realized by, for example, an adder 111, a comparator 112, a multiplexer 113, an adder 114, and an adder 115. Here, the required power of the CPU core dies D00, D01, D10, and D11 will be referred to as the D00 required power, the D01 required power, the D10 required power, and the D11 required power, respectively.

[0037] Adder 114 receives the D00 required power and the D01 required power as input, adds the D00 required power and the D01 required power, and calculates and outputs the VRM required power, which is the overall power requirement of the die group requesting power supply from voltage regulator V0. Hereinafter, the VRM required power, which is the overall power requirement of the die group requesting power supply from voltage regulator V0, will be referred to as the V0 required power. For example, under the conditions for this explanation, adder 114 outputs 130W + 150W = 280W.

[0038] In addition, adder 115 receives input of the D10 required power and the D11 required power, adds the D10 required power and the D11 required power, and calculates and outputs the VRM required power, which is the overall power requirement of the die group that requests power supply from voltage regulator V1. Hereinafter, the VRM required power, which is the overall power requirement of the die group that requests power supply from voltage regulator V1, will be referred to as the V1 required power. Furthermore, the V0 required power and the V1 required power will be collectively referred to as the VRM required power. For example, under the conditions for this explanation, adder 115 outputs 180W + 200W = 380W.

[0039] Adder 111 receives an input of the V0 required power from adder 114. Adder 111 also receives an input of the V1 required power from adder 115. Adder 111 then adds the V0 required power and the V1 required power together to calculate and output the package-unit required power. For example, under the conditions for this explanation, adder 111 outputs 280W + 380W = 660W.

[0040] Comparator 112 receives the package-unit required power output from adder 111 as an input. Comparator 112 also receives the package-unit power limit as an input. Comparator 112 then compares the package-unit required power with the package-unit power limit. If the package-unit required power is greater than the package-unit power limit, comparator 112 outputs 1. If the package-unit required power is equal to or greater than the package-unit power limit, comparator 112 outputs 0. For example, in the case of the illustrative conditions, the package-unit required power is 660 W and the package-unit power limit is 650 W, so comparator 112 outputs 1.

[0041] The multiplexer 113 receives as input the package-unit required power output from the adder 111. The multiplexer 113 also receives as input the package-unit power limit. The multiplexer 113 then receives as input the output value from the comparator 112, and if the output value from the comparator 112 is 0, it outputs the package-unit required power. Conversely, if the output value from the comparator 112 is 1, the multiplexer 113 outputs the package-unit power limit. The information output from this multiplexer 113 is the corrected package-unit required power and also corresponds to the package-unit allowable power. For example, in the case of the illustrative conditions, the output value from the comparator 112 is 1, so the multiplexer 113 outputs 650 W.

[0042] Returning to Figure 2, the explanation continues. The post-modification per-VRM required power determiner 103 receives input of the VRM per-power limit and the per-die required power of the CPU core dies D00, D01, D10, and D11 from the information receiver 101. Next, the post-modification per-VRM required power determiner 103 calculates the V0 required power by summing the D00 required power and the D01 required power. The post-modification per-VRM required power determiner 103 also calculates the V1 required power by summing the D10 required power and the D11 required power.

[0043] Next, the post-modification VRM per-unit required power determination unit 103 selects voltage regulator V0 or V1 in turn. For example, if voltage regulator V0 is selected, the post-modification VRM per-unit required power determination unit 103 determines whether the V0 required power is greater than the VRM per-unit power limit. If the V0 required power is greater than the VRM per-unit power limit, the post-modification VRM per-unit required power determination unit 103 sets the V0 required power to the modified VRM per-unit power limit by modifying the V0 required power. If the V0 required power is equal to or less than the VRM per-unit power limit, the post-modification VRM per-unit required power determination unit 103 sets the V0 required power to the modified V0 required power.

[0044] The modified VRM per unit required power determiner 103 calculates the modified V1 required power in the same manner for the V1 required power. Thereafter, the modified VRM per unit required power determiner 103 outputs the modified V0 required power and the modified V1 required power to the VRM per unit allowed power determiner 105.

[0045] The die group of CPU core dies D00 and D01 and the die group of CPU core dies D10 and D11 are examples of "the plurality of arithmetic units divided into a plurality of groups." The VRM-per-unit required power is an example of "third required power." The VRM-per-unit power limit is an example of "third power limit." The modified VRM-per-unit required power is an example of "modified third required power." The modified VRM-per-unit required power determiner 103 is an example of "modified third required power determiner." The modified VRM-per-unit required power determiner 103 calculates the third required power by summing the second required powers of the respective arithmetic units that supply power to the voltage regulator V0 or V1, and determines the smaller of the third required power or the third power limit as the modified third required power.

[0046] 3, an example of a hardware configuration for realizing the function of the post-modification VRM per unit required power determiner 103 will be described. The function of the post-modification VRM per unit required power determiner 103 is realized by, for example, adder 114, adder 115, comparator 116, multiplexer 117, comparator 118, and multiplexer 119.

[0047] Adder 114 receives the D00 required power and the D01 required power as input, and adds the D00 required power and the D01 required power to calculate the V0 required power. Adder 115 receives the D10 required power and the D11 required power as input, and adds the D10 required power and the D11 required power to calculate the V1 required power.

[0048] Comparator 116 receives an input of the V0 required power from adder 114. Comparator 116 also receives an input of the VRM unit power limit. Comparator 116 then compares the V0 required power with the VRM unit power limit. If the V0 required power is greater than the VRM unit power limit, comparator 116 outputs 1. If the V0 required power is equal to or less than the VRM unit power limit, comparator 116 outputs 0. For example, in the illustrative conditions, the V0 required power is 280 W and the VRM unit power limit is 350 W, so comparator 116 outputs 0.

[0049] The multiplexer 117 receives the V0 required power as an input from the adder 114. The multiplexer 117 also receives the VRM unit power limit as an input. The multiplexer 117 also receives the output value from the comparator 116. If the output value from the comparator 116 is 0, the multiplexer 117 outputs the V0 required power. If the output value from the comparator 116 is 1, the multiplexer 117 outputs the VRM power limit. The information output from the multiplexer 117 corresponds to the corrected V0 required power. For example, in the case of the illustrative conditions, the output value from the comparator 116 is 0, so the multiplexer 117 outputs 280 W.

[0050] Similar to comparator 116 and multiplexer 117, comparator 118 and multiplexer 119 also output either the V1 required power or the VRM power limit based on the V1 required power and the VRM power limit. The information output from multiplexer 119 corresponds to the corrected V1 required power. For example, in the case of the illustrative conditions, the V1 required power is 380 and the VRM unit power limit is 350 W, so comparator 116 outputs 1 and multiplexer 119 outputs 350 W.

[0051] Continuing the explanation, returning to Figure 2, the modified per-die required power determiner 104 receives input of the per-die power limit and the per-die required power of the CPU core dies D00, D01, D10, and D11 from the information receiver 101. Next, the modified per-die required power determiner 104 selects the CPU core die D00, D01, D10, or D11 in turn.

[0052] For example, when CPU core die D00 is selected, modified die-by-die required power determination unit 104 determines whether D00 required power is greater than the die-by-die power limit. If D00 required power is greater than the die-by-die power limit, modified die-by-die required power determination unit 104 modifies the D00 required power to obtain modified D00 required power. If D00 required power is equal to or less than the die-by-die power limit, modified die-by-die required power determination unit 104 modifies the D00 required power to obtain modified D00 required power.

[0053] The modified die-unit required power determiner 104 calculates the modified D01 required power, the modified D10 required power, and the modified D11 required power in the same manner for the D01, D10, and D11 required powers, respectively. Thereafter, the modified die-unit required power determiner 104 outputs the modified D00 required power, the modified D01 required power, the modified D10 required power, and the modified D11 required power to the die-unit allowable power determiner 106.

[0054] The per-die power limits for CPU core dies D00, D01, D10, and D11 are an example of a "second power limit." Furthermore, the modified D00 required power, the modified D01 required power, the modified D10 required power, and the modified D11 required power are examples of a "modified second required power" for each computing unit. Furthermore, the modified per-die required power determiner 104 is an example of a "modified second required power determiner." The modified per-die required power determiner 104 determines, for each computing unit, the smaller of the second required power or the second power limit as the modified second required power.

[0055] 3, an example of a hardware configuration for realizing the function of post-modification die-unit required power determiner 104 will be described. The function of post-modification die-unit required power determiner 104 is realized by comparator 128, multiplexer 129, comparator 130, multiplexer 131, comparator 132, and multiplexer 133.

[0056] Comparator 128 receives an input of the D00 required power. Comparator 128 also receives an input of the per-die power limit. Comparator 128 then compares the D00 required power with the per-die power limit. If the D00 required power is greater than the per-die power limit, comparator 128 outputs 1. If the D00 required power is less than or equal to the per-die power limit, comparator 128 outputs 0. For example, in the illustrative conditions, the D00 required power is 130 W and the per-die power limit is 200 W, so comparator 128 outputs 0.

[0057] The multiplexer 129 receives an input of the D00 required power. The multiplexer 129 also receives an input of the die-by-die power limit. The multiplexer 129 also receives an input of the output value from the comparator 128. If the output value from the comparator 128 is 0, the multiplexer 129 outputs the D00 required power. If the output value from the comparator 128 is 1, the multiplexer 129 outputs the core power limit. The information output from the multiplexer 129 corresponds to the corrected D00 required power. For example, in the case of the illustrative conditions, the comparator 128 outputs 0, so the multiplexer 129 outputs 130 W.

[0058] Comparator 130 and multiplexer 131 output the D01 required power or core power limit based on the D01 required power and the die-by-die power limit in the same manner as comparator 128 and multiplexer 129. The information output from multiplexer 131 corresponds to the corrected D01 required power. For example, in the case of the illustrative conditions, comparator 130 outputs 0, and multiplexer 131 outputs 150 W.

[0059] Comparator 132 and multiplexer 133 output the D10 required power or core power limit based on the D10 required power and the die-by-die power limit in the same manner as comparator 128 and multiplexer 129. The information output from multiplexer 133 corresponds to the corrected D10 required power. For example, in the case of the illustrative conditions, comparator 132 outputs 0, and multiplexer 133 outputs 150 W.

[0060] Comparator 134 and multiplexer 135 output the D11 required power or core power limit based on the D11 required power and the die-by-die power limit in the same manner as comparator 128 and multiplexer 129. The information output from multiplexer 135 corresponds to the corrected D11 required power. For example, in the case of the illustrative conditions, comparator 134 outputs 1, and multiplexer 135 outputs 200 W.

[0061] Returning to Figure 2, the explanation will continue. VRM per allowable power determination unit 105 receives an input of the package per allowable power from package per allowable power determination unit 102. Furthermore, VRM per allowable power determination unit 105 receives an input of the modified V0 required power and modified V1 required power, which are the modified VRM per required power, from modified VRM per required power determination unit 103. Next, VRM per allowable power determination unit 105 selects voltage regulator V0 and voltage regulator V1 in that order.

[0062] For example, when the voltage regulator V0 is selected, the VRM-based allowable power determination unit 105 compares the modified V0 required power with half the package-based allowable power. If the modified V0 required power is equal to or less than half the package-based allowable power, the VRM-based allowable power determination unit 105 sets the modified V0 required power to the V0 allowable power, which is the overall allowable power of a set of die groups that receives power from the voltage regulator V0.

[0063] On the other hand, if the modified V0 required power is greater than half the package allowable power, the VRM allowable power determination unit 105 compares the modified V1 required power with half the package allowable power. If the modified V1 required power is greater than half the package allowable power, the VRM allowable power determination unit 105 sets the V0 allowable power to half the package allowable power.

[0064] On the other hand, if the modified V1 required power is less than half the package allowable power, the VRM allowable power determination unit 105 compares the value obtained by subtracting the modified V1 required power from the package allowable power with the modified V0 required power. If the modified V0 required power is greater than the value obtained by subtracting the modified V1 required power from the package allowable power, the VRM allowable power determination unit 105 determines the value obtained by subtracting the modified V1 required power from the package allowable power as the V0 allowable power.

[0065] On the other hand, if the modified V0 required power is equal to or less than the value obtained by subtracting the modified V1 required power from the package-based allowable power, the VRM-based allowable power determination unit 105 sets the modified V0 required power as the V0 allowable power.

[0066] The VRM-based allowable power determination unit 105 similarly calculates the V1 allowable power using the package-based allowable power and the corrected V1 required power. Then, the VRM-based allowable power determination unit 105 outputs the V0 allowable power and the V1 allowable power to the die-based allowable power determination unit 106.

[0067] The VRM-unit allowable power is an example of a "third allowable power." The VRM-unit allowable power determination unit 105 is an example of a "third allowable power determination unit." The VRM-unit allowable power determination unit 105 determines the third allowable power for each group based on the smaller of the third required power or the third power limit value and the first allowable power for each of the voltage regulators V0 and V1. In this embodiment, the number of voltage regulators V0 and V1 installed in the server 1, ie, two, is an example of a "first predetermined number." Specifically, the VRM-unit allowable power determination unit 105 determines the third allowable power for each of the voltage regulators V0 and V1 based on the modified third required power and the value obtained by dividing the first allowable power by the first predetermined number.

[0068] 3, an example of a hardware configuration for realizing the function of VRM-unit allowable power determination unit 105 will be described. The function of VRM-unit allowable power determination unit 105 is realized by divider 120, comparator 121, subtractor 122, comparator 123, subtractor 124, comparator 125, comparator 126, and selector 127.

[0069] Divider 120 receives the package-unit allowable power output from multiplexer 113. Next, divider 120 performs division by 2 by shifting the package-unit allowable power data one bit to the right. Divider 120 then outputs package-unit allowable power x 1 / 2. For example, in the case of the illustrative conditions, since the package-unit allowable power is 650 W, divider 120 outputs 325 W.

[0070] Comparator 121 receives as input the modified V0 required power output from multiplexer 117. Comparator 121 also receives as input half the package allowable power output from divider 120. Next, comparator 121 compares the modified V0 required power with half the package allowable power. If the modified V0 required power is greater than half the package allowable power, comparator 121 outputs 1, indicating True. If the modified V0 required power is equal to or less than half the package allowable power, comparator 121 outputs 0, indicating False. For example, in the case of the illustrative conditions, the modified V0 required power is 280 W and half the package allowable power is 325 W, so comparator 121 outputs 0.

[0071] Subtractor 122 receives as input the package-unit allowable power output from multiplexer 113. Subtractor 122 also receives as input the modified V0 required power output from multiplexer 117. Subtractor 122 then outputs a value obtained by subtracting the modified V0 required power from the package-unit allowable power. For example, in the case of the illustrative conditions, the package-unit allowable power is 650 W and the modified V0 required power is 280 W, so subtractor 122 outputs 370 W.

[0072] Comparator 123 receives as input the modified V1 required power output from multiplexer 119. Comparator 123 also receives as input half the package allowable power output from divider 120. Next, comparator 123 compares the modified V1 required power with half the package allowable power. If the modified V1 required power is greater than half the package allowable power, comparator 123 outputs 1, indicating True. If the modified V1 required power is equal to or less than half the package allowable power, comparator 123 outputs 0, indicating False. For example, in the case of the illustrative conditions, the modified V1 required power is 350 W and half the package allowable power is 325 W, so comparator 123 outputs 1.

[0073] Subtractor 124 receives as input the package unit required power output from multiplexer 113. Subtractor 124 also receives as input the corrected V1 required power output from multiplexer 119. Next, subtractor 122 outputs a value obtained by subtracting the corrected V1 required power from the package unit required power. For example, in the case of the illustrative conditions, the package unit allowable power is 650 W and the corrected V1 required power is 350 W, so comparator 121 outputs 300 W.

[0074] Comparator 125 receives as input the modified V0 required power output from multiplexer 117. Also, comparator 125 receives as input the value obtained by subtracting the modified V1 required power from the package unit allowable power output from subtracter 124. Then, comparator 125 compares the modified V0 required power with the value obtained by subtracting the modified V1 required power from the package unit allowable power. If the modified V0 required power is greater than the value obtained by subtracting the modified V1 required power from the package unit allowable power, comparator 125 outputs 1 indicating True. If the modified V0 required power is equal to or less than the value obtained by subtracting the modified V1 required power from the package unit allowable power, comparator 125 outputs 0 indicating False. For example, in the case of the illustrative conditions, the modified V0 required power is 280 W, and the value obtained by subtracting the modified V1 required power from the package unit allowable power is 300 W, so comparator 125 outputs 0.

[0075] Comparator 126 receives as input the modified V1 required power output from multiplexer 119. Comparator 126 also receives as input the value obtained by subtracting the modified V0 required power from the package unit allowable power output from subtracter 122. Comparator 126 then compares the modified V1 required power with the value obtained by subtracting the modified V0 required power from the package unit allowable power. If the modified V1 required power is greater than the value obtained by subtracting the modified V0 required power from the package unit allowable power, comparator 125 outputs 1 indicating True. If the modified V1 required power is equal to or less than the value obtained by subtracting the modified V0 required power from the package unit allowable power, comparator 125 outputs 0 indicating False. For example, in the case of the illustrative conditions, the modified V1 required power is 350 W, and the value obtained by subtracting the modified V0 required power from the package unit allowable power is 370 W, so comparator 126 outputs 0.

[0076] Selector 127 receives as input package-unit allowable power×½ output from divider 120, corrected V0 required power output from multiplexer 117, and corrected V1 required power output from multiplexer 119. Selector 127 also receives as input the output value of comparator 121, the output value of comparator 123, the output value of comparator 125, and the output value of comparator 126.

[0077] 4 is a diagram showing a VRM-based allowable power determination table. In VRM-based allowable power determination table 230, column 231 indicates the output value of comparator 121. Column 232 indicates the output value of comparator 123. Column 233 indicates the output value of comparator 125. Column 234 indicates the output value of comparator 126. Column 235 corresponds to the V0 allowable power output by selector 127. Column 236 corresponds to the V1 allowable power output by selector 127. In VRM-based allowable power determination table 230, items with a "- (hyphen)" registered are items that do not affect the selection of selector 127, regardless of the value.

[0078] 4. Selector 127 determines data to be selected in accordance with VRM-based allowable power determination table 230 based on the output values ​​of comparators 121, 123, 125, and 126. Selector 127 then outputs the selected data as the V0 allowable power and the V1 allowable power. For example, in the case of the illustrative conditions, the output values ​​of comparators 121, 123, 125, and 126 are 0, 1, 0, and 0, respectively, so selector 127 outputs 280 W as the V0 allowable power and 350 W as the V1 allowable power.

[0079] Continuing the explanation, returning to Figure 2, the die-per-die allowable power determiner 106 receives inputs of the modified D00 required power, the modified D01 required power, the modified D10 required power, and the modified D11 required power from the modified die-per-die required power determiner 104. The die-per-die allowable power determiner 106 also receives inputs of the V0 allowable power and the V1 allowable power from the VRM-per-allowable power determiner 105. Next, the die-per-die allowable power determiner 106 selects the voltage regulator V0 and the voltage regulator V1 in that order.

[0080] If the voltage regulator V0 is selected, the die-by-die allowable power determination unit 106 then selects the CPU core die D00 or D01 in turn. For example, if the CPU core die D00 is selected, the die-by-die allowable power determination unit 106 compares the modified D00 required power with half the V0 allowable power. If the modified D00 required power is less than half the V0 allowable power, the die-by-die allowable power determination unit 106 sets the modified D00 required power as the D00 allowable power, which is the power allowed for the CPU core die D00.

[0081] On the other hand, if the modified D00 required power is greater than half the V0 allowable power, the die-by-die allowable power determination unit 106 compares the modified D01 required power with half the V0 allowable power. If the modified D01 required power is greater than half the V0 allowable power, the die-by-die allowable power determination unit 106 sets half the V0 allowable power as the D00 allowable power.

[0082] On the other hand, if the modified D01 required power is less than half the V0 allowable power, the die-by-die allowable power determination unit 106 compares the value obtained by subtracting the modified D01 required power from the V0 allowable power with the modified D00 required power. If the modified D00 required power is greater than the value obtained by subtracting the modified D01 required power from the V0 allowable power, the die-by-die allowable power determination unit 106 determines the value obtained by subtracting the modified D01 required power from the V0 allowable power as the D00 allowable power.

[0083] On the other hand, if the modified D00 required power is equal to or less than the value obtained by subtracting the modified D01 required power from the V0 allowable power, the die-by-die allowable power determination unit 106 sets the modified D00 required power as the D00 allowable power.

[0084] The die-by-die allowable power determination unit 106 similarly determines the D01 allowable power. Furthermore, the die-by-die allowable power determination unit 106 similarly determines the D10 allowable power and the D11 allowable power using the V1 allowable power, the modified D10 required power, and the modified D11 required power. The die-by-die allowable power determination unit 106 then outputs the D00 allowable power, the D01 allowable power, the D10 allowable power, and the D11 allowable power to the transmitter 107.

[0085] The die-by-die allowable power determination unit 106 is an example of a "second allowable power determination unit." The die-by-die allowable power determination unit 106 determines the second allowable power for each of the CPU core dies D00, D01, D10, and D11, which are the computing units, based on the smaller of the two required powers or the second power limit, and the first allowable power. The die-by-die allowable power determination unit 106 also determines the second allowable power for each computing unit based on the smaller of the second required power or the second power limit, and the third allowable power. In this embodiment, the number of CPU core dies D00 and D01 to which the voltage regulator V0 supplies power, and the number of CPU core dies D10 and D11 to which the voltage regulator V0 supplies power, which is two, are an example of a "second predetermined number." The die-by-die allowable power determination unit 106 determines the second allowable power for each computing unit based on the modified second required power and a value obtained by dividing the third allowable power of the voltage regulator V0 or V1 that supplies the power by a second predetermined number.

[0086] 3 , an example of a hardware configuration for realizing the function of the die-by-die allowable power determiner 106 will be described. The function of the die-by-die allowable power determiner 106 is realized by a divider 136, a comparator 137, a subtractor 138, a comparator 139, a subtractor 140, a divider 141, a comparator 142, a subtractor 143, a comparator 144, and a subtractor 145. In addition, the function of the die-by-die allowable power determiner 106 is realized by a comparator 146, a comparator 147, a selector 148, a comparator 149, a comparator 150, and a selector 151.

[0087] Divider 136 receives the V0 allowable power output from selector 127. Next, divider 136 performs division by 2 by shifting the V0 allowable power data one bit to the right. Divider 136 then outputs half the value of the V0 allowable power. For example, in the case of the illustrative conditions, since the V0 allowable power is 280 W, divider 136 outputs 140 W.

[0088] Comparator 137 receives as input the modified D00 required power output from multiplexer 129. Comparator 137 also receives as input the value of half the V0 allowable power output from divider 136. Next, comparator 137 compares the modified D00 required power with half the V0 allowable power. If the modified D00 required power is greater than half the V0 allowable power, comparator 137 outputs 1, indicating True. If the modified D00 required power is equal to or less than half the V0 allowable power, comparator 137 outputs 0, indicating False. For example, in the case of the illustrative conditions, the modified D00 required power is 130 W, and V0 allowable power x 1 / 2 is 140 W, so comparator 121 outputs 0.

[0089] Subtractor 138 receives as input the V0 allowable power output from selector 127. Subtractor 138 also receives as input the corrected D00 required power output from multiplexer 129. Subtractor 138 then outputs a value obtained by subtracting the corrected D00 required power from the V0 allowable power. For example, in the case of the illustrative conditions, the V0 allowable power is 280 W and the corrected D00 required power is 130 W, so subtractor 138 outputs 150 W.

[0090] Comparator 139 receives the input of the modified D01 required power output from multiplexer 131. Comparator 139 also receives the input of V0 allowable power × 1 / 2 output from divider 136. Next, comparator 137 compares the modified D01 required power with V0 allowable power × 1 / 2. If the modified D01 required power is greater than V0 allowable power × 1 / 2, comparator 137 outputs 1, indicating True. If the modified D01 required power is equal to or less than V0 allowable power × 1 / 2, comparator 137 outputs 0, indicating False. For example, in the case of the illustrative conditions, the modified D01 required power is 150 W and V0 allowable power × 1 / 2 is 140 W, so comparator 137 outputs 1.

[0091] Subtractor 140 receives as input the V0 allowable power output from selector 127. Subtractor 140 also receives as input the corrected D01 required power output from multiplexer 131. Subtractor 140 then outputs the value obtained by subtracting the V0 allowable power from the corrected D01 required power. For example, in the case of the illustrative conditions, the V0 allowable power is 280 W and the corrected D01 required power is 150 W, so subtractor 140 outputs 130 W.

[0092] Comparator 146 receives the input of the modified D00 required power output from multiplexer 129. Comparator 146 also receives the value obtained by subtracting the modified D01 required power from the V0 allowable power output from subtractor 140. Next, comparator 146 compares the modified D00 required power with the value obtained by subtracting the modified D01 required power from the V0 allowable power. Comparator 146 outputs 1, indicating True, if the modified D00 required power is greater than the value obtained by subtracting the modified D01 required power from the V0 allowable power. Comparator 146 also outputs 0, indicating False, if the modified D00 required power is equal to or less than the value obtained by subtracting the modified D01 required power from the V0 allowable power. For example, in the illustrative conditions, the modified D00 required power is 130 W, and the value obtained by subtracting the modified D01 required power from the V0 allowable power is 130 W, so comparator 121 outputs 0.

[0093] Comparator 147 receives as input the modified D01 required power output from multiplexer 131. Comparator 147 also receives as input the value obtained by subtracting the modified D00 required power from the V0 allowable power output from subtractor 138. Next, comparator 147 compares the modified D01 required power with the value obtained by subtracting the modified D00 required power from the V0 allowable power. If the modified D01 required power is greater than the value obtained by subtracting the modified D00 required power from the V0 allowable power, comparator 147 outputs 1 indicating True. If the modified D01 required power is equal to or less than the value obtained by subtracting the modified D00 required power from the V0 allowable power, comparator 147 outputs 0 indicating False. For example, in the case of the illustrative conditions, the modified D01 required power is 150 W, and the value obtained by subtracting the modified D00 required power from the V0 allowable power is 150 W, so comparator 121 outputs 0.

[0094] Selector 148 receives as input half the value of the VRM allowable power output from divider 136, the modified D00 required power output from multiplexer 129, and the modified D01 required power output from multiplexer 131. Selector 148 also receives as input the output value of comparator 137, the output value of comparator 139, the output value of comparator 146, and the output value of comparator 147.

[0095] 5 is a diagram showing a die-by-die allowable power determination table. In die-by-die allowable power determination table 240, column 241 indicates the output value of comparator 137. Column 242 indicates the output value of comparator 139. Column 243 indicates the output value of comparator 146. Column 244 indicates the output value of comparator 147. Column 245 corresponds to the D00 allowable power output by selector 148. Column 246 corresponds to the D01 allowable power output by selector 148.

[0096] Selector 148 has die-by-die allowable power determination table 240 shown in Fig. 5. Selector 148 determines information to be selected in accordance with die-by-die allowable power determination table 240 based on the output value of comparator 137, the output value of comparator 139, the output value of comparator 146, and the output value of comparator 147. Selector 148 then outputs the selected information as the D00 allowable power and the D01 allowable power. For example, in the case of the illustrative conditions, the output values ​​of comparators 137, 139, 146, and 147 are 0, 1, 0, and 0, respectively, so selector 127 outputs 130 W as the D00 allowable power and 150 W as the D01 allowable power.

[0097] Divider 141, comparator 142, subtractor 143, comparator 144, subtractor 145, comparator 149, comparator 150, and selector 151 similarly determine the D10 allowable power and the D11 allowable power. For example, under the conditions for explanation, divider 141 outputs 175 W. Comparator 142 outputs 1. Subtractor 143 outputs 170 W, and comparator 144 outputs 1. Subtractor 145 outputs 150 W. Comparator 149 outputs 1. Comparator 150 outputs 1. The output values ​​of comparators 142, 144, 149, and 150 are 1, 1, 1, and 1, respectively, so selector 151 outputs 175 W as the D10 allowable power and 175 W as the D11 allowable power.

[0098] Returning to FIG. 2, the explanation will continue. The transmitting unit 107 is an interface for transmitting information. The transmitting unit 107 receives the D00 allowable power, the D01 allowable power, the D10 allowable power, and the D11 allowable power from the die-by-die allowable power determination unit 106. Then, the transmitting unit 107 transmits the D00 allowable power to the power control circuit 300 of the CPU core die D00. The transmitting unit 107 also transmits the D01 allowable power to the power control circuit 301 of the CPU core die D01. The transmitting unit 107 also transmits the D10 allowable power to the power control circuit 310 of the CPU core die D10. The transmitting unit 107 also transmits the D11 allowable power to the power control circuit 311 of the CPU core die D11.

[0099] 6 is a flowchart of the allowable power adjustment process by the allowable power adjustment circuit according to the embodiment 1. Next, the overall flow of the allowable power adjustment process by the allowable power adjustment circuit 100 according to the embodiment 1 will be described with reference to FIG.

[0100] The information receiving unit 101 receives the required power D00, required power D01, required power D10, and required power D11 per die from the CPU core die D00, the CPU core die D01, the CPU core die D10, and the CPU core die D11 (step S1).

[0101] The package-unit allowable power determining unit 102 determines the package-unit allowable power using the D00 required power, the D01 required power, the D10 required power, and the D11 required power, as well as the package-unit power limit (step S2).

[0102] The modified per-VRM required power determiner 103 determines the modified per-VRM required power for each of the voltage regulators V0 and V1 using the per-die required power and the per-VRM power limit (step S3). More specifically, the modified per-VRM required power determiner 103 determines the modified V0 required power and the modified V1 required power.

[0103] The modified per-die required power determiner 104 determines the modified per-die required power for each of the CPU core die D00, D01, D10, and D11 using the per-die required power and the per-die power limit (step S4). In detail, the modified per-die required power determiner 104 determines the modified D00 required power, the modified D01 required power, the modified D10 required power, and the modified D11 required power, respectively.

[0104] Based on the package-based allowable power and the corrected VRM-based required power, VRM-based allowable power determination unit 105 determines the VRM-based allowable power for each of voltage regulators V0 and V1 (step S5). More specifically, VRM-based allowable power determination unit 105 determines the V0 allowable power and the V1 allowable power.

[0105] The die-by-die allowable power determination unit 106 determines the die-by-die allowable power for each of the CPU core die D00, D01, D10, and D11 based on the VRM-by-VRM allowable power and the modified die-by-die required power (step S6). Specifically, the die-by-die allowable power determination unit 106 determines the D00 allowable power, the D01 allowable power, the D10 allowable power, and the D11 allowable power.

[0106] The transmitting unit 107 transmits the D00 allowable power, the D01 allowable power, the D10 allowable power, and the D11 allowable power to the CPU core die D00, the CPU core die D01, the CPU core die D10, and the CPU core die D11, respectively (step S7).

[0107] Fig. 7 is a flowchart of the process of determining the allowable power per package. Next, the flow of the process of determining the allowable power per package by the package allowable power determination unit 102 will be described with reference to Fig. 7. Each process shown in the flow of Fig. 7 is an example of the process executed in step S2 in Fig. 6.

[0108] The package-unit allowable power determining unit 102 calculates the package-unit allowable power by summing the D00 required power, the D01 required power, the D10 required power, and the D11 required power (step S11).

[0109] Next, the package-unit allowable power determining unit 102 determines whether the calculated package-unit required power is greater than the package-unit power limit (step S12).

[0110] If the package-unit required power is greater than the package-unit power limit (step S12: Yes), the package-unit allowable power determining unit 102 sets the package-unit power limit as the corrected package-unit required power (step S13).

[0111] On the other hand, if the package-unit required power is equal to or less than the package-unit power limit (step S12: No), the package-unit allowable power determining unit 102 sets the package-unit required power as the modified package-unit required power (step S14).

[0112] Next, the package-unit allowable power determining unit 102 sets the corrected package-unit required power as the package-unit allowable power (step S15).

[0113] Fig. 8 is a flowchart of the process of determining the modified VRM unit required power. Next, the flow of the process of determining the modified VRM unit required power by the modified VRM unit required power determiner 103 will be described with reference to Fig. 8. Each process shown in the flow of Fig. 8 is an example of the process executed in step S3 in Fig. 6.

[0114] The post-correction VRM unit required power determiner 103 calculates the VRM unit required power for each of the voltage regulators V0 and V1. Specifically, the post-correction VRM unit required power determiner 103 calculates the V0 unit required power by summing the D00 required power and the D01 required power. The post-correction VRM unit required power determiner 103 also calculates the V1 unit required power by summing the D10 required power and the D11 required power (step S21).

[0115] Next, post-correction VRM unit required power determiner 103 selects either voltage regulator V0 or V1 (step S22). Post-correction VRM unit required power determiner 103 executes the following process for the selected one of voltage regulators V0 or V1.

[0116] Next, post-correction VRM per unit required power determiner 103 determines whether the VRM per unit required power of the selected voltage regulator V0 or V1 is greater than the VRM per unit power limit (step S23).

[0117] If the VRM per unit required power is greater than the VRM per unit power limit (step S23: Yes), modified VRM per unit required power determiner 103 sets the VRM per unit power limit as the modified VRM per unit required power (step S24).

[0118] On the other hand, if the VRM unit required power is equal to or less than the VRM unit power limit (step S23: No), post-modification VRM unit required power determiner 103 sets the VRM unit required power as post-modification VRM unit required power (step S25).

[0119] Thereafter, post-correction VRM unit required power determiner 103 determines whether or not post-correction VRM unit required power has been determined for both voltage regulators V0 and V1 (step S26).

[0120] If the revised VRM per unit required power has not been determined for either voltage regulator V0 or V1 (step S26: No), the revised VRM per unit required power determiner 103 returns to step S22. On the other hand, if the revised VRM per unit required power has been determined for both voltage regulators V0 and V1 (step S26: Yes), the revised VRM per unit required power determiner 103 ends the process of determining the revised VRM per unit required power.

[0121] 9 is a flowchart of the process of determining the post-modification die-unit required power. Next, the flow of the process of determining the post-modification die-unit required power by post-modification die-unit required power determiner 104 will be described with reference to FIG. 9. Each process shown in the flow of FIG. 9 corresponds to an example of the process executed in step S4 in FIG. 6.

[0122] The modified die-by-die required power determiner 104 selects one of the CPU core dies D00, D01, D10, and D11 (step S31). The modified die-by-die required power determiner 104 executes the following process for the selected one of the CPU core dies D00, D01, D10, and D11.

[0123] Next, the post-modification die-per-die required power determiner 104 determines whether the die-per-die required power is greater than the die-per-die power limit (step S32).

[0124] If the per-die required power is greater than the per-die power limit (step S32: Yes), modified per-die required power determiner 104 sets the per-die power limit as the modified per-die required power (step S33).

[0125] On the other hand, if the die-unit required power is equal to or less than the die-unit power limit (step S23: No), modified die-unit required power determiner 104 sets the die-unit required power as modified die-unit required power (step S34).

[0126] Thereafter, the modified die-unit required power determiner 104 determines whether modified die-unit required power has been determined for all of the CPU core dies D00, D01, D10, and D11 (step S35).

[0127] If the modified per-die required power determination unit 104 determines the modified per-die required power for any of the CPU core dies D00, D01, D10, and D11 (step S35: No), the modified per-die required power determination unit 104 returns to step S31. On the other hand, if the modified per-die required power has been determined for all of the CPU core dies D00, D01, D10, and D11 (step S35: Yes), the modified per-die required power determination unit 104 ends the process of determining the modified per-die required power.

[0128] Fig. 10 is a flowchart of the process of determining the VRM permissible power. Next, the flow of the process of determining the VRM permissible power by the VRM permissible power determination unit 105 will be described with reference to Fig. 10. Each process shown in the flow of Fig. 10 is an example of the process executed in step S5 in Fig. 6.

[0129] VRM unit allowable power determiner 105 selects one of voltage regulators V0 or V1 (step S41). VRM unit allowable power determiner 105 executes the following process for the selected one of voltage regulators V0 or V1.

[0130] VRM unit allowable power determination unit 105 determines whether the corrected VRM unit required power is greater than half the package unit allowable power (step S42).

[0131] If the modified VRM required power is greater than half the package allowable power (step S42: Yes), VRM allowable power determination unit 105 determines whether the other modified VRM required power is greater than half the package allowable power (step S43). Here, the other modified VRM required power is the modified VRM required power of the voltage regulator V0 or V1 that is not selected.

[0132] If the other modified VRM required power is greater than half the package allowable power (step S43: Yes), the VRM allowable power determination unit 105 sets the VRM allowable power to half the package allowable power (step S44).

[0133] On the other hand, if the other modified VRM required power is less than half the package allowable power (step S43: No), the VRM allowable power determination unit 105 calculates a value obtained by subtracting the other modified VRM required power from the package allowable power.The VRM allowable power determination unit 105 then determines whether the modified VRM required power is greater than the value obtained by subtracting the other modified VRM required power from the package allowable power (step S45).If the value obtained by subtracting the modified V1 required power from the package allowable power is greater than the modified V0 required power (step S45: Yes), the VRM allowable power determination unit 105 performs the following process.That is, the VRM allowable power determination unit 105 sets the VRM allowable power to the value obtained by subtracting the other modified VRM required power from the package allowable power (step S46).

[0134] On the other hand, if the value obtained by subtracting the modified V1 required power from the package allowable power is equal to or less than the modified V0 required power (step S45: No), VRM per allowable power determination unit 105 sets the modified VRM per required power as the VRM per allowable power (step S47).Furthermore, if the modified VRM per required power is equal to or less than half the package per allowable power (step S42: No), VRM per allowable power determination unit 105 also sets the modified VRM per required power as the VRM per allowable power (step S47).

[0135] Thereafter, VRM unit allowable power determination unit 105 determines whether or not the VRM unit allowable power has been determined for both voltage regulators V0 and V1 (step S48).

[0136] If the VRM per unit allowable power has not been determined for either the voltage regulators V0 or V1 (step S48: No), the VRM per unit allowable power determination unit 105 returns to step S41. On the other hand, if the VRM per unit allowable power has been determined for both the voltage regulators V0 and V1 (step S48: Yes), the VRM per unit allowable power determination unit 105 ends the VRM per unit allowable power determination process.

[0137] Fig. 11 is a flowchart of the process of determining the per-die allowable power. Next, the flow of the process of determining the per-VRM allowable power by the per-die allowable power determiner 106 will be described with reference to Fig. 11. Each process shown in the flow of Fig. 11 corresponds to an example of the process executed in step S6 in Fig. 6.

[0138] The die-by-die allowable power determination unit 106 selects one of the voltage regulators V0 or V1 (step S50). The die-by-die allowable power determination unit 106 executes the following process for the selected one of the voltage regulators V0 or V1.

[0139] Next, the die-by-die allowable power determination unit 106 selects one of the CPU core dies D00 and D10, or the CPU core dies D10 and D11, connected to the selected voltage regulator V0 or V1 (step S51). The die-by-die allowable power determination unit 106 executes the following process for the selected one of the CPU core dies D00, D01, D10, and D11.

[0140] Next, the die-based allowable power determination unit 106 determines whether the modified die-based required power is greater than half the VRM-based allowable power (step S52).

[0141] If the modified die-by-die required power is greater than half the VRM-by-VRM allowed power (step S52: Yes), the die-by-die allowable power determination unit 106 determines whether the other modified die-by-die required power is greater than half the VRM-by-VRM allowed power (step S53). The other modified die-by-die required power is the CPU core die opposite to the selected one of the CPU core dies D00 and D01, or the CPU core dies D10 and D11.

[0142] If the other modified per-die required power is greater than half the VRM allowable power (step S53: Yes), the per-die allowable power determination unit 106 sets the per-die allowable power to half the VRM allowable power (step S54).

[0143] On the other hand, if the modified per-die required power is equal to or less than half of the VRM allowable power (step S53: No), the per-die allowable power determiner 106 performs the following process: That is, the per-die allowable power determiner 106 determines whether the modified VRM required power is greater than the value obtained by subtracting the other modified per-die required power from the VRM allowable power (step S55).

[0144] If the modified VRM required power is greater than the value obtained by subtracting the other modified per-die required power from the VRM allowed power (step S55: Yes), the per-die allowable power determination unit 106 executes the following process. That is, the per-die allowable power determination unit 106 determines the value obtained by subtracting the other modified per-die required power from the VRM allowed power as the per-die allowable power (step S56). Here, the other modified per-die required power is the modified per-die required power of the CPU core die D00 and D01, or the CPU core die D10 and D11, that is not selected and that is connected to the selected voltage regulator V0 or V1.

[0145] On the other hand, if the modified VRM required power is equal to or less than the value obtained by subtracting the other modified per-die required power from the VRM allowable power (step S55: No), the per-die allowable power determination unit 106 sets the modified per-die required power as the per-die allowable power (step S57).Furthermore, if the modified per-die required power is equal to or less than half the per-VRM allowable power (step S52: No), the per-die allowable power determination unit 106 also sets the modified per-die required power as the per-die allowable power (step S57).

[0146] Thereafter, the die-by-die allowable power determination unit 106 determines whether or not the die-by-die allowable power has been determined for all of the CPU core dies D00 and D01, or the CPU core die D10 or D11, connected to the selected voltage regulator V0 or V1 (step S58). If the die-by-die allowable power determination remains to be determined (step S58: No), the die-by-die allowable power determination unit 106 returns to step S51.

[0147] When the die-by-die allowable power has been determined for all of the CPU core dies D00 and D01, or the CPU core die D10 or D11, connected to the selected voltage regulator V0 or V1 (step S58: Yes), the die-by-die allowable power determination unit 106 performs the following process: That is, the die-by-die allowable power determination unit 106 determines whether all of the die-by-die allowable power has been determined for both the voltage regulators V0 and V1 (step S59).

[0148] If the die-by-die allowable power determination unit 106 has not yet determined the die-by-die allowable power for either the voltage regulator V0 or V1 (step S59: No), the die-by-die allowable power determination unit 106 returns to step S50. On the other hand, if all the die-by-die allowable powers have been determined for both the voltage regulators V0 and V1 (step S59: Yes), the die-by-die allowable power determination unit 106 ends the process of determining the die-by-die allowable power.

[0149] Fig. 12 is a diagram showing an example of a circuit for performing strict equal allocation. For example, when allocating power strictly equally to each of the CPU core dies D00, D01, D10, and D11, a circuit such as that shown in Fig. 12 is used. In this case, for example, a first circuit 501, a second circuit 502, a third circuit 503, and a fourth circuit 504 are provided.

[0150] The first circuit 501 has a sorting circuit 511. The sorting circuit 511 is a circuit that sorts the die-by-die required power in ascending order, and the circuit size increases with the number of CPU core dies. In addition, the circuits 521 and 522 included in the second circuit 502 and the third circuit 503 have the same circuit configuration. In addition, the selection circuit in the third circuit 503 is a circuit that selects the smaller of two input values.

[0151] 13 is a flowchart of a process for determining the die-by-die allowable power when performing strict equal allocation. For example, the first circuit 501 receives the die-by-die required power from each of the CPU core dies D00, D01, D10, and D11 (step S61).

[0152] Next, the first circuit 501 uses the sorting circuit 511 to generate an intermediate signal using a table from the comparison results of each die-by-die request signal, and generates an ascending die-by-die request power using the intermediate signal. Thereafter, the first circuit 501 compares the first smallest ascending die-by-die request power with ¼ of the package-by-package power limit to correct the first smallest ascending die-by-die request power. Next, the first circuit 501 compares the second smallest ascending die-by-die request power with ⅓ of the package-by-package power limit minus the corrected first smallest ascending die-by-die request power to correct the second smallest ascending die-by-die request power. Next, the first circuit 501 compares the third smallest ascending die-by-die request power with ½ of the package-by-package power limit minus the corrected first and second smallest ascending die-by-die request power to correct the third smallest ascending die-by-die request power. Next, the first circuit 501 compares the fourth smallest ascending die required power with a value obtained by subtracting the corrected first to third smallest ascending die required power from the package power limit, and corrects the fourth smallest ascending die required power. In this way, the first circuit 501 corrects each die required power so as to satisfy the package power limit (step S62).

[0153] The second circuit 502 calculates each VRM required power from the die required power for each CPU core die D00, D01, D10, and D11. Then, the second circuit 502 corrects the die required power for each of the voltage regulators V0 and V1 using the VRM power limit and each VRM required power so as to satisfy the VRM power limit (step S63).

[0154] The third circuit 503 calculates the excess of each VRM per-die power over the VRM per-die power limit. If the power of either the voltage regulator V0 or V1 is reduced by correcting the per-die required power, the third circuit 503 corrects the per-die required power of either the voltage regulator V0 or V1 from the side with a margin in the VRM per-die power limit (step S64).

[0155] The fourth circuit 504 corrects the required power per die so as to satisfy the per-die power limit, and sets the corrected value as the per-die allowable power (step S65).

[0156] Thereafter, the fourth circuit 504 transmits the die-by-die allowable power for each CPU core die D00, D01, D10, or D11 to each of the CPU core die D00, D01, D10, or D11 (step S66).

[0157] Here, the size of the first circuit 501 increases in proportion to the number of CPU core dies. The first circuit 501 includes a divider that divides by three. While division by two or division by four is performed by a one-bit or two-bit right shift, division by three requires a relatively large circuit. Therefore, the circuit size of the first circuit 501 increases. Since the circuit size of the first circuit 501 increases, strictly equalizing power allocation increases the circuit size and complexity. In contrast, the allowable power adjustment circuit 100 according to this embodiment, as shown in FIG. 3 , does not use a sorting circuit or a divider that divides by three, thereby reducing the circuit size.

[0158] As described above, the allowable power adjustment circuit according to this embodiment sets the allowable power to the smaller of the power limit and the required power for the package-based allowable power, the allowable power for each die group connected to the voltage regulator, and the allowable power for each die. By allocating the allowable power roughly equally rather than strictly equally, it is possible to reduce the circuit size and prevent an increase in circuit size and complexity when the number of CPU core dies is increased. [Example]

[0159] 14 is a hardware configuration diagram according to Example 2. The LSI package 10 according to this example is equipped with multiple CPU core dies including CPU core dies 601 and 602. Here, when the multiple CPU core dies equipped in the LSI package 10 are not distinguished from one another, they are referred to as CPU core dies 600.

[0160] Furthermore, an L1 die group 603 includes CPU core dies 601 and 602. The L1 die group 603 is a die group in the hierarchical level above the CPU core dies 601 and 602. Similarly to the L1 die group 603, an L1 die group 604 includes two CPU core dies 600.

[0161] The L2 die group 605 includes the L1 die groups 603 and 604. That is, the L2 die group 605 includes four CPU core dies 600. The L2 die group 606 has a structure similar to that of the L2 die group 605 and also includes four CPU core dies 600.

[0162] Similarly, an L2 die group 605, which is one layer below, includes the L1 die groups 603 and 604. That is, the L2 die group 605 includes four CPU core dies 600. The L2 die group 605 is a die group one layer above the L1 die groups 603 and 604. Furthermore, an L2 die group 606 has a structure similar to that of the L2 die group 605 and includes four CPU core dies 600.

[0163] As described above, the Li die group is a die group at a level one level above the L(i-1) die group, which includes two L(i-1) die groups. The Li die group includes 2^i CPU core dies 600, where 2^i represents 2 to the i-th power. The LSI package 10 has the largest die group, the Ln die group 609, which includes the L(n-1) die groups 607 and 608. The Ln die group 609 includes 2^n CPU core dies 600.

[0164] Each of the 2^i CPU core dies 600 is connected to the allowable power adjustment circuit 100. The 2^i CPU core dies 600 are driven by power supplied from a single voltage regulator (not shown). Hereinafter, the layer of the CPU core die 600 will be referred to as the L0 layer, and the layer of the Li die group will be referred to as the Li layer.

[0165] That is, the multiple CPU core dies 600 form groups having a hierarchical structure in which each CPU core die 600 is the group at the lowest level and multiple groups at the next lower level are included.

[0166] The allowed power adjustment circuit 100 receives from the OS / Firmware 2 the Li tier power limit, which is a power limit for each die group in each die group of the L0 to Ln tiers. The allowed power adjustment circuit 100 receives the die-by-die required power for each of the 2^i CPU core dies 600. The allowed power adjustment circuit 100 then determines the die-by-die allowed power for each of the 2^i CPU core dies 600 using the die-by-die required power, the die-by-die power limit, and the Li tier-by-Li tier power limit. Here, the die-by-die required power is the L0 tier required power. The die-by-die power limit is the L0 tier power limit. The die-by-die allowed power is the L0 tier allowed power.

[0167] 15 is a flowchart of the allowable power adjustment process by the allowable power adjustment circuit according to the second embodiment. The allowable power adjustment process by the allowable power adjustment circuit 100 according to the second embodiment will be described below with reference to FIG. The allowable power adjustment circuit 100 according to this embodiment is also shown in the block diagram of FIG.

[0168] The package-based allowable power determination unit 102 receives the die-based required power of each of the 2̂i CPU core dies 600, in other words, the L0 hierarchical required power (step S101).

[0169] Next, the package-unit allowable power determining unit 102 determines the Ln tier required power so as to satisfy the L0 tier required power and the Ln tier power limit (step S102).

[0170] Next, the package-unit allowable power determination unit 102 sets the determined Ln tier required power as the Ln tier allowable power (step S103). Here, the Ln die group 609 includes all the CPU core dies 600 included in the LSI package 10, and the Ln tier allowable power matches the package allowable power.

[0171] The post-modification die-unit required power determiner 104 sets i=n-1 (step S104).

[0172] Next, the post-modification die-by-die required power determiner 104 determines the post-modification Li tier required power so as to satisfy the L0 tier required power and the Li tier power limit (step S105).

[0173] Next, the post-modification die-unit required power determiner 104 determines the Li tier allowable power so as to satisfy the post-modification Li tier required power and the L(i+1) tier allowable power (step S106).

[0174] Next, the modified die-unit required power determiner 104 determines whether i=1 (step S107). If i=1 is not true (step S107: No), the modified die-unit required power determiner 104 decrements i by 1 (step S108). Thereafter, the modified die-unit required power determiner 104 returns to step S105.

[0175] On the other hand, if i=n-1 (step S107: Yes), the modified die-by-die required power determiner 104 determines the modified L0 tier required power so as to satisfy the L0 tier required power and the L0 tier power limit (step S109).

[0176] Next, the die-by-die allowable power determination unit 106 determines the L0 tier allowable power so as to satisfy the L0 tier required power and the L1 tier allowable power (step S110).

[0177] Thereafter, the die-by-die allowable power determination unit 106 transmits the L0 tier allowable power to each CPU core die 600 (step S111).

[0178] 16 is a flowchart of the process of determining the modified Ln tier required power. Each process performed in the flow of FIG. 16 corresponds to an example of the process performed in step S102 in FIG.

[0179] The package-unit allowable power determination unit 102 calculates the Ln tier required power by adding up the die-unit required power of each of the 2̂n CPU core dies 600 (step S121).

[0180] Next, the package-unit allowable power determining unit 102 determines whether the Ln tier required power is greater than the Ln tier power limit (step S122).

[0181] If the Ln tier required power is greater than the Ln tier power limit (step S122: Yes), the package-unit allowable power determination unit 102 sets the Ln tier power limit as the modified Ln tier required power (step S123).

[0182] On the other hand, if the Ln tier required power is equal to or less than the Ln tier power limit (step S122: No), the package-unit allowable power determiner 102 sets the Ln tier required power as the modified Ln tier required power (step S124).

[0183] Figure 17 is a flowchart of the process for determining the modified Li tier required power. Each process performed in the flow of Figure 17 is an example of the process performed in step S105 in Figure 15. Here, since there are 2^(n+1-i) Li die groups, the process described below is performed for each of the 2^(n+1-i) Li die groups.

[0184] The post-modification die-by-die required power determiner 104 calculates the Li tier required power by adding up the die-by-die required power of each of the CPU core dies 600 included in the Li die group (step S131).

[0185] Next, the post-modification die-unit required power determiner 104 determines whether the Li tier required power is greater than the Li tier power limit (step S132).

[0186] If the Li tier required power is greater than the Li tier power limit (step S132: Yes), the modified die-by-die required power determiner 104 sets the Li tier power limit as the modified Li tier required power (step S133).

[0187] On the other hand, if the Li tier required power is equal to or less than the Li tier power limit (step S132: No), the modified die-by-die required power determiner 104 sets the Li tier required power as the modified Li tier required power (step S134).

[0188] Fig. 18 is a flowchart of the process for determining the Li tier allowable power. Each process performed in the flow of Fig. 18 corresponds to an example of the process performed in step S106 in Fig. 15. Here, the process described below is also performed for each of the 2^(ni) Li die groups.

[0189] The post-modification die-unit required power determiner 104 calculates whether the post-modification Li tier required power is greater than half the L(i+1) tier allowable power (step S141).

[0190] If the revised Li tier required power is greater than half of the L(i+1) tier allowable power (step S141: Yes), the revised die-by-die required power determiner 104 executes the following process. That is, the revised die-by-die required power determiner 104 determines whether the other revised Li tier required power is greater than half of the L(i+1) tier allowable power (step S142). The other revised Li tier required power is the revised Li tier required power for another Li die group connected to the L(i+1) die group to which the Li die group for which the Li tier allowable power is being determined is connected.

[0191] If the other modified Li tier required power is greater than half the L(i+1) tier allowable power (step S142: Yes), the modified die-by-die required power determination unit 104 sets half of the L(i+1) tier allowable power as the Li tier allowable power (step S143).

[0192] On the other hand, if the other modified Li tier required power is less than half the L(i+1) tier allowable power (step S142: No), the modified die-by-die required power determiner 104 executes the following process: That is, the modified die-by-die required power determiner 104 determines whether the modified Li tier required power is greater than the value obtained by subtracting the other modified Li tier required power from the L(i+1) tier allowable power (step S144).

[0193] If the modified Li tier required power is greater than the value obtained by subtracting the other modified Li tier required power from the L(i+1) tier allowable power (step S144: Yes), the modified die-by-die required power determiner 104 executes the following process: The modified die-by-die required power determiner 104 determines the value obtained by subtracting the other modified Li tier required power from the L(i+1) tier allowable power as the Li tier allowable power (step S145).

[0194] On the other hand, if the revised Li tier required power is equal to or less than the value obtained by subtracting the other revised Li tier required power from the L(i+1) tier allowable power (step S144: No), the revised die-by-die required power determiner 104 executes the following process. Also, if the revised Li tier required power is equal to or less than half the L(i+1) tier allowable power (step S141: No), the revised die-by-die required power determiner 104 executes the following process. That is, the revised Li tier allowable power determiner 104 sets the revised Li tier allowable power as the Li tier allowable power (step S146).

[0195] Fig. 19 is a flowchart of the process for determining the modified L0 hierarchical required power. Each process performed in the flow of Fig. 19 is an example of the process performed in step S109 in Fig. 15. Here, since there are 2^n L0 die groups, the process described below is performed for each of the 2^n L0 die groups.

[0196] The post-modification die-unit required power determiner 104 determines whether the L0 tier required power is greater than the L0 tier power limit (step S151).

[0197] If the L0 tier required power is greater than the L0 tier power limit (step S151: Yes), the post-modification die-per-die required power determiner 104 sets the L0 tier power limit as the post-modification L0 tier required power (step S152).

[0198] On the other hand, if the L0 tier required power is equal to or less than the L0 tier power limit (step S151: No), the post-modification die-per-die required power determiner 104 sets the L0 tier required power as the post-modification L0 tier required power (step S153).

[0199] Fig. 20 is a flowchart of the process of determining the L0 tier allowable power. Each process performed in the flow of Fig. 20 corresponds to an example of the process performed in step S110 in Fig. 15. Here, the process described in the following flow is also performed for each of the 2^n L0 die groups.

[0200] The die-by-die allowable power determination unit 106 calculates whether the modified L0 tier required power is greater than half the L1 tier allowable power (step S161).

[0201] If the modified L0 tier required power is greater than half the L1 tier allowable power (step S161: Yes), the die-by-die allowable power determination unit 106 determines whether the other modified L0 tier required power is greater than half the L1 tier allowable power (step S162). The other modified L0 tier required power is the modified L0 tier required power for another CPU core die 600 connected to the L1 die group 603 to which the CPU core die 600 for which the L0 tier allowable power is being determined is connected.

[0202] If the other corrected L0 tier required power is greater than half the L1 tier allowable power (step S162: Yes), the die-by-die allowable power determination unit 106 sets half the L1 tier allowable power as the L0 tier allowable power (step S163).

[0203] On the other hand, if the other modified L0 tier required power is equal to or less than half of the L1 tier allowable power (step S162: No), the die-by-die allowable power determination unit 106 executes the following process: That is, the die-by-die allowable power determination unit 106 determines whether the modified L0 tier required power is greater than the value obtained by subtracting the other modified L0 tier required power from the L1 tier allowable power (step S164).

[0204] If the modified L0 tier required power is greater than the value obtained by subtracting the modified L0 tier required power of the other from the L1 tier allowable power (step S164: Yes), the die-by-die allowable power determination unit 106 executes the following process: That is, the die-by-die allowable power determination unit 106 determines the value obtained by subtracting the modified L0 tier required power of the other from the L1 tier allowable power as the L0 tier allowable power (step S165).

[0205] On the other hand, if the revised L0 tier required power is equal to or less than the value obtained by subtracting the other revised L0 tier required power from the L1 tier allowable power (step S164: No), the die-by-die allowable power determination unit 106 executes the following process. Also, if the revised L0 tier required power is equal to or less than half the L1 tier allowable power (step S161: No), the die-by-die allowable power determination unit 106 executes the following process. That is, the die-by-die allowable power determination unit 106 sets the revised L0 tier required power as the L0 tier allowable power (step S166).

[0206] If the predetermined layer is the Li layer, the layer immediately above the predetermined layer is the L(i+1) layer, in which case the die-by-die allowable power determination unit 106 performs the following process: That is, the die-by-die allowable power determination unit 106 determines the allowable power for each Li die group based on the smaller of the required power and the power limit for each Li die group in the Li layer and the allowable power for the L(i+1) die group in the L(i+1) layer.

[0207] Here, in this embodiment, the case where there is one multi-tier die group connected to one voltage regulator has been described, but when there are multiple multi-tier die groups connected to multiple voltage regulators, respectively, the function is a combination of Embodiments 1 and 2. In this case, the allowable power adjustment circuit 100 determines the VRM-based allowable voltage for each voltage regulator as in Embodiment 1, and then determines the die-based allowable voltage for each CPU core die 600 included in the die group connected to each voltage regulator as in Embodiment 2.

[0208] As described above, the power adjustment circuit according to this embodiment has a plurality of hierarchical die groups, and determines the allowable power for each die group in turn to determine the allowable power per die for each CPU core die. In this way, even when the die groups have a hierarchical structure, the allowable power can be easily determined, making it possible to reduce the circuit size and prevent an increase in circuit size and circuit complexity when the number of CPU core dies is increased. [Explanation of symbols]

[0209] 1 server 2 OS / Firmware 10 LSI Package 11 Power Control Die 12 Voltage Regulator 20 Power supply device 100 Allowable power adjustment circuit 101 Information Receiving Unit 102 Package unit allowable power determination unit 103 Corrected VRM unit required power determination section 104 Corrected die-by-die power requirement determination section 105 VRM unit allowable power determination section 106 Die-by-Die Allowable Power Determination Unit 107 Transmitter 200 Power control CPU 300, 301, 310, 311 Power control circuit 400, 401, 410, 411 CPU cores D00, D01, D10, D11 CPU core dies V0, V1 voltage regulator

Claims

1. a plurality of computing units; a first allowable power determination unit that determines a smaller value of a first required power required by all of the plurality of arithmetic units or a first power limit for all of the plurality of arithmetic units as a first allowable power that is allowed for all of the plurality of arithmetic units; a second allowable power determination unit that determines a second allowable power for each of the arithmetic units based on a second required power or a second power limit, whichever is smaller, and the first allowable power; a transmitter that transmits the second allowable power to the computing device to receive the second allowable power; A processor comprising:

2. a third allowable power determination unit for determining, for each of a plurality of voltage regulators corresponding to each of the groups that supply power to the plurality of computing units divided into a plurality of groups, a third allowable power for each of the groups based on a third required power required by all of the computing units to be supplied with power or a third power limit value for all of the computing units to be supplied with power, whichever is smaller, and the first allowable power; The second allowable power determination unit determines the second allowable power for each of the arithmetic units based on the second required power for each of the arithmetic units or the second power limit value, whichever is smaller, and the third allowable power. The processor of claim 1 .

3. a modified third required power determiner that calculates the third required power by adding up the second required power for each of the computing units that supplies power to the voltage regulator, and sets the smaller of the third required power and the third power limit as the modified third required power; a first predetermined number of the voltage regulators; The third allowable power determiner determines the third allowable power for each voltage regulator based on the corrected third required power and a value obtained by dividing the first allowable power by the first predetermined number. The processor of claim 2 .

4. a modified second required power determiner for each of the computing units that determines a smaller value of the second required power or the second power limit as a modified second required power; the voltage regulator supplies power to a second predetermined number of the computing units; The second allowable power determination unit determines the second allowable power for each of the computing units based on the corrected second required power and a value obtained by dividing the third allowable power of the voltage regulator that supplies the power by the second predetermined number.

4. The processor of claim 3.

5. 2 . The processor according to claim 1 , wherein the first allowable power determination unit calculates the first required power by adding up the second required power of each of the plurality of arithmetic units.

6. The plurality of arithmetic units are formed into groups having a hierarchical structure in which each of the arithmetic units is a group in the lowest hierarchical layer and includes a plurality of groups in a layer one level lower, The second allowable power determination unit determines the allowable power for each group in a predetermined hierarchical layer based on the smaller of the required power for each group in the predetermined hierarchical layer and the power limit, and the allowable power for a group in the hierarchical layer one layer above the predetermined hierarchical layer. The processor of claim 1 .

7. a processor having a plurality of arithmetic units and a power conditioning circuit; one or more voltage regulators, each corresponding to one or more groups, for supplying power to a plurality of computing units divided into one or more groups; an information processing apparatus having a power supply device that supplies power to the voltage regulator, The power conditioning circuit a first allowable power determination unit that determines a smaller value of a first required power required by all of the plurality of arithmetic units or a first power limit for all of the plurality of arithmetic units as a first allowable power that is allowed for all of the plurality of arithmetic units; a second allowable power determination unit that determines a second allowable power for each of the arithmetic units based on a second required power or a second power limit, whichever is smaller, and the first allowable power; a transmitter that transmits the second allowable power to the computing device and causes the computing device to receive the second allowable power from the voltage regulator; An information processing device comprising:

8. A method for controlling a processor including a plurality of arithmetic units, comprising: the processor, determining a first required power required by all of the plurality of arithmetic units or a first power limit for all of the plurality of arithmetic units, whichever is smaller, as a first allowable power to be allowed for all of the plurality of arithmetic units; determining a second allowable power for each of the arithmetic units based on a second required power for each of the arithmetic units or a second power limit for each of the arithmetic units, whichever is smaller, and the first allowable power; Transmitting the second allowable power to the computing unit to receive the second allowable power. A method for controlling a processor, characterized by causing the processor to execute a process.

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