Semiconductor device

Abstract

To improve the breakdown voltage of a semiconductor device.SOLUTION: The semiconductor device 10 includes a semiconductor layer 12, a plurality of cell trenches 14 extending in the Y-axis direction and spaced apart from each other in the X-axis direction, a cell insulating layer 30 and a cell electrode 56 provided in the cell trench 14, a first peripheral trench 70 provided in a frame shape so as to surround the plurality of cell trenches 14, and a peripheral insulating layer 112 and a peripheral electrode 68 provided in the first peripheral trench 70. The first outer peripheral extension 102 includes an inner side surface 104 facing the cell end portion 32 in the Y-axis direction and a protrusion 106 protruding inward from the inner side surface 104 in the Y-axis direction. The plurality of cell trenches 14 include a first cell trench side 14P and a second cell trench side 14Q that are adjacent to each other in the X-axis direction. The protrusion 106 is located on the inner surface 104 between the first cell trench side 14P and the second cell trench side 14Q. The peripheral electrodes 68 have protruding electrodes 110A.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having a trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-067820

[0004] [overview] There is a demand for improved breakdown voltage of semiconductor devices.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer including a cell region and a peripheral region surrounding the cell region; a plurality of cell trenches provided in the cell region, extending in a first direction when viewed in a thickness direction of the semiconductor layer and spaced apart in a second direction perpendicular to the first direction in a plan view; a cell insulating layer provided in the plurality of cell trenches; a cell electrode embedded in the cell insulating layer; a first peripheral trench provided in a frame shape to surround the plurality of cell trenches in the peripheral region; a peripheral insulating layer provided in the first peripheral trench; and a peripheral electrode provided in the first peripheral trench. Each of the cell trenches includes a cell end which is an end in the first direction, the first peripheral trench includes a first peripheral extension portion extending in the second direction, the first peripheral extension portion includes an inner surface facing the cell ends of the plurality of cell trenches at a distance in the first direction, and a protrusion portion protruding inward from the inner surface, the plurality of cell trenches include a first cell trench and a second cell trench adjacent to each other in the second direction, the protrusion portion is arranged in a portion between the first cell trench and the second cell trench on the inner surface, and the peripheral electrode has a protrusion electrode provided within the protrusion portion. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is an exemplary schematic plan view of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing the arrangement of cell trenches and peripheral trenches provided in the semiconductor layer of the semiconductor device shown in FIG. [Figure 3] FIG. 3 is a schematic plan view showing an enlarged portion of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line F4-F4 of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view taken along line F5-F5 of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view taken along line F6-F6 of the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view taken along line F7-F7 of the semiconductor device shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view taken along line F8-F8 of the semiconductor device shown in FIG. [Figure 9] FIG. 9 is a schematic plan view showing an enlarged portion of the semiconductor device 10 shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view taken along line F10-F10 of the semiconductor device shown in FIG. [Figure 11] FIG. 11 is a schematic plan view of a part of the cell region, the boundary region, and the outer periphery region in a semiconductor device of the comparative example. [Figure 12] FIG. 12 is a schematic plan view of a part of the cell region, the boundary region, and the outer periphery region in the semiconductor device of the first embodiment. [Figure 13] FIG. 13 is a schematic plan view showing an enlarged portion of the semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view taken along line F14-F14 of the semiconductor device shown in FIG. [Figure 15]FIG. 15 is a schematic plan view showing an enlarged portion of the semiconductor device according to the third embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view taken along line F16-F16 of the semiconductor device shown in FIG. [Figure 17] FIG. 17 is an illustrative schematic plan view of a semiconductor device according to a modified example. [Figure 18] FIG. 18 is a schematic plan view showing an exemplary layout pattern of a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] First Embodiment [Planar structure of semiconductor device] The planar structure of a semiconductor device 10 according to a first embodiment will be described with reference to Figures 1 and 2. Figure 1 is a schematic plan view of an exemplary semiconductor device 10 according to the first embodiment. Figure 2 is a schematic plan view of the semiconductor device 10 of Figure 1, omitting a source wiring 22, a gate wiring 24, and a portion of an insulating layer 16, which will be described later.

[0010] 1 and 2, the semiconductor device 10 may be, for example, a metal-insulator-semiconductor field-effect transistor (MISFET) having a trench gate structure. The semiconductor device 10 may include a semiconductor layer 12, a plurality of cell trenches 14 provided in the semiconductor layer 12, and an insulating layer 16 provided on the semiconductor layer 12. The Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 is a direction perpendicular to the plane of the semiconductor layer 12. Note that the term "plan view" used in this disclosure refers to viewing the semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise.

[0011] 1, the semiconductor layer 12 is covered with an insulating layer 16, and therefore the reference numeral 12 indicates the outer edge of the semiconductor layer 12. The area defined by the outer edge of the semiconductor layer 12 shown in FIG. 1 may correspond to one chip (die). The insulating layer 16 may include at least one of a silicon oxide (SiO2) layer and a silicon nitride (SiN) layer.

[0012] 2, the semiconductor layer 12 includes a cell region 15 and a peripheral region 17 surrounding the cell region 15. The cell region 15 may be rectangular in plan view. The peripheral region 17 may be annular in plan view. Details of the semiconductor layer 12 will be described later with reference to FIG. 3.

[0013] A plurality of cell trenches 14 are provided in a cell region 15 . The multiple cell trenches 14 extend in the Y-axis direction in a plan view seen from the Z-axis direction, which is the thickness direction, and are spaced apart in the X-axis direction. In the present disclosure, the Y-axis direction may be referred to as the first direction, and the X-axis direction may be referred to as the second direction. That is, the second direction is perpendicular to the first direction in a plan view. In the example of FIG. 1, the multiple cell trenches 14 may have the same length. The multiple cell trenches 14 are arranged at a first pitch P1 (see FIG. 3) in the X-axis direction in a plan view.

[0014] The semiconductor device 10 may further include one or more periphery trenches 18 provided in the semiconductor layer 12. The one or more periphery trenches 18 are arranged to surround the cell region 15 in a planar view. More specifically, the one or more periphery trenches 18 may form a loop that surrounds the cell region 15 in a planar view. The one or more periphery trenches 18 may be arranged to surround a plurality of cell trenches 14. The one or more periphery trenches 18 are provided in the periphery region 17. Note that the number of periphery trenches 18 is not limited to the number of periphery trenches 18 shown in FIG. 1 , for example, and can be changed as desired.

[0015] 1, the semiconductor device 10 may further include a gate wiring 24 provided on the insulating layer 16, and a source wiring 22 provided on the insulating layer 16 and spaced apart from the gate wiring 24. The gate wiring 24 and the source wiring 22 may be made of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0016] The gate wiring 24 may include a gate pad 25 arranged at one corner of the semiconductor layer 12 in a plan view, and a gate finger 26. The gate finger 26 may extend from the gate pad 25 in the X-axis direction and overlap some of the multiple cell trenches 14 in a plan view. The gate pad 25 and the gate finger 26 may be integrally formed. The source wiring 22 may include an inner segment 23 overlapping some of the multiple cell trenches 14 and a peripheral segment 28 overlapping some of the multiple peripheral trenches 18. The inner segment 23 and the peripheral segment 28 may be connected to the gate finger 26 at a distance from each other at an end of the semiconductor device 10 opposite the gate pad 25 in the X-axis direction. The inner segment 23 and the peripheral segment 28 may be integrally formed.

[0017] [Cross-sectional structure of the trench gate of the cell trench] The cross-sectional structure of the cell trench 14 will be described with reference to FIGS. Fig. 3 is a schematic plan view enlarging a portion of the semiconductor device 10 shown in Fig. 2. Fig. 4 is a schematic cross-sectional view of the semiconductor device 10 taken along line F4-F4 in Fig. 3. Fig. 4 shows four cell trenches 14 included in the cell region 15 (see Fig. 2).

[0018] As shown in FIG. 4 , the semiconductor layer 12 may include a top surface 12A and a bottom surface 12B opposite the top surface 12A. The Z-axis direction may be perpendicular to the top surface 12A and the bottom surface 12B of the semiconductor layer 12. The semiconductor layer 12 may include a semiconductor substrate 40 and an epitaxial layer 42 provided on the semiconductor substrate 40. The semiconductor substrate 40 may include the bottom surface 12B of the semiconductor layer 12. The epitaxial layer 42 may include the top surface 12A of the semiconductor layer 12. In this embodiment, the semiconductor substrate 40 may be a Si substrate. Furthermore, the epitaxial layer 42 may be a Si epitaxial layer. The semiconductor substrate 40 may correspond to the drain region of the MISFET.

[0019] In the cell region 15 (see Figure 2) where the cell trench 14 is arranged, the epitaxial layer 42 may include a drift region 44 provided on the semiconductor substrate 40 (drain region), a body region 46 provided on the drift region 44, and a source region 20 provided on the body region 46.

[0020] The drain region provided by the semiconductor substrate 40 may be an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 40 is 1×10 18 cm -3 More than 1×10 20 cm - The thickness of the semiconductor substrate 40 may be equal to or less than 3. The semiconductor substrate 40 may have a thickness of equal to or greater than 50 μm and equal to or less than 450 μm.

[0021] The drift region 44 may be an n-type region containing n-type impurities at a concentration lower than that of the semiconductor substrate 40 (drain region). The n-type impurity concentration of the drift region 44 is 1×10 15 cm-3 More than 1×10 18 cm -3 or less. The drift region 44 may have a thickness of 1 μm or more and 25 μm or less. In a MISFET having a trench gate structure, the on-resistance includes the resistance of the semiconductor substrate 40 and the resistance of the drift region 44. That is, the resistance of the drift region 44 constitutes part of the on-resistance. Therefore, increasing the n-type impurity concentration of the drift region 44 decreases the resistance of the drift region 44, thereby decreasing the on-resistance of the MISFET. On the other hand, decreasing the n-type impurity concentration of the drift region 44 increases the resistance of the drift region 44, thereby increasing the on-resistance of the MISFET.

[0022] The body region 46 may be a p-type region containing p-type impurities. The p-type impurity concentration of the body region 46 is 1×10 16 cm -3 More than 1×10 18 cm -3 The body region 46 may have a thickness of not less than 0.2 μm and not more than 1.0 μm.

[0023] The source region 20 may be an n-type region containing n-type impurities at a higher concentration than the drift region 44. The n-type impurity concentration of the source region 20 is 1×10 19 cm -3 More than 1×10 21 cm -3 The source region 20 may have a thickness of 0.1 μm or more and 1 μm or less.

[0024] In this disclosure, n-type is also referred to as the first conductivity type, and p-type is also referred to as the second conductivity type. The n-type impurity may be, for example, phosphorus (P) or arsenic (As). The p-type impurity may be, for example, boron (B) or aluminum (Al).

[0025] The semiconductor device 10 may further include a drain wiring 50 provided on the bottom surface 12B of the semiconductor layer 12. The drain wiring 50 is electrically connected to the semiconductor substrate 40 (drain region). The drain wiring 50 may be made of at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy.

[0026] The cell trench 14 may have an opening in the upper surface 12A of the semiconductor layer 12 and may have a depth in the Z-axis direction. The cell trench 14 may have sidewalls 14A and a bottom wall 14B. The cell trench 14 may extend through the source region 20 and the body region 46 of the epitaxial layer 42 to reach the drift region 44. Therefore, the bottom wall 14B of the cell trench 14 may be adjacent to the drift region 44. The cell trench 14 may have a depth of 1 μm or more and 10 μm or less. The depth of the cell trench 14 may correspond to the distance in the Z-axis direction from the upper surface 12A of the semiconductor layer 12 to the bottom wall 14B of the cell trench 14. Hereinafter, the Z-axis direction may be referred to as the "depth direction of the cell trench 14" or the "trench depth direction."

[0027] The sidewall 14A of the cell trench 14 may extend in the Z-axis direction (a direction perpendicular to the upper surface 12A of the semiconductor layer 12) or may be inclined with respect to the Z-axis direction. In one example, the sidewall 14A may be inclined with respect to the Z-axis direction so that the width of the cell trench 14 decreases toward the bottom wall 14B. Furthermore, the bottom wall 14B of the cell trench 14 does not necessarily have to be flat, and may be curved in part or entirely, for example.

[0028] The semiconductor device 10 may further include a plurality of cell electrodes 56 and a cell insulating layer 30. In one example, the plurality of cell electrodes 56 may be made of conductive polysilicon. In another example, the plurality of cell electrodes 56 may be made of any other metallic material. The cell insulating layer 30 may be provided within the plurality of cell trenches 14. The cell electrodes 56 may be embedded within the cell insulating layer 30.

[0029] The multiple cell electrodes 56 may include multiple gate electrodes 58. The gate electrodes 58 may be embedded in the cell trenches 14 via the cell insulating layer 30. The multiple gate electrodes 58 are electrically connected to the gate wiring 24 (see FIG. 1).

[0030] The plurality of cell electrodes 56 may further include a plurality of first field plate electrodes 60. The first field plate electrodes 60 may be embedded in the cell trench 14 with the cell insulating layer 30 interposed therebetween and spaced apart from the gate electrode 58.

[0031] The gate electrode 58 may be configured to have a gate voltage applied thereto, and the first field plate electrode 60 may be configured to have a source voltage or a voltage different from the source voltage applied thereto.

[0032] 4, two cell electrodes 56, namely, the gate electrode 58 and the first field plate electrode 60, may be embedded in the cell trench 14. In another example, only the gate electrode 58 may be embedded in the cell trench 14.

[0033] The gate electrode 58 may include an upper surface 58A covered by the insulating layer 16 and a bottom surface 58B opposite the upper surface 58A. The first field plate electrode 60 may be disposed below the gate electrode 58 in the cell trench 14. More specifically, the first field plate electrode 60 may be disposed between the bottom surface 58B of the gate electrode 58 and the bottom wall 14B of the cell trench 14. At least a portion of the bottom surface 58B of the gate electrode 58 may face the first field plate electrode 60 across the cell insulating layer 30. The gate electrode 58 may further include a side surface 58C facing the sidewall 14A of the cell trench 14.

[0034] An upper surface 58A of the gate electrode 58 may be located lower than an upper surface 12A of the semiconductor layer 12. A bottom surface 58B of the gate electrode 58 may be located near the interface between the drift region 44 and the body region 46 in the Z-axis direction, and preferably lower than the interface. The upper surface 58A and the bottom surface 58B of the gate electrode 58 may be flat or curved.

[0035] The gate electrode 58 and the first field plate electrode 60 may be surrounded by the cell insulating layer 30. The first field plate electrode 60 may have a width smaller than that of the gate electrode 58 when viewed in the X-axis direction. Because the first field plate electrode 60 has a width smaller than that of the gate electrode 58, the thickness of the cell insulating layer 30 surrounding the first field plate electrode 60 is greater than the thickness of the cell insulating layer 30 surrounding the gate electrode 58.

[0036] The cell insulating layer 30 may include a gate insulating portion 66 interposed between the gate electrode 58 and the semiconductor layer 12 and covering the sidewall 14A of the cell trench 14. The gate insulating portion 66 is a portion of the cell insulating layer 30 located between the side surface 58C of the gate electrode 58 and the sidewall 14A of the cell trench 14. The gate electrode 58 faces the semiconductor layer 12 via the gate insulating portion 66. The thickness of the gate insulating portion 66 may or may not be constant. In one example, the thickness of the gate insulating portion 66 at a portion where the side surface 58C of the gate electrode 58 faces the drift region 44 is set to be greater than the thickness of the portion where the side surface 58C faces the source region 20 and the body region 46. This is to reduce the capacitance Cgd between the gate electrode 58 and the drift region 44.

[0037] The cell insulating layer 30 may include a first field insulating layer 30A. The first field insulating layer 30A is a part of the cell insulating layer 30 interposed between the first field plate electrode 60 and the sidewall 14A of the cell trench 14. The first field insulating layer 30A is in contact with both the side surface of the first field plate electrode 60 and the sidewall 14A of the cell trench 14. Therefore, the first field plate electrode 60 may face the sidewall 14A of the cell trench 14 in the X-axis direction of the cell trench 14, while being spaced apart from the sidewall 14A of the cell trench 14 via the first field insulating layer 30A. The first field insulating layer 30A is also interposed between the first field plate electrode 60 and the bottom wall 14B of the cell trench 14. The first field insulating layer 30A is in contact with both the bottom surface of the first field plate electrode 60 and the bottom wall 14B of the cell trench 14. Therefore, the first field plate electrode 60 may be opposed to the bottom wall 14B of the cell trench 14 while being spaced apart from it in the depth direction of the cell trench 14 within the cell trench 14.

[0038] The semiconductor device 10 may further include a plurality of source contacts 62 connected to the source wiring 22. Each source contact 62 may extend parallel to the cell trench 14 in a plan view. In one example, one cell trench 14 may be disposed between two source contacts 62.

[0039] The epitaxial layer 42 may further include a contact region 64. The contact region 64 may be a p-type region containing p-type impurities. The p-type impurity concentration of the contact region 64 is higher than that of the body region 46, and may be 1×10 19 cm -3 More than 1×10 21 cm -3 The source contact 62 extends through the cell insulating layer 30 and the source region 20 to contact the contact region 64. The contact region 64 is electrically connected to the source wiring 22 via the source contact 62. The contact region 64 is also electrically connected to the body region 46. That is, the source region 20 is electrically connected to the body region 46.

[0040] When a predetermined voltage is applied to the gate electrode 58, a channel is induced in the p-type body region 46 adjacent to the gate insulating portion 66. The semiconductor device 10 can control the flow of electrons in the Z-axis direction between the n-type source region 20 and the n-type drift region 44 via this channel. Furthermore, because the first field plate electrode 60 is electrically connected to the source wiring 22, it is possible to alleviate electric field concentration in the drift region 44 between the cell trenches 14. This can improve the breakdown voltage of the semiconductor device 10.

[0041] When the MISFET is turned off by applying, for example, 0 V to the gate electrode 58, the breakdown voltage when a voltage is applied to the drain is called BVDSS (drain-source breakdown voltage when the gate and source are shorted). If the BVDSS is low, there is a risk that drain current will flow even when the MISFET is in the off state. Without the first field plate electrode 60, the potential difference when a voltage is applied to the drain will be concentrated in the depletion layer at the pn boundary between the p-type body region 46 and the n-type drift region 44.

[0042] In particular, when a drain voltage of 60 V or more and 300 V or less is used, the electric field generated in the depletion layer at the pn boundary is strong, which may cause avalanche breakdown at the pn boundary and may make it impossible to ensure the BVDSS of the semiconductor device 10. As a result, it may be impossible to ensure the breakdown voltage of the semiconductor device 10.

[0043] Therefore, the first field plate electrode 60 is used. In one example, when a source potential (0 V) is applied to the first field plate electrode 60 and a drain voltage is applied to the n-type region including the drift region 44, a potential difference is generated between the first field plate electrode 60 and the drift region 44. That is, because 0 V is applied to the first field plate electrode 60 and the maximum drain voltage is applied to the drift region 44, the potential difference is at most equal to the drain voltage. Because the first field insulating layer 30A, which is part of the cell insulating layer 30 embedded in the cell trench 14, is included between the first field plate electrode 60 and the drift region 44, the first field plate electrode 60, the first field insulating layer 30A, and the drift region 44 form an MIS structure. Therefore, an electric field is generated in the first field insulating layer 30A.

[0044] This electric field is generated in a direction that depletes electrons, which are carriers, in the n-type drift region 44 adjacent to the cell trench 14. Here, the spacing between the cell trenches 14 in the X-axis direction is set so that the depletion layers extending from both sidewalls 14A of adjacent cell trenches 14 toward the drift region 44 sandwiched between the adjacent cell trenches 14 are circumscribed within the drift region 44 sandwiched between the adjacent cell trenches 14. At this time, the drift region 44 in the portion sandwiched between the adjacent cell trenches 14 is depleted.

[0045] In this case, the potential difference between the drain and source is divided between the depletion layer at the pn boundary between the p-type body region 46 and the n-type drift region 44, and the depleted region of the drift region 44 between adjacent cell trenches 14.

[0046] This alleviates localized electric field concentration at the pn boundary between the p-type body region 46 and the n-type drift region 44, thereby reducing the electric field strength and improving the BVDSS of the semiconductor device 10. As a result, the breakdown voltage of the semiconductor device 10 can be ensured.

[0047] [Cross-sectional structure of the cell edge of the cell trench] The cross-sectional structure of the cell trench 14 will be described with reference to Figures 3 and 5. As shown in Figure 3, the multiple cell trenches 14 may include cell ends 32, which are ends in the Y-axis direction. Figure 5 is a schematic cross-sectional view of the semiconductor device 10 taken along line F5-F5 in Figure 3. Figure 5 shows four cell trenches 14 included in the cell ends 32.

[0048] As shown in FIG. 5, in the region of the cell end 32 where the cell trench 14 is located, the epitaxial layer 42 may include a drift region 44 formed on the semiconductor substrate 40 (drain region) and a body region 46 formed on the drift region 44.

[0049] The first field plate electrode 60 includes an electrode end 61 provided at the cell end 32. The electrode end 61 is located closer to the outer periphery region 17 than the gate electrode 58 in the Y-axis direction. The electrode end 61 includes a portion that is separated from the gate electrode 58 in the Y-axis direction and faces the gate electrode 58. In other words, an upper end 61A of the electrode end 61 in the depth direction of the cell trench 14 is located higher than a bottom surface 58B of the gate electrode 58. The electrode end 61 is buried in the cell insulating layer 30. Therefore, the dimension of the electrode end 61 in the depth direction of the cell trench 14 is larger than the dimension of the first field plate electrode 60 in the depth direction of the cell trench 14 at a portion closer to the cell region 15 than the electrode end 61 of the first field plate electrode 60.

[0050] The width in the X-axis direction of electrode end 61 of first field plate electrode 60 is equal to the width of the portion of first field plate electrode 60 closer to cell region 15 than electrode end 61. Therefore, electrode end 61 may have a width smaller than gate electrode 58. Since electrode end 61 has a width smaller than gate electrode 58, the thickness of cell insulating layer 30 surrounding electrode end 61 is greater than the thickness of cell insulating layer 30 surrounding gate electrode 58.

[0051] The semiconductor device 10 may further include a plurality of field plate contacts 78 connected to the source wiring 22. The electrode end 61 is electrically connected to the source wiring 22 via the field plate contacts 78. As a result, the first field plate electrode 60 is electrically connected to the source wiring 22.

[0052] The cell insulating layer 30 may include a first electrode end field insulating layer 30B. The first electrode end field insulating layer 30B is a part of the cell insulating layer 30 interposed between the electrode end 61 of the first field plate electrode 60 and the sidewall 14A of the cell trench 14. The first electrode end field insulating layer 30B contacts both the side surface of the electrode end 61 and the sidewall 14A of the cell trench 14. Therefore, the electrode end 61 may face the sidewall 14A of the cell trench 14 in the X-axis direction of the cell trench 14, while being spaced apart from the sidewall 14A of the cell trench 14 via the first electrode end field insulating layer 30B. The first electrode end field insulating layer 30B is interposed between the electrode end 61 and the bottom wall 14B of the cell trench 14. The first electrode end field insulating layer 30B contacts both the bottom surface of the electrode end 61 and the bottom wall 14B of the cell trench 14. Therefore, the electrode end portion 61 may be opposed to the bottom wall 14B of the cell trench 14 while being spaced apart from it in the depth direction of the cell trench 14 within the cell trench 14.

[0053] The electrode end 61 of the first field plate electrode 60 is electrically connected to the source wiring 22, which can alleviate electric field concentration in the drift region 44 between the cell trenches 14. This can improve the breakdown voltage of the semiconductor device 10.

[0054] For example, it is desirable that the first field insulating layer 30A and the first electrode end field insulating layer 30B have the same thickness. The first field insulating layer 30A and the first electrode end field insulating layer 30B are both part of the cell insulating layer 30 and are made of the same material.

[0055] [Cross-sectional structure from the outer trench to the cell edge] The cross-sectional structures of the cell trench 14 and the peripheral trench 18 in the Y-axis direction will be described with reference to Figures 3 and 6. Figure 6 is a schematic cross-sectional view of the semiconductor device 10 taken along line F6-F6 in Figure 3. Figure 6 shows a portion of the cell trench 14 arranged at the cell end 32 of the cell region 15 and two peripheral trenches 18.

[0056] The semiconductor device 10 may further include a border region 19 . The boundary region 19 is a region between the cell region 15 and the outer peripheral region 17 in a planar view. The boundary region 19 may be annular in shape surrounding the cell region 15 in a planar view. The outer peripheral region 17 surrounds both the cell region 15 and the boundary region 19 in a planar view.

[0057] 6 , in the boundary region 19 and the peripheral region 17, the epitaxial layer 42 may include a drift region 44 formed on the semiconductor substrate 40 (drain region) and a body region 46 formed on the drift region 44. In other words, in the boundary region 19 and the peripheral region 17, the epitaxial layer 42 does not include the source region 20.

[0058] The peripheral trench 18 may have an opening in the upper surface 12A of the semiconductor layer 12 and may have a depth in the Z-axis direction. The peripheral trench 18 may have sidewalls 18A and a bottom wall 18B. The peripheral trench 18 may extend through the body region 46 of the epitaxial layer 42 to reach the drift region 44. Thus, the bottom wall 18B of the peripheral trench 18 is adjacent to the drift region 44. The peripheral trench 18 may have a depth of 1 μm or more and 10 μm or less. The depth of the peripheral trench 18 may correspond to the distance in the Z-axis direction from the upper surface 12A of the semiconductor layer 12 to the bottom wall 18B of the peripheral trench 18.

[0059] The sidewall 18A of the periphery trench 18 may extend in the Z-axis direction (a direction perpendicular to the upper surface 12A of the semiconductor layer 12) or may be inclined with respect to the Z-axis direction. In one example, the sidewall 18A may be inclined with respect to the Z-axis direction so that the width of the periphery trench 18 decreases toward the bottom wall 18B. In addition, the bottom wall 18B of the periphery trench 18 does not necessarily have to be flat, and may be curved in part or in its entirety, for example.

[0060] 2, 3, and 6, in the first embodiment, a plurality of periphery trenches 18 are provided. In this case, the plurality of periphery trenches 18 may include a first periphery trench 70 that is arranged innermost among the plurality of periphery trenches 18 in a plan view, and one or more second periphery trenches 72 that surround the first periphery trench 70. As shown in FIG. 6, the first periphery trench 70 may be located between the cell end 32 of the cell trench 14 and the second periphery trench 72.

[0061] The semiconductor device 10 may include a plurality of peripheral electrodes 68 and a peripheral insulating layer 112. In one example, the plurality of peripheral electrodes 68 may be made of conductive polysilicon. In another example, the plurality of peripheral electrodes 68 may be made of any other metallic material. A peripheral insulating layer 112 is provided within the first peripheral trench 70. A peripheral insulating layer 112 is provided within each second peripheral trench 72, similar to the first peripheral trench 70. The peripheral electrode 68 may be embedded in the peripheral insulating layer 112 provided within the first peripheral trench 70. The peripheral electrode 68 may also be embedded in the peripheral insulating layer 112 provided within the second peripheral trench 72. Each of the plurality of peripheral electrodes 68 is electrically connected to the source wiring 22.

[0062] Each peripheral electrode 68 is surrounded by a peripheral insulating layer 112. The peripheral electrodes 68 may have a width smaller than that of the gate electrodes 58. Because the peripheral electrodes 68 have a width smaller than that of the gate electrodes 58, the thickness of the peripheral insulating layer 112 surrounding the peripheral electrodes 68 is greater than the thickness of the cell insulating layer 30 surrounding the gate electrodes 58.

[0063] As shown in FIG. 6 , the peripheral insulating layer 112 may include a peripheral field insulating layer 112B. The peripheral field insulating layer 112B is a part of the peripheral insulating layer 112 interposed between the peripheral electrode 68 and the sidewall 70A of the first peripheral trench 70. The peripheral field insulating layer 112B contacts both the side surface of the peripheral electrode 68 and the sidewall 70A of the first peripheral trench 70. Therefore, the peripheral electrode 68 may face the sidewall 70A of the first peripheral trench 70 in the Y-axis direction of the first peripheral trench 70, while being spaced apart from the sidewall 70A of the first peripheral trench 70 via the peripheral field insulating layer 112B. The peripheral field insulating layer 112B is interposed between the peripheral electrode 68 and the bottom wall 70B of the first peripheral trench 70. The peripheral field insulating layer 112B contacts both the bottom surface of the peripheral electrode 68 and the bottom wall 70B of the first peripheral trench 70. For this reason, the peripheral electrode 68 may face the bottom wall 70B of the first peripheral trench 70 while being spaced apart from it in the depth direction of the first peripheral trench 70 within the first peripheral trench 70. Furthermore, the upper end 68A of the peripheral electrode 68 in the Z direction may be located higher than the bottom surface 58B of the gate electrode 58. The upper end 68A of the peripheral electrode 68 is covered by the peripheral field insulating layer 112B.

[0064] The semiconductor device 10 may further include a plurality of field plate contacts 78 connected to the source wiring 22. The plurality of field plate contacts 78 are provided corresponding to the plurality of periphery trenches 18. Each field plate contact 78 is connected to a peripheral electrode 68. As a result, the plurality of peripheral electrodes 68 may be electrically connected to the source wiring 22 via the field plate contacts 78 provided in the peripheral insulating layer 112.

[0065] Furthermore, because the peripheral electrode 68 is electrically connected to the source wiring 22, it is possible to alleviate electric field concentration in the drift region 44 adjacent to the first peripheral trench 70. This makes it possible to improve the breakdown voltage of the semiconductor device 10.

[0066] In one example, the second perimeter trench 72 may have a width greater than that of the first perimeter trench 70. In this case, the depth of the second perimeter trench 72 may be greater than the depth of the first perimeter trench 70. Also, in this case, the first perimeter trench 70 may have the same width as the cell trench 14. In another example, the second perimeter trench 72 may have the same width as the first perimeter trench 70.

[0067] The multiple second outer periphery trenches 72 may be arranged at a pitch larger than the pitch at which the cell trenches 14 are arranged. Furthermore, the pitch at which the first outer periphery trenches 70 and the second outer periphery trenches 72 are arranged may be smaller than the pitch at which the cell trenches 14 are arranged.

[0068] The semiconductor device 10 may further include a plurality of field plate contacts 78 that connect at least one of the plurality of peripheral electrodes 68 to the source wiring 22. In the example of FIG. 6 , two field plate contacts 78 connect the peripheral electrode 68 embedded in the first periphery trench 70 and the peripheral electrode 68 embedded in the second periphery trench 72 located adjacent to the first periphery trench 70 to the source wiring 22, respectively. In this example, the peripheral electrodes 68 embedded in the other second periphery trenches 72 do not need to be connected to a field plate contact 78. In another example, all of the plurality of peripheral electrodes 68 embedded in the plurality of periphery trenches 18 may be connected to the source wiring 22 via the field plate contacts 78.

[0069] 3, the cell trenches 14 may be arranged at a first pitch P1 in the X-axis direction in a plan view. The cell trenches 14 may also be arranged at a first interval G1. The first interval G1 may correspond to the first pitch P1 minus the width of the cell trench 14 (the dimension of the cell trench 14 in the short direction). The first interval G1 can also be defined as the distance between adjacent cell trenches 14 in the X-axis direction among the multiple cell trenches 14 arranged at the first pitch P1.

[0070] At the cell edge 32, the cell insulating layer 30 may include a second electrode edge field insulating layer 30C. The second electrode end field insulating layer 30C is a part of the cell insulating layer 30 interposed between the electrode end 61 included in the cell trench 14 and the sidewall 14A of the cell trench 14. The second electrode end field insulating layer 30C contacts both the side surface of the electrode end 61 and the sidewall 14A of the cell trench 14. Therefore, the electrode end 61 may face the sidewall 14A of the cell trench 14 at the end of the cell trench 14 in the Y-axis direction, while being spaced apart from the sidewall 14A of the cell trench 14 via the second electrode end field insulating layer 30C. The second electrode end field insulating layer 30C is also interposed between the electrode end 61 and the bottom wall 14B of the cell trench 14. The second electrode end field insulating layer 30C contacts both the bottom surface of the electrode end 61 and the bottom wall 14B of the cell trench 14. Therefore, the electrode end portion 61 may be opposed to the bottom wall 14B of the cell trench 14 while being spaced apart from it in the depth direction of the cell trench 14 within the cell trench 14.

[0071] As shown in FIG. 6 , the electrode end 61 protrudes upward from a portion of the first field plate electrode 60 that is different from the electrode end 61. The electrode end 61 faces the gate electrode 58 in the Y-axis direction. A cell insulating layer 30 is interposed between the electrode end 61 and the gate electrode 58 in the Y-axis direction. An upper end 61A of the electrode end 61 is located above a bottom surface 58B of the gate electrode 58. The upper end 61A of the electrode end 61 is covered by the cell insulating layer 30. In this way, it can be said that the electrode end 61 is embedded in the cell trench 14 via the cell insulating layer 30.

[0072] In the boundary region 19, the first outer periphery trench 70 and the cell trench 14 face each other in the Y-axis direction, sandwiching the drift region 44. In other words, the first outer periphery trench 70 is disposed on the opposite side of the cell trench 14 with the drift region 44 sandwiched therebetween.

[0073] Since the electrode end portion 61 and the peripheral electrode 68 are each electrically connected to the source wiring 22, localized electric field concentration in the drift region 44 in the boundary region 19 can be alleviated, as in the case of the first field plate electrode 60. This allows the breakdown voltage of the semiconductor device 10 to be improved.

[0074] For example, it is desirable that the peripheral field insulating layer 112B on the first peripheral trench 70 side and the second electrode end field insulating layer 30C on the cell trench 14 side have the same thickness. The peripheral field insulating layer 112B and the second electrode end field insulating layer 30C are both made of the same material and are part of the peripheral insulating layer 112 and the cell insulating layer 30, respectively. Therefore, when the same potential is applied to the peripheral electrode 68 and the electrode end 61, the insulating layer thickness is the same, and they face the drift region 44, the same electric field is generated within the insulating layer. This allows the width of the depletion layer extending toward the drift region 44 to be constant when the first peripheral trench 70 including the peripheral electrode 68 and the cell end 32 of the cell trench 14 including the electrode end 61 face each other across the drift region 44. In this way, the spacing between the trenches can be designed to be constant so that the depletion layers extending toward the drift region 44 circumscribe each other, regardless of whether the spacing between the trenches is the spacing between the trench end and the trench sidewall or the spacing between the trench sidewalls.

[0075] [Configuration of the outer trench and its surrounding area] 4 to 10, a schematic plan view showing an enlargement of a portion of the semiconductor device 10 shown in FIG. 3 will be described. FIG. 7 is a schematic cross-sectional view taken along line F7-F7 of the semiconductor device 10 shown in FIG. 3. FIG. 7 shows cross sections of three protrusions 106. FIG. 8 is a schematic cross-sectional view taken along line F8-F8 of the semiconductor device 10 shown in FIG. 3. FIG. 9 is a schematic plan view showing an enlargement of a portion of the semiconductor device 10 shown in FIG. 2. FIG. 10 is a schematic cross-sectional view taken along line F10-F10 of the semiconductor device 10 shown in FIG. 9.

[0076] As shown in FIG. 3 , the semiconductor device 10 may include an active region 99 in which a MISFET having a trench gate structure is disposed, and a non-active region 101 disposed to surround the active region 99 in a plan view. In one example, the cell trench 14 may extend across the boundary between the active region 99 and the non-active region 101. The non-active region 101 may be provided to surround the active region 99 in a plan view. The non-active region 101 may be, for example, annular in a plan view. The cell region 15 may be disposed across the boundary between the active region 99 and the non-active region 101. The cell region 15 may include cell ends 32 at both ends in the Y-axis direction. The cell ends 32 may be the non-active region 101. In another example, in addition to the cell ends 32, the cell trench 14 adjacent to the peripheral trench 18 may be included in the non-active region 101. Additionally, the first perimeter trench 70 and the plurality of second perimeter trenches 72 are disposed in the inactive region 101 .

[0077] In the region of the cell region 15 where the electrode end 61 is arranged (see FIG. 3 ), the epitaxial layer 42 may include a drift region 44 arranged on the semiconductor substrate 40 (drain region) and a body region 46 arranged on the drift region 44. That is, in the non-active region 101, the epitaxial layer 42 includes the drift region 44 and the body region 46, but does not include the source region 20.

[0078] In the region of the cell region 15 where the gate electrode 58 is disposed (see FIG. 3 ), the epitaxial layer 42 may include a drift region 44 disposed on the semiconductor substrate 40 (drain region), a body region 46 disposed on the drift region 44, and a source region 20 disposed on the body region 46. That is, in the active region 99, the epitaxial layer 42 includes the drift region 44, the body region 46, and the source region 20.

[0079] (perimeter trench) 3, the first outer periphery trench 70 may include a first outer periphery extension portion 102 extending in the X-axis direction. As shown in Fig. 9, the first outer periphery trench 70 may further include a second outer periphery extension portion 103 extending in the Y-axis direction, and a connection portion 105 connecting the first outer periphery extension portion 102 and the second outer periphery extension portion 103.

[0080] The connecting portion 105 may be curved in a generally arc shape of approximately one-quarter of the circumference so as to surround the cell region 15. The second outer peripheral extension portion 103 may be adjacent to the cell trench 14 arranged outermost in the X-axis direction of the cell region 15.

[0081] The first outer periphery extension portion 102 may include an inner surface 104 that faces the cell ends 32 of the multiple cell trenches 14 at a distance in the Y-axis direction, and a protrusion 106 that protrudes inward from the inner surface 104. The inner surface 104 extends in the X-axis direction in a plan view. The first outer periphery trench 70 includes an outer surface that faces the opposite side to the inner surface 104. The outer surface of the first outer periphery trench 70 extends in the X-axis direction. No protrusion 106 is provided on this outer surface.

[0082] The inner surface 104 may be adjacent to the border region 19 . The protrusions 106 protrude in the direction of the cell region 15 towards the boundary region 19. It can also be said that the protrusions 106 are provided in the boundary region 19. In one example, a plurality of the protrusions 106 are provided spaced apart from each other in the X-axis direction. In one example, the plurality of protrusions 106 are arranged at a second pitch P2 in the X-axis direction. In another example, the plurality of protrusions 106 may be arranged at a second interval G2 in the X-axis direction. The second interval G2 may correspond to the second pitch P2 minus the width of the protrusions 106 (the dimension of the protrusions 106 in the short direction). The second interval G2 can also be defined by the distance between adjacent protrusions 106 in the X-axis direction among the plurality of protrusions 106 arranged at the second pitch P2.

[0083] In the boundary region 19 where the protrusion 106 is disposed, the epitaxial layer 42 may include a drift region 44 disposed on the semiconductor substrate 40 (drain region) and a body region 46 disposed on the drift region 44.

[0084] The protrusion 106 is disposed between two cell trenches 14 adjacent to each other in the X-axis direction in a plan view. More specifically, among the cell trenches 14, a pair of cell trenches 14 adjacent to each other in the X-axis direction is defined as a first cell trench 14P and a second cell trench 14Q. That is, the multiple cell trenches 14 include a first cell trench 14P and a second cell trench 14Q. Furthermore, among the protrusions 106, a pair of protrusions 106 adjacent to each other in the X-axis direction is defined as a first protrusion 106P and a second protrusion 106Q. That is, the multiple protrusions 106 include a first protrusion 106P and a second protrusion 106Q.

[0085] The protrusion 106 is disposed in a portion between the first cell trench 14P and the second cell trench 14Q on the inner surface 104. In one example, the protrusion 106 is located at the center between the first cell trench 14P and the second cell trench 14Q on the inner surface 104. More specifically, the first protrusion 106P is disposed in a portion between the first cell trench 14P and the second cell trench 14Q in the outer circumferential region 17. The first protrusion 106P is located at the center between the first cell trench 14P and the second cell trench 14Q in the X-axis direction. The second cell trench 14Q is disposed in a portion between the first protrusion 106P and the second protrusion 106Q in the cell region 15. The second cell trench 14Q is located at the center between the first protrusion 106P and the second protrusion 106Q in the X-axis direction.

[0086] Each protrusion 106 extends along the Y-axis direction in plan view. Each protrusion 106 is provided in the boundary region 19, but is provided closer to the outer periphery region 17 than the cell region 15. Therefore, each protrusion 106 is provided closer to the outer periphery region 17 than the cell trench 14 in the Y-axis direction. Each protrusion 106 is spaced apart from the cell trench 14 in the Y-axis direction. In one example, the tip of each protrusion 106 in the Y-axis direction is semicircular and convex toward the cell trench 14 in plan view.

[0087] In one example, a first distance 600, which is the distance between the cell end 32 of the cell trench 14 and the protrusion 106 in the Y-axis direction, may be smaller than a second pitch P2, which is the arrangement pitch of the multiple protrusions 106. In another example, the first distance 600 may be smaller than a first pitch P1, which is the arrangement pitch of the multiple cell trenches 14. Here, the first pitch P1 may be equal to the second pitch P2. In another example, a DCgap500 (Disconnected Gap), which is the distance between the cell region 15 and the first outer periphery trench 70, may be larger than the first distance 600.

[0088] In another example, the first distance 600 may be smaller than a first interval G1 in the X-axis direction between the multiple cell trenches 14. In another example, the first distance 600 may be smaller than a second interval G2 in the X-axis direction between the multiple protrusions 106. In another example, the sum of the first interval G1 and the second interval G2 is greater than twice the first distance 600.

[0089] The peripheral electrode 68 provided in the first peripheral trench 70 may include at least an electrode main body 110 provided in the first peripheral extension portion 102 and a protruding electrode 110A provided in the protruding portion 106. In one example, the electrode main body 110 and the protruding electrode 110A are integrated. The electrode main body 110 is provided in the first peripheral extension portion 102, the second peripheral extension portion 103, and the connecting portion 105. That is, the electrode main body 110 extends across the first peripheral extension portion 102, the second peripheral extension portion 103, and the connecting portion 105 in a plan view. The electrode main body 110 extends along the X-axis direction in the first peripheral extension portion 102. The electrode main body 110 may be curved in a substantially arc shape of approximately one-quarter of the circumference to match the shape of the connecting portion 105. The electrode main body 110 extends along the Y-axis direction in the second peripheral extension portion 103.

[0090] The protruding electrode 110A extends along the Y-axis direction in plan view. A plurality of protruding electrodes 110A are provided corresponding to the plurality of protruding portions 106. Therefore, the plurality of protruding portions 106 are arranged at intervals in the X-axis direction. When the plurality of protruding portions 106 are arranged at equal pitches, the plurality of protruding electrodes 110A are also arranged at equal pitches in the X-axis direction. Corresponding to the shape of the tip of the protruding portion 106 in the Y-axis direction, the tip of the protruding electrode 110A in the Y-axis direction has a semicircular shape that is convex toward the cell trench 14 in plan view.

[0091] The tip of the protrusion 106 in the Y-axis direction does not have to be semicircular in plan view, and may be, for example, partially or entirely elliptical. The tip of the protrusion electrode 110A in the Y-axis direction does not have to be semicircular in plan view, and may be, for example, partially or entirely elliptical.

[0092] The dimension of the protruding electrode 110A in the depth direction of the first peripheral trench 70 may be equal to the dimension of the electrode main body 110 in the depth direction of the first peripheral trench 70. Furthermore, the dimension of the electrode main body 110 in the depth direction of the first peripheral trench 70 may be equal to the dimension of the peripheral electrode 68 provided in the second peripheral trench 72 in the depth direction of the second peripheral trench 72.

[0093] The protruding electrode 110A may be electrically connected to the source wiring 22. The protruding electrode 110A may be configured to receive a source voltage or a voltage different from the source voltage. In the first embodiment, the protruding electrode 110A is electrically connected to the source wiring 22, and is therefore configured to receive a source voltage. This allows the protruding electrode 110A to alleviate localized electric field concentration in the drift region 44 between the protruding portions 106, similar to the case of the first field plate electrode 60. This allows the semiconductor device 10 to have an improved breakdown voltage.

[0094] The outer peripheral insulating layer 112 may cover both the electrode main body 110 and the protruding electrode 110A within the first outer peripheral extension portion 102. The electrode main body 110 and the protruding electrode 110A may be electrically connected within the outer peripheral insulating layer 112.

[0095] The peripheral insulating layer 112 may include a protruding insulating layer 112A provided in the protruding portion 106 and a peripheral field insulating layer 112B provided in the first peripheral extension portion 102. The protruding insulating layer 112A may cover the inner walls of the protrusion 106 (the side walls 106A and the bottom wall 106B in FIG. 7).

[0096] The protruding electrode 110A may extend above a position spaced apart from the bottom wall of the protrusion 106 (bottom wall 106B in FIG. 7) by the protruding insulating layer 112A, to a position higher than the bottom surface of the gate electrode 58 of the cell trench 14 (bottom surface 58B in FIG. 4).

[0097] The protruding insulating layer 112A may include a first protruding field insulating layer 112C and a second protruding field insulating layer 112D. In one example, the first protruding field insulating layer 112C and the second protruding field insulating layer 112D are integrated.

[0098] The first protruding field insulating layer 112C is a part of the protruding insulating layer 112A that is interposed in the X-axis direction between the protruding electrode 110A (see FIG. 7) and the sidewall 106A (see FIG. 7) of the protruding portion 106. The first protruding field insulating layer 112C is in contact with both the side surface of the protruding electrode 110A and the sidewall 106A of the protruding portion 106. Therefore, the protruding electrode 110A may face the sidewall 106A of the protruding portion 106 in the X-axis direction of the protruding portion 106, while being spaced apart from it, via the first protruding field insulating layer 112C.

[0099] The second protruding field insulating layer 112D is a part of the protruding insulating layer 112A that is interposed in the Y-axis direction between the protruding electrode 110A (see FIG. 8) and the sidewall 106A (see FIG. 8) of the protruding portion 106. The second protruding field insulating layer 112D is in contact with both the side surface of the protruding electrode 110A and the sidewall 106A of the protruding portion 106. Therefore, the protruding electrode 110A may face the sidewall 106A of the protruding portion 106 in the Y-axis direction of the protruding portion 106, while being spaced apart from it, via the second protruding field insulating layer 112D.

[0100] The protruding electrode 110A may have a width smaller than that of the gate electrode 58 when viewed from the X-axis direction. Because the protruding electrode 110A has a width smaller than that of the gate electrode 58, the thickness of the protruding insulating layer 112A surrounding the protruding electrode 110A is greater than the thickness of the cell insulating layer 30 surrounding the gate electrode 58.

[0101] For example, it is desirable that the peripheral field insulating layer 112B and the first protruding field insulating layer 112C have the same film thickness. The peripheral field insulating layer 112B and the first protruding field insulating layer 112C are both part of the peripheral insulating layer 112 and are made of the same material. Therefore, when the same potential is applied to the electrode body 110 and the protruding electrode 110A, the insulating layer has the same film thickness, and faces the drift region 44, the same electric field is generated within the insulating layer. This allows the width of the depletion layer extending toward the drift region 44 to be constant in the X-axis and Y-axis directions.

[0102] For example, the first protruding field insulating layer 112C and the second protruding field insulating layer 112D preferably have the same thickness. The first protruding field insulating layer 112C and the second protruding field insulating layer 112D are both part of the protruding insulating layer 112A and are made of the same material. Therefore, when the same potential is applied to the protruding electrode 110A, the insulating layer thickness is the same, and they face the drift region 44, the same electric field is generated within the insulating layer. This allows the width of the depletion layer extending toward the drift region 44 to be constant in the X-axis and Y-axis directions.

[0103] (cell edge of cell trench) 3, the Y-axis direction tip of cell end 32 of cell trench 14 has a semicircular shape that convex toward first outer peripheral trench 70 in plan view. Corresponding to the shape of the Y-axis direction tip of cell end 32, the Y-axis direction tip of electrode end 61 of first field plate electrode 60 has a semicircular shape that convex toward first outer peripheral trench 70 in plan view.

[0104] The tip of the cell end 32 of the cell trench 14 in the Y-axis direction does not have to be semicircular in plan view, and may be partially or entirely elliptical, for example. The tip of the electrode end 61 of the first field plate electrode 60 in the Y-axis direction does not have to be semicircular in plan view, and may be partially or entirely elliptical, for example. In the inactive region 101, the semiconductor layer 12 located between the cell trench 14 and the first outer peripheral trench 70 may include a p-type region 114. The p-type region 114 may be electrically connected to the body region 46.

[0105] In one example, the second protruding field insulating layer 112D of the protruding portion 106 and the second electrode end field insulating layer 30C of the cell end 32 preferably have the same thickness. The second protruding field insulating layer 112D and the second electrode end field insulating layer 30C are part of the peripheral insulating layer 112 and the cell insulating layer 30, respectively, and are made of the same material. Therefore, when the same potential is applied to the protruding electrode 110A and the electrode end 61 of the first field plate electrode 60, the insulating layer thickness is the same, and they face the drift region 44, the same electric field is generated within the insulating layer. This allows the width of the depletion layer extending toward the drift region 44 to be constant when the protruding portion 106 including the protruding electrode 110A and the cell end 32 including the electrode end 61 of the first field plate electrode 60 face each other across the drift region 44.

[0106] [Operation of the first embodiment] The operation of the semiconductor device 10 of the first embodiment will be described with reference to FIGS. 11 and 12. FIG. 11 is a schematic plan view of the cell region 15, boundary region 19, and part of the periphery region 17 in a semiconductor device 11 of a comparative example. FIG. 12 is a schematic plan view of the cell region 15, boundary region 19, and part of the periphery region 17 in the semiconductor device 10 of the first embodiment. FIG. 11 shows the relationship between the depletion layer DL1 in the cell end 32 of the cell trench 14 and the depletion layer DL3 in the first periphery trench 70 in the semiconductor device 11 of the comparative example. FIG. 12 shows the relationship between the depletion layer DL1 in the cell end 32 of the cell trench 14 and the depletion layer DL2 in the protrusion 106 of the first periphery trench 70 in the semiconductor device 10 of the first embodiment. In FIGS. 11 and 12, the outer edges of the depletion layers DL1 to DL3 are indicated by dashed lines.

[0107] To improve the BVDSS of the semiconductor device 10 and thereby ensure the breakdown voltage, the semiconductor device 10 includes a peripheral electrode 68 in the first peripheral trench 70 and an electrode edge 61 provided at the cell edge 32 of the cell trench 14. This allows depletion layers to extend from both sides into the drift region 44 in the boundary region 19 between the cell region 15 and the first peripheral trench 70, thereby depleting the drift region 44 in the boundary region 19. This reduces local electric field concentration caused by the drain voltage applied between the source and drain, improving the BVDSS of the semiconductor device 10.

[0108] 11 includes a structure in which the drift region 44 in the boundary region 19 is depleted, in which the protrusion 106 is omitted from the first outer periphery trench 70. Note that in the semiconductor device 11 of the comparative example, components common to those in the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

[0109] In semiconductor device 11 of the comparative example, depletion layer DL3 extending from first outer peripheral trench 70 extends a distance b from the inner side surface 104 of first outer peripheral trench 70. The outer edge of depletion layer DL3 extending from first outer peripheral trench 70 is parallel to inner side surface 104 of first outer peripheral trench 70. Depletion layer DL1 extending from cell end 32 of cell trench 14 extends a distance a from the side wall of cell trench 14. The outer edge of depletion layer DL1 extending from cell trench 14 has a substantially arc shape centered on the tip of electrode end 61 of first field plate electrode 60 provided at cell end 32 of cell trench 14.

[0110] The interval between the cell trenches 14 is set to a first interval G1=2a so that the outer edges of the depletion layers DL1 extending from adjacent cell trenches 14 come into contact with each other in the X-axis direction. This allows depletion to occur at least between adjacent cell trenches 14 on the cell end 32 side.

[0111] Furthermore, when the outer edge of the depletion layer DL1 extending from the tip of the cell end 32 of the adjacent cell trench 14 and the outer edge of the depletion layer DL3 extending parallel to the inner surface 104 of the first outer peripheral trench 70 are in contact with each other, the region not reached by the depletion layers DL1 and DL3 is a region that is insufficiently depleted (undepleted region 300).

[0112] In this way, when the cell region 15 is surrounded by the first outer peripheral trench 70, the undepleted region 300 tends to become large when the depletion layer DL3 extending from the inner side surface 104 of the first outer peripheral trench 70 and the depletion layer DL1 extending from the cell edge 32 extend from both sides. Since electric field concentration is likely to occur in the undepleted region 300, if the undepleted region 300 is large, the BVDSS decreases.

[0113] Therefore, it is conceivable to reduce the n-type impurity concentration of the drift region 44, for example, so that both the depletion layer DL3 extending from the first outer peripheral trench 70 and the depletion layer DL1 extending from the cell end 32 of the cell trench 14 can easily extend. However, reducing the n-type impurity concentration of the drift region 44 increases the resistance of the drain region including the drift region 44, which increases the on-resistance of the semiconductor device 11.

[0114] Alternatively, instead of reducing the n-type impurity concentration of the drift region 44, it is possible to reduce the distance DCgap500 between the cell edge 32 and the first outer peripheral trench 70, for example, to facilitate contact between the depletion layer DL3 extending from the first outer peripheral trench 70 and the depletion layer DL1 extending from the cell edge 32. However, if DCgap500 is reduced too much, the depletion layer DL3 and the depletion layer DL1 may overlap, resulting in an over-depleted region. This results in a reduction in BVDSS. Therefore, there is a trade-off between reducing the on-resistance of the semiconductor device 11 and ensuring the allowable range of DCgap500.

[0115] 12 shows a state in which the outer edge of the depletion layer DL2 extending from the protruding portion 106 of the first outer peripheral trench 70 and the outer edge of the depletion layer DL1 extending from the tip of the cell trench 14 are in contact with each other. In Fig. 12, the outer edges of both depletion layers DL1 and DL2 are indicated by dashed lines. The region that both depletion layers DL1 and DL2 do not reach is a region that is insufficiently depleted (an undepleted region 400).

[0116] 12, the depletion layer DL1 extending from the protruding portion 106 of the first outer peripheral trench 70 extends a distance b from the sidewall of the protruding portion 106. The outer edge of the depletion layer DL1 extending from the protruding portion 106 has a substantially arc shape centered on the tip of the protruding electrode 110A included in the protruding portion 106. The spacing between the protruding portions 106 is set to a second spacing G2=2b so that the outer edges of the depletion layers DL1 extending from adjacent protruding portions 106 come into contact with each other. This allows depletion to occur at least between adjacent protruding portions 106 on the protruding portion 106 side.

[0117] The semiconductor device 10 of the first embodiment includes a protruding portion 106 disposed on the inner surface 104 of the first outer peripheral trench 70 in a portion between the first cell trench 14P and the second cell trench 14Q. The depletion layer DL2 extending from the protruding portion 106 of the first outer peripheral trench 70 penetrates between the depletion layers DL1 extending from the first cell trench 14P and the second cell trench 14Q, two adjacent trenches in the X-axis direction. Therefore, the area of ​​the undepleted region 400 between the depletion layer DL2 extending from the protruding portion 106 of the first outer peripheral trench 70 and the depletion layers DL2 extending from the first cell trench 14P and the second cell trench 14Q is smaller than the undepleted region 300 in the comparative example shown in FIG. 11 . Therefore, the semiconductor device 10 of the first embodiment can improve BVDSS compared to the semiconductor device 11 of the comparative example.

[0118] Incidentally, when DCgap500 is small, a portion is generated in which the depletion layer DL2 extending from the protruding portion 106 of the first outer peripheral trench 70 and the depletion layer DL1 extending from the first cell trench 14P and the second cell trench 14Q overlap. In the semiconductor device 11 of the comparative example shown in FIG. 11 , the outer edge of the depletion layer DL3 extending from the first outer peripheral trench 70 is parallel to the inner side surface 104 of the first outer peripheral trench 70. In contrast, in the semiconductor device 10 of the first embodiment, the depletion layer DL3 extends from the protruding portion 106 of the first outer peripheral trench 70 in a substantially arc shape centered on the tip of the protruding electrode 110A. The center of the depletion layer DL2 extending from the protruding portion 106 is misaligned in the X-axis direction from the center of the depletion layer DL1 extending from the first cell trench 14P and the second cell trench 14Q. For this reason, in the semiconductor device 10 of the first embodiment, the area of ​​the portion where the depletion layers DL1, DL2 overlap is smaller than that of the semiconductor device 11 of the comparative example. Therefore, the difference between DCgap500 when the outer edges of the depletion layers DL1, DL2 contact each other and DCgap500 when the BVDSS decreases due to the overlap of the depletion layers DL1, DL2 is larger than that of the semiconductor device 11 of the comparative example. Therefore, the tolerance range of DCgap500 in the direction in which the first outer peripheral trench 70 approaches the first cell trench 14P and the second cell trench 14Q can be increased.

[0119] On the other hand, when DCgap500 increases, the area of ​​the undepleted region 400 between the depletion layer DL2 extending from the protruding portion 106 of the first outer peripheral trench 70 and the depletion layer DL1 extending from the first cell trench 14P and the second cell trench 14Q increases. However, the area of ​​the undepleted region 400 in the semiconductor device 10 of the first embodiment is smaller than the undepleted region 300 in the semiconductor device 11 of the comparative example. Therefore, the difference between DCgap500 when the outer edges of the depletion layers DL1 and DL2 contact each other and DCgap500 when the undepleted region 400 increases and the BVDSS decreases is larger than in the semiconductor device 11 of the comparative example. Therefore, the allowable range of DCgap500 in the direction in which the first outer peripheral trench 70 moves away from the first cell trench 14P and the second cell trench 14Q can be increased.

[0120] As described above, the semiconductor device 10 of the first embodiment can improve the BVDSS compared to the semiconductor device 11 of the comparative example. Furthermore, the semiconductor device 10 of the first embodiment can widen the allowable range of DCgap500 without reducing the impurity concentration of the drift region 44. The inventors of the present application have confirmed experimental data that shows that by using the configuration of the first embodiment, the allowable range of DCgap500 can be increased by at least 1.5 times without reducing the impurity concentration of the drift region 44. Therefore, the on-resistance of the semiconductor device 10 can be reduced without reducing the allowable range of DCgap500.

[0121] 12 , the depletion layer extending from the first outer peripheral extension portion 70 includes a depletion layer extending from the first outer peripheral extension portion 102 and a depletion layer DL2 extending from the protruding portion 106. Depending on the size of the protruding portions 106, the depletion layer extending from the first outer peripheral extension portion 102 extends toward the cell end portion 32 of the cell trench 14 between the depletion layers DL2 extending from the protruding portions 106 adjacent to each other in the X-axis direction. When the outer edge of the depletion layer DL2 extending from the protruding portion 106 contacts the outer edge of the depletion layer DL1 extending from the cell trench 14, it can be said that the undepleted region 400 includes a region between the depletion layers DL1, DL2 and a region between the depletion layers DL1, DL2 and the depletion layer extending from the first outer peripheral extension portion 102. Therefore, by setting the position of the first outer peripheral extension portion 102 so that the depletion layer extending from the first outer peripheral extension portion 102 contacts the depletion layer DL1 extending from the cell trench 14, the undepleted region 400 between the depletion layer extending from the first outer peripheral trench 70 and the depletion layer DL1 extending from the cell trench 14 can be made smaller.

[0122] [Effects of the first embodiment] (1-1) A semiconductor device 10 includes a semiconductor layer 12 including a cell region 15 and a peripheral region 17 surrounding the cell region 15, a plurality of cell trenches 14 provided in the cell region 15, extending in the Y-axis direction in a plan view and spaced apart in the X-axis direction in a plan view, a cell insulating layer 30 provided in the plurality of cell trenches 14, a cell electrode 56 embedded in the cell insulating layer 30, a first peripheral trench 70 provided in a frame shape surrounding the plurality of cell trenches 14 in the peripheral region 17, a peripheral insulating layer 112 provided in the first peripheral trench 70, and a peripheral electrode 68 provided in the first peripheral trench 70. Each of the plurality of cell trenches 14 includes a cell end 32 that is an end in the Y-axis direction. The first peripheral trench 70 includes a first peripheral extension portion 102 extending in the X-axis direction. The first outer peripheral extension portion 102 includes an inner surface 104 that faces the cell ends 32 of the multiple cell trenches 14 at a distance in the Y-axis direction, and a protrusion 106 that protrudes inward from the inner surface 104. The multiple cell trenches 14 include a first cell trench 14P and a second cell trench 14Q that are adjacent in the X-axis direction. The protrusion 106 is located in a portion of the inner surface 104 between the first cell trench 14P and the second cell trench 14Q. The outer peripheral electrode 68 has a protrusion electrode 110A provided within the protrusion 106.

[0123] This configuration makes it possible to reduce the undepleted region 400, which is the gap between the depletion layers DL1 and DL2 when the outer edge of the depletion layer DL1 extending from the tip of the cell end 32 of the adjacent cell trench 14 and the outer edge of the depletion layer DL2 extending from the tip of the protruding portion 106 of the first outer peripheral trench 70 facing in the Y-axis direction are in contact with each other. As a result, the breakdown voltage (BVDSS) of the semiconductor device 10 can be improved.

[0124] (1-2) It is possible to reduce the undepleted region 400, which is the gap between the depletion layers DL1 and DL2 when the outer edge of the depletion layer DL1 extending from the tip of the cell end 32 of the adjacent cell trench 14 and the outer edge of the depletion layer DL2 extending from the tip of the protruding portion 106 of the first outer peripheral trench 70 facing in the Y-axis direction are circumscribed. As a result, it is possible to widen the allowable range of the DCgap500 without reducing the impurity concentration of the semiconductor layer 12. Therefore, it is possible to reduce the on-resistance of the semiconductor device 10 without reducing the allowable range of the DCgap500.

[0125] (1-3) The protruding portion 106 is located on the inner side surface 104 between the first cell trench 14P and the second cell trench 14Q, in the center of both the cell trenches 14P, 14Q. With this configuration, the undepleted region 400, which is the gap between the depletion layers DL1 and DL2 when the depletion layer DL1 extending from the tip of the cell end 32 of adjacent cell trenches 14P and 14Q and the depletion layer DL2 extending from the tip of the protrusion 106 of the first outer peripheral trench 70 facing them in the Y-axis direction are in contact with each other, can be reduced.

[0126] (1-4) The multiple cell trenches 14 are arranged at a first pitch P1 in the X-axis direction. A first distance 600, which is the distance between the cell end 32 and the protrusion 106 in the Y-axis direction, is smaller than the first pitch P1. With this configuration, the BVDSS in the boundary region 19 between the cell region 15 and the first outer peripheral trench 70 can be made at least as high as that of the cell region 15.

[0127] (1-5) The protrusions 106 are arranged in a plurality of rows at a second pitch P2 in the X-axis direction. The first distance 600 is smaller than the second pitch P2. This configuration allows the BVDSS in the boundary region 19 between the cell region 15 and the first outer periphery trench 70 to be at least as strong as that of the cell region 15.

[0128] (1-6) The first pitch P1 of the multiple cell trenches 14 is equal to the second pitch P2 of the multiple protrusions 106. With this configuration, it is possible to continuously realize a configuration in which the protrusions 106 are positioned at the center between adjacent cell trenches 14 on the inner surface 104 in the X-axis direction.

[0129] (1-7) The cell trenches 14 are arranged in the X-axis direction at a first interval G1. The first distance 600 is smaller than the first interval G1. According to this configuration, if the distance of the depletion layers extending from the tips of the cell ends 32 of adjacent cell trenches 14 is a, the interval between the cell trenches 14 can be set to the first interval G1=2a so that the depletion layers DL1 and DL2 circumscribe each other in the X-axis direction. This makes it possible to deplete at least the semiconductor layer 12 between adjacent cell trenches 14.

[0130] (1-8) The protrusions 106 are arranged in the X-axis direction at second intervals G2. The first distance 600 is smaller than the second intervals G2. According to this configuration, if the distance of the depletion layers extending from the tips of the protruding portions 106 of adjacent first outer peripheral trenches 70 is b, the spacing between the protruding portions 106 can be set to the second spacing G2=2b so that the depletion layers DL1, DL2 circumscribe each other in the X-axis direction. This makes it possible to deplete at least the semiconductor layer 12 between the adjacent protruding portions 106.

[0131] (1-9) The sum of the first interval G1 and the second interval G2 is greater than twice the first distance 600. With this configuration, the undepleted region 400, which is the gap between the depletion layers DL1 and DL2 when the depletion layer DL1 extending from the tip of the cell end 32 of the adjacent cell trench 14 and the depletion layer DL2 extending from the tip of the protrusion 106 of the first outer peripheral trench 70 facing in the Y-axis direction are in contact with each other, can be reduced.

[0132] 12, when the depletion layer DL2 extending from the protruding portion 106 of the first outer peripheral trench 70 and the depletion layer DL1 extending from the cell end portion 32 of the cell trench 14 are circumscribing each other, in order for the undepleted region 400 to be smaller than the undepleted region 300 shown in Fig. 11, the depletion layer DL2 extending from the protruding portion 106 and the depletion layer DL1 extending from the cell trench 14 need to be circumscribing each other alternately. In other words, the depletion layer DL2 extending from the cell trench 14 needs to penetrate into the recess formed by the outer edge of the depletion layer DL2 extending from the adjacent protruding portion 106, and the depletion layer DL2 extending from the protruding portion 106 needs to penetrate into the recess formed by the depletion layer DL1 of the adjacent cell trench 14.

[0133] In this case, the width of the depletion layer extending from the cell end 32 of the cell trench 14 = a, the width of the depletion layer extending from the protrusion 106 of the first outer peripheral trench 70 = b, the first spacing G1 = 2a, the second spacing G2 = 2b, and a + b > the first distance, so the sum of the first spacing G1 and the second spacing G2 is greater than twice the first distance 600.

[0134] That is, by making the sum of the first gap G1 and the second gap G2 greater than twice the first distance 600, the depletion layer DL1 extending from the protrusion 106 can be inserted between the depletion layers DL1 extending from the cell trench 14, thereby reducing the undepleted region 400. As a result, the allowable range of DCgap500 can be increased without reducing the impurity concentration of the drift region 44. In other words, the on-resistance of the semiconductor device 10 can be reduced while maintaining the allowable range of DCgap500.

[0135] (1-10) DCgap500, which is the distance in the Y-axis direction between the cell end 32 and the inner surface 104, is greater than the first distance 600. According to this configuration, the depletion layer DL2 extending from the protrusion 106 and the depletion layer DL1 extending from the cell trench 14 are alternately inserted, so that the undepleted region 400 can be made small.

[0136] (1-11) The cell electrode 56 includes a gate electrode 58 and a first field plate electrode 60. The first field plate electrode 60 is embedded in a position spaced apart from the gate electrode 58 and closer to the bottom wall 14B of the cell trench 14, via the cell insulating layer 30. With this configuration, the drift region 44 adjacent to the cell trench 14 can be depleted by the first field plate electrode 60.

[0137] (1-12) The cell trench 14 includes a cell edge 32. The first field plate electrode 60 includes an electrode edge 61 provided at the cell edge 32. An upper end 61A of the electrode edge 61 in the trench depth direction is located higher than a bottom surface 58B of the gate electrode 58. The electrode edge 61 is embedded via the cell insulating layer 30. With this configuration, the drift region 44 adjacent to the cell trench 14 can be depleted by the electrode edge 61 provided at the cell edge 32 of the first field plate electrode 60.

[0138] (1-13) The upper end 68A of the peripheral electrode 68 in the first peripheral trench 70 in the trench depth direction is located higher than the bottom surface 58B of the gate electrode 58. The peripheral electrode 68 is embedded via the peripheral insulating layer 112. With this configuration, the peripheral electrode 68 can deplete the drift region 44 adjacent to the cell trench 14.

[0139] (1-14) The source wiring 22 is provided on the cell insulating layer 30 and the peripheral insulating layer 112. The electrode end 61 of the first field plate electrode 60 is electrically connected to the source wiring 22. With this configuration, the first field plate electrode 60 and the electrode end 61 have a source potential, so that the drift region 44 adjacent to the cell trench 14 can be depleted.

[0140] (1-15) The peripheral electrode 68 is electrically connected to the source wiring 22. With this configuration, the peripheral electrode 68 has a source potential, and therefore the drift region 44 adjacent to the cell trench 14 can be depleted.

[0141] (1-16) The peripheral region 17 includes a plurality of peripheral trenches 18, a peripheral insulating layer 112 provided in each of the plurality of peripheral trenches 18, and a peripheral electrode 68 provided in each of the plurality of peripheral trenches 18 and embedded in the peripheral insulating layer 112. The plurality of peripheral trenches 18 includes a first peripheral trench 70. The first peripheral trench 70 is disposed at the innermost periphery of the plurality of peripheral trenches 18. With this configuration, the breakdown voltage of the semiconductor device 10 can be ensured by using the plurality of peripheral trenches 18.

[0142] Second Embodiment A semiconductor device 10 according to a second embodiment will be described with reference to Fig. 13 and Fig. 14. Fig. 13 is a schematic plan view showing an enlarged portion of the semiconductor device 10 according to the second embodiment. Fig. 14 is a schematic cross-sectional view taken along line F14-F14 of the semiconductor device 10 shown in Fig. 13.

[0143] The semiconductor device 10 of the second embodiment differs from the semiconductor device 10 of the first embodiment mainly in that the cell trench 14 arranged outermost in the X-axis direction of the cell region 15 does not include a gate electrode 58, a first field plate electrode 60, and an electrode end 61 provided at the cell end 32. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0144] 13, of the multiple cell trenches 14, the cell trench 14 arranged outermost in the X-axis direction of the cell region 15 (hereinafter referred to as an "end cell trench 14Y") includes a cell electrode 56. The cell electrode 56 may include a second field plate electrode 80.

[0145] 14, the second field plate electrodes 80 may be embedded in the cell insulating layer 30 provided in the end cell trench 14Y. Each of the multiple second field plate electrodes 80 is electrically connected to the source wiring 22.

[0146] Each second field plate electrode 80 is surrounded by the cell insulating layer 30. The second field plate electrodes 80 may have a width smaller than that of the gate electrode 58. Because the second field plate electrodes 80 have a width smaller than that of the gate electrode 58, the thickness of the cell insulating layer 30 surrounding the second field plate electrodes 80 is greater than the thickness of the cell insulating layer 30 surrounding the gate electrode 58.

[0147] The cell insulating layer 30 may include a second field insulating layer 30D. The second field insulating layer 30D is a part of the cell insulating layer 30 interposed between the second field plate electrode 80 and the sidewall 14A of the end cell trench 14Y. The second field insulating layer 30D contacts both the side surface of the second field plate electrode 80 and the sidewall 14A of the end cell trench 14Y. Therefore, the second field plate electrode 80 may face the sidewall 14A of the end cell trench 14Y in the X-axis direction of the end cell trench 14Y while being spaced apart from the sidewall 14A of the end cell trench 14Y via the second field insulating layer 30D. The second field insulating layer 30D is also interposed between the second field plate electrode 80 and the bottom wall 14B of the end cell trench 14Y. The second field insulating layer 30D contacts both the bottom surface of the second field plate electrode 80 and the bottom wall 14B of the end cell trench 14Y. Therefore, the second field plate electrode 80 may be opposed to but spaced apart from the bottom wall 14B of the end cell trench 14Y in the depth direction of the end cell trench 14Y within the end cell trench 14Y.

[0148] An upper end 80A of the second field plate electrode 80 may be located higher in the Z direction than a bottom surface 58B of the gate electrode 58. The upper end 80A of the second field plate electrode 80 may be covered with a second field insulating layer 30D (cell insulating layer 30).

[0149] The semiconductor device 10 may further include a plurality of field plate contacts 78 connected to the source wiring 22. The second field plate electrode 80 may be electrically connected to the source wiring 22 via the field plate contacts 78.

[0150] Furthermore, because the second field plate electrode 80 is electrically connected to the source wiring 22, it is possible to alleviate electric field concentration in the drift region 44 between the cell trench 14 adjacent in the X-axis direction on the opposite side of the periphery region 17. Furthermore, it is possible to alleviate electric field concentration in the drift region 44 between the first periphery trench 70 adjacent in the X-axis direction on the periphery region 17 side. Therefore, it is possible to improve the breakdown voltage of the semiconductor device 10.

[0151] In one example, it is desirable that second field insulating layer 30D and peripheral field insulating layer 112B have the same thickness. Second field insulating layer 30D and peripheral field insulating layer 112B are part of cell insulating layer 30 and peripheral insulating layer 112, respectively, and are made of the same material. Therefore, when the same potential is applied to second field plate electrode 80 and peripheral electrode 68, the insulating layer thickness is the same, and they face drift region 44, the same electric field is generated within the insulating layer. This allows the width of the depletion layer extending toward drift region 44 to be constant in the X-axis direction.

[0152] [Effects of the second embodiment] According to the semiconductor device 10 of the second embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0153] (2-1) The cell electrode 56 in the end cell trench 14Y, which is located among the multiple cell trenches 14 closest to the first outer peripheral trench 70 in the X-axis direction in plan view, includes a second field plate electrode 80 whose upper end 80A in the trench depth direction is located above the bottom surface 58B of the gate electrode 58. The second field plate electrode 80 is embedded via the cell insulating layer 30. With this configuration, the second field plate electrode 80 can deplete the drift region 44 adjacent to the end cell trench 14Y.

[0154] (2-2) The device includes a source wiring 22 provided on the cell insulating layer 30 and the peripheral insulating layer 112. The second field plate electrode 80 is electrically connected to the source wiring 22. With this configuration, the second field plate electrode 80 has a source potential, and therefore can deplete the drift region 44 adjacent to the end cell trench 14Y.

[0155] (2-3) The semiconductor device 10 includes a source wiring 22 provided on the cell insulating layer 30 and the peripheral insulating layer 112. The cell trench 14 includes a cell edge 32. The first field plate electrode 60 includes an electrode edge 61 provided at the cell edge 32. At least one of the first field plate electrode 60, the electrode edge 61 of the first field plate electrode 60, the second field plate electrode 80, and the peripheral electrode 68 is configured to be supplied with a potential different from that of the source wiring 22. With this configuration, the amount by which the depletion layer extends from the trench in which each electrode is embedded can be changed as desired, thereby adjusting the breakdown voltage of the semiconductor device 10.

[0156] <Third embodiment> A semiconductor device 10 according to a third embodiment will be described with reference to Fig. 15 and Fig. 16. Fig. 15 is a schematic plan view showing an enlarged portion of the semiconductor device 10 according to the third embodiment. Fig. 16 is a schematic cross-sectional view taken along line F16-F16 of the semiconductor device 10 shown in Fig. 15.

[0157] The semiconductor device 10 of the third embodiment differs from the semiconductor device 10 of the first embodiment mainly in the electrode structure within the cell trench 14 arranged outermost in the X-axis direction of the cell region 15. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0158] 15, the cell trench 14 (hereinafter referred to as "end cell trench 14Z") that is arranged outermost in the X-axis direction of the cell region 15 among the multiple cell trenches 14 includes a cell electrode 56. The cell electrode 56 of the end cell trench 14Z of the third embodiment may include an upper field plate electrode 84 and a lower field plate electrode 82 instead of the gate electrode 58 and first field plate electrode 60 of the first embodiment.

[0159] The lower field plate electrode 82 and the upper field plate electrode 84 may be embedded in the cell insulating layer 30 provided in the end cell trench 14Z. The lower field plate electrode 82 and the upper field plate electrode 84 are electrically connected to the source wiring 22.

[0160] The lower field plate electrode 82 includes a bottom surface 82B and a top surface 82A. The lower field plate electrode 82 may be formed with a uniform width in the trench depth direction (Z-axis direction), or may be formed with widths that vary in the trench depth direction. In the example of FIG. 16 , the width of the lower field plate electrode 82 decreases from the top surface 82A to the bottom surface 82B. The bottom surface 82B and the top surface 82A of the lower field plate electrode 82 may be flat or curved. The bottom surface 82B includes the lower end of the lower field plate electrode 82 (e.g., the lowest part of the bottom surface 82B), and the top surface 82A includes the upper end of the lower field plate electrode 82 (e.g., the top part of the top surface 82A).

[0161] The lower field plate electrode 82 is surrounded by the cell insulating layer 30 and is separated from the upper field plate electrode 84 in the trench depth direction by the cell insulating layer 30. The lower field plate electrode 82 in the end cell trench 14Z may have the same configuration as the first field plate electrode 60 in the cell trench 14.

[0162] The upper field plate electrode 84 is located above the lower field plate electrode 82 in the trench depth direction (Z-axis direction) and is separated from the lower field plate electrode 82 by the cell insulating layer 30. The upper field plate electrode 84 includes a bottom surface 84B and an upper surface 84A. The upper field plate electrode 84 may be formed with a uniform width in the trench depth direction, or may be formed with widths that vary in the trench depth direction. In the example of FIG. 16 , the width of the upper field plate electrode 84 decreases from the top surface 84A to the bottom surface 84B. The upper field plate electrode 84 may have a width greater than that of the lower field plate electrode 82 in the X-axis direction. The bottom surface 84B of the upper field plate electrode 84 may be flat or curved. The bottom surface 84B includes the lower end of the upper field plate electrode 84 (e.g., the lowest part of the bottom surface 84B). The bottom surface 84B of the upper field plate electrode 84 at least partially faces the top surface 82A of the lower field plate electrode 82. The upper surface 84A of the upper field plate electrode 84 may be flat. The upper surface 84A of the upper field plate electrode 84 is provided as the upper end of the upper field plate electrode 84 that contacts the source wiring 22. In the example of FIG. 16 , the entire upper surface 84A of the upper field plate electrode 84 contacts the source wiring 22.

[0163] The bottom surface 84B of the upper field plate electrode 84 may be located lower than the lower end of the source contact 62 in the trench depth direction (Z-axis direction). For example, the bottom surface 84B of the upper field plate electrode 84 may be located lower than the p-n junction interface between the drift region 44 and the body region 46 in the trench depth direction. In the example of FIG. 16 , the bottom surface 84B of the upper field plate electrode 84 is located at the same position as or lower than the bottom surface 58B of the gate electrode 58 in the trench depth direction. However, the bottom surface 84B of the upper field plate electrode 84 may also be located at the same position as or higher than the p-n junction interface between the drift region 44 and the body region 46.

[0164] Although not shown, the lower field plate electrode 82 includes an electrode end 61 provided at the cell end 32. The electrode end 61 of the lower field plate electrode 82 has the same configuration as the electrode end 61 of the first field plate electrode 60 (see FIG. 6 ). That is, the upper end 61A of the electrode end 61 of the lower field plate electrode 82 is located higher in the Z direction than the bottom surface 58B of the gate electrode 58. That is, the upper end 61A of the electrode end 61 is located higher than the upper surface 82A of the lower field plate electrode 82. In this way, the upper surface 82A of the lower field plate electrode 82 is the upper surface of a portion of the lower field plate electrode 82 that is different from the electrode end 61. The upper end 61A of the electrode end 61 of the lower field plate electrode 82 is covered by the cell insulating layer 30.

[0165] The upper field plate electrode 84 is surrounded by the cell insulating layer 30 except for an upper surface 84A. The upper field plate electrode 84 is electrically connected to the source wiring 22. By applying a source voltage to the upper field plate electrode 84, the upper field plate electrode 84 has the effect of extending the depletion layer in the drift region 44, thereby improving the drain-source breakdown voltage of the semiconductor device 10.

[0166] As shown in FIG. 16 , the cell insulating layer 30 may include a lower field insulating layer 30E. The lower field insulating layer 30E is a part of the cell insulating layer 30 interposed between the lower field plate electrode 82 and the sidewall 14A of the end cell trench 14Z. The lower field insulating layer 30E contacts both the side surface of the lower field plate electrode 82 and the sidewall 14A of the end cell trench 14Z. Therefore, the lower field plate electrode 82 may face the sidewall 14A of the end cell trench 14Z in the X-axis direction of the end cell trench 14Z, while being spaced apart from the sidewall 14A of the end cell trench 14Z, via the lower field insulating layer 30E. The lower field insulating layer 30E is also interposed between the lower field plate electrode 82 and the bottom wall 14B of the end cell trench 14Z. The lower field insulating layer 30E contacts both the bottom surface of the lower field plate electrode 82 and the bottom wall 14B of the end cell trench 14Z. Therefore, the lower field plate electrode 82 may face the bottom wall 14B of the end cell trench 14Z within the end cell trench 14Z while being spaced apart from it in the depth direction of the end cell trench 14Z.

[0167] The semiconductor device 10 may further include a plurality of field plate contacts 78 connected to the source wiring 22. The lower field plate electrode 82 may be electrically connected to the source wiring 22 via the field plate contacts 78.

[0168] Furthermore, because the lower field plate electrode 82 is electrically connected to the source wiring 22, it is possible to alleviate electric field concentration in the drift region 44 between the cell trench 14 adjacent in the X-axis direction on the opposite side of the periphery region 17. Furthermore, it is possible to alleviate electric field concentration in the drift region 44 between the first periphery trench 70 adjacent in the X-axis direction on the periphery region 17 side. Therefore, it is possible to improve the breakdown voltage of the semiconductor device 10.

[0169] For example, it is desirable that the lower field insulating layer 30E and the peripheral field insulating layer 112B have the same thickness. The lower field insulating layer 30E and the peripheral field insulating layer 112B are part of the cell insulating layer 30 and the peripheral insulating layer 112, respectively, and are made of the same material. Therefore, when the same potential is applied to the lower field plate electrode 82 and the peripheral electrode 68, the insulating layer thicknesses are the same, and they face the drift region 44, the same electric field is generated within the insulating layer. This allows the width of the depletion layer extending toward the drift region 44 to be constant in the X-axis direction.

[0170] [Effects of the third embodiment] According to the semiconductor device 10 of the third embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0171] (3-1) The cell electrode 56 in the end cell trench 14Z, which is located among the multiple cell trenches 14 closest to the first outer peripheral trench 70 in the X-axis direction in plan view, includes an upper field plate electrode 84 and a lower field plate electrode 82. The upper field plate electrode 84 is embedded at a position spaced apart from the lower field plate electrode 82 via the cell insulating layer 30. With this configuration, the lower field plate electrode 82 can deplete the drift region 44 adjacent to the end cell trench 14Z.

[0172] (3-2) The multiple end cell trenches 14Z include cell ends 32. The lower field plate electrode 82 includes an electrode end 61 provided at the cell end 32. An upper end 61A of the electrode end 61 in the trench depth direction is located above the bottom surface 58B of the gate electrode 58. The electrode end 61 is embedded via the cell insulating layer 30. With this configuration, the lower field plate electrode 82 and the electrode end 61 of the lower field plate electrode 82 can deplete the drift region 44 adjacent to the end cell trench 14Z.

[0173] (3-3) A source wiring 22 is provided on the cell insulating layer 30 and the peripheral insulating layer 112. The electrode ends 61 of the upper field plate electrode 84 and the lower field plate electrode 82 are electrically connected to the source wiring 22. With this configuration, the electrode end 61 of the lower field plate electrode 82 has a source potential, and therefore the drift region 44 adjacent to the end cell trench 14Z can be depleted.

[0174] (3-4) Source wiring 22 is provided on cell insulating layer 30 and peripheral insulating layer 112. At least one of lower field plate electrode 82, electrode end 61 of lower field plate electrode 82, upper field plate electrode 84, and peripheral electrode 68 is configured to be supplied with a potential different from that of the source wiring. With this configuration, the amount of extension of the depletion layer from the trench in which each electrode is buried can be changed as desired, thereby adjusting the breakdown voltage of semiconductor device 10.

[0175] <Example of change> Each embodiment can be modified as follows: Each embodiment and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0176] In the first to third embodiments, the positional relationship between the protrusion 106 and the first and second cell trenches 14P and 14Q can be changed as desired. In one example, the protrusion 106 may be disposed closer to the first cell trench 14P than to the second cell trench 14Q. In another example, the protrusion 106 may be disposed closer to the second cell trench 14Q than to the first cell trench 14P.

[0177] In the first to third embodiments, the relationship between the first pitch P1, which is the arrangement pitch of the multiple cell trenches 14, and the first distance 600 between the cell end 32 of the cell trench 14 and the protrusion 106 in the Y-axis direction can be changed as desired. In one example, the first distance 600 may be equal to the first pitch P1 of the multiple cell trenches 14. In another example, the first distance 600 may be greater than the first pitch P1 of the multiple cell trenches 14.

[0178] In the first to third embodiments, the relationship between the second pitch P2, which is the arrangement pitch of the multiple protrusions 106, and the first distance 600 between the cell end 32 of the cell trench 14 and the protrusion 106 in the Y-axis direction, can be changed as desired. In one example, the first distance 600 may be equal to the second pitch P2 of the multiple protrusions 106. In another example, the first distance 600 may be greater than the second pitch P2 of the multiple protrusions 106.

[0179] In the first to third embodiments, the relationship between the first pitch P1, which is the arrangement pitch of the multiple cell trenches 14, and the second pitch P2, which is the arrangement pitch of the multiple protrusions 106, can be changed as desired. In one example, the first pitch P1 and the second pitch P2 may be different from each other. Therefore, in one example, the first pitch P1 may be larger than the second pitch P2. In another example, the second pitch P2 may be larger than the first pitch P1.

[0180] In the first to third embodiments, the relationship between the first distance 600 between the cell end 32 of the cell trench 14 and the protrusion 106 in the Y-axis direction and the first interval G1 between the multiple cell trenches 14 in the X-axis direction can be changed as desired. In one example, the first distance 600 may be equal to the first interval G1. In another example, the first distance 600 may be greater than the first interval G1.

[0181] In the first to third embodiments, the relationship between the first distance 600 between the cell end 32 of the cell trench 14 and the protrusion 106 in the Y-axis direction and the second interval G2 between the multiple protrusions 106 in the X-axis direction can be changed as desired. In one example, the first distance 600 may be equal to the second interval G2. In another example, the first distance 600 may be greater than the second interval G2.

[0182] In the first to third embodiments, the relationship between the sum of the first interval G1 in the X-axis direction between the multiple cell trenches 14 and the second interval G2 in the X-axis direction between the multiple protrusions 106 and the first distance 600 between the cell end 32 of the cell trench 14 and the protrusion 106 in the Y-axis direction can be changed as desired. In one example, the sum of the first interval G1 and the second interval G2 is equal to twice the first distance 600. In another example, the sum of the first interval G1 and the second interval G2 is less than twice the first distance 600.

[0183] In the first to third embodiments, the relationship between DCgap500, which is the distance between the cell region 15 and the first outer peripheral trench 70, and the first distance 600 between the cell end 32 of the cell trench 14 and the protrusion 106 in the Y-axis direction, can be changed as desired. In one example, DCgap500 may be equal to the first distance 600. In another example, DCgap500 may be smaller than the first distance 600.

[0184] In the first to third embodiments, the configuration of the cell electrode 56 can be changed as desired. In one example, the cell electrode 56 may not include the gate electrode 58, but may include the first field plate electrode 60. In another example, the cell electrode 56 may not include the first field plate electrode 60, but may include the gate electrode 58.

[0185] In the first to third embodiments, the electrode end 61 of the first field plate electrode 60 may be embedded in the cell trench 14 by an insulating layer different from the cell insulating layer 30. The insulating layer different from the cell insulating layer 30 may be, for example, an insulating layer made of an insulating material different from that of the cell insulating layer 30.

[0186] In the first to third embodiments, the position of the upper end 61A of the electrode end 61 in the Z direction can be changed as desired. In one example, the upper end 61A of the electrode end 61 may be at the same position as the bottom surface 58B of the gate electrode 58 in the Z direction. In another example, the upper end 61A of the electrode end 61 may be located lower than the bottom surface 58B of the gate electrode 58 in the Z direction.

[0187] In the first to third embodiments, the electrode end 61 of the first field plate electrode 60 does not have to be electrically connected to the source wiring 22. In one example, the electrode end 61 of the first field plate electrode 60 may be electrically connected to the gate electrode 58 via the gate wiring 24.

[0188] 17 is an illustrative schematic plan view of a semiconductor device 10 according to a modified example. As shown in FIG. 17 , the gate wiring 24 may include a gate pad 25 disposed at one corner of the semiconductor layer 12 in a plan view, and gate fingers 26 and 27. The gate finger 26 may extend from the gate pad 25 in the X-axis direction and overlap with some of the cell trenches 14 in a plan view. The gate finger 27 may extend from the gate pad 25 in the X-axis direction and overlap with some of the cell trenches 14 in a plan view. The gate pad 25, the gate finger 26, and the gate finger 27 may be integrally formed. One of the gate finger 26 and the gate finger 27 may be connected to the gate electrode 58, and the other may be connected to an electrode end 61 of the first field plate electrode 60. The source wiring 22 may include an inner segment 23 overlapping some of the cell trenches 14, and outer periphery segments 28 and 29 overlapping some of the outer periphery trenches 18. The inner segment 23, outer periphery segments 28, and outer periphery segments 29 may be connected to the gate fingers 26 and 27 at ends opposite the gate pad 25 of the semiconductor device 10 in the X-axis direction, while being spaced apart from each other. The inner segment 23, outer periphery segments 28, and outer periphery segments 29 may be integrally formed. With this configuration, the extent to which the depletion layers extend from the trenches in which the respective electrodes are embedded can be changed depending on the gate voltage. This improves the breakdown voltage of the semiconductor device 10.

[0189] In the second embodiment, the upper end 80A of the second field plate electrode 80 may be embedded in the cell trench 14 by an insulating layer different from the cell insulating layer 30. The insulating layer different from the cell insulating layer 30 may be, for example, an insulating layer made of an insulating material different from that of the cell insulating layer 30.

[0190] In the second embodiment, the position in the Z direction of the upper end 80A of the second field plate electrode 80 can be changed as desired. In one example, the upper end 80A of the second field plate electrode 80 may be located at the same position in the Z direction as the bottom surface 58B of the gate electrode 58. In another example, the upper end 80A of the second field plate electrode 80 may be located lower than the bottom surface 58B of the gate electrode 58 in the Z direction.

[0191] In the second embodiment, the second field plate electrode 80 does not have to be electrically connected to the source wiring 22. In one example, the second field plate electrode 80 may be electrically connected to the gate electrode 58 via the gate wiring 24.

[0192] In the third embodiment, the electrode ends 61 of the upper field plate electrode 84 and the lower field plate electrode 82 do not have to be electrically connected to the source wiring 22. In one example, the electrode ends 61 of the upper field plate electrode 84 and the lower field plate electrode 82 may be electrically connected to the gate electrode 58 via the gate wiring 24.

[0193] 17 may be modified as follows. That is, when one of gate finger 26 and gate finger 27 is connected to gate electrode 58, the other of gate finger 26 and gate finger 27 may be connected to electrode end 61 of lower field plate electrode 82, instead of to electrode end 61 of first field plate electrode 60. With this configuration, the extent to which the depletion layer extends from the trenches in which the respective electrodes are embedded can be changed depending on the gate voltage. This improves the breakdown voltage of semiconductor device 10.

[0194] In the third embodiment, the electrode end 61 of the lower field plate electrode 82 may be embedded in the cell trench 14 by an insulating layer different from the cell insulating layer 30. The insulating layer different from the cell insulating layer 30 may be, for example, an insulating layer made of an insulating material different from that of the cell insulating layer 30.

[0195] In the third embodiment, the position in the Z direction of the upper end 61A of the electrode end 61 of the lower field plate electrode 82 can be changed as desired. In one example, the upper end 61A of the electrode end 61 of the lower field plate electrode 82 may be at the same position in the Z direction as the bottom surface 58B of the gate electrode 58. In another example, the upper end 61A of the electrode end 61 of the lower field plate electrode 82 may be located lower than the bottom surface 58B of the gate electrode 58 in the Z direction.

[0196] In the first to third embodiments, the first outer circumferential extension portion 102 and the connecting portion 105 connecting the first outer circumferential extension portion 102 and the second outer circumferential extension portion 103 may be omitted. As an example, Fig. 18 is a schematic plan view showing an exemplary arrangement pattern of a semiconductor device 10 according to a modified example. As shown in Fig. 18, the first outer circumferential extension portion 102 connecting the protrusions 106 in the X-axis direction may be omitted, and multiple island-shaped protrusions 106 that extend short in the Y-axis direction may be arranged at intervals in the X-axis direction.

[0197] The positional relationship between the cell end 32 and the protrusion 106 in the modified example shown in Fig. 18 is the same as the positional relationship between the cell end 32 and the protrusion 106 in the first embodiment shown in Fig. 12. According to this configuration, the depletion layers extending from both sides are circumscribed by the boundary region 19, thereby improving the breakdown voltage of the semiconductor device 10.

[0198] In the first to third embodiments, the position in the Z direction of the upper end 68A of the peripheral electrode 68 can be changed as desired. In one example, the upper end 68A of the peripheral electrode 68 may be flush with the bottom surface 58B of the gate electrode 58 in the Z direction. In another example, the upper end 68A of the peripheral electrode 68 may be located lower than the bottom surface 58B of the gate electrode 58 in the Z direction.

[0199] In the first to third embodiments, the peripheral electrode 68 does not have to be electrically connected to the source wiring 22. In other words, the peripheral electrode 68 may be electrically connected to the gate electrode 58 via the gate wiring 24.

[0200] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0201] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, the various structures according to this disclosure are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0202] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0203] [Appendix 1] a semiconductor layer (12) including a cell region (15) and a peripheral region (17) surrounding the cell region (15); a plurality of cell trenches (14) provided in the cell region (15), extending in a first direction (Y) when viewed in the thickness direction of the semiconductor layer (12), and spaced apart in a second direction (X) perpendicular to the first direction (Y) in a plan view; a cell insulating layer (30) disposed within the plurality of cell trenches (14); a cell electrode (56) embedded within the cell insulating layer (30); a first outer periphery trench (70) provided in a frame shape so as to surround the plurality of cell trenches (14) in the outer periphery region (17); a peripheral insulating layer (112) provided in the first peripheral trench (70); a peripheral electrode (68) provided in the first peripheral trench (70); Equipped with Each of the plurality of cell trenches (14) includes a cell end (32) that is an end in the first direction (Y), The first outer periphery trench (70) includes a first outer periphery extension portion (102) extending in the second direction (X), The first outer peripheral extension portion (102) is an inner surface (104) facing the cell ends (32) of the plurality of cell trenches (14) and spaced apart in the first direction (Y); a protrusion (106) protruding inward from the inner surface (104); Including, the plurality of cell trenches (14) include a first cell trench (14P) and a second cell trench (14Q) adjacent to each other in the second direction (X), the protrusion (106) is disposed in a portion of the inner side surface (104) between the first cell trench (14P) and the second cell trench (14Q), The peripheral electrode (68) has a protruding electrode (110A) provided within the protruding portion (106). A semiconductor device (10).

[0204] [Appendix 2] The protrusion (106) is located at the center of both the first cell trench (14P) and the second cell trench (14Q) on the inner side surface (104). The semiconductor device (10) according to appendix 1.

[0205] [Appendix 3] The plurality of cell trenches (14) are arranged at a first pitch (P1) in the second direction (X), A first distance (600) between the cell end (32) and the protrusion (106) in the first direction (Y) is smaller than the first pitch (P1). The semiconductor device (10) according to appendix 1 or 2.

[0206] [Appendix 4] The protrusions (106) are arranged in the second direction (X) at a second pitch (P2), A first distance (600) between the cell end (32) and the protrusion (106) in the first direction (Y) is smaller than the second pitch (P2). A semiconductor device (10) according to any one of appendices 1 to 3.

[0207] [Appendix 5] The plurality of cell trenches (14) are arranged at a first pitch (P1) in the second direction (X), The protrusions (106) are arranged in the second direction (X) at a second pitch (P2), The first pitch (P1) is equal to the second pitch (P2). A semiconductor device (10) according to any one of appendices 1 to 4.

[0208] [Appendix 6] The plurality of cell trenches (14) are arranged at first intervals (G1) in the second direction (X), A first distance (600) between the cell end (32) and the protrusion (106) in the first direction (Y) is smaller than the first interval (G1). A semiconductor device (10) according to any one of appendices 1 to 5.

[0209] [Appendix 7] The protrusions (106) are arranged in the second direction (X) at second intervals (G2), A first distance (600) between the cell end (32) and the protrusion (106) in the first direction (Y) is smaller than the second interval (G2). A semiconductor device (10) according to any one of appendices 1 to 6.

[0210] [Appendix 8] The plurality of cell trenches (14) are arranged at first intervals (G1) in the second direction (X), The protrusions (106) are arranged in the second direction (X) at second intervals (G2), The sum of the first distance (G1) and the second distance (G2) is greater than twice the first distance (600), which is the distance between the cell end (32) and the protrusion (106) in the first direction (Y). A semiconductor device (10) according to any one of appendices 1 to 7.

[0211] [Appendix 9] The distance (DCgap (500)) in the first direction (Y) between the cell end (32) and the inner surface (104) is greater than a first distance (600) that is the distance between the cell end (32) and the protrusion (106) in the first direction (Y). A semiconductor device (10) according to any one of appendices 1 to 8.

[0212] [Appendix 10] The cell electrode (56) includes a gate electrode (58) and a first field plate electrode (60); The first field plate electrode (60) is embedded in the cell trench (14) at a position spaced apart from the gate electrode (58) toward the bottom wall (14B) of the cell trench (14) through the cell insulating layer (30). A semiconductor device (10) according to any one of appendices 1 to 9.

[0213] [Appendix 11] the plurality of cell trenches (14) include the cell edges (32); the first field plate electrode (60) includes an electrode end (61) provided at the cell end (32), an upper end (61A) of the electrode end (61) in the trench depth direction is located above a bottom surface (58B) of the gate electrode; The electrode end (61) is embedded through the cell insulating layer (30). The semiconductor device (10) according to appendix 10.

[0214] [Appendix 12] The upper end (68A) of the peripheral electrode (68) in the trench depth direction within the first peripheral trench (70) is located above the bottom surface (58B) of the gate electrode (58) and is embedded via the peripheral insulating layer (112). A semiconductor device (10) according to appendix 10 or 11.

[0215] [Appendix 13] a source wiring (22) provided on the cell insulating layer (30) and the peripheral insulating layer (112); The electrode end (61) of the first field plate electrode (60) is electrically connected to the source wiring (22). 12. The semiconductor device (10) according to claim 11.

[0216] [Appendix 14] a source wiring (22) provided on the cell insulating layer (30) and the peripheral insulating layer (112); The peripheral electrode (68) is electrically connected to the source wiring (22). The semiconductor device (10) according to claim 12.

[0217] [Appendix 15] a gate wiring (24) provided on the cell insulating layer (30); The gate wiring (24) is electrically connected to the gate electrode (58). A semiconductor device (10) according to any one of appendices 10 to 14.

[0218] [Appendix 16] a plurality of peripheral trenches (18) in the peripheral region (17); the peripheral insulating layer (112) provided in each of the plurality of peripheral trenches (18); the peripheral electrodes (68) provided in the plurality of peripheral trenches (18) and embedded in the peripheral insulating layer (112); Equipped with the plurality of perimeter trenches (18) includes the first perimeter trench (70); The first outer circumferential trench (70) is disposed at the innermost periphery of the plurality of outer circumferential trenches (18). A semiconductor device (10) according to any one of appendices 1 to 15.

[0219] [Appendix 17] the cell electrode (56) in the cell trench (14) among the plurality of cell trenches (14) that is located closest to the first outer peripheral trench (70) in the second direction (X) in the plan view includes a second field plate electrode (80) whose upper end (80A) in the trench depth direction is located above a bottom surface of the gate electrode (58); The second field plate electrode (80) is embedded through the cell insulating layer (30). A semiconductor device (10) according to any one of appendices 10 to 15.

[0220] [Appendix 18] the cell electrode (56) in the cell trench (14) among the plurality of cell trenches (14) that is located closest to the first outer peripheral trench (70) in the second direction (X) in the plan view includes an upper field plate electrode (84) and a lower field plate electrode (82); The upper field plate electrode (84) is embedded at a position spaced apart from the lower field plate electrode (82) through the cell insulating layer (30). A semiconductor device (10) according to any one of appendices 10 to 15.

[0221] [Appendix 19] the plurality of cell trenches (14) include the cell edges (32); the lower field plate electrode (82) includes an electrode end (61) provided at the cell end (32); an upper end (61A) of the electrode end (61) in the trench depth direction is located above a bottom surface (58B) of the gate electrode (58); The electrode end (61) is embedded through the cell insulating layer (30). 19. The semiconductor device (10) according to claim 18.

[0222] [Appendix 20] a source wiring (22) provided on the cell insulating layer (30) and the peripheral insulating layer (112); The second field plate electrode (80) is electrically connected to the source wiring (22). 18. The semiconductor device (10) according to claim 17.

[0223] [Appendix 21] a source wiring (22) provided on the cell insulating layer (30) and the peripheral insulating layer (112); The electrode ends (61) of the upper field plate electrode (84) and the lower field plate electrode (82) are electrically connected to the source wiring (22). The semiconductor device (10) according to Appendix 19.

[0224] [Appendix 22] a source wiring (22) provided on the cell insulating layer (30) and the peripheral insulating layer (112); the plurality of cell trenches (14) include the cell edges (32); the first field plate electrode (60) includes an electrode end (61) provided at the cell end (32), At least one of the first field plate electrode (60), the electrode end (61) of the first field plate electrode (60), the second field plate electrode (80), and the peripheral electrode (68) is configured to be given a potential different from the potential of the source wiring (22). 18. The semiconductor device (10) according to claim 17.

[0225] [Appendix 23] a source wiring (22) provided on the cell insulating layer (30) and the peripheral insulating layer (112); At least one of the lower field plate electrode (82), the electrode end (61) of the lower field plate electrode (82), the upper field plate electrode (84), and the peripheral electrode (68) is configured to be given a potential different from the potential of the source wiring (22). The semiconductor device (10) according to Appendix 19.

[0226] [Appendix 24] the plurality of cell trenches (14) include the cell edges (32); The first field plate electrode (60) includes an electrode end (61) provided at the cell end (32), and the electrode end (61) of the first field plate electrode (60) is electrically connected to the gate electrode (58) via a gate wiring (24). 18. The semiconductor device (10) according to claim 17.

[0227] [Appendix 25] The upper field plate electrode (84) and the electrode end (61) are electrically connected to the gate electrode (58) via the gate wiring (24). The semiconductor device (10) according to Appendix 19.

[0228] [Appendix 26] a semiconductor layer (12) including a cell region (15) and a peripheral region (17) surrounding the cell region (15); a plurality of cell trenches (14) provided in the cell region (15), extending in a first direction (Y) when viewed in the thickness direction of the semiconductor layer (12), and spaced apart in a second direction (X) perpendicular to the first direction (Y) in a plan view; a cell insulating layer (30) disposed within the plurality of cell trenches (14); a cell electrode (56) embedded within the cell insulating layer (30); a first outer periphery trench (70) provided in the outer periphery region (17) so as to surround the plurality of cell trenches (14); a peripheral insulating layer (112) provided in the first peripheral trench (70); a peripheral electrode (68) provided in the first peripheral trench (70); Equipped with Each of the plurality of cell trenches (14) includes a cell end (32) that is an end in the first direction (Y), The first outer circumferential trench (70) includes a plurality of protrusions (106) spaced apart in the second direction (X), The plurality of protrusions (106) are spaced apart from the cell ends (32) of the plurality of cell trenches (14) in the first direction (Y), the plurality of cell trenches (14) include a first cell trench (14P) and a second cell trench (14Q) adjacent to each other in the second direction (X), the plurality of protrusions (106) include a first protrusion (106P) and a second protrusion (106Q) adjacent to each other in the second direction (X), the first protrusion (106P) is disposed in a portion between the first cell trench (14P) and the second cell trench (14Q) in the outer circumferential region (17), the second cell trench (14Q) is disposed in a portion between the first protrusion (106P) and the second protrusion (106Q) in the cell region (15); The peripheral electrode (68) has a protruding electrode (110A) provided within the protruding portion (106). A semiconductor device (10).

[0229] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0230] 10, 11...Semiconductor device 12...Semiconductor layer 12A…Top surface 12B…Bottom surface 14...Cell trench 14A…Side wall 14B…Bottom wall 14P...1st cell trench 14Q...Second cell trench 14Y, 14Z...End cell trench 15...Cell area 16...Insulating layer 17...Outer area 18...Periphery trench 18A…Side wall 18B…Bottom wall 19…boundary area 20...Source region 22...Source wiring 23...medial segment 24...Gate wiring 25...Gate pad 26,27...Gate finger 28, 29...periphery segments 30...Cell insulating layer 30A...First field insulation layer 30B...First electrode end field insulating layer 30C...Second electrode end field insulating layer 30D: Second field insulating layer 30E...Lower field insulation layer 32...Cell edge 40...Semiconductor substrate 42...Epitaxial layer 44...Drift region 46...Body area 50...Drain wiring 56...Cell electrode 58...Gate electrode 58A…Top surface 58B…Bottom surface 58C…side 60...First field plate electrode 61...Electrode end 61A…Top end 62...Source Contact 64...Contact area 66...Gate insulation 68...Outer electrode 68A…Top end 70...First outer perimeter trench 70A…Side wall 70B…Bottom wall 72...Second outer perimeter trench 78...Field plate contact 80...Second field plate electrode 80A…Top end 82...Lower field plate electrode 82A…Top surface 82B…Bottom surface 84...Upper field plate electrode 84A…Top surface 84B...Bottom 99…Active area 101...Inactive area 102...First outer circumference extension part 103…Second outer peripheral extension part 104...Inner surface 105...Connection 106...Protrusion 106A…Side wall 106B…Bottom wall 106P…1st protrusion 106Q…Second protrusion 110...Electrode body part 110A…Protruding electrode 112...Outer insulating layer 112A...Protruding insulating layer 112B...Peripheral field insulating layer 112C...First protruding field insulating layer 112D...Second protruding field insulating layer 114...p-type region 300,400…Undepleted region 500…DCgap 600…1st distance G1: First interval G2…Second interval P1...First pitch P2: Second pitch DL1~DL3… Depletion Layer

Claims

1. a semiconductor layer including a cell region and a peripheral region surrounding the cell region; a plurality of cell trenches provided in the cell region, extending in a first direction as viewed in a thickness direction of the semiconductor layer, and spaced apart in a second direction perpendicular to the first direction in a plan view; a cell insulating layer disposed within the plurality of cell trenches; a cell electrode embedded within the cell insulating layer; a first outer periphery trench provided in a frame shape so as to surround the plurality of cell trenches in the outer periphery region; a peripheral insulating layer disposed in the first peripheral trench; a peripheral electrode provided in the first peripheral trench; Equipped with each of the plurality of cell trenches includes a cell end portion that is an end portion in the first direction; the first outer periphery trench includes a first outer periphery extension portion extending in the second direction, The first outer circumferential extension portion is inner surfaces of the cell trenches facing the cell ends and spaced apart in the first direction; a protrusion protruding inward from the inner surface; Including, the plurality of cell trenches include a first cell trench and a second cell trench adjacent to each other in the second direction, the protrusion is disposed in a portion of the inner surface between the first cell trench and the second cell trench, The peripheral electrode has a protruding electrode provided within the protruding portion. Semiconductor device.

2. The protrusion is located at the center of the first cell trench and the second cell trench on the inner side surface. The semiconductor device according to claim 1 .

3. the plurality of cell trenches are arranged at a first pitch in the second direction; a first distance between the cell end and the protrusion in the first direction, the first distance being smaller than the first pitch; The semiconductor device according to claim 1 .

4. The protrusions are arranged in plurality at a second pitch in the second direction, a first distance between the cell end and the protrusion in the first direction, the first distance being smaller than the second pitch; The semiconductor device according to claim 1 .

5. the plurality of cell trenches are arranged at a first pitch in the second direction; The protrusions are arranged in plurality at a second pitch in the second direction, The first pitch is equal to the second pitch. The semiconductor device according to claim 1 .

6. the plurality of cell trenches are arranged at first intervals in the second direction; a first distance between the cell end and the protrusion in the first direction, the first distance being smaller than the first interval; The semiconductor device according to claim 1 .

7. The protrusions are arranged in plurality at second intervals in the second direction, a first distance between the cell end and the protrusion in the first direction, the first distance being smaller than the second distance; The semiconductor device according to claim 1 .

8. the plurality of cell trenches are arranged at first intervals in the second direction; The protrusions are arranged in plurality at second intervals in the second direction, The sum of the first distance and the second distance is greater than twice the first distance, which is the distance between the cell end and the protrusion in the first direction. The semiconductor device according to claim 1 .

9. The distance in the first direction between the cell end and the inner side surface is greater than a first distance that is a distance between the cell end and the protrusion in the first direction. The semiconductor device according to claim 1 .

10. the cell electrodes include a gate electrode and a first field plate electrode; The first field plate electrode is embedded in the cell trench at a position spaced apart from the gate electrode and closer to the bottom wall of the cell trench, with the cell insulating layer interposed therebetween. The semiconductor device according to any one of claims 1 to 9.

11. the plurality of cell trenches include the cell edges; the first field plate electrode includes an electrode edge provided at the cell edge, an upper end of the electrode end in the trench depth direction is located above a bottom surface of the gate electrode, The electrode end is embedded through the cell insulating layer. The semiconductor device according to claim 10.

12. The upper end of the peripheral electrode in the first peripheral trench in the trench depth direction is located above the bottom surface of the gate electrode and is embedded via the peripheral insulating layer. The semiconductor device according to claim 10.

13. a source wiring provided on the cell insulating layer and the peripheral insulating layer; The electrode end of the first field plate electrode is electrically connected to the source line. The semiconductor device according to claim 11.

14. a source wiring provided on the cell insulating layer and the peripheral insulating layer; The peripheral electrode is electrically connected to the source wiring. The semiconductor device according to claim 12.

15. a plurality of perimeter trenches in the perimeter region; the peripheral insulating layer provided in each of the plurality of peripheral trenches; the peripheral electrodes provided in the plurality of peripheral trenches and embedded in the peripheral insulating layer; Equipped with the plurality of perimeter trenches includes the first perimeter trench; The first outer periphery trench is disposed on the innermost periphery of the plurality of outer periphery trenches. The semiconductor device according to claim 1 .

16. the cell electrode in the cell trench that is located closest to the first outer peripheral trench in the second direction in the plan view among the plurality of cell trenches includes a second field plate electrode whose upper end in the trench depth direction is located above a bottom surface of the gate electrode, The second field plate electrode is embedded through the cell insulating layer. The semiconductor device according to claim 10.

17. the cell electrode in a cell trench among the plurality of cell trenches that is located closest to the first outer peripheral trench in the second direction in the plan view includes an upper field plate electrode and a lower field plate electrode; The upper field plate electrode is embedded at a position spaced apart from the lower field plate electrode via the cell insulating layer. The semiconductor device according to claim 10.

18. the plurality of cell trenches include the cell edges; the lower field plate electrode includes an electrode edge provided at the cell edge, an upper end of the electrode end in the trench depth direction is located above a bottom surface of the gate electrode, The electrode end is embedded through the cell insulating layer.

18. The semiconductor device according to claim 17.

19. a source wiring provided on the cell insulating layer and the peripheral insulating layer; The second field plate electrode is electrically connected to the source line. The semiconductor device according to claim 16.

20. a source wiring provided on the cell insulating layer and the peripheral insulating layer; The electrode ends of the upper field plate electrode and the lower field plate electrode are electrically connected to the source wiring.

19. The semiconductor device according to claim 18.

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