MEMORY SYSTEM, METHOD FOR RESETTING A MEMORY SYSTEM, AND ELECTRONIC DEVICE -

Abstract

To provide a memory system, a power protection device, and a method for resetting the memory system.SOLUTION: The present disclosure relates to a method and apparatus for power loss protection in a memory system. In one example, a memory system includes a memory device, a controller, a power loss protection (PLP) circuit, and a protection circuit. The controller is coupled to the memory device. A reset terminal of the controller is coupled to the capacitor. The protection circuit is coupled to the controller and the PLP circuit. The protection circuit is configured to receive the PLP output voltage from the PLP circuit, receive a system supply voltage, and provide a reset signal to a reset terminal of the controller in response to determining that the PLP output voltage is less than a portion of the system supply voltage.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates generally to memory devices and memory systems, and more particularly to power loss protection and reset signal generation in memory systems. [Background technology]

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. The growing demands of consumer electronics, cloud computing, and big data are constantly driving the need for larger-capacity, higher-performance flash memory. Today's flash memory devices, such as solid-state drives (SSDs) and SSD expansion drives, have been designed with stringent performance and reliability requirements. Power outages can potentially damage memory devices, corrupt data stored in them, and affect their performance and reliability. Therefore, most memory devices require a power loss protection (PLP) mechanism. Summary of the Invention [Means for solving the problem]

[0003] The present disclosure relates to a method and apparatus for power loss protection (PLP) in a memory system. In one example, the memory system includes a memory device, a controller, a power management integrated circuit (PMIC), and a protection circuit. The controller is coupled to the memory device. A reset terminal of the controller is coupled to a capacitor. The protection circuit is coupled to the controller and the PMIC. The protection circuit is configured to receive a PLP output voltage from the PMIC, receive a system supply voltage, and provide a reset signal to the reset terminal of the controller in response to determining that the PLP output voltage is lower than a fraction of the system supply voltage.

[0004] While generally described as computer-implemented software embodied in a tangible medium that processes and transforms respective data, some or all of the aspects may also be computer-implemented methods or may further be included in respective systems or other devices for performing the described functions. Details of these and other aspects and embodiments of the present disclosure are set forth in the accompanying drawings and the description that follows. Other features, objects, and advantages of the present disclosure will be apparent from the description and drawings, and from the claims. [Brief explanation of the drawings]

[0005] [Figure 1] 1 illustrates an example block diagram of a system having a memory system in accordance with some aspects of the present disclosure. [Figure 2A] 1 illustrates an exemplary storage device according to some aspects of the present disclosure. [Figure 2B] 1 illustrates an exemplary storage device according to some aspects of the present disclosure. [Figure 3] 1 illustrates a block diagram of an example protection circuit according to some aspects of the present disclosure. [Figure 4] 4 illustrates example waveforms of a system supply voltage, a power loss protection (PLP) output voltage, and a reset signal generated by the protection circuit of FIG. 3 in accordance with some aspects of the present disclosure. [Figure 5] 1 illustrates a flowchart of an exemplary method for resetting a memory system in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] Like reference numbers and designations in the various drawings indicate like elements.

[0007] Power outages, typically caused by battery malfunctions, power outages, or accidental removal of a device from a computer, can damage memory devices and potentially corrupt data stored on them unless an effective power loss protection (PLP) mechanism is in place. Non-volatile memory devices, such as solid-state drives (SSDs), can use temporary buffers (e.g., volatile memory) when writing data to non-volatile storage media. An unexpected power loss while accessing the temporary buffer can cause data corruption or data loss, or even render the memory device unusable. Therefore, SSDs can be vulnerable to unexpected power outages.

[0008] During a normal power-off procedure, the SSD's host can notify the SSD that the power is about to be shut down, allowing the SSD sufficient time to prepare for power-off. Preparation can include a series of operations performed by both the SSD's controller and the SSD's NAND memory. For example, the controller can flush data from volatile memory, such as dynamic random access memory (DRAM), to the NAND memory. The controller can also update a mapping table that records the mapping relationship between logical addresses and physical addresses. In addition, the SSD can store its current status in several flag registers. After these operations, the SSD can send a signal to the host indicating that it is ready to power off. Upon receiving the instruction signal from the SSD, the host can shut off the power.

[0009] In the event of an unexpected power outage, the SSD can rely on the PLP mechanism to provide hold-up power, allowing the controller and the SSD's NAND memory to perform the operations described above to safely preserve data and operational state. A typical PLP mechanism uses a special energy storage device, such as a battery or capacitor, to power the SSD for a sufficient period of time if the SSD's power source is suddenly removed.

[0010] When the SSD is powered back on, the controller can receive a reset signal from a power management integrated circuit (PMIC) to a reset terminal of the controller. In some implementations, the reset signal is a voltage signal that triggers the controller to start operating when the voltage is high. That is, the controller stops operating when the voltage level of the reset terminal falls below a reset threshold and starts operating when the voltage level of the reset terminal rises above the reset threshold. Because proper functioning of the controller may require other devices to be ready, the SSD may need to precisely coordinate the timing of activating the controller with some other devices in the SSD. For example, the other devices may need to finish their preparatory operations or receive power before the controller can start.

[0011] For this purpose, the reset terminal of the controller may be coupled to ground via a capacitor. The capacitor serves to create a power-on delay for the controller, as described below. During a normal power-on procedure, before receiving a reset signal, the reset terminal is held at a low voltage level, approximately 0 volts (V). When the reset terminal receives a high voltage level reset signal, the reset signal charges the capacitor, causing the voltage level at the reset terminal to increase from a low level to a high level. The time it takes for the voltage level at the reset terminal to rise from a low level to the reset threshold that triggers the controller to start up can be referred to as the power-on delay. The power-on delay should be long enough to meet the above-mentioned regulation requirements (so that other devices in the SSD can prepare and become ready before the controller starts up).

[0012] However, the power-on delay may not meet the regulation requirements during an unexpected power outage, which may lead to malfunction of the SSD's controller. When the power supply is removed or becomes unstable, the PMIC can still provide a reset signal to the controller's reset terminal due to holdup power generated by the PLP mechanism. Therefore, the capacitor coupled to the reset terminal can still hold a voltage, which may be significantly higher than 0 V. The reset signal charges the capacitor from that voltage when the power supply returns to a stable level. Compared to a normal power-on procedure in which the reset signal charges the capacitor from approximately 0 V, the power-on delay during the reset procedure caused by a power outage is shortened and therefore may not be sufficient to regulate the startup of the controller and other devices in the SSD.

[0013] The present disclosure provides techniques for a memory system to delay proper power-on of a controller of the memory system using a protection circuit. The protection circuit is configured to receive a PLP output voltage and a system supply voltage from a PMIC. The protection circuit can compare the PLP output voltage with the system supply voltage and provide a reset signal to the controller if the protection circuit determines that the PLP output voltage is lower than a fraction of the system supply voltage. The above and several other aspects of the present disclosure are described in more detail below.

[0014] FIG. 1 illustrates an example block diagram of a system 100 having a memory system 102 in accordance with some aspects of the present disclosure. As shown in FIG. 1, the system 100 may include a host 114 and a memory system 102 having one or more memory devices 106 and a controller 104. The memory system 102 further includes a DRAM 108, a PMIC 110, and a protection circuit 112. In some implementations, the memory system 102 is an SSD. The host 114 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 114 may be configured to send and receive data to and from the memory device 106.

[0015] According to some embodiments, the controller 104 is coupled to the memory device 106 and the host 114 and configured to control the memory device 106. The controller 104 can manage data stored in the memory device 106 and communicate with the host 114. In some embodiments, the controller 104 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the controller 104 is designed to operate in high-duty-cycle environments, such as mobile devices, such as smartphones, tablets, and laptop computers, and solid-state drives (SSDs) or embedded multimedia cards (eMMCs) used as data storage in enterprise storage arrays. The controller 104 can be configured to control operations of the memory device 106, such as read, erase, and program operations. The controller 104 may also be configured to manage various functions related to data stored in or to be stored in the memory device 106, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the controller 104 is further configured to process error correction codes (ECC) on data read from or written to the memory device 106. Any other suitable functions, such as formatting the memory device 106, may also be performed by the controller 104. The memory device 106 may be a NAND flash memory or any of the memory devices disclosed in this disclosure. It may be a memory device.

[0016] In some implementations, memory system 102 does not include controller 104, and host 114 is directly coupled to memory device 106. Controller 104 may be located on host 114. Alternatively, host 114 may not include controller 104 and may be configured to perform similar functions as controller 104, as described above.

[0017] The controller 104 includes one or more processors 116, a host interface 118, a memory interface 120, a cache 122, and a DRAM controller 124. The controller 104 can communicate with an external device (e.g., the host 114) according to a particular communication protocol. As shown in FIG. 1 , the processor 116 is coupled to the host 114 via the host interface 118. The host interface 118 enables the controller 104 to communicate with the external device via at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0018] The processor 116 may be coupled to the memory device 106 via a memory interface 120 and configured to control the memory device 106. The processor 116 may be coupled to a cache 122 and a DRAM controller 124. The cache 122 may be configured to store temporary information. The DRAM controller 124 may be configured to access the information store in the DRAM 108.

[0019] The PMIC 110 includes a PLP circuit configured to provide a PLP mechanism. The PLP circuit can be configured to provide a stable output voltage when the system supply voltage is lost. In some implementations, the PMIC 110 is a PLP circuit integrated with several other power management-related circuits. In some implementations, the PMIC 110 is a single PLP circuit configured to provide PLP-related functions, with other power management functions provided by separate power management circuits. Both the PMIC 110 (also referred to as the PLP circuit 110) and the protection circuit 112 receive a system supply voltage 126. The PMIC 110 is configured to generate a PLP output voltage 128 to the controller 104 and the protection circuit 112. The protection circuit is configured to provide a reset signal 130 to a reset terminal 132 of the controller 104.

[0020] The controller 104 and one or more memory devices 106 can be integrated into various types of storage devices, such as in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged in different types of final electronic products. In one example shown in FIG. 2A , the controller 104 and a single memory device 106 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS card, etc. The memory card 202 further includes a memory card connector 204 that couples the memory card 202 to a host (e.g., host 114 of FIG. 1 ). 2B , the controller 104 and the plurality of memory devices 106 may be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 114 of FIG. 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than that of the memory card 202.

[0021] FIG. 3 shows a block diagram of an exemplary protection circuit 112 according to some aspects of the disclosure. The protection circuit 112 includes a comparator 304 having inputs 306 and 308 and an output 310. One of the inputs 306 and 308 is coupled to the PLP output voltage 128 from the PMIC 110, and the other is coupled to the system supply voltage 126. In some implementations, the input 306 is a non-inverting input, and the input 308 is an inverting input. As shown in FIG. 3, the comparator 304 may also be powered by the system supply voltage 126. The output 310 of the comparator 304 is coupled to the reset terminal 132 of the controller 104. As mentioned above, the capacitor 302 is coupled between the reset terminal 132 and ground and is configured to assist in delaying the power-on of the controller 104.

[0022] In some implementations, input 306 may be coupled to PLP output voltage 128 through a current-limiting resistor 312. Input 308 may be coupled to system supply voltage 126 through a voltage divider. That is, the voltage divider divides the system supply voltage 126 and outputs a portion of the system supply voltage 126 to input 308. The voltage divider may include two or more resistors. For example, as shown in FIG. 3 , the voltage divider includes resistor 314 and resistor 316. Resistor 314 is coupled between input 308 and system supply voltage 126, and resistor 316 is coupled between input 308 and ground.

[0023] Protection circuit 112 is configured to compare PLP output voltage 128 to system supply voltage 126 and provide reset signal 130 in response to determining that PLP output voltage 128 is less than a fraction of system supply voltage 126. The fraction of system supply voltage 126 is determined based on a voltage divider. In the example of FIG. 3, the fraction is on the order of the resistance of resistor 316 divided by the sum of the resistances of resistors 314 and 316.

[0024] In some implementations, the voltage divider is configured to generate a portion of the system supply voltage 126 such that the portion of the system supply voltage 126 is lower than the PLP output voltage 128 when the system supply voltage 126 is within a suitable operating range.

[0025] In some implementations, the comparator 304 is an open-drain comparator, i.e., the output 310 of the comparator 304 is further coupled to ground in response to determining that the PLP output voltage 128 is less than a portion of the system supply voltage 126.

[0026] In some implementations, upon determining that the PLP output voltage 128 is lower than a fraction of the system supply voltage 126, the protection circuit 112 is configured to hold the reset signal below the reset threshold voltage level for a period of time. This period of time may be referred to as a power-on delay for the controller 104, and may be increased or decreased by adjusting at least one of the two or more resistors in the voltage divider.

[0027] The controller 104 may receive a voltage input 318. The voltage input 318 is coupled to a reset terminal 132 via a resistor 320 disposed within the controller 104. In some implementations, the resistor 320 is a pull-up resistor. In response to determining that the PLP output voltage 128 is higher than a portion of the system supply voltage 126, the protection circuit 112 is configured to output a resistance high enough so that the voltage at the reset terminal 132 is close to the voltage input 318. The voltage at the reset terminal 132 is higher than the voltage input 318. The voltage drop between the voltage input 318 and the voltage at the reset terminal 132 is determined by the resistance of the resistor 320 and the current through the resistor 320. The voltage input 318 is configured to pull the voltage at the reset terminal 132 to a higher level (higher than the reset threshold of the controller 104) so ​​that the controller 104 continues to operate.

[0028] In some implementations, comparator 304 may be any suitable type of comparator, such as an operational amplifier (op-amp) comparator or a push-pull comparator. Any suitable modifications to the described protection circuitry apparent to one skilled in the art may be applied.

[0029] In some implementations, the capacitor 302 may be located either inside or outside the protection circuit 112 .

[0030] In some implementations, the protection circuitry 112 may be integrated into the PMIC 110 .

[0031] FIG. 4 illustrates exemplary waveforms of the system supply voltage 126, the PLP output voltage 128, and the reset signal 130 generated by the protection circuit 112 of FIG. 3 in accordance with some embodiments of the present disclosure. Waveform 400 is the waveform of the reset signal 130 before, during, and after a power outage. Waveforms 402 and 404 are the waveforms of the PLP output voltage 128 and the system supply voltage 126, respectively, under the same scenario. As shown in FIG. 4, a power outage occurs at time 406. Before time 406, the system supply voltage is close to 5 V under normal operating conditions. At time 406, a power outage occurs, causing the system supply voltage to drop to a value close to 0 V. In some implementations, the system supply voltage may even oscillate, as shown in waveform 404 of FIG. 4. The PLP output voltage is close to the system supply voltage before the power outage. When the system supply voltage is lost, the PMIC activates the PLP mechanism and continues to supply the PLP output voltage at a level close to 5 V. The PLP output voltage may drop slightly but still maintain a relatively high level (e.g., 4.26 V). As mentioned above, the PLP output voltage at 4.26V is the hold-up power. In some embodiments, the hold-up power during a power failure is generated by the PMIC's internal buck circuit and energy storage capacitor.

[0032] In this example, resistor 314 has a resistance of 10 kOhms (Ω) and resistor 316 has a resistance of 40.2 kΩ. Thus, the divided system supply voltage applied at input 308 is close to 4V when the system supply voltage is approximately 5V.

[0033] Sometime later, before time 408, the system supply voltage resumes and returns to normal (approximately 5V). At time 408, the PMIC's energy storage capacitor is depleted and therefore the PLP output voltage begins to decrease.

[0034] Between time 406 and time 408, the system supply voltage is unstable due to power loss, and therefore, the portion of the system supply voltage also varies (between 0 V and 4 V). During this period, the PLP output voltage applied to input 306 (4.26 V) is always higher than the maximum value of the portion of the system supply voltage applied to input 308 (which is 4 V). Therefore, output 310 can be treated as a sufficiently large resistor connecting reset terminal 132 to ground. As a result, the voltage at reset terminal 132 is pulled up to voltage input 318 in FIG. 3. For example, if voltage input 318 is 3.3 V and pull-up resistor 320 has a resistance of 58 kΩ, the voltage at the reset terminal is approximately 3.1 V, which is higher than the reset threshold 412 (e.g., 3 V) of the controller. Therefore, even though the system supply voltage is unstable between time 406 and time 408, the hold-up power provided by the PLP mechanism of the PMIC and the reset signal provided by the protection circuitry will ensure that the controller and memory device are properly powered. This allows the system to operate properly and perform the necessary operations to safely preserve data and operational state.

[0035] After time 408, the PLP output voltage applied to input 306 drops rapidly to approximately 0 V, which is lower than the fraction of the system supply voltage applied at input 308 (which is 4 V). Thus, output 310 generated by protection circuit 112 pulls the voltage at reset terminal 132 to ground (approximately 0 V). Controller 104 stops operating because the voltage at reset terminal 132 is lower than the reset threshold 412 (e.g., 3 V) of controller 104. The energy stored in capacitor 302 is also released.

[0036] After the PLP output voltage 128 drops to 0 V, the PMIC can detect that the system supply voltage 126 has resumed its normal level (approximately 5 V) and can therefore connect the PLP output voltage 128 to the system supply voltage 126. The PLP output voltage 128 applied to the input 306 also quickly returns to approximately 5 V, higher than the portion of the system supply voltage applied at the input 308 (which is 4 V). Therefore, the output 310 can be treated as a sufficiently large resistor connecting the reset terminal 132 to ground. In this case, the voltage input 318 begins to charge the capacitor 302, causing the voltage at the reset terminal 132 to rise from approximately 0 V to approximately 3.1 V (pulled up by the voltage input 318). At time 410, the voltage at the reset terminal 132 rises to the reset threshold 412 (3 V), and the controller 104 begins operating. The period 414 between times 408 and 410 is a delay in powering on the controller 104. In this example, the period 414 is approximately 50 ms, which is long enough to coordinate the activation of the controller 104 and other devices in the memory system.

[0037] Without the protection circuit 112, the reset signal 130 may not drop below the reset threshold 412 or may drop to a level significantly higher than 0V, which would result in a much shorter power-on delay (compared to the period 414) and cause the controller 104 to malfunction.

[0038] 5 is a flowchart of an example method 500 for resetting a memory system according to some aspects of the present disclosure. Method 500 may be performed by any suitable device disclosed herein, such as memory system 102, controller 104, memory device 106, PMIC 110, and protection circuit 112 of FIG. 1, and any combination thereof. The operations illustrated in method 500 may not be all-inclusive, and other operations may be performed before, after, or between any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 5.

[0039] At 502, a protection circuit (e.g., protection circuit 112) of a memory system (e.g., memory system 102) receives a PLP output voltage from a PMIC (e.g., PMIC 110) of the memory system. For example, the PLP output voltage can vary between 4.26V and 5V.

[0040] At 504, the protection circuit receives a system supply voltage. An example system supply voltage is 5V.

[0041] At 506, in response to determining that the PLP output voltage of the PMIC is lower than a portion of the system supply voltage, the protection circuit provides a reset signal to a reset terminal of a controller (e.g., controller 104) of the memory system, the controller being coupled to the memory device and the reset terminal of the controller being coupled to the capacitor.

[0042] In some embodiments, a capacitor is coupled between the reset terminal of the controller and ground, with an example capacitance of 680 nF.

[0043] In some embodiments, the protection circuit comprises a comparator, a first input of the comparator coupled to the PLP output voltage, a second input of the comparator coupled to a portion of the system supply voltage, and an output of the comparator coupled to a reset terminal of the controller.

[0044] In some embodiments, the comparator is an open-drain comparator, and the output of the comparator is further coupled to ground in response to determining that the PLP output voltage is less than a portion of the system supply voltage.

[0045] In some implementations, the first input of the comparator is coupled to the PLP output voltage through a current-limiting resistor, an exemplary resistance of which is 10 kΩ.

[0046] In some implementations, the second input of the comparator is coupled to a system supply voltage through a voltage divider comprising two or more resistors, the voltage divider being configured to generate a portion of the system supply voltage that is lower than the PLP output voltage in response to at least the system supply voltage being within a suitable operating range. For example, one resistor of the voltage divider may have a resistance of 10 kΩ and another resistor may have a resistance of 40.2 kΩ.

[0047] In some implementations, the protection circuit is configured to hold the reset signal below a reset threshold voltage level for a period of time, which is increased or decreased by adjusting at least one of the two or more resistors of the voltage divider. An example reset threshold voltage is 3V.

[0048] In some implementations, the controller performs one or more initialization operations on the memory device upon receiving the reset signal.

[0049] In some implementations, the controller receives the system supply voltage as a power source.

[0050] In some embodiments, the controller receives a second voltage input. The second voltage input is coupled to the reset terminal through a pull-up resistor disposed within the controller. The second voltage input and the pull-up resistor are configured to pull the voltage at the reset terminal above the reset threshold voltage. An example of the second voltage input is 3.3V. An example of the pull-up resistor is 58kΩ.

[0051] While this specification contains details of many specific embodiments, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be unique to particular embodiments. Certain features described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented in multiple embodiments, separately, or in any subcombination. Furthermore, while the foregoing features may be described as working in a particular combination and may even initially be claimed as such, one or more features from a claimed combination can, in some cases, be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0052] As used in this disclosure, the terms "a," "an," or "the" are used to include one or more, unless the context clearly dictates otherwise. The term "or" is used to refer to a non-exclusive "or" unless otherwise specified. The phrase "at least one of A and B" is synonymous with "A, B, or A and B." Additionally, phrases or terms used in this disclosure, unless otherwise defined, are for descriptive purposes only and not for limiting purposes. The use of any section headings is intended to aid in the reading of the document and should not be construed as limiting. Information associated with a section heading may occur within or outside that particular section.

[0053] As used in this disclosure, the term "about" or "approximately" can allow for some variation in a value or range, for example, within 10%, within 5%, or within 1% of a stated value or the limits of a stated range.

[0054] As used in this disclosure, the term "substantially" refers to a majority or majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0055] Values ​​expressed in range format should be interpreted flexibly to include not only the numerical values ​​explicitly recited as the limits of the range, but also all individual numerical values ​​or subranges subsumed within that range, as if each numerical value and subrange were explicitly recited. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the recited range. The term "X to Y" is equivalent to "about X to about Y" unless otherwise specified. Similarly, the term "X, Y, or Z" is equivalent to "about X, about Y, or about Z" unless otherwise specified.

[0056] Specific embodiments of the present subject matter have been described. Other embodiments, modifications, and permutations of the described embodiments, as will be apparent to those skilled in the art, are within the scope of the following claims. Although operations may be shown in the drawings or claims in a particular order, such operations need not be performed in the particular order shown, or in sequential order, to achieve desirable results, or even that all of the operations shown be performed (although some operations may be considered optional). In particular situations, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and performed as deemed appropriate.

[0057] Furthermore, the separation or integration of the various system modules and components in the foregoing embodiments may not be required in all embodiments, and the described components and systems may generally be integrated together or packaged into multiple products.

[0058] Accordingly, the foregoing exemplary embodiments do not define or limit the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

[0059] According to one aspect of the present disclosure, a memory system is disclosed, the memory system including: a memory device; a controller coupled to the memory device, wherein a reset terminal of the controller is coupled to a capacitor; a PMIC; and a protection circuit coupled to the controller and the PMIC. The protection circuit is configured to receive a PLP output voltage from the PMIC, receive a system supply voltage, and provide a reset signal to the reset terminal of the controller in response to determining that the PLP output voltage is lower than a fraction of the system supply voltage.

[0060] In some implementations, a capacitor is coupled between the reset terminal of the controller and ground.

[0061] In some embodiments, the protection circuit comprises a comparator, a first input of the comparator coupled to the PLP output voltage, a second input of the comparator coupled to a portion of the system supply voltage, and an output of the comparator coupled to a reset terminal of the controller.

[0062] In some embodiments, the comparator is an open-drain comparator, and the output of the comparator is further coupled to ground in response to determining that the PLP output voltage is less than a portion of the system supply voltage.

[0063] In some embodiments, the first input of the comparator is coupled to the PLP output voltage through a current-limiting resistor.

[0064] In some implementations, the second input of the comparator is coupled to the system supply voltage via a voltage divider comprising two or more resistors, the voltage divider configured to generate a portion of the system supply voltage that is lower than the PLP output voltage in response to at least the system supply voltage being within a suitable operating range.

[0065] In some implementations, the protection circuit is configured to hold the reset signal below the reset threshold voltage level for a period of time, the period of time being increased or decreased by adjusting at least one of the two or more resistors of the voltage divider.

[0066] In some implementations, the controller performs one or more initialization operations on the memory device upon receiving the reset signal.

[0067] In some implementations, the controller receives the system supply voltage as a power source.

[0068] In some implementations, the controller receives a second voltage input coupled to the reset terminal through a pull-up resistor disposed within the controller, the second voltage input and the pull-up resistor configured to pull the voltage at the reset terminal above a reset threshold voltage.

[0069] According to another aspect of the present disclosure, a power protection device is disclosed. The power protection device includes a controller, wherein a reset terminal of the controller is coupled to a capacitor, a PMIC, and a protection circuit coupled to the controller and the PMIC. The protection circuit includes a comparator configured to receive a PLP output voltage of the PMIC, receive a system supply voltage, and provide a reset signal to the reset terminal of the controller in response to determining that the PLP output voltage of the PMIC is lower than a fraction of the system supply voltage. A first input of the comparator is coupled to the PLP output voltage. A second input of the comparator is coupled to the fraction of the system supply voltage. An output of the comparator is coupled to the reset terminal of the controller.

[0070] In some implementations, a capacitor is coupled between the reset terminal of the controller and ground.

[0071] In some embodiments, the comparator is an open-drain comparator, and the output of the comparator is further coupled to ground in response to determining that the PLP output voltage is less than a portion of the system supply voltage.

[0072] In some embodiments, the first input of the comparator is coupled to the PLP output voltage through a current-limiting resistor.

[0073] In some implementations, the second input of the comparator is coupled to the system supply voltage via a voltage divider comprising two or more resistors, the voltage divider configured to generate a portion of the system supply voltage that is lower than the PLP output voltage in response to at least the system supply voltage being within a suitable operating range.

[0074] In some implementations, the protection circuit is configured to hold the reset signal for a period of time, the period being increased or decreased by adjusting at least one of the two or more resistors of the voltage divider.

[0075] In some implementations, upon receiving a reset signal, the controller performs one or more initialization operations on memory devices coupled to the controller.

[0076] In some implementations, the controller receives the system supply voltage as a power source.

[0077] In some implementations, the controller receives a second voltage input coupled to the reset terminal through a pull-up resistor disposed within the controller, the second voltage input and the pull-up resistor configured to pull the voltage at the reset terminal above a reset threshold voltage.

[0078] According to another aspect of the present disclosure, a method for resetting a memory system is disclosed. The memory system includes a memory device, a controller, a PMIC, and a protection circuit. The method includes receiving, by the protection circuit, a PLP output voltage from the PMIC, receiving, by the protection circuit, a system supply voltage, and, in response to the protection circuit determining that the PLP output voltage of the PMIC is lower than a fraction of the system supply voltage, providing a reset signal to a reset terminal of the controller, the controller coupled to the memory device, and the reset terminal of the controller coupled to a capacitor.

[0079] In some implementations, a capacitor is coupled between the reset terminal of the controller and ground.

[0080] In some embodiments, the protection circuit comprises a comparator, a first input of the comparator coupled to the PLP output voltage, a second input of the comparator coupled to a portion of the system supply voltage, and an output of the comparator coupled to a reset terminal of the controller.

[0081] In some embodiments, the comparator is an open-drain comparator, and the output of the comparator is further coupled to ground in response to determining that the PLP output voltage is less than a portion of the system supply voltage.

[0082] In some embodiments, the first input of the comparator is coupled to the PLP output voltage through a current-limiting resistor.

[0083] In some implementations, the second input of the comparator is coupled to the system supply voltage via a voltage divider comprising two or more resistors, the voltage divider configured to generate a portion of the system supply voltage that is lower than the PLP output voltage in response to at least the system supply voltage being within a suitable operating range.

[0084] In some implementations, the protection circuitry may be configured to hold the reset signal at the reset threshold voltage level for a period of time. The voltage divider is configured to hold the voltage lower than the threshold for a period of time that is increased or decreased by adjusting at least one of the two or more resistors of the voltage divider.

[0085] In some implementations, the controller performs one or more initialization operations on the memory device upon receiving the reset signal.

[0086] In some implementations, the controller receives the system supply voltage as a power source.

[0087] In some implementations, the controller receives a second voltage input coupled to the reset terminal through a pull-up resistor disposed within the controller, the second voltage input and the pull-up resistor configured to pull the voltage at the reset terminal above a reset threshold voltage.

[0088] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium is disclosed. The non-transitory computer-readable storage medium includes programmable instructions that are executed by at least one processor of a memory system to cause the memory system to perform operations including receiving a command from a host coupled to the memory system, the memory system including a memory device, the memory device including a memory cell array, the memory cell array including a number of memory cells. The operations further include performing a memory operation on the memory device based on the command. The operations further include scanning at least a first group of memory cells of the memory cell array by performing a number of scans within a first scan period of the memory operation.

[0089] The foregoing description of specific embodiments may be readily modified and / or adapted for a variety of uses. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the taught embodiments, based on the teaching and guidance presented herein.

[0090] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. 1. A memory system comprising: a memory device; a controller coupled to the memory device, the controller having a reset terminal; a power loss protection (PLP) circuit coupled to the controller; a protection circuit coupled to the reset terminal of the controller and the PLP circuit, the protection circuit comprising: comparing a PLP output voltage from said PLP circuit with a portion of a system supply voltage; a protection circuit configured to output a reset signal to the reset terminal of the controller in response to the PLP output voltage being less than the portion of the system supply voltage; A memory system comprising:

2. The memory system described in claim 1, wherein the PLP output voltage is output to the controller by the PLP circuit.

3. The memory system of claim 1, further comprising a capacitor connected between the reset terminal of the controller and ground.

4. 2. The memory system of claim 1, wherein the protection circuit comprises a comparator, a first input of the comparator coupled to the PLP circuit, the portion of the system supply voltage input to a second input of the comparator, and an output of the comparator coupled to the reset terminal of the controller.

5. 5. The memory system of claim 4, wherein the comparator is an open-drain comparator, and the output of the comparator is further coupled to ground in response to the PLP output voltage being less than the portion of the system supply voltage.

6. The memory system of claim 4, wherein the protection circuit further comprises a current-limiting resistor coupled to the PLP circuit, and the first input of the comparator is coupled to the PLP circuit via the current-limiting resistor.

7. The memory system of claim 4, wherein the protection circuit further comprises a voltage divider comprising two or more resistors, the second input of the comparator being coupled to the voltage divider, and the voltage divider being configured to generate the portion of the system supply voltage lower than the PLP output voltage in response to at least that portion of the system supply voltage being within a suitable operating range.

8. 8. The memory system of claim 7, wherein the protection circuit is configured to hold the reset signal below a reset threshold voltage level for a period of time, the period of time being increased or decreased by adjusting at least one of the two or more resistors of the voltage divider.

9. The memory system of claim 1 , wherein the controller performs one or more initialization operations based on the reset signal.

10. 1. A method for resetting a memory system comprising a memory device, a controller, a power loss protection (PLP) circuit, and a protection circuit, comprising: comparing, by the protection circuit, a PLP output voltage from the PLP circuit with a portion of a system supply voltage; outputting, by the protection circuit, a reset signal to a reset terminal of the controller in response to the PLP output voltage being less than the portion of the system supply voltage; A method comprising:

11. The method of claim 10, further comprising outputting the PLP output voltage to the controller by the PLP circuit.

12. The method of claim 10, further comprising: performing, by the controller, one or more initialization operations based on the reset signal.

13. The memory system further comprising a capacitor connected between the reset terminal of the controller and ground; 11. The method of claim 10, further comprising: in response to the PLP output voltage being less than the portion of the system supply voltage, causing a power-on delay of the controller by charging the capacitor with the reset signal.

14. 11. The method of claim 10, wherein the protection circuit comprises a comparator, a first input of the comparator coupled to the PLP circuit, the portion of the system supply voltage input to a second input of the comparator, and an output of the comparator coupled to the reset terminal of the controller.

15. 15. The method of claim 14, wherein the comparator is an open-drain comparator, and the output of the comparator is further coupled to ground in response to the PLP output voltage being less than the portion of the system supply voltage.

16. The method described in claim 14, wherein the protection circuit further comprises a current-limiting resistor coupled to the PLP circuit, and the first input of the comparator is coupled to the PLP circuit via the current-limiting resistor.

17. The method of claim 14, wherein the protection circuit further comprises a voltage divider comprising two or more resistors, the second input of the comparator is coupled to the voltage divider, and the voltage divider is configured to generate the portion of the system supply voltage that is lower than the PLP output voltage in response to at least that system supply voltage being within a proper operating range, and the protection circuit is configured to hold the reset signal for a period of time, the period being increased or decreased by adjusting at least one of the two or more resistors of the voltage divider.

18. A controller having a reset terminal; a power loss protection (PLP) circuit having a first output; a protection circuit having a first input, a second input, and a second output; An electronic device comprising: the first input of the protection circuit is coupled to the first output of the PLP circuit; a system supply voltage is input to the second input of the protection circuit; the second output of the protection circuit is coupled to the reset terminal of the controller; An electronic device, wherein the second output of the protection circuit is configured to output a reset signal to the reset terminal of the controller based on a PLP output voltage output from the first output of the PLP circuit and the system supply voltage.

19. The electronic device of claim 18, wherein the first output of the PLP circuit is configured to output the PLP output voltage to the controller.

20. The electronic device of claim 18, further comprising a capacitor connected between the reset terminal of the controller and ground.

21. The protection circuit a current limiting resistor; a voltage divider; a comparator, a third input of the comparator coupled to the first input of the protection circuit via the current limiting resistor, a fourth input of the comparator coupled to the second input of the protection circuit via the voltage divider, an output of the comparator determined to be the second output of the protection circuit, the output of the comparator configured to output the reset signal to the reset terminal of the controller in response to the PLP output voltage being lower than the portion of the system supply voltage output by the voltage divider; 20. The electronic device of claim 18, comprising:

22. The electronic device of claim 21, wherein the comparator is an open-drain comparator, and the output of the comparator is further coupled to ground in response to the PLP output voltage being lower than the portion of the system supply voltage.

23. The electronic device of claim 21, wherein the voltage divider comprises two or more resistors, and the voltage divider is configured to generate the portion of the system supply voltage that is lower than the PLP output voltage in response to at least that portion of the system supply voltage being within an appropriate operating range.

24. The electronic device of claim 23, wherein the protection circuit is configured to hold the reset signal below a reset threshold voltage level for a period of time, the period being increased or decreased by adjusting at least one of the two or more resistors of the voltage divider.

25. The electronic device of claim 18, wherein the controller performs one or more initialization operations based on the reset signal.

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