Array substrate and display device

Abstract

To prevent impurities from easily diffusing into a semiconductor part.SOLUTION: The array substrate 21 includes the semiconductor-portion 27D, the first insulating film 3435 disposed on the upper layer side of the semiconductor-portion 27D, the first electrode 27D disposed on the upper layer side of the first insulating film 3435 and at least partially overlapping a part of the semiconductor-portion 27C, the second insulating film 36 disposed on the upper layer side of the first electrode 27C, and the third insulating film 37 disposed on the upper layer side of the second insulating film 36, the first electrode 27C is made of a transparent material, and the first insulating film 3435 is made of an inorganic insulating material. A first contact hole 27D connecting the semiconductor-part 27C and the first electrode 27D is provided at a position overlapping both the semiconductor-part 27C and the drain-electrode CH2, the third insulating film 37 is made of an organic insulating material, and the second insulating film 36 is made of an inorganic insulating material and covers at least a first overlapping portion 27C that is a portion of the first electrode CH2 overlapping the first contact hole 27C1A.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to an array substrate and a display device in which impurities are less likely to diffuse into a semiconductor portion. [Background technology]

[0002] Conventionally, one example of a display device and an array substrate provided in a display device is known, as described in Patent Document 1 below. Patent Document 1 discloses an organic light-emitting display device as a display device. The organic light-emitting display device described in Patent Document 1 includes an insulating layer formed on a substrate (array substrate), a resistive layer made of an oxide semiconductor formed on the insulating layer, wiring layers connected to both sides of the resistive layer, an organic layer formed on the upper part including the resistive layer and the wiring layer, and a capping layer formed on the organic layer so as to overlap the resistive layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2011 / 0127519 Summary of the Invention [Problem to be solved by the invention]

[0004] In the pixel region of the organic light-emitting display device described in Patent Document 1, contact holes are formed in an insulating layer interposed between an active layer made of an oxide semiconductor material and source / drain electrodes, and the active layer and source / drain electrodes are connected through the contact holes. Here, using a transparent electrode material, for example, as the material for the source / drain electrodes can improve the light transmittance of the pixel region. However, transparent electrode materials are easily permeable to impurities such as moisture contained in the organic layer disposed above the source / drain electrodes. Therefore, after the organic light-emitting display device is manufactured, impurities continue to permeate the source / drain electrodes and diffuse into the active layer. This can cause fluctuations in the characteristics of thin-film transistors containing the active layer.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to make it difficult for impurities to diffuse into the semiconductor portion. [Means for solving the problem]

[0006] (1) An array substrate related to the technology described in this specification comprises a semiconductor portion made of a semiconductor material, a first insulating film arranged on the upper side of the semiconductor portion, a first electrode arranged on the upper side of the first insulating film and at least a portion of which overlaps a portion of the semiconductor portion, a second insulating film arranged on the upper side of the first electrode, and a third insulating film arranged on the upper side of the second insulating film, wherein the first electrode is made of a transparent electrode material, the first insulating film is made of an inorganic insulating material, and has a first contact hole connecting the semiconductor portion and the first electrode at a position overlapping both the semiconductor portion and the first electrode, the third insulating film is made of an organic insulating material, and the second insulating film is made of an inorganic insulating material and covers at least a first overlapping portion which is a portion of the first electrode that overlaps with the first contact hole.

[0007] (2) In addition to (1), the array substrate may also include a pixel electrode arranged above the third insulating film and partially overlapping the first electrode, and a second contact hole connecting the first electrode to the pixel electrode may be provided in the third insulating film at a position that overlaps both the first electrode and the pixel electrode but does not overlap the first contact hole, and the second insulating film may have a third contact hole communicating with the second contact hole and cover the entire area except for a second overlapping portion that is the portion of the first electrode that overlaps with the second contact hole.

[0008] (3) In addition to the above (2), the array substrate may be configured such that the second insulating film includes a first insulating portion overlapping the first electrode and a second insulating portion surrounding the first insulating portion.

[0009] (4) In addition to the above (2) or (3), the array substrate may be configured such that the pixel electrode has an electrode overlapping portion that overlaps with the first electrode and an electrode non-overlapping portion that does not overlap with the first electrode, and the second insulating film is not formed in the area that overlaps with the electrode non-overlapping portion.

[0010] (5) In addition to the above (2) or (3), the array substrate may be configured such that the pixel electrode has an electrode overlapping portion that overlaps with the first electrode and an electrode non-overlapping portion that does not overlap with the first electrode, and the second insulating film is formed in a range that overlaps with the electrode non-overlapping portion.

[0011] (6) In addition to (1), the array substrate may further include a pixel electrode arranged above the third insulating film and partially overlapping the first electrode, and a second contact hole connecting the first electrode to the pixel electrode may be provided in the third insulating film at a position that overlaps both the first electrode and the pixel electrode but does not overlap the first contact hole, and the second insulating film may be formed in an area overlapping the first overlapping portion and a peripheral portion of the first electrode of the first overlapping portion, and may not be formed in an area overlapping the second overlapping portion, which is a portion of the first electrode that overlaps the second contact hole, and the peripheral portion of the first electrode of the second overlapping portion.

[0012] (7) In addition to any one of (1) to (6), the array substrate may further include a pixel electrode arranged above the third insulating film and partially overlapping the first electrode, and a first wiring made of a conductive material having light-shielding properties and arranged below the first insulating film, and a second contact hole connecting the first electrode and the pixel electrode may be provided at a position of the third insulating film that overlaps both the first electrode and the pixel electrode and overlaps the first wiring.

[0013] (8) In addition to any one of (1) to (7), the array substrate may be configured such that the second insulating film contains silicon nitride as the inorganic insulating material.

[0014] (9) Furthermore, in addition to any one of (1) to (8), the array substrate may further include a fourth insulating film arranged below the semiconductor portion, a second electrode arranged below the fourth insulating film and overlapping a portion of the semiconductor portion, and a third electrode arranged so as not to overlap the first electrode and the second electrode and connected to the semiconductor portion, wherein the first electrode, the second electrode, the third electrode and the semiconductor portion may form a transistor.

[0015] (10) Furthermore, in addition to any one of (1) to (8), the array substrate may further include a fifth insulating film arranged above the semiconductor portion and below the first insulating film, a fourth electrode arranged above the fifth insulating film and below the first insulating film and overlapping a portion of the semiconductor portion, and a third electrode arranged so as not to overlap the first electrode and the fourth electrode and connected to the semiconductor portion, wherein the first electrode, the fourth electrode, the third electrode and the semiconductor portion may form a transistor.

[0016] (11) A display device according to the technology described in this specification includes an array substrate according to any one of (1) to (10) above, and an opposing substrate disposed opposite the array substrate. [Effects of the Invention]

[0017] According to the technology described in this specification, it is possible to make it difficult for impurities to diffuse into the semiconductor portion. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a schematic perspective view showing a state in which a user wears a head-mounted display according to a first embodiment on their head. [Figure 2] FIG. 1 is a schematic side view showing the optical relationship between a liquid crystal display device and a lens unit provided in a head-mounted device constituting a head-mounted display according to a first embodiment, and the user's eyeballs. [Figure 3] 1 is a schematic plan view of a liquid crystal panel and a flexible substrate provided in a liquid crystal display device according to Embodiment 1. [Figure 4] 1 is a schematic cross-sectional view of a liquid crystal panel according to a first embodiment. [Figure 5] FIG. 1 is a plan view showing a pixel arrangement in a display area of ​​an array substrate provided in a liquid crystal panel according to a first embodiment; [Figure 6] 1 is an enlarged plan view of the TFT and its surroundings in the array substrate according to the first embodiment; [Figure 7] 7 is a cross-sectional view of the array substrate according to the first embodiment taken along line vii-vii in FIG. 5 . [Figure 8] 8 is a cross-sectional view of the array substrate according to the first embodiment taken along line VIII-VIII in FIG. 6. [Figure 9] 6A and 6B are cross-sectional views of the array substrate according to the first embodiment; [Figure 10] 8 is a cross-sectional view of an array substrate according to a second embodiment taken along the same line as FIG. 7; [Figure 11] 9 is a cross-sectional view of the array substrate according to the second embodiment taken along the same line as FIG. 8; [Figure 12] 10 is a cross-sectional view of an array substrate according to a second embodiment taken along the same line as FIG. 9; [Figure 13] FIG. 10 is an enlarged plan view of the TFT and its vicinity in the array substrate according to the third embodiment. [Figure 14] 14 is a cross-sectional view of the array substrate according to the third embodiment taken along line xiv-xiv in FIG. 13. DETAILED DESCRIPTION OF THE INVENTION

[0019] <Embodiment 1> A first embodiment will be described with reference to Figures 1 to 9. In this embodiment, a goggle-type head-mounted display (HMD) 10 and a liquid crystal display device (display device) 10 used therein are illustrated. Note that an X-axis, a Y-axis, and a Z-axis are shown in a portion of each drawing, and each axis is drawn so that it corresponds to the direction shown in each drawing.

[0020] The appearance of the goggle-type head-mounted display 10HMD will be described using Figure 1. The head-mounted display 10HMD includes a head-mounted device 10HMDa that is worn on the user's head 10HD, as shown in Figure 1. The head-mounted device 10HMDa surrounds both of the user's eyes.

[0021] The configuration of the head-worn device 10HMDa will be described with reference to FIG. 2. As shown in FIG. 2, the head-worn device 10HMDa incorporates at least a liquid crystal display device 10 that displays an image and a lens unit 10RE that focuses the image displayed on the liquid crystal display device 10 onto the user's eyeball 10EY. The liquid crystal display device 10 includes at least a liquid crystal panel (display device) 11 and a backlight device (illumination device) 12 that irradiates the liquid crystal panel 11 with light. The main surface of the liquid crystal panel 11 facing the lens unit 10RE serves as a display surface 11DS that displays an image. The lens unit 10RE is disposed between the liquid crystal display device 10 and the user's eyeball 10EY. The lens unit 10RE imparts a refracting effect to light. By adjusting the focal length of the lens unit 10RE, the user can perceive an image that is focused on the retina 10EYb via the lens 10EYa of the eyeball 10EY as being displayed on a virtual display 10VD that appears to be located at a distance L2 from the eyeball 10EY. This distance L2 is much greater than the actual distance L1 from the eyeball 10EY to the liquid crystal display device 10. This allows the user to view an enlarged image, which is a virtual image, displayed on the virtual display 10VD, which has a screen size (e.g., about several tens of inches to several hundred inches) that is much larger than the screen size (e.g., about several tenths of an inch to a few inches) of the liquid crystal display device 10.

[0022] It is possible to mount one liquid crystal display device 10 in the head-mounted device 10HMDa and display an image for the right eye and an image for the left eye on that liquid crystal display device 10. Alternatively, it is possible to mount two liquid crystal display devices 10 in the head-mounted device 10HMDa and display an image for the right eye on one liquid crystal display device 10 and an image for the left eye on the other liquid crystal display device 10. The head-mounted device 10HMDa may also be equipped with earphones or the like that are placed against the user's ears to output sound.

[0023] The configuration of the liquid crystal panel 11 included in the liquid crystal display device 10 will be described using Figure 3 and other figures. The backlight device 12 has a known configuration, and includes, for example, a light source such as an LED and an optical member that converts light from the light source into planar light by applying an optical effect. As shown in Figure 3, the liquid crystal panel 11 has an overall rectangular shape in a planar view. The central portion of the screen of the liquid crystal panel 11 is a display area AA where an image is displayed. The frame-like outer peripheral portion of the screen of the liquid crystal panel 11 surrounding the display area AA is a non-display area NAA where no image is displayed. The area surrounded by a dashed line in Figure 3 is the display area AA. The liquid crystal panel 11 according to this embodiment is used in the head-mounted display 10HMD described above, and therefore has extremely high resolution, with a pixel density of, for example, approximately 1000 ppi or more.

[0024] As shown in FIG. 3, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. The substrate 20, 21, which is disposed on the front side, is a counter substrate (second substrate, CF substrate) 20, and the substrate 20, 21, which is disposed on the back side, is an array substrate (first substrate, active matrix substrate) 21. The counter substrate 20 and the array substrate 21 are formed by laminating various films on the inner surfaces of glass substrates 20GS and 21GS, respectively, which are substantially transparent and have excellent light-transmitting properties. The substrates 20GS and 21GS are primarily made of, for example, alkali-free glass. The array substrate 21 is larger than the counter substrate 20, and a portion of it protrudes laterally from the counter substrate 20. A flexible substrate 13 is mounted on the protruding portion 21A of the array substrate 21. The flexible substrate 13 is configured by forming multiple wiring patterns on an insulating and flexible base material. One end of the flexible substrate 13 is connected to the array substrate 21, and the other end is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0025] As shown in FIG. 3, a circuit unit (peripheral circuit unit) 14 is provided in the non-display area NAA of the liquid crystal panel 11. The circuit unit 14 includes a first circuit unit 14A and a second circuit unit 14B. A pair of first circuit units 14A are arranged to sandwich the display area AA from both sides in the X-axis direction. The first circuit unit 14A is provided in a strip-shaped area extending along the Y-axis direction. The first circuit unit 14A supplies scanning signals to both gate lines 25 and 29 (described later) and is monolithically provided on the array substrate 21. The first circuit unit 14A is a GDM (Gate Driver Monolithic) circuit. The scanning signals include a potential higher than the threshold voltage of the TFTs 27 (described later). The first circuit unit 14A includes a shift register circuit that outputs scanning signals at a predetermined timing, a buffer circuit that amplifies the scanning signals, and the like. The second circuit unit 14B is arranged in a position sandwiched between the display area AA and the flexible substrate 13 in the Y-axis direction. The second circuit section 14B is provided in a strip-shaped range extending along the X-axis direction. The second circuit section 14B is for supplying image signals (data signals) to the source lines 26 described below, and is provided monolithically on the array substrate 21. The second circuit section 14B includes an SSD (Source Shared Driving) circuit and the like. The second circuit section 14B has a switch function for distributing image signals supplied by the flexible substrate 13 to each of the source lines 26. The second circuit section 14B may be arranged to overlap the counter substrate 20, similar to the first circuit section 14A.

[0026] Next, a cross-sectional configuration of the liquid crystal panel 11 will be outlined with reference to FIG. 4. As shown in FIG. 4, the pair of substrates 20, 21 are disposed facing each other with a gap in the Z-axis direction, which is the normal direction to the principal surfaces of the substrates 20, 21. Between the pair of substrates 20, 21, there are at least a liquid crystal layer 22 and a sealing portion 23 that seals the liquid crystal layer 22. The liquid crystal layer 22 contains liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied. The sealing portion 23 has a rectangular frame shape (endless ring) in plan view as a whole, and surrounds the liquid crystal layer 22 all around in the non-display area NAA. The sealing portion 23 maintains a gap (cell gap) equal to the thickness of the liquid crystal layer 22. A polarizing plate 24 is attached to the outer surface of each of the pair of substrates 20, 21.

[0027] An outline of the pixel arrangement in the display area AA of the array substrate 21 will be described using FIG. 5. As shown in FIG. 5, on the inner surface of the display area AA of the array substrate 21, a plurality of lower-layer gate wirings (first wirings, lower-layer scanning wirings, first scanning wirings) 25, upper-layer gate wirings (upper-layer scanning wirings, second scanning wirings) 29, and source wirings (image wirings, signal wirings) 26 are arranged. The lower-layer gate wirings 25 and the upper-layer gate wirings 29 all extend along the X-axis direction (first direction) across the display area AA and are arranged to overlap each other. The upper-layer gate wirings 29 have a narrower line width than the lower-layer gate wirings 25. The lower-layer gate wirings 25 and the upper-layer gate wirings 29 may be arranged so that their centers coincide with each other in the width direction (Y-axis direction), or may be arranged so that their centers are offset from each other. The lower-layer gate wirings 25 and the upper-layer gate wirings 29 are arranged side by side with a gap between them in the Y-axis direction. The plurality of lower-layer gate wirings 25 and upper-layer gate wirings 29 are supplied with scanning signals output from the first circuit unit 14A. The lower-layer gate wirings 25 and upper-layer gate wirings 29, which overlap each other, are supplied with scanning signals at the same timing from the first circuit unit 14A, so that they are always at the same potential. The source wirings 26 extend along the Y-axis direction (a second direction intersecting with the first direction) vertically across the display area AA and intersect with the lower-layer gate wirings 25 and upper-layer gate wirings 29. The plurality of source wirings 26 are spaced apart in the X-axis direction. Therefore, the plurality of lower-layer gate wirings 25 and upper-layer gate wirings 29 and the plurality of source wirings 26 form a grid in a plan view. The image signals output from the second circuit unit 14B are distributed to the source wirings 26.

[0028] As shown in FIG. 5 , a TFT (transistor, switching element) 27 and a pixel electrode 28 are provided near the intersection of the gate lines 25, 29 and the source line 26. The TFTs 27 and pixel electrodes 28 are regularly arranged in groups along the X-axis and Y-axis directions. The TFT 27 includes at least a lower gate electrode (second electrode) 27A, a source electrode (third electrode) 27B, a drain electrode (first electrode) 27C, a semiconductor portion 27D, and an upper gate electrode (fourth electrode) 27E. The lower gate electrode 27A is formed from a portion of the lower gate line 25. The upper gate electrode 27E is formed from a portion of the upper gate line 29. The source electrode 27B is formed from a portion of the source line 26. The drain electrode 27C is disposed at a distance from the source electrode 27B and is connected to the pixel electrode 28. The semiconductor portion 27D is connected to the source electrode 27B and the drain electrode 27C, respectively, and has portions overlapping the lower gate electrode 27A and the upper gate electrode 27E, respectively. The detailed configuration of the TFT 27 will be described later. The pixel electrode 28 is arranged in an area surrounded by two gate lines 25, 29 adjacent to each other with a gap in the Y-axis direction and two source lines 26 adjacent to each other with a gap in the X-axis direction. The pixel electrode 28 has a vertically elongated, approximately rectangular shape with its long side aligned with the Y-axis direction. The pixel electrode 28, together with a color filter (not shown) provided on the counter substrate 20 or the array substrate 21, constitutes a pixel, which is a display unit.

[0029] Next, various films laminated on the glass substrate 21GS of the array substrate 21 will be described in detail using Figures 7 and 8. As shown in Figures 7 and 8, the glass substrate 21GS of the array substrate 21 has at least a base coat film 30, a first semiconductor film, a first gate insulating film 31, a first metal film, a second gate insulating film (fourth insulating film) 32, a second semiconductor film, a third gate insulating film (fifth insulating film) 33, a second metal film, a first interlayer insulating film (first insulating film) 34, a third metal film, a second interlayer insulating film (first insulating film) 35, a first transparent electrode film, a third interlayer insulating film (second insulating film) 36, a first planarization film (third insulating film) 37, a second transparent electrode film, a second planarization film 38, and a third transparent electrode film laminated thereon in this order from the lower layer side (glass substrate 21GS side). Note that the first semiconductor film is not shown in the drawings. An alignment film for aligning liquid crystal molecules contained in the liquid crystal layer 22 is provided on the innermost surface of the array substrate 21 facing the liquid crystal layer 22 .

[0030] The first metal film, the second metal film, and the third metal film are each a single layer film made of one type of metal material, or a laminated film or alloy made of different types of metal materials (conductive materials), thereby providing electrical conductivity and light-shielding properties. The first metal film is, for example, a single layer film of MoW (molybdenum tungsten) or a laminated film of W (tungsten) / TaN (tantalum nitride). As shown in FIGS. 7 and 8, the first metal film constitutes the lower gate wiring 25 and the lower gate electrode 27A, etc. The second metal film is, for example, a laminated film of Ti (titanium) / Al (aluminum) / Ti. The second metal film constitutes the upper gate wiring 29 and the upper gate electrode 27E, etc. The third metal film is, for example, a laminated film of Ti / Al / Ti. The third metal film constitutes the source wiring 26, etc. The first transparent electrode film, the second transparent electrode film, and the third transparent electrode film are made of transparent electrode materials such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide). The first transparent electrode film constitutes the drain electrode 27C, etc. The second transparent electrode film and the third transparent electrode film constitute the pixel electrode 28, etc.

[0031] The first semiconductor film is made of, for example, a silicon semiconductor material. More specifically, the first semiconductor film can be a CG silicon (Continuous Grain Silicon) thin film, a type of polycrystalline silicon thin film (polycrystalline silicon thin film). The CG silicon thin film is formed, for example, by adding a metal material to an amorphous silicon thin film and performing a short-term heat treatment at a low temperature of approximately 550°C or less, thereby providing continuity in the atomic arrangement at the grain boundaries of the silicon crystals. The silicon semiconductor material of the first semiconductor film has higher electron mobility than oxide semiconductor materials. Such a first semiconductor film can be used to provide circuit elements such as TFTs included in the circuit unit 14 arranged in the non-display area NAA. The first semiconductor film constitutes the semiconductor portion of the circuit elements such as TFTs included in the circuit unit 14. This increases the switching speed of the TFTs included in the circuit unit 14, thereby reducing display defects such as flicker and afterimages in the images displayed by the pixel electrodes 28 in the display area AA. The first metal film may also constitute the gate electrodes of the TFTs included in the circuit unit 14. The third metal film may also constitute the source electrode and drain electrode of the TFT included in the circuit section 14.

[0032] The second semiconductor film is made of an oxide semiconductor material. Specifically, the second semiconductor film is made of, for example, an oxide thin film containing indium (In), gallium (Ga), and zinc (Zn), which are oxide semiconductors. The oxide thin film containing indium (In), gallium (Ga), and zinc (Zn) is amorphous or crystalline. The oxide semiconductor material of the second semiconductor film has a higher resistance value when no voltage is applied (off state) compared to silicon semiconductor material. Furthermore, the oxide semiconductor material of the second semiconductor film has a higher electron mobility compared to amorphous silicon semiconductor material. The second semiconductor film constitutes the semiconductor portion 27D of the TFT 27. By using the second semiconductor film to provide the TFT 27 in the display area AA, the off-leak current of the TFT 27 can be reduced, thereby achieving low power consumption, etc. Furthermore, the TFT 27 can be miniaturized, which is advantageous for improving the resolution of the liquid crystal panel 11. This is particularly advantageous for using the liquid crystal panel 11 in a head-mounted display 10HMD.

[0033] As shown in FIG. 8, a portion of the semiconductor portion 27D of the TFT 27 made of the second semiconductor film is selectively made conductive (reduced resistance). In FIG. 8, the conductive portion of the semiconductor portion 27D is shown shaded. The portion of the semiconductor portion 27D that is not made conductive is designated as a non-conductive region (non-low-resistance region) 27D1. The non-conductive region 27D1 is designated as a portion of the semiconductor portion 27D that overlaps with the upper gate electrode 27E. The non-conductive region 27D1 allows charge movement only under specific conditions (when a scanning signal is supplied to each of the gate electrodes 27A and 27E). In other words, the non-conductive region 27D1 functions as a channel region under specific conditions. The conductive portions of the semiconductor portion 27D (conductive region, low-resistance region) are designated as a source region (first conductive region) 27D2 and a drain region (second conductive region) 27D3. The source region 27D2 and the drain region 27D3 are portions of the semiconductor portion 27D that do not overlap with the upper gate electrode 27E. The source region 27D2 and the drain region 27D3 have extremely low resistivity, for example, about 1 / 10000000000 to 1 / 100, compared to the non-conductive region 27D1, and are always capable of transferring charges, functioning as conductors. The conductive treatment (resistance reduction treatment) of the semiconductor film is performed during the manufacturing process of the array substrate 21, after the upper gate wiring 29 and the upper gate electrode 27E made of a second metal film are provided, using the upper gate wiring 29 and the upper gate electrode 27E as a mask. In the conductivization treatment, the conductivization treatment is selectively performed on the portion of the semiconductor film that is not covered by the upper gate wiring 29 and the upper gate electrode 27E (non-overlapping portion, exposed portion), and the conductivization treatment is not performed on the portion that is covered by the upper gate wiring 29 and the upper gate electrode 27E (overlapping portion, non-exposed portion). The conductivization treatment includes, for example, plasma treatment using gas such as NH3, H2, N2, He, and annealing treatment.

[0034] The base coat film 30, the first gate insulating film 31, the second gate insulating film 32, the third gate insulating film 33, the first interlayer insulating film 34, and the second interlayer insulating film 35 are all made of SiO2 (silicon oxide, silicon oxide) or SiN xThe third interlayer insulating film 36 is made of an inorganic insulating material such as silicon nitride. x The base coat film 30 is made of an inorganic insulating material (inorganic material) such as silicon nitride. The base coat film 30 is directly laminated on the glass substrate 21GS and is located below the first semiconductor film. The first gate insulating film 31 is located above the first semiconductor film and below the first metal film. For example, the first gate insulating film 31 keeps the gate electrode of the TFT included in the circuit unit 14 insulated from the semiconductor unit. The second gate insulating film 32 is made of, for example, SiO2. The second gate insulating film 32 is located above the first metal film and below the second semiconductor film. The second gate insulating film 32 keeps the lower gate electrode 27A of the TFT 27 insulated from the semiconductor unit 27D. The third gate insulating film 33 is made of, for example, SiO2. The third gate insulating film 33 is located above the second semiconductor film and below the second metal film. The third gate insulating film 33 keeps the semiconductor unit 27D of the TFT 27 insulated from the upper gate electrode 27E. The first interlayer insulating film 34 is located above the second metal film and below the third metal film. The first interlayer insulating film 34 is made of, for example, SiO2. The first interlayer insulating film 34, together with the second gate insulating film 32, keeps the lower gate wiring 25 and the source wiring 26 insulated. The first interlayer insulating film 34 also keeps the upper gate wiring 29 and the source wiring 26 insulated. The second interlayer insulating film 35 is located above the third metal film and below the first transparent electrode film. The second interlayer insulating film 35, together with the first interlayer insulating film 34, keeps the drain electrode 27C and the upper gate wiring 29 insulated. The third interlayer insulating film 36 is located above the first transparent electrode film and below the first planarization film 37. The third interlayer insulating film 36 will be described in detail later.

[0035] The first planarization film 37 and the second planarization film 38 are made of an organic insulating material (organic material) such as PMMA (acrylic resin). The first planarization film 37 and the second planarization film 38 made of an organic insulating material have a thickness greater than that of any of the base coat film 30, the first gate insulating film 31, the second gate insulating film 32, the third gate insulating film 33, the first interlayer insulating film 34, the second interlayer insulating film 35, and the third interlayer insulating film 36 made of an inorganic insulating material. Specifically, the base coat film 30, the first gate insulating film 31, the second gate insulating film 32, the third gate insulating film 33, the first interlayer insulating film 34, the second interlayer insulating film 35, and the third interlayer insulating film 36 made of an inorganic insulating material have a thickness of, for example, several tens to several hundreds of nanometers, whereas the thickness of the first planarization film 37 and the second planarization film 38 is, for example, approximately 1 μm to 3 μm. The first planarization film 37 is located above the second interlayer insulating film 35 and below the second transparent electrode film. The first planarization film 37 keeps the drain electrode 27C and the pixel electrode 28 in an insulated state. The second planarization film 38 is located above the second transparent electrode film and below the third transparent electrode film.

[0036] When the display mode of the liquid crystal panel 11 is, for example, FFS (Fringe Field Switching) mode, a fourth interlayer insulating film is formed on the upper side of the third transparent electrode film, and a fourth transparent electrode film is formed on the upper side of the fourth interlayer insulating film on the array substrate 21. In this case, the fourth transparent electrode film forms a common electrode having a common potential. On the other hand, when the display mode of the liquid crystal panel 11 is, for example, VA (Vertical Alignment) mode or TN (Twisted Nematic) mode, a counter electrode is provided on the counter substrate 20.

[0037] Next, the configuration of the TFT 27 will be described in detail. As shown in FIGS. 6 and 8, the semiconductor portion 27D of the TFT 27 extends in a direction inclined with respect to both the X-axis direction and the Y-axis direction, and intersects with both the gate wirings 25 and 29 and the source wiring 26. A central portion of the semiconductor portion 27D configured in this manner in the extending direction (diagonal direction) overlaps with the lower gate electrode 27A and the upper gate electrode 27E. The central portion of the semiconductor portion 27D in the extending direction that overlaps with the upper gate electrode 27E is defined as a non-conductive region 27D1. Of both end portions of the semiconductor portion 27D in the extending direction, the end portions that intersect with the source wiring 26 (source electrode 27B) are defined as source regions 27D2. Of both end portions of the semiconductor portion 27D in the extending direction, the end portions that intersect with the drain electrode 27C are defined as drain regions 27D3.

[0038] As shown in FIG. 8 , the non-conductive region 27D1 of the semiconductor portion 27D is disposed above the lower gate electrode 27A with the second gate insulating film 32 interposed therebetween, and below the upper gate electrode 27E with the third gate insulating film 33 interposed therebetween. Thus, the TFT 27 according to this embodiment has a double-gate structure in which the non-conductive region 27D1 of the semiconductor portion 27D is sandwiched between two upper and lower gate electrodes 27A and 27E. When the TFT 27 is driven based on scanning signals supplied from the lower gate wiring 25 and the upper gate wiring 29 to the lower gate electrode 27A and the upper gate electrode 27E, two channel regions are generated, one on the upper side and one on the lower side, in the non-conductive region 27D1 of the semiconductor portion 27D. An image signal supplied from the source wiring 26 to the source electrode 27B is supplied to the drain electrode 27C via the channel regions generated in the non-conductive region 27D1 of the semiconductor portion 27D, and the pixel electrode 28 is charged to a potential based on the image signal. In this way, two channel regions are generated in the semiconductor portion 27D, thereby increasing the charge mobility.

[0039] 8, an end portion of the source region 27D2 of the semiconductor portion 27D opposite to the non-conductive region 27D1 side is disposed below the source electrode 27B, which is part of the source wiring 26, via a first interlayer insulating film 34. A source contact hole CH1 is opened and provided in the first interlayer insulating film 34 at a position where the first interlayer insulating film 34 overlaps both the source region 27D2 and the source electrode 27B. The source region 27D2 and the source electrode 27B are connected to each other through the source contact hole CH1.

[0040] 8, an end portion of the drain region 27D3 of the semiconductor portion 27D opposite to the non-conductive region 27D1 side is disposed below and overlaps a portion of the drain electrode 27C via the first interlayer insulating film 34 and the second interlayer insulating film 35. A drain contact hole (first contact hole) CH2 is opened and provided in the first interlayer insulating film 34 and the second interlayer insulating film 35 at a position where the first interlayer insulating film 34 and the second interlayer insulating film 35 overlap both the drain region 27D3 and the drain electrode 27C. The drain contact hole CH2 is provided to communicate with both the first interlayer insulating film 34 and the second interlayer insulating film 35. The drain region 27D3 and the drain electrode 27C are connected to each other through the drain contact hole CH2.

[0041] As shown in FIG. 5, the drain electrode 27C extends along the Y-axis direction and has a vertically elongated rectangular shape in a plan view. The drain electrode 27C is disposed near a position midway between two source lines 26 that are spaced apart in the X-axis direction (the central position of the pixel electrode 28 in the X-axis direction). The entire area of ​​the drain electrode 27C overlaps with the pixel electrode 28 to be connected. As shown in FIGS. 6 and 8, one end of the drain electrode 27C in the Y-axis direction (the lower side in FIG. 6) overlaps with the drain region 27D3 of the semiconductor portion 27D and is connected to the drain region 27D3 through the drain contact hole CH2. One end of the drain electrode 27C in the Y-axis direction is defined as a first connection portion 27C1 connected to the drain region 27D3. The first connection portion 27C1 includes a first overlapping portion 27C1A that overlaps the drain contact hole CH2 and a peripheral portion 27C1B of the first overlapping portion 27C1A.

[0042] As shown in FIGS. 5 and 9, the pixel electrode 28 has a connection portion 28A connected to the drain electrode 27C and a pixel body portion 28B connected to the connection portion 28A. The connection portion 28A is made of a second transparent electrode film and has an island shape so as to overlap a portion of the drain electrode 27C. The other end of the drain electrode 27C in the Y-axis direction (the upper side in FIG. 5) is arranged to overlap the connection portion 28A of the pixel electrode 28 and serves as a second connection portion 27C2 connected to the connection portion 28A. A first planarization film 37 is interposed between the connection portion 28A made of the second transparent electrode film and the second connection portion 27C2 made of the first transparent electrode film. A first pixel contact hole (second contact hole) CH3 is opened and provided in the first planarization film 37 at a position overlapping both the connection portion 28A and the second connection portion 27C2. The first pixel contact hole CH3 is disposed at a position spaced apart from the drain contact hole CH2 in the Y-axis direction and is disposed so as not to overlap with the drain contact hole CH2. The connection portion 28A and the second connection portion 27C2 are connected to each other through the first pixel contact hole CH3. The second connection portion 27C2 includes a second overlapping portion 27C2A that overlaps with the first pixel contact hole CH3 and a peripheral portion 27C2B of the second overlapping portion 27C2A.

[0043] As shown in FIG. 5, the pixel body portion 28B is made of a third transparent electrode film. The pixel body portion 28B constitutes the majority of the pixel electrode 28 and functions as a main component for generating an electric field between the pixel body portion 28B and the common electrode and the counter electrode. The pixel body portion 28B is disposed in a region surrounded by two adjacent gate lines 25 and 29 spaced apart in the Y-axis direction and two adjacent source lines 26 spaced apart in the X-axis direction, forming a vertically elongated, approximately rectangular shape. A portion of the pixel body portion 28B overlaps almost the entire area of ​​the connection portion 28A, while the majority of the remaining portion does not overlap with the connection portion 28A. As shown in FIG. 9, a second planarization film 38 is interposed between the pixel body portion 28B made of the third transparent electrode film and the connection portion 28A made of the second transparent electrode film. The second planarization film 38 is selectively provided to cover the portion of the connection portion 28A that overlaps with the first pixel contact hole CH3. The portion of the connection portion 28A that overlaps with the first pixel contact hole CH3 is recessed into the first pixel contact hole CH3 compared to the other portion, forming a concave shape. The second planarization film 38 is provided to fill (fill) the concave portion of the connection portion 28A, and flattens the upper surface (surface) of the connection portion 28A. The second planarization film 38 is not formed in an area that does not overlap with the first pixel contact hole CH3. Therefore, the portions of the pixel body portion 28B and the connection portion 28A that do not overlap with the first pixel contact hole CH3 are connected to each other in a direct contact manner without the second planarization film 38 interposed therebetween.

[0044] 6 and 9, the portion of the pixel electrode 28 that overlaps with the drain electrode 27C is an electrode overlapping portion 28C, and the portion that does not overlap with the drain electrode 27C is an electrode non-overlapping portion 28D. The electrode overlapping portion 28C includes a majority of the connection portion 28A and a portion of the pixel main body portion 28B. The electrode non-overlapping portion 28D includes a portion of the connection portion 28A and a majority of the pixel main body portion 28B.

[0045] As shown in FIG. 8 , the semiconductor portion 27D of the TFT 27 is covered from above by the second interlayer insulating film 35, which prevents impurities such as moisture contained in the first planarization film 37 made of an organic insulating material from directly penetrating and diffusing into the semiconductor portion 27D. The first overlapping portion 27C1A of the drain electrode 27C is connected to the semiconductor portion 27D through a drain contact hole CH2 in the second interlayer insulating film 35. The drain electrode 27C is made of a transparent electrode material and is therefore light-transmitting. Therefore, compared to a case where the drain electrode 27C is made of a metal material, light that transmits through the electrode overlapping portion 28C of the pixel electrode 28 can be used for display, in addition to light that transmits through the electrode non-overlapping portion 28D, thereby improving the light transmittance of the pixel electrode 28. On the other hand, the drain electrode 27C made of a transparent electrode material is more likely to transmit impurities contained in the first planarization film 37 made of an organic insulating material than a case where a metal material is used. Therefore, there is a concern that impurities may diffuse into the semiconductor portion 27D via the drain electrode 27C.

[0046] Therefore, as shown in FIG. 6, the array substrate 21 according to this embodiment is provided with a third interlayer insulating film 36 made of an inorganic insulating material, which is located above the drain electrode 27C and below the first planarization film 37. The third interlayer insulating film 36 is provided so as to cover at least the first overlapping portion 27C1A of the drain electrode 27C. Therefore, impurities contained in the first planarization film 37 are less likely to permeate the third interlayer insulating film 36 interposed between the first planarization film 37 and the drain electrode 27C, and are less likely to reach the first overlapping portion 27C1A of the drain electrode 27C. This makes it difficult for impurities contained in the first planarization film 37 to diffuse into the semiconductor portion 27D via the drain electrode 27C, which reduces fluctuations in the characteristics of the TFT 27 and reduces the likelihood of malfunctions of the TFT 27. In this embodiment, the third interlayer insulating film 36 is made of SiN x Since the third interlayer insulating film is a single layer made of SiO2, the film quality is denser and less permeable to impurities such as moisture than if the third interlayer insulating film were a single layer made of SiO2, which makes it difficult for impurities to diffuse into the semiconductor portion 27D.

[0047] As shown in FIGS. 6 and 9 , the third interlayer insulating film 36 is provided to cover substantially the entire area of ​​the drain electrode 27C. Specifically, the third interlayer insulating film 36 extends along the Y-axis direction and has a vertically elongated rectangular shape in a plan view. That is, the third interlayer insulating film 36 has an island-like planar shape similar to the drain electrode 27C. The island-like third interlayer insulating films 36 are arranged in a matrix in the display region AA of the array substrate 21, with the same number of third interlayer insulating films 36 as the TFTs 27 (pixel electrodes 28). The third interlayer insulating film 36 is provided with a second pixel contact hole (third contact hole) CH4 that is opened at a position overlapping the first pixel contact hole CH3 and communicates with the first pixel contact hole CH3. The third interlayer insulating film 36 covers the entire area of ​​the drain electrode 27C except for a second overlapping portion 27C2A that overlaps the first pixel contact hole CH3. With this configuration, the connection portion 28A constituting the pixel electrode 28 is connected to the second overlapping portion 27C2A of the drain electrode 27C through the first pixel contact hole CH3 in the first planarization film 37 and the second pixel contact hole CH4 in the third interlayer insulating film 36. Because the entire drain electrode 27C except for the second overlapping portion 27C2A is covered by the third interlayer insulating film 36, impurities contained in the first planarization film 37 are less likely to penetrate into any part of the drain electrode 27C. This makes it more difficult for impurities to diffuse into the semiconductor portion 27D via the drain electrode 27C.

[0048] As shown in FIGS. 6 and 9 , the third interlayer insulating film 36 is formed in the area of ​​the pixel electrode 28 that overlaps with the electrode overlapping portion 28C, but is not formed in the area that overlaps with the electrode non-overlapping portion 28D. The amount of light absorbed by the third interlayer insulating film 36 is reduced compared to when the third interlayer insulating film 36 is solid and is formed in the area that overlaps with the electrode non-overlapping portion 28D. The reduced amount of light absorbed by the third interlayer insulating film 36 increases the amount of light transmitted through the electrode non-overlapping portion 28D and reduces the amount of light reflected at the interface (lower surface) between the third interlayer insulating film 36 and the drain electrode 27C and the interface (upper surface) between the third interlayer insulating film 36 and the first planarization film 37. The electrode non-overlapping portion 28D includes most of the pixel body portion 28B and is the portion that contributes most to pixel display. Therefore, by not forming the third interlayer insulating film 36 in the area overlapping with the electrode non-overlapping portion 28D, the light transmittance of the pixel electrode 28 is improved, resulting in a good pixel display.

[0049] 6, 8, and 9, the third interlayer insulating film 36 is provided so as to be disposed over an area wider than the drain electrode 27C in a plan view. Specifically, the third interlayer insulating film 36 is provided so as to include a first insulating portion 36A overlapping the drain electrode 27C and a second insulating portion 36B surrounding the first insulating portion 36A. In this manner, the outer peripheral edge of the drain electrode 27C is surrounded over the entire periphery by the second insulating portion 36B included in the third interlayer insulating film 36. This makes it difficult for impurities contained in the first planarization film 37 to penetrate the outer peripheral edge of the drain electrode 27C, and therefore makes it difficult for the impurities to diffuse into the semiconductor portion 27D via the drain electrode 27C.

[0050] As shown in FIG. 6 , the pixel electrode 28 has a portion of the electrode overlapping portion 28C overlapping both gate lines 25 and 29. The second overlapping portion 27C2A of the drain electrode 27C is arranged to overlap the portion of the electrode overlapping portion 28C that overlaps both gate lines 25 and 29. That is, the first planarization film 37 is provided so that the first pixel contact hole CH3 overlaps both gate lines 25 and 29. The third interlayer insulating film 36 is provided so that the second pixel contact hole CH4 overlaps both gate lines 25 and 29. The connection portion 28A of the pixel electrode 28 is connected to the second overlapping portion 27C2A of the drain electrode 27C through the first pixel contact hole CH3 of the first planarization film 37 and the second pixel contact hole CH4 of the third interlayer insulating film 36. The first pixel contact hole CH3 is disposed at a position overlapping both gate lines 25, 29, and therefore light directed toward the first pixel contact hole CH3 and the second pixel contact hole CH4 can be blocked by both gate lines 25, 29 made of a metal material with light-blocking properties. This prevents degradation of display quality caused by poor alignment even if poor alignment occurs in the liquid crystal molecules near the first pixel contact hole CH3 and the second pixel contact hole CH4.

[0051] As described above, the array substrate 21 of this embodiment includes the semiconductor portion 27D made of a semiconductor material, the first interlayer insulating film 34 and the second interlayer insulating film 35 which are first insulating films arranged on the upper layer side of the semiconductor portion 27D, the drain electrode (first electrode) 27C which is arranged on the upper layer side of the first interlayer insulating film 34 and the second interlayer insulating film 35 which are first insulating films and at least a part of which overlaps with a part of the semiconductor portion 27D, the third interlayer insulating film (second insulating film) 36 which is arranged on the upper layer side of the drain electrode 27C, and the first planarization film (third insulating film) 37 which is arranged on the upper layer side of the third interlayer insulating film 36. The inner electrode 27C is made of a transparent electrode material, the first insulating film 34 and the second interlayer insulating film 35, which are the first insulating films, are made of an inorganic insulating material, and have a drain contact hole (first contact hole) CH2 connecting the semiconductor portion 27D and the drain electrode 27C at a position overlapping both the semiconductor portion 27D and the drain electrode 27C, the first planarization film 37 is made of an organic insulating material, and the third interlayer insulating film 36 is made of an inorganic insulating material and covers at least the first overlapping portion 27C1A, which is the portion of the drain electrode 27C that overlaps with the drain contact hole CH2.

[0052] The semiconductor portion 27D is covered from above by the first interlayer insulating film 34 and the second interlayer insulating film 35, which are first insulating films. This prevents impurities, such as moisture, contained in the first planarization film 37, which is made of an organic insulating material, from directly penetrating and diffusing into the semiconductor portion 27D. The first overlapping portion 27C1A of the drain electrode 27C is connected to the semiconductor portion 27D through the drain contact hole CH2 in the first interlayer insulating film 34 and the second interlayer insulating film 35, which are first insulating films. The drain electrode 27C is made of a transparent electrode material and can transmit light. This improves light transmittance. However, because the drain electrode 27C made of a transparent electrode material is easily permeable to impurities contained in the first planarization film 37, which is made of an organic insulating material, there is a concern that the impurities may diffuse into the semiconductor portion 27D via the drain electrode 27C. In this regard, the third interlayer insulating film 36 made of an inorganic insulating material is interposed between the drain electrode 27C and the first planarization film 37, and this third interlayer insulating film 36 covers at least the first overlapping portion 27C1A, which is the portion of the drain electrode 27C that overlaps with the drain contact hole CH2, so that impurities contained in the first planarization film 37 are less likely to penetrate into the first overlapping portion 27C1A. This makes it less likely that impurities will diffuse into the semiconductor portion 27D via the drain electrode 27C.

[0053] The pixel electrode 28 is disposed above the first planarization film 37 and partially overlaps with the drain electrode 27C. A first pixel contact hole (second contact hole) CH3 connecting the drain electrode 27C and the pixel electrode 28 is provided in the first planarization film 37 at a position that overlaps both the drain electrode 27C and the pixel electrode 28 but does not overlap with the drain contact hole CH2. The third interlayer insulating film 36 has a second pixel contact hole (third contact hole) CH4 that communicates with the first pixel contact hole CH3 and covers the entire area of ​​the drain electrode 27C except for a second overlapping portion 27C2A that is a portion of the drain electrode 27C that overlaps with the first pixel contact hole CH3. The pixel electrode 28 is connected to the second overlapping portion 27C2A of the drain electrode 27C through the first pixel contact hole CH3 in the first planarization film 37 and the second pixel contact hole CH4 in the third interlayer insulating film 36. The drain electrode 27C is entirely covered with the third interlayer insulating film 36 except for the second overlapping portion 27C2A, so that impurities contained in the first planarization film 37 are less likely to penetrate into any part of the drain electrode 27C. This makes it more difficult for impurities to diffuse into the semiconductor portion 27D via the drain electrode 27C.

[0054] The third interlayer insulating film 36 also includes a first insulating portion 36A overlapping the drain electrode 27C and a second insulating portion 36B surrounding the first insulating portion 36A. In this way, the outer peripheral edge of the drain electrode 27C is surrounded by the second insulating portion 36B included in the third interlayer insulating film 36. This makes it difficult for impurities included in the first planarizing film 37 to penetrate into the outer peripheral edge of the drain electrode 27C, and therefore makes it difficult for the impurities to diffuse into the semiconductor portion 27D via the drain electrode 27C.

[0055] Furthermore, the pixel electrode 28 has an electrode overlapping portion 28C that overlaps with the drain electrode 27C and an electrode non-overlapping portion 28D that does not overlap with the drain electrode 27C, and the third interlayer insulating film 36 is not formed in the area that overlaps with the electrode non-overlapping portion 28D. Compared to a case in which the third interlayer insulating film is also formed in the area that overlaps with the electrode non-overlapping portion 28D, the amount of light absorbed by the third interlayer insulating film 36 is reduced, which increases the amount of light that passes through the electrode non-overlapping portion 28D of the pixel electrode 28 and reduces the amount of light reflected at the interface with the third interlayer insulating film 36. This improves the light transmittance of the pixel electrode 28.

[0056] The pixel electrode 28 is disposed above the first planarization film 37, with a portion of the pixel electrode 28 overlapping the drain electrode 27C. A lower gate wiring (first wiring) 25 is made of a light-shielding conductive material and is disposed below the first interlayer insulating film 34 and the second interlayer insulating film 35, which are first insulating films. A first pixel contact hole CH3 is provided in the first planarization film 37 at a position where the first planarization film 37 overlaps both the drain electrode 27C and the pixel electrode 28 and also overlaps with the lower gate wiring 25. The pixel electrode 28 is connected to the drain electrode 27C through the first pixel contact hole CH3 in the first planarization film 37. Because the first pixel contact hole CH3 is disposed at a position where it overlaps with the lower gate wiring 25, the lower gate wiring 25, which is made of a light-shielding conductive material, can block light directed toward the first pixel contact hole CH3.

[0057] The third interlayer insulating film 36 contains silicon nitride as an inorganic insulating material. Compared to a case where the inorganic insulating material of the third interlayer insulating film is silicon oxide alone, the film is denser and therefore less permeable to impurities such as moisture. This makes it more difficult for impurities to diffuse into the semiconductor portion 27D.

[0058] The TFT 27 also includes a second gate insulating film (fourth insulating film) 32 disposed below the semiconductor portion 27D, a lower gate electrode (second electrode) 27A disposed below the second gate insulating film 32 and overlapping a portion of the semiconductor portion 27D, and a source electrode (third electrode) 27B disposed so as not to overlap the drain electrode 27C and the lower gate electrode 27A and connected to the semiconductor portion 27D. The drain electrode 27C, the lower gate electrode 27A, the source electrode 27B, and the semiconductor portion 27D constitute a TFT (transistor) 27. When a voltage equal to or greater than the threshold voltage of the TFT 27 is applied to the lower gate electrode 27A, a channel region is generated in the semiconductor portion 27D, and charge moves between the drain electrode 27C and the source electrode 27B via the channel region. The first planarization film 37 prevents impurities from diffusing into the semiconductor portion 27D, thereby preventing fluctuations in the characteristics of the TFT 27. This reduces the likelihood of malfunctions in the TFT 27.

[0059] The TFT 27 also includes a third gate insulating film (fifth insulating film) 33 arranged above the semiconductor portion 27D and below the first interlayer insulating film 34 and second interlayer insulating film 35, which are first insulating films, an upper gate electrode (fourth electrode) 27E arranged above the third gate insulating film 33 and below the first interlayer insulating film 34 and second interlayer insulating film 35, which are first insulating films, and overlaps a portion of the semiconductor portion 27D, and a source electrode 27B arranged not to overlap the drain electrode 27C and the upper gate electrode 27E and connected to the semiconductor portion, wherein the drain electrode 27C, the upper gate electrode 27E, the source electrode 27B, and the semiconductor portion 27D constitute the TFT 27. When a voltage equal to or greater than a threshold voltage of the TFT 27 is applied to the upper gate electrode 27E, a channel region is generated in the semiconductor portion 27D, and charge moves between the drain electrode 27C and the source electrode 27B via the channel region. The first planarization film 37 makes it difficult for impurities to diffuse into the semiconductor portion 27D, which makes it difficult for the characteristics of the TFT 27 to fluctuate. As a result, the TFT 27 is less likely to malfunction.

[0060] Furthermore, the liquid crystal panel (display device) 11 according to this embodiment includes the above-described array substrate 21 and an opposing substrate 20 disposed opposite the array substrate 21. With such a liquid crystal panel 11, impurities are less likely to diffuse into the semiconductor portion 27D provided on the array substrate 21, thereby achieving good display quality.

[0061] <Embodiment 2> 10 to 12, a second embodiment will be described. In this second embodiment, the formation range of the third interlayer insulating film 136 is changed. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0062] As shown in FIGS. 10 to 12 , the third interlayer insulating film 136 according to this embodiment is provided on the array substrate 121 so as to extend solidly across at least the entire display area AA. The third interlayer insulating film 136 overlaps all pixel electrodes 128 arranged in the display area AA. The third interlayer insulating film 136 is formed in a range that overlaps not only the electrode overlapping portion 128C but also the electrode non-overlapping portion 128D of each pixel electrode 128. As in the first embodiment described above, when the third interlayer insulating film 36 is not formed in a range that overlaps the electrode non-overlapping portion 28D (see FIG. 6 ), the end of the third interlayer insulating film 36 overlaps the pixel electrode 28, but this arrangement is avoided. This reduces the likelihood of light refracted or reflected by the end of the third interlayer insulating film 136 passing through the pixel electrode 128. The third interlayer insulating film 136 may be disposed only in the display area AA, or may be disposed so as to straddle the non-display area AA and the non-display area NAA.

[0063] As described above, according to this embodiment, the pixel electrode 128 has an electrode overlapping portion 128C that overlaps with the drain electrode 127C and an electrode non-overlapping portion 128D that does not overlap with the drain electrode 127C, and the third interlayer insulating film 136 is formed in a range that overlaps with the electrode non-overlapping portion 128D. If the third interlayer insulating film were not formed in a range that overlaps with the electrode non-overlapping portion 28D, the end of the third interlayer insulating film 36 would be positioned to overlap the pixel electrode 28, but this positioning is avoided. This makes it less likely that light refracted or reflected by the end of the third interlayer insulating film 136 will be transmitted through the pixel electrode 128.

[0064] <Embodiment 3> Embodiment 3 will be described with reference to Fig. 13 or 14. In this embodiment 3, the formation range of the third interlayer insulating film 236 is changed from that of the above-mentioned embodiment 1. Note that redundant explanations of the structure, action, and effects similar to those of the above-mentioned embodiment 1 will be omitted.

[0065] As shown in FIGS. 13 and 14 , the third interlayer insulating film 236 according to this embodiment is formed in an area overlapping a portion of the drain electrode 227C. Specifically, the third interlayer insulating film 236 is formed in an area overlapping a first overlapping portion 227C1A of the drain electrode 227C that overlaps the drain contact hole CH202 and a peripheral portion 227C1B of the first overlapping portion 227C1A. The third interlayer insulating film 236 is not formed in an area overlapping a second overlapping portion 227C2A of the drain electrode 227C that overlaps the first pixel contact hole CH203 and a peripheral portion 227C2B of the second overlapping portion 227C2A. The third interlayer insulating film 236 has a rectangular shape in a plan view and is disposed concentrically with the drain contact hole CH202 and the first overlapping portion 227C1A. The third interlayer insulating film 236 extends beyond the peripheral portion 227C1B of the first overlapping portion 227C1A and includes a portion that does not overlap with the drain electrode 227C. In detail, the third interlayer insulating film 236 includes a first insulating portion 236A that overlaps with the first overlapping portion 227C1A and its peripheral portion 227C1B of the drain electrode 227C, and a second insulating portion 236B that surrounds the first insulating portion 236A.

[0066] As described above, the drain electrode 227C has the first overlapping portion 227C1A and its peripheral portion 227C1B covered by the third interlayer insulating film 236, but the second overlapping portion 227C2A and its peripheral portion 227C2B not covered by the third interlayer insulating film 236. Therefore, compared to the case where the entire drain electrode 27C except for the second overlapping portion 27C2A is covered by the third interlayer insulating film 236 (see FIG. 6 ), as in the first embodiment described above, the area in which the third interlayer insulating film 236 is formed is reduced. Reducing the area in which the third interlayer insulating film 236 is formed reduces the amount of light absorbed by the third interlayer insulating film 236, thereby increasing the amount of light transmitted through the pixel electrode 228 and reducing the amount of light reflected at the interface (lower surface) between the third interlayer insulating film 236 and the drain electrode 227C and the interface (upper surface) between the third interlayer insulating film 236 and the first planarization film 237. This improves the light transmittance of the pixel electrode 228. The third interlayer insulating film 236 is not formed in an area overlapping with the connection portion 228A of the pixel electrode 228, and therefore does not have the second pixel contact hole CH4 (see FIG. 9) described in the above-described embodiment 1. Therefore, the connection portion 228A is connected to the second overlapping portion 227C2A of the drain electrode 227C through the first pixel contact hole CH203 in the first planarization film 237.

[0067] As described above, according to this embodiment, the pixel electrode 228 is disposed above the first planarization film 237 and is disposed so as to partially overlap the drain electrode 227C, and the first pixel contact hole CH203 that connects the drain electrode 227C and the pixel electrode 228 is provided at a position of the first planarization film 237 that overlaps both the drain electrode 227C and the pixel electrode 228 but does not overlap the drain contact hole CH202. The third interlayer insulating film 236 is formed in a range overlapping the first overlapping portion 227C1A and a peripheral portion 227C1B of the drain electrode 227C around the first overlapping portion 227C1A, but is not formed in a range overlapping the second overlapping portion 227C2A, which is a portion of the drain electrode 227C that overlaps with the first pixel contact hole CH203, and a peripheral portion 227C2B of the second overlapping portion 227C2A of the drain electrode 227C. The pixel electrode 228 is connected to the second overlapping portion 227C2A of the drain electrode 227C through the first pixel contact hole CH203 in the first planarization film 237. In the drain electrode 227C, the first overlapping portion 227C1A and its peripheral portion 227C1B are covered by the third interlayer insulating film 236, but the second overlapping portion 227C2A and its peripheral portion 227C2B are not covered by the third interlayer insulating film 236. Therefore, compared to a case where the entire drain electrode except for the second overlapping portion is covered by the third interlayer insulating film, the area where the third interlayer insulating film 236 is formed is reduced. If the area where the third interlayer insulating film 236 is formed is reduced, the amount of light absorbed by the third interlayer insulating film 236 decreases, thereby increasing the amount of light transmitted through the pixel electrode 228 and reducing the amount of light reflected at the interface of the third interlayer insulating film 236. This improves the light transmittance of the pixel electrode 228.

[0068] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0069] (1) The third interlayer insulating film 36, 136, 236 is made of, for example, SiN x and SiO2 may be laminated.

[0070] (2) The specific formation range of the third interlayer insulating film 36, 136, 236 in plan view can be changed as appropriate from that shown in the drawings. For example, as a modification of the first and third embodiments, the third interlayer insulating film 36, 236 may be disposed only in the range overlapping with the drain electrode 27C, 227C. In other words, the third interlayer insulating film 36, 236 may be configured to include only the first insulating portion 36A, 236A and not include the second insulating portion 36B, 236B. Furthermore, in the configurations described in the first and third embodiments, the formation range of the second insulating portion 36B, 236B may be expanded or contracted compared to that shown in the drawings.

[0071] (3) The pixel contact holes CH3, CH4, and CH203 may be arranged so as not to overlap with the gate lines 25 and 29. For example, the pixel contact holes CH3, CH4, and CH203 may be arranged at a position spaced apart from the drain contact hole CH2 on the opposite side of the gate lines 25 and 29 in the Y-axis direction. Alternatively, the pixel contact holes CH3, CH4, and CH203 may be arranged between the drain contact hole CH2 and the gate lines 25 and 29 in the Y-axis direction. In any case, the formation area and arrangement of the drain electrodes 27C, 127C, and 227C may be changed according to the arrangement of the pixel contact holes CH3, CH4, and CH203, and the formation area and arrangement of the third interlayer insulating films 36, 136, and 236 may also be changed.

[0072] (4) The connection portions 28A and 228A made of the second transparent electrode film may be omitted. In this case, the pixel electrode 28 is configured only by the pixel body portion 28B made of the third transparent electrode film, and the pixel body portion 28B is directly connected to the drain electrodes 27C, 127C, and 227C through the first pixel contact holes CH3 and CH203 and the second pixel contact hole CH4.

[0073] (5) The upper gate wiring 29 and the upper gate electrode 27E may be omitted. In this case, the third gate insulating film 33 is also omitted, and the TFT 27 has a bottom gate structure.

[0074] (6) The lower gate wiring 25 and the lower gate electrode 27A may be omitted. In this case, the second gate insulating film 32 is also omitted, and the TFT 27 has a top gate structure.

[0075] (7) The second semiconductor film may be omitted. In this case, the second metal film (upper gate wiring 29 and upper gate electrode 27E) and the third gate insulating film 33 are also omitted, and the semiconductor portion 27D of the TFT 27 is made of the first semiconductor film, and the gate electrode of the TFT 27 is made of the first metal film, so that the TFT 27 has a top-gate structure.

[0076] (8) The first semiconductor film may be omitted. In this case, the first gate insulating film 31 is also omitted, and the TFT included in the circuit unit 14 arranged in the non-display area NAA has a semiconductor portion made of the second semiconductor film.

[0077] (9) The specific method for making the second semiconductor film conductive can be changed as appropriate in addition to the above.

[0078] (10) Instead of the second circuit section 14B, a source driver may be attached to the array substrate 21, 121.

[0079] (11) A source driver may be attached to the flexible substrate 13 instead of the second circuit section 14B.

[0080] (12) Instead of the first circuit section 14A, a gate driver may be attached to the array substrate 21, 121.

[0081] (13) The planar shape of the liquid crystal panel 11 may be a horizontally long rectangle, a vertically long rectangle, a square, a circle, a semicircle, an oval, an ellipse, a trapezoid, or the like.

[0082] (14) The second semiconductor film may be an amorphous silicon thin film.

[0083] (15) The liquid crystal panel 11 may be a reflective or semi-transmissive type in addition to a transmissive type. If the liquid crystal panel 11 is a reflective type, the backlight device 12 can be omitted.

[0084] (16) In addition to the liquid crystal panel 11, an organic EL display device, which is a self-luminous display device, may also be used.

[0085] (17) In addition to the head-mounted display 10 HMD, the present invention can also be applied to devices such as head-up displays and projectors that use lenses to enlarge an image displayed on the liquid crystal panel 11. The present invention can also be applied to display devices that do not have an enlargement function (such as television receivers, tablet terminals, and smartphones).

[0086] (18) As in the above (5), when the upper gate wiring 29 and the upper gate electrode 27E are omitted (when the TFT 27 has a bottom gate structure), the first interlayer insulating film 34 may not be formed. In that case, a second interlayer insulating film 35 is disposed as a “first insulating film” above the semiconductor portion 27D and below the drain electrodes 27C, 127C, and 227C, and drain contact holes CH2 and CH202 are provided in the second interlayer insulating film 35.

[0087] (19) The second interlayer insulating film 35 may not be formed. In that case, a first interlayer insulating film 34 is disposed as a "first insulating film" above the semiconductor portion 27D and below the drain electrodes 27C, 127C, and 227C, and the drain contact holes CH2 and CH202 are provided in the first interlayer insulating film 34. When the second interlayer insulating film 35 is not formed, the source wiring 26 and the drain electrodes 27C, 127C, and 227C are arranged in the same layer, but they are not overlapped with each other, so that short-circuiting is avoided even if they are in the same layer. [Explanation of symbols]

[0088] 11...liquid crystal panel (display device), 20...opposing substrate, 21, 121...array substrate, 25...lower layer gate wiring (first wiring), 27...TFT (transistor), 27A...lower layer gate electrode (second electrode), 27B...source electrode (third electrode), 27C, 127C, 227C...drain electrode (first electrode), 27C1A, 227C1A...first overlapping portion, 27C1B, 227C1B...peripheral portion, 27C2A, 227C2A...second overlapping portion, 27C2B, 227C2B...peripheral portion, 27D...semiconductor portion, 27E...upper layer gate electrode (fourth electrode), 28, 128, 228...pixel electrode, 28C, 128C...electrode overlapping portion, 28D, 128D... Electrode non-overlapping portion, 29...upper layer gate wiring (second wiring), 32...second gate insulating film (fourth insulating film), 33...third gate insulating film (fifth insulating film), 34...first interlayer insulating film (first insulating film), 35...second interlayer insulating film (first insulating film), 36, 136, 236...third interlayer insulating film (second insulating film), 36A, 236A...first insulating portion, 36B, 236B...second insulating portion, 37, 237...first planarization film (third insulating film), CH2, CH202...drain contact hole (first contact hole), CH3, CH203...first pixel contact hole (second contact hole), CH4...second pixel contact hole (third contact hole)

Claims

1. a semiconductor portion made of a semiconductor material; a first insulating film disposed on an upper layer side of the semiconductor portion; a first electrode disposed on an upper layer side of the first insulating film, at least a portion of which overlaps a portion of the semiconductor portion; a second insulating film disposed on an upper layer side of the first electrode; a third insulating film disposed on an upper layer side of the second insulating film, the first electrode is made of a transparent electrode material, the first insulating film is made of an inorganic insulating material and has a first contact hole that connects the semiconductor portion and the first electrode at a position where the first insulating film overlaps both the semiconductor portion and the first electrode; the third insulating film is made of an organic insulating material, The second insulating film is made of an inorganic insulating material and covers at least a first overlapping portion of the first electrode, which is a portion of the first electrode that overlaps with the first contact hole.

2. a pixel electrode disposed above the third insulating film and partially overlapping the first electrode; a second contact hole that connects the first electrode and the pixel electrode is provided in the third insulating film at a position that overlaps both the first electrode and the pixel electrode but does not overlap the first contact hole; 2. The array substrate according to claim 1, wherein the second insulating film has a third contact hole communicating with the second contact hole and covers the entire area of ​​the first electrode except for a second overlapping portion which is the portion of the first electrode that overlaps with the second contact hole.

3. 3. The array substrate according to claim 2, wherein the second insulating film includes a first insulating portion overlapping the first electrode and a second insulating portion surrounding the first insulating portion.

4. the pixel electrode has an electrode overlapping portion that overlaps with the first electrode and an electrode non-overlapping portion that does not overlap with the first electrode, 4. The array substrate according to claim 2, wherein the second insulating film is not formed in an area overlapping the electrode non-overlapping portion.

5. the pixel electrode has an electrode overlapping portion that overlaps with the first electrode and an electrode non-overlapping portion that does not overlap with the first electrode, 4. The array substrate according to claim 2, wherein the second insulating film is formed in a range overlapping the electrode non-overlapping portion.

6. a pixel electrode disposed above the third insulating film and partially overlapping the first electrode; a second contact hole that connects the first electrode and the pixel electrode is provided in the third insulating film at a position that overlaps both the first electrode and the pixel electrode but does not overlap the first contact hole; 2. The array substrate according to claim 1, wherein the second insulating film is formed in an area overlapping the first overlapping portion and a peripheral portion of the first electrode of the first overlapping portion, and is not formed in an area overlapping the second overlapping portion, which is a portion of the first electrode that overlaps the second contact hole, and a peripheral portion of the first electrode of the second overlapping portion.

7. a pixel electrode disposed above the third insulating film and partially overlapping the first electrode; a first wiring made of a conductive material having a light-shielding property and arranged below the first insulating film; 7. The array substrate according to claim 1, wherein a second contact hole connecting the first electrode and the pixel electrode is provided in the third insulating film at a position where the third insulating film overlaps both the first electrode and the pixel electrode and also overlaps the first wiring.

8. 7. The array substrate according to claim 1, wherein the second insulating film contains silicon nitride as the inorganic insulating material.

9. a fourth insulating film disposed below the semiconductor portion; a second electrode disposed below the fourth insulating film and overlapping a portion of the semiconductor portion; a third electrode that is arranged so as not to overlap the first electrode and the second electrode and is connected to the semiconductor portion, 7. The array substrate according to claim 1, wherein the first electrode, the second electrode, the third electrode and the semiconductor portion constitute a transistor.

10. a fifth insulating film disposed above the semiconductor portion and below the first insulating film; a fourth electrode disposed above the fifth insulating film and below the first insulating film, the fourth electrode overlapping a portion of the semiconductor portion; a third electrode that is arranged so as not to overlap the first electrode and the fourth electrode and is connected to the semiconductor portion, 7. The array substrate according to claim 1, wherein the first electrode, the fourth electrode, the third electrode and the semiconductor portion constitute a transistor.

11. an array substrate according to any one of claims 1 to 3 and 6; a counter substrate disposed opposite the array substrate.

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